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Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6
[net-next-2.6.git] / drivers / scsi / bfa / bfa_ioc_cb.c
CommitLineData
0a20de44 1/*
a36c61f9 2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
0a20de44
KG		 3 * All rights reserved
4 * www.brocade.com
5 *
6 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License (GPL) Version 2 as
10 * published by the Free Software Foundation
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 */
17
a36c61f9
KG		 18#include "bfa_ioc.h"
19#include "bfi_cbreg.h"
20#include "bfa_defs.h"
0a20de44
KG		 21
22BFA_TRC_FILE(CNA, IOC_CB);
23
24/*
25 * forward declarations
26 */
0a20de44
KG		 27static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc);
28static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc);
0a20de44
KG		 29static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc);
30static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc);
31static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix);
32static void bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc);
33static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc);
34
293f82d5 35struct bfa_ioc_hwif_s hwif_cb;
0a20de44 36
5fbe25c7 37/*
0a20de44
KG		 38 * Called from bfa_ioc_attach() to map asic specific calls.
39 */
40void
41bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc)
42{
293f82d5
JH		 43 hwif_cb.ioc_pll_init = bfa_ioc_cb_pll_init;
44 hwif_cb.ioc_firmware_lock = bfa_ioc_cb_firmware_lock;
45 hwif_cb.ioc_firmware_unlock = bfa_ioc_cb_firmware_unlock;
46 hwif_cb.ioc_reg_init = bfa_ioc_cb_reg_init;
47 hwif_cb.ioc_map_port = bfa_ioc_cb_map_port;
48 hwif_cb.ioc_isr_mode_set = bfa_ioc_cb_isr_mode_set;
49 hwif_cb.ioc_notify_hbfail = bfa_ioc_cb_notify_hbfail;
50 hwif_cb.ioc_ownership_reset = bfa_ioc_cb_ownership_reset;
0a20de44 51
293f82d5 52 ioc->ioc_hwif = &hwif_cb;
0a20de44
KG		 53}
54
5fbe25c7 55/*
0a20de44
KG		 56 * Return true if firmware of current driver matches the running firmware.
57 */
58static bfa_boolean_t
59bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc)
60{
61 return BFA_TRUE;
62}
63
64static void
65bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc)
66{
67}
68
5fbe25c7 69/*
0a20de44
KG		 70 * Notify other functions on HB failure.
71 */
72static void
73bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc)
74{
53440260
JH		 75 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
76 readl(ioc->ioc_regs.err_set);
0a20de44
KG		 77}
78
5fbe25c7 79/*
0a20de44
KG		 80 * Host to LPU mailbox message addresses
81 */
d1c61f8e 82static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
0a20de44
KG		 83 { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
84 { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 }
85};
86
5fbe25c7 87/*
0a20de44
KG		 88 * Host <-> LPU mailbox command/status registers
89 */
d1c61f8e 90static struct { u32 hfn, lpu; } iocreg_mbcmd[] = {
a36c61f9 91
0a20de44
KG		 92 { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
93 { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT }
94};
95
96static void
97bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc)
98{
53440260 99 void __iomem *rb;
0a20de44
KG		 100 int pcifn = bfa_ioc_pcifn(ioc);
101
102 rb = bfa_ioc_bar0(ioc);
103
104 ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
105 ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
106 ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
107
108 if (ioc->port_id == 0) {
109 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
110 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
111 } else {
112 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
113 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
114 }
115
5fbe25c7 116 /*
0a20de44
KG		 117 * Host <-> LPU mailbox command/status registers
118 */
119 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn;
120 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu;
121
122 /*
123 * PSS control registers
124 */
125 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
8b651b42 126 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
0a20de44
KG		 127 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_400_CTL_REG);
128 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_212_CTL_REG);
129
130 /*
131 * IOC semaphore registers and serialization
132 */
133 ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
134 ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
135
5fbe25c7 136 /*
0a20de44
KG		 137 * sram memory access
138 */
139 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
140 ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB;
141
142 /*
143 * err set reg : for notification of hb failure
144 */
145 ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
146}
147
5fbe25c7 148/*
0a20de44
KG		 149 * Initialize IOC to port mapping.
150 */
a36c61f9 151
0a20de44
KG		 152static void
153bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc)
154{
5fbe25c7 155 /*
0a20de44
KG		 156 * For crossbow, port id is same as pci function.
157 */
158 ioc->port_id = bfa_ioc_pcifn(ioc);
a36c61f9 159
0a20de44
KG		 160 bfa_trc(ioc, ioc->port_id);
161}
162
5fbe25c7 163/*
0a20de44
KG		 164 * Set interrupt mode for a function: INTX or MSIX
165 */
166static void
167bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
168{
169}
170
5fbe25c7 171/*
a36c61f9
KG		 172 * Cleanup hw semaphore and usecnt registers
173 */
174static void
175bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc)
0a20de44 176{
0a20de44
KG		 177
178 /*
a36c61f9
KG		 179 * Read the hw sem reg to make sure that it is locked
180 * before we clear it. If it is not locked, writing 1
181 * will lock it instead of clearing it.
0a20de44 182 */
53440260 183 readl(ioc->ioc_regs.ioc_sem_reg);
a36c61f9
KG		 184 bfa_ioc_hw_sem_release(ioc);
185}
186
187
188
189bfa_status_t
53440260 190bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode)
a36c61f9
KG		 191{
192 u32 pll_sclk, pll_fclk;
0a20de44
KG		 193
194 pll_sclk = __APP_PLL_212_ENABLE | __APP_PLL_212_LRESETN |
a36c61f9
KG		 195 __APP_PLL_212_P0_1(3U) |
196 __APP_PLL_212_JITLMT0_1(3U) |
197 __APP_PLL_212_CNTLMT0_1(3U);
0a20de44 198 pll_fclk = __APP_PLL_400_ENABLE | __APP_PLL_400_LRESETN |
a36c61f9
KG		 199 __APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) |
200 __APP_PLL_400_JITLMT0_1(3U) |
201 __APP_PLL_400_CNTLMT0_1(3U);
53440260
JH		 202 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
203 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
204 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
205 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
206 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
207 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
208 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
209 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
210 writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG);
211 writel(__APP_PLL_212_BYPASS | __APP_PLL_212_LOGIC_SOFT_RESET,
212 rb + APP_PLL_212_CTL_REG);
213 writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG);
214 writel(__APP_PLL_400_BYPASS | __APP_PLL_400_LOGIC_SOFT_RESET,
215 rb + APP_PLL_400_CTL_REG);
6a18b167 216 udelay(2);
53440260
JH		 217 writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG);
218 writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG);
219 writel(pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET,
220 rb + APP_PLL_212_CTL_REG);
221 writel(pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET,
222 rb + APP_PLL_400_CTL_REG);
6a18b167 223 udelay(2000);
53440260
JH		 224 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
225 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
226 writel(pll_sclk, (rb + APP_PLL_212_CTL_REG));
227 writel(pll_fclk, (rb + APP_PLL_400_CTL_REG));
0a20de44
KG		 228
229 return BFA_STATUS_OK;
230}
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