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7725ccfd | 1 | /* |
a36c61f9 | 2 | * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. |
7725ccfd JH |
3 | * All rights reserved |
4 | * www.brocade.com | |
5 | * | |
6 | * Linux driver for Brocade Fibre Channel Host Bus Adapter. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License (GPL) Version 2 as | |
10 | * published by the Free Software Foundation | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | */ | |
17 | ||
a36c61f9 KG |
18 | #include "bfa_modules.h" |
19 | #include "bfi_cbreg.h" | |
7725ccfd JH |
20 | |
21 | void | |
22 | bfa_hwcb_reginit(struct bfa_s *bfa) | |
23 | { | |
24 | struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; | |
53440260 | 25 | void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); |
a36c61f9 | 26 | int i, q, fn = bfa_ioc_pcifn(&bfa->ioc); |
7725ccfd JH |
27 | |
28 | if (fn == 0) { | |
29 | bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS); | |
30 | bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK); | |
31 | } else { | |
32 | bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS); | |
33 | bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK); | |
34 | } | |
35 | ||
36 | for (i = 0; i < BFI_IOC_MAX_CQS; i++) { | |
37 | /* | |
38 | * CPE registers | |
39 | */ | |
40 | q = CPE_Q_NUM(fn, i); | |
41 | bfa_regs->cpe_q_pi[i] = (kva + CPE_Q_PI(q)); | |
42 | bfa_regs->cpe_q_ci[i] = (kva + CPE_Q_CI(q)); | |
43 | bfa_regs->cpe_q_depth[i] = (kva + CPE_Q_DEPTH(q)); | |
44 | ||
45 | /* | |
46 | * RME registers | |
47 | */ | |
48 | q = CPE_Q_NUM(fn, i); | |
49 | bfa_regs->rme_q_pi[i] = (kva + RME_Q_PI(q)); | |
50 | bfa_regs->rme_q_ci[i] = (kva + RME_Q_CI(q)); | |
51 | bfa_regs->rme_q_depth[i] = (kva + RME_Q_DEPTH(q)); | |
52 | } | |
53 | } | |
54 | ||
f5713c5d KG |
55 | void |
56 | bfa_hwcb_reqq_ack(struct bfa_s *bfa, int reqq) | |
57 | { | |
58 | } | |
59 | ||
60 | static void | |
61 | bfa_hwcb_reqq_ack_msix(struct bfa_s *bfa, int reqq) | |
62 | { | |
53440260 JH |
63 | writel(__HFN_INT_CPE_Q0 << CPE_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), reqq), |
64 | bfa->iocfc.bfa_regs.intr_status); | |
f5713c5d KG |
65 | } |
66 | ||
7725ccfd JH |
67 | void |
68 | bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq) | |
69 | { | |
70 | } | |
71 | ||
72 | static void | |
73 | bfa_hwcb_rspq_ack_msix(struct bfa_s *bfa, int rspq) | |
74 | { | |
53440260 JH |
75 | writel(__HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq), |
76 | bfa->iocfc.bfa_regs.intr_status); | |
7725ccfd JH |
77 | } |
78 | ||
79 | void | |
80 | bfa_hwcb_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap, | |
81 | u32 *num_vecs, u32 *max_vec_bit) | |
82 | { | |
83 | #define __HFN_NUMINTS 13 | |
84 | if (bfa_ioc_pcifn(&bfa->ioc) == 0) { | |
85 | *msix_vecs_bmap = (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | | |
86 | __HFN_INT_CPE_Q2 | __HFN_INT_CPE_Q3 | | |
87 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | | |
88 | __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | | |
89 | __HFN_INT_MBOX_LPU0); | |
90 | *max_vec_bit = __HFN_INT_MBOX_LPU0; | |
91 | } else { | |
92 | *msix_vecs_bmap = (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | | |
93 | __HFN_INT_CPE_Q6 | __HFN_INT_CPE_Q7 | | |
94 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | | |
95 | __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | | |
96 | __HFN_INT_MBOX_LPU1); | |
97 | *max_vec_bit = __HFN_INT_MBOX_LPU1; | |
98 | } | |
99 | ||
100 | *msix_vecs_bmap |= (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | | |
101 | __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS); | |
102 | *num_vecs = __HFN_NUMINTS; | |
103 | } | |
104 | ||
5fbe25c7 | 105 | /* |
7725ccfd JH |
106 | * No special setup required for crossbow -- vector assignments are implicit. |
107 | */ | |
108 | void | |
109 | bfa_hwcb_msix_init(struct bfa_s *bfa, int nvecs) | |
110 | { | |
111 | int i; | |
112 | ||
113 | bfa_assert((nvecs == 1) || (nvecs == __HFN_NUMINTS)); | |
114 | ||
115 | bfa->msix.nvecs = nvecs; | |
116 | if (nvecs == 1) { | |
117 | for (i = 0; i < BFA_MSIX_CB_MAX; i++) | |
118 | bfa->msix.handler[i] = bfa_msix_all; | |
119 | return; | |
120 | } | |
121 | ||
122 | for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q7; i++) | |
123 | bfa->msix.handler[i] = bfa_msix_reqq; | |
124 | ||
125 | for (i = BFA_MSIX_RME_Q0; i <= BFA_MSIX_RME_Q7; i++) | |
126 | bfa->msix.handler[i] = bfa_msix_rspq; | |
127 | ||
128 | for (; i < BFA_MSIX_CB_MAX; i++) | |
129 | bfa->msix.handler[i] = bfa_msix_lpu_err; | |
130 | } | |
131 | ||
5fbe25c7 | 132 | /* |
7725ccfd JH |
133 | * Crossbow -- dummy, interrupts are masked |
134 | */ | |
135 | void | |
136 | bfa_hwcb_msix_install(struct bfa_s *bfa) | |
137 | { | |
138 | } | |
139 | ||
140 | void | |
141 | bfa_hwcb_msix_uninstall(struct bfa_s *bfa) | |
142 | { | |
143 | } | |
144 | ||
5fbe25c7 | 145 | /* |
7725ccfd JH |
146 | * No special enable/disable -- vector assignments are implicit. |
147 | */ | |
148 | void | |
149 | bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix) | |
150 | { | |
f5713c5d | 151 | bfa->iocfc.hwif.hw_reqq_ack = bfa_hwcb_reqq_ack_msix; |
7725ccfd JH |
152 | bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack_msix; |
153 | } | |
154 | ||
36d345a7 JH |
155 | void |
156 | bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end) | |
157 | { | |
158 | *start = BFA_MSIX_RME_Q0; | |
159 | *end = BFA_MSIX_RME_Q7; | |
160 | } |