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Merge of /spare/repo/libata-dev branch bridge-detect
[net-next-2.6.git] / drivers / scsi / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
4 * Copyright 2004 Red Hat, Inc.
5 *
6 * The contents of this file are subject to the Open
7 * Software License version 1.1 that can be found at
8 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
9 * by reference.
10 *
11 * Alternatively, the contents of this file may be used under the terms
12 * of the GNU General Public License version 2 (the "GPL") as distributed
13 * in the kernel source COPYING file, in which case the provisions of
14 * the GPL are applicable instead of the above. If you wish to allow
15 * the use of your version of this file only under the terms of the
16 * GPL and not to allow others to use your version of this file under
17 * the OSL, indicate your decision by deleting the provisions above and
18 * replace them with the notice and other provisions required by the GPL.
19 * If you do not delete the provisions above, a recipient may use your
20 * version of this file under either the OSL or the GPL.
21 *
22 * Version 1.0 of the AHCI specification:
23 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
24 *
25 */
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/blkdev.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
34#include <linux/sched.h>
87507cfd 35#include <linux/dma-mapping.h>
1da177e4
LT		 36#include "scsi.h"
37#include <scsi/scsi_host.h>
38#include <linux/libata.h>
39#include <asm/io.h>
40
41#define DRV_NAME "ahci"
ead5de99 42#define DRV_VERSION "1.01"
1da177e4
LT		 43
44
45enum {
46 AHCI_PCI_BAR = 5,
47 AHCI_MAX_SG = 168, /* hardware max is 64K */
48 AHCI_DMA_BOUNDARY = 0xffffffff,
49 AHCI_USE_CLUSTERING = 0,
50 AHCI_CMD_SLOT_SZ = 32 * 32,
51 AHCI_RX_FIS_SZ = 256,
52 AHCI_CMD_TBL_HDR = 0x80,
53 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
54 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
55 AHCI_RX_FIS_SZ,
56 AHCI_IRQ_ON_SG = (1 << 31),
57 AHCI_CMD_ATAPI = (1 << 5),
58 AHCI_CMD_WRITE = (1 << 6),
59
60 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
61
62 board_ahci = 0,
63
64 /* global controller registers */
65 HOST_CAP = 0x00, /* host capabilities */
66 HOST_CTL = 0x04, /* global host control */
67 HOST_IRQ_STAT = 0x08, /* interrupt status */
68 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
69 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
70
71 /* HOST_CTL bits */
72 HOST_RESET = (1 << 0), /* reset controller; self-clear */
73 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
74 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
75
76 /* HOST_CAP bits */
77 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
78
79 /* registers for each SATA port */
80 PORT_LST_ADDR = 0x00, /* command list DMA addr */
81 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
82 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
83 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
84 PORT_IRQ_STAT = 0x10, /* interrupt status */
85 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
86 PORT_CMD = 0x18, /* port command */
87 PORT_TFDATA = 0x20, /* taskfile data */
88 PORT_SIG = 0x24, /* device TF signature */
89 PORT_CMD_ISSUE = 0x38, /* command issue */
90 PORT_SCR = 0x28, /* SATA phy register block */
91 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
92 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
93 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
94 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
95
96 /* PORT_IRQ_{STAT,MASK} bits */
97 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
98 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
99 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
100 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
101 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
102 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
103 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
104 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
105
106 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
107 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
108 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
109 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
110 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
111 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
112 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
113 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
114 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
115
116 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
117 PORT_IRQ_HBUS_ERR |
118 PORT_IRQ_HBUS_DATA_ERR |
119 PORT_IRQ_IF_ERR,
120 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
121 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
122 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
123 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
124 PORT_IRQ_D2H_REG_FIS,
125
126 /* PORT_CMD bits */
127 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
128 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
129 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
130 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
131 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
132 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
133
134 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
135 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
136 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 137
138 /* hpriv->flags bits */
139 AHCI_FLAG_MSI = (1 << 0),
1da177e4
LT		 140};
141
142struct ahci_cmd_hdr {
143 u32 opts;
144 u32 status;
145 u32 tbl_addr;
146 u32 tbl_addr_hi;
147 u32 reserved[4];
148};
149
150struct ahci_sg {
151 u32 addr;
152 u32 addr_hi;
153 u32 reserved;
154 u32 flags_size;
155};
156
157struct ahci_host_priv {
158 unsigned long flags;
159 u32 cap; /* cache of HOST_CAP register */
160 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
161};
162
163struct ahci_port_priv {
164 struct ahci_cmd_hdr *cmd_slot;
165 dma_addr_t cmd_slot_dma;
166 void *cmd_tbl;
167 dma_addr_t cmd_tbl_dma;
168 struct ahci_sg *cmd_tbl_sg;
169 void *rx_fis;
170 dma_addr_t rx_fis_dma;
171};
172
173static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
174static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
175static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
176static int ahci_qc_issue(struct ata_queued_cmd *qc);
177static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
178static void ahci_phy_reset(struct ata_port *ap);
179static void ahci_irq_clear(struct ata_port *ap);
180static void ahci_eng_timeout(struct ata_port *ap);
181static int ahci_port_start(struct ata_port *ap);
182static void ahci_port_stop(struct ata_port *ap);
183static void ahci_host_stop(struct ata_host_set *host_set);
184static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
185static void ahci_qc_prep(struct ata_queued_cmd *qc);
186static u8 ahci_check_status(struct ata_port *ap);
187static u8 ahci_check_err(struct ata_port *ap);
188static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
907f4678 189static void ahci_remove_one (struct pci_dev *pdev);
1da177e4
LT		 190
191static Scsi_Host_Template ahci_sht = {
192 .module = THIS_MODULE,
193 .name = DRV_NAME,
194 .ioctl = ata_scsi_ioctl,
195 .queuecommand = ata_scsi_queuecmd,
196 .eh_strategy_handler = ata_scsi_error,
197 .can_queue = ATA_DEF_QUEUE,
198 .this_id = ATA_SHT_THIS_ID,
199 .sg_tablesize = AHCI_MAX_SG,
200 .max_sectors = ATA_MAX_SECTORS,
201 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
202 .emulated = ATA_SHT_EMULATED,
203 .use_clustering = AHCI_USE_CLUSTERING,
204 .proc_name = DRV_NAME,
205 .dma_boundary = AHCI_DMA_BOUNDARY,
206 .slave_configure = ata_scsi_slave_config,
207 .bios_param = ata_std_bios_param,
208 .ordered_flush = 1,
209};
210
211static struct ata_port_operations ahci_ops = {
212 .port_disable = ata_port_disable,
213
214 .check_status = ahci_check_status,
215 .check_altstatus = ahci_check_status,
216 .check_err = ahci_check_err,
217 .dev_select = ata_noop_dev_select,
218
219 .tf_read = ahci_tf_read,
220
221 .phy_reset = ahci_phy_reset,
222
223 .qc_prep = ahci_qc_prep,
224 .qc_issue = ahci_qc_issue,
225
226 .eng_timeout = ahci_eng_timeout,
227
228 .irq_handler = ahci_interrupt,
229 .irq_clear = ahci_irq_clear,
230
231 .scr_read = ahci_scr_read,
232 .scr_write = ahci_scr_write,
233
234 .port_start = ahci_port_start,
235 .port_stop = ahci_port_stop,
236 .host_stop = ahci_host_stop,
237};
238
239static struct ata_port_info ahci_port_info[] = {
240 /* board_ahci */
241 {
242 .sht = &ahci_sht,
243 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
244 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
245 ATA_FLAG_PIO_DMA,
246 .pio_mask = 0x03, /* pio3-4 */
247 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
248 .port_ops = &ahci_ops,
249 },
250};
251
252static struct pci_device_id ahci_pci_tbl[] = {
253 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
254 board_ahci }, /* ICH6 */
255 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
256 board_ahci }, /* ICH6M */
257 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
258 board_ahci }, /* ICH7 */
259 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
260 board_ahci }, /* ICH7M */
261 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 board_ahci }, /* ICH7R */
263 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_ahci }, /* ULi M5288 */
680d3235
JG		 265 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_ahci }, /* ESB2 */
267 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_ahci }, /* ESB2 */
269 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_ahci }, /* ESB2 */
1da177e4
LT		 271 { } /* terminate list */
272};
273
274
275static struct pci_driver ahci_pci_driver = {
276 .name = DRV_NAME,
277 .id_table = ahci_pci_tbl,
278 .probe = ahci_init_one,
907f4678 279 .remove = ahci_remove_one,
1da177e4
LT		 280};
281
282
283static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
284{
285 return base + 0x100 + (port * 0x80);
286}
287
288static inline void *ahci_port_base (void *base, unsigned int port)
289{
290 return (void *) ahci_port_base_ul((unsigned long)base, port);
291}
292
293static void ahci_host_stop(struct ata_host_set *host_set)
294{
295 struct ahci_host_priv *hpriv = host_set->private_data;
296 kfree(hpriv);
aa8f0dc6
JG		 297
298 ata_host_stop(host_set);
1da177e4
LT		 299}
300
301static int ahci_port_start(struct ata_port *ap)
302{
303 struct device *dev = ap->host_set->dev;
304 struct ahci_host_priv *hpriv = ap->host_set->private_data;
305 struct ahci_port_priv *pp;
306 int rc;
307 void *mem, *mmio = ap->host_set->mmio_base;
308 void *port_mmio = ahci_port_base(mmio, ap->port_no);
309 dma_addr_t mem_dma;
310
311 rc = ata_port_start(ap);
312 if (rc)
313 return rc;
314
315 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
316 if (!pp) {
317 rc = -ENOMEM;
318 goto err_out;
319 }
320 memset(pp, 0, sizeof(*pp));
321
322 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
323 if (!mem) {
324 rc = -ENOMEM;
325 goto err_out_kfree;
326 }
327 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
328
329 /*
330 * First item in chunk of DMA memory: 32-slot command table,
331 * 32 bytes each in size
332 */
333 pp->cmd_slot = mem;
334 pp->cmd_slot_dma = mem_dma;
335
336 mem += AHCI_CMD_SLOT_SZ;
337 mem_dma += AHCI_CMD_SLOT_SZ;
338
339 /*
340 * Second item: Received-FIS area
341 */
342 pp->rx_fis = mem;
343 pp->rx_fis_dma = mem_dma;
344
345 mem += AHCI_RX_FIS_SZ;
346 mem_dma += AHCI_RX_FIS_SZ;
347
348 /*
349 * Third item: data area for storing a single command
350 * and its scatter-gather table
351 */
352 pp->cmd_tbl = mem;
353 pp->cmd_tbl_dma = mem_dma;
354
355 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
356
357 ap->private_data = pp;
358
359 if (hpriv->cap & HOST_CAP_64)
360 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
361 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
362 readl(port_mmio + PORT_LST_ADDR); /* flush */
363
364 if (hpriv->cap & HOST_CAP_64)
365 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
366 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
367 readl(port_mmio + PORT_FIS_ADDR); /* flush */
368
369 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
370 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
371 PORT_CMD_START, port_mmio + PORT_CMD);
372 readl(port_mmio + PORT_CMD); /* flush */
373
374 return 0;
375
376err_out_kfree:
377 kfree(pp);
378err_out:
379 ata_port_stop(ap);
380 return rc;
381}
382
383
384static void ahci_port_stop(struct ata_port *ap)
385{
386 struct device *dev = ap->host_set->dev;
387 struct ahci_port_priv *pp = ap->private_data;
388 void *mmio = ap->host_set->mmio_base;
389 void *port_mmio = ahci_port_base(mmio, ap->port_no);
390 u32 tmp;
391
392 tmp = readl(port_mmio + PORT_CMD);
393 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
394 writel(tmp, port_mmio + PORT_CMD);
395 readl(port_mmio + PORT_CMD); /* flush */
396
397 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
398 * this is slightly incorrect.
399 */
400 msleep(500);
401
402 ap->private_data = NULL;
403 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
404 pp->cmd_slot, pp->cmd_slot_dma);
405 kfree(pp);
406 ata_port_stop(ap);
407}
408
409static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
410{
411 unsigned int sc_reg;
412
413 switch (sc_reg_in) {
414 case SCR_STATUS: sc_reg = 0; break;
415 case SCR_CONTROL: sc_reg = 1; break;
416 case SCR_ERROR: sc_reg = 2; break;
417 case SCR_ACTIVE: sc_reg = 3; break;
418 default:
419 return 0xffffffffU;
420 }
421
422 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
423}
424
425
426static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
427 u32 val)
428{
429 unsigned int sc_reg;
430
431 switch (sc_reg_in) {
432 case SCR_STATUS: sc_reg = 0; break;
433 case SCR_CONTROL: sc_reg = 1; break;
434 case SCR_ERROR: sc_reg = 2; break;
435 case SCR_ACTIVE: sc_reg = 3; break;
436 default:
437 return;
438 }
439
440 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
441}
442
443static void ahci_phy_reset(struct ata_port *ap)
444{
445 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
446 struct ata_taskfile tf;
447 struct ata_device *dev = &ap->device[0];
448 u32 tmp;
449
450 __sata_phy_reset(ap);
451
452 if (ap->flags & ATA_FLAG_PORT_DISABLED)
453 return;
454
455 tmp = readl(port_mmio + PORT_SIG);
456 tf.lbah = (tmp >> 24) & 0xff;
457 tf.lbam = (tmp >> 16) & 0xff;
458 tf.lbal = (tmp >> 8) & 0xff;
459 tf.nsect = (tmp) & 0xff;
460
461 dev->class = ata_dev_classify(&tf);
462 if (!ata_dev_present(dev))
463 ata_port_disable(ap);
464}
465
466static u8 ahci_check_status(struct ata_port *ap)
467{
468 void *mmio = (void *) ap->ioaddr.cmd_addr;
469
470 return readl(mmio + PORT_TFDATA) & 0xFF;
471}
472
473static u8 ahci_check_err(struct ata_port *ap)
474{
475 void *mmio = (void *) ap->ioaddr.cmd_addr;
476
477 return (readl(mmio + PORT_TFDATA) >> 8) & 0xFF;
478}
479
480static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
481{
482 struct ahci_port_priv *pp = ap->private_data;
483 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
484
485 ata_tf_from_fis(d2h_fis, tf);
486}
487
488static void ahci_fill_sg(struct ata_queued_cmd *qc)
489{
490 struct ahci_port_priv *pp = qc->ap->private_data;
491 unsigned int i;
492
493 VPRINTK("ENTER\n");
494
495 /*
496 * Next, the S/G list.
497 */
498 for (i = 0; i < qc->n_elem; i++) {
499 u32 sg_len;
500 dma_addr_t addr;
501
502 addr = sg_dma_address(&qc->sg[i]);
503 sg_len = sg_dma_len(&qc->sg[i]);
504
505 pp->cmd_tbl_sg[i].addr = cpu_to_le32(addr & 0xffffffff);
506 pp->cmd_tbl_sg[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
507 pp->cmd_tbl_sg[i].flags_size = cpu_to_le32(sg_len - 1);
508 }
509}
510
511static void ahci_qc_prep(struct ata_queued_cmd *qc)
512{
513 struct ahci_port_priv *pp = qc->ap->private_data;
514 u32 opts;
515 const u32 cmd_fis_len = 5; /* five dwords */
516
517 /*
518 * Fill in command slot information (currently only one slot,
519 * slot 0, is currently since we don't do queueing)
520 */
521
522 opts = (qc->n_elem << 16) | cmd_fis_len;
523 if (qc->tf.flags & ATA_TFLAG_WRITE)
524 opts |= AHCI_CMD_WRITE;
525
526 switch (qc->tf.protocol) {
527 case ATA_PROT_ATAPI:
528 case ATA_PROT_ATAPI_NODATA:
529 case ATA_PROT_ATAPI_DMA:
530 opts |= AHCI_CMD_ATAPI;
531 break;
532
533 default:
534 /* do nothing */
535 break;
536 }
537
538 pp->cmd_slot[0].opts = cpu_to_le32(opts);
539 pp->cmd_slot[0].status = 0;
540 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
541 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
542
543 /*
544 * Fill in command table information. First, the header,
545 * a SATA Register - Host to Device command FIS.
546 */
547 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
548
549 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
550 return;
551
552 ahci_fill_sg(qc);
553}
554
555static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
556{
557 void *mmio = ap->host_set->mmio_base;
558 void *port_mmio = ahci_port_base(mmio, ap->port_no);
559 u32 tmp;
560 int work;
561
562 /* stop DMA */
563 tmp = readl(port_mmio + PORT_CMD);
564 tmp &= ~PORT_CMD_START;
565 writel(tmp, port_mmio + PORT_CMD);
566
567 /* wait for engine to stop. TODO: this could be
568 * as long as 500 msec
569 */
570 work = 1000;
571 while (work-- > 0) {
572 tmp = readl(port_mmio + PORT_CMD);
573 if ((tmp & PORT_CMD_LIST_ON) == 0)
574 break;
575 udelay(10);
576 }
577
578 /* clear SATA phy error, if any */
579 tmp = readl(port_mmio + PORT_SCR_ERR);
580 writel(tmp, port_mmio + PORT_SCR_ERR);
581
582 /* if DRQ/BSY is set, device needs to be reset.
583 * if so, issue COMRESET
584 */
585 tmp = readl(port_mmio + PORT_TFDATA);
586 if (tmp & (ATA_BUSY | ATA_DRQ)) {
587 writel(0x301, port_mmio + PORT_SCR_CTL);
588 readl(port_mmio + PORT_SCR_CTL); /* flush */
589 udelay(10);
590 writel(0x300, port_mmio + PORT_SCR_CTL);
591 readl(port_mmio + PORT_SCR_CTL); /* flush */
592 }
593
594 /* re-start DMA */
595 tmp = readl(port_mmio + PORT_CMD);
596 tmp |= PORT_CMD_START;
597 writel(tmp, port_mmio + PORT_CMD);
598 readl(port_mmio + PORT_CMD); /* flush */
599
600 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
601}
602
603static void ahci_eng_timeout(struct ata_port *ap)
604{
605 void *mmio = ap->host_set->mmio_base;
606 void *port_mmio = ahci_port_base(mmio, ap->port_no);
607 struct ata_queued_cmd *qc;
608
609 DPRINTK("ENTER\n");
610
611 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
612
613 qc = ata_qc_from_tag(ap, ap->active_tag);
614 if (!qc) {
615 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
616 ap->id);
617 } else {
618 /* hack alert! We cannot use the supplied completion
619 * function from inside the ->eh_strategy_handler() thread.
620 * libata is the only user of ->eh_strategy_handler() in
621 * any kernel, so the default scsi_done() assumes it is
622 * not being called from the SCSI EH.
623 */
624 qc->scsidone = scsi_finish_command;
625 ata_qc_complete(qc, ATA_ERR);
626 }
627
628}
629
630static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
631{
632 void *mmio = ap->host_set->mmio_base;
633 void *port_mmio = ahci_port_base(mmio, ap->port_no);
634 u32 status, serr, ci;
635
636 serr = readl(port_mmio + PORT_SCR_ERR);
637 writel(serr, port_mmio + PORT_SCR_ERR);
638
639 status = readl(port_mmio + PORT_IRQ_STAT);
640 writel(status, port_mmio + PORT_IRQ_STAT);
641
642 ci = readl(port_mmio + PORT_CMD_ISSUE);
643 if (likely((ci & 0x1) == 0)) {
644 if (qc) {
645 ata_qc_complete(qc, 0);
646 qc = NULL;
647 }
648 }
649
650 if (status & PORT_IRQ_FATAL) {
651 ahci_intr_error(ap, status);
652 if (qc)
653 ata_qc_complete(qc, ATA_ERR);
654 }
655
656 return 1;
657}
658
659static void ahci_irq_clear(struct ata_port *ap)
660{
661 /* TODO */
662}
663
664static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
665{
666 struct ata_host_set *host_set = dev_instance;
667 struct ahci_host_priv *hpriv;
668 unsigned int i, handled = 0;
669 void *mmio;
670 u32 irq_stat, irq_ack = 0;
671
672 VPRINTK("ENTER\n");
673
674 hpriv = host_set->private_data;
675 mmio = host_set->mmio_base;
676
677 /* sigh. 0xffffffff is a valid return from h/w */
678 irq_stat = readl(mmio + HOST_IRQ_STAT);
679 irq_stat &= hpriv->port_map;
680 if (!irq_stat)
681 return IRQ_NONE;
682
683 spin_lock(&host_set->lock);
684
685 for (i = 0; i < host_set->n_ports; i++) {
686 struct ata_port *ap;
687 u32 tmp;
688
689 VPRINTK("port %u\n", i);
690 ap = host_set->ports[i];
691 tmp = irq_stat & (1 << i);
692 if (tmp && ap) {
693 struct ata_queued_cmd *qc;
694 qc = ata_qc_from_tag(ap, ap->active_tag);
695 if (ahci_host_intr(ap, qc))
696 irq_ack |= (1 << i);
697 }
698 }
699
700 if (irq_ack) {
701 writel(irq_ack, mmio + HOST_IRQ_STAT);
702 handled = 1;
703 }
704
705 spin_unlock(&host_set->lock);
706
707 VPRINTK("EXIT\n");
708
709 return IRQ_RETVAL(handled);
710}
711
712static int ahci_qc_issue(struct ata_queued_cmd *qc)
713{
714 struct ata_port *ap = qc->ap;
715 void *port_mmio = (void *) ap->ioaddr.cmd_addr;
716
717 writel(1, port_mmio + PORT_SCR_ACT);
718 readl(port_mmio + PORT_SCR_ACT); /* flush */
719
720 writel(1, port_mmio + PORT_CMD_ISSUE);
721 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
722
723 return 0;
724}
725
726static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
727 unsigned int port_idx)
728{
729 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
730 base = ahci_port_base_ul(base, port_idx);
731 VPRINTK("base now==0x%lx\n", base);
732
733 port->cmd_addr = base;
734 port->scr_addr = base + PORT_SCR;
735
736 VPRINTK("EXIT\n");
737}
738
739static int ahci_host_init(struct ata_probe_ent *probe_ent)
740{
741 struct ahci_host_priv *hpriv = probe_ent->private_data;
742 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
743 void __iomem *mmio = probe_ent->mmio_base;
744 u32 tmp, cap_save;
745 u16 tmp16;
746 unsigned int i, j, using_dac;
747 int rc;
748 void __iomem *port_mmio;
749
750 cap_save = readl(mmio + HOST_CAP);
751 cap_save &= ( (1<<28) | (1<<17) );
752 cap_save |= (1 << 27);
753
754 /* global controller reset */
755 tmp = readl(mmio + HOST_CTL);
756 if ((tmp & HOST_RESET) == 0) {
757 writel(tmp | HOST_RESET, mmio + HOST_CTL);
758 readl(mmio + HOST_CTL); /* flush */
759 }
760
761 /* reset must complete within 1 second, or
762 * the hardware should be considered fried.
763 */
764 ssleep(1);
765
766 tmp = readl(mmio + HOST_CTL);
767 if (tmp & HOST_RESET) {
768 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
769 pci_name(pdev), tmp);
770 return -EIO;
771 }
772
773 writel(HOST_AHCI_EN, mmio + HOST_CTL);
774 (void) readl(mmio + HOST_CTL); /* flush */
775 writel(cap_save, mmio + HOST_CAP);
776 writel(0xf, mmio + HOST_PORTS_IMPL);
777 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
778
779 pci_read_config_word(pdev, 0x92, &tmp16);
780 tmp16 |= 0xf;
781 pci_write_config_word(pdev, 0x92, tmp16);
782
783 hpriv->cap = readl(mmio + HOST_CAP);
784 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
785 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
786
787 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
788 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
789
790 using_dac = hpriv->cap & HOST_CAP_64;
791 if (using_dac &&
792 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
793 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
794 if (rc) {
795 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
796 if (rc) {
797 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
798 pci_name(pdev));
799 return rc;
800 }
801 }
1da177e4
LT		 802 } else {
803 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
804 if (rc) {
805 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
806 pci_name(pdev));
807 return rc;
808 }
809 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
810 if (rc) {
811 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
812 pci_name(pdev));
813 return rc;
814 }
815 }
816
817 for (i = 0; i < probe_ent->n_ports; i++) {
818#if 0 /* BIOSen initialize this incorrectly */
819 if (!(hpriv->port_map & (1 << i)))
820 continue;
821#endif
822
823 port_mmio = ahci_port_base(mmio, i);
824 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
825
826 ahci_setup_port(&probe_ent->port[i],
827 (unsigned long) mmio, i);
828
829 /* make sure port is not active */
830 tmp = readl(port_mmio + PORT_CMD);
831 VPRINTK("PORT_CMD 0x%x\n", tmp);
832 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
833 PORT_CMD_FIS_RX | PORT_CMD_START)) {
834 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
835 PORT_CMD_FIS_RX | PORT_CMD_START);
836 writel(tmp, port_mmio + PORT_CMD);
837 readl(port_mmio + PORT_CMD); /* flush */
838
839 /* spec says 500 msecs for each bit, so
840 * this is slightly incorrect.
841 */
842 msleep(500);
843 }
844
845 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
846
847 j = 0;
848 while (j < 100) {
849 msleep(10);
850 tmp = readl(port_mmio + PORT_SCR_STAT);
851 if ((tmp & 0xf) == 0x3)
852 break;
853 j++;
854 }
855
856 tmp = readl(port_mmio + PORT_SCR_ERR);
857 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
858 writel(tmp, port_mmio + PORT_SCR_ERR);
859
860 /* ack any pending irq events for this port */
861 tmp = readl(port_mmio + PORT_IRQ_STAT);
862 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
863 if (tmp)
864 writel(tmp, port_mmio + PORT_IRQ_STAT);
865
866 writel(1 << i, mmio + HOST_IRQ_STAT);
867
868 /* set irq mask (enables interrupts) */
869 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
870 }
871
872 tmp = readl(mmio + HOST_CTL);
873 VPRINTK("HOST_CTL 0x%x\n", tmp);
874 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
875 tmp = readl(mmio + HOST_CTL);
876 VPRINTK("HOST_CTL 0x%x\n", tmp);
877
878 pci_set_master(pdev);
879
880 return 0;
881}
882
883/* move to PCI layer, integrate w/ MSI stuff */
907f4678 884static void pci_intx(struct pci_dev *pdev, int enable)
1da177e4 885{
907f4678 886 u16 pci_command, new;
1da177e4
LT		 887
888 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
907f4678
JG		 889
890 if (enable)
891 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
892 else
893 new = pci_command | PCI_COMMAND_INTX_DISABLE;
894
895 if (new != pci_command)
1da177e4 896 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
1da177e4
LT		 897}
898
899static void ahci_print_info(struct ata_probe_ent *probe_ent)
900{
901 struct ahci_host_priv *hpriv = probe_ent->private_data;
902 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
903 void *mmio = probe_ent->mmio_base;
904 u32 vers, cap, impl, speed;
905 const char *speed_s;
906 u16 cc;
907 const char *scc_s;
908
909 vers = readl(mmio + HOST_VERSION);
910 cap = hpriv->cap;
911 impl = hpriv->port_map;
912
913 speed = (cap >> 20) & 0xf;
914 if (speed == 1)
915 speed_s = "1.5";
916 else if (speed == 2)
917 speed_s = "3";
918 else
919 speed_s = "?";
920
921 pci_read_config_word(pdev, 0x0a, &cc);
922 if (cc == 0x0101)
923 scc_s = "IDE";
924 else if (cc == 0x0106)
925 scc_s = "SATA";
926 else if (cc == 0x0104)
927 scc_s = "RAID";
928 else
929 scc_s = "unknown";
930
931 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
932 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
933 ,
934 pci_name(pdev),
935
936 (vers >> 24) & 0xff,
937 (vers >> 16) & 0xff,
938 (vers >> 8) & 0xff,
939 vers & 0xff,
940
941 ((cap >> 8) & 0x1f) + 1,
942 (cap & 0x1f) + 1,
943 speed_s,
944 impl,
945 scc_s);
946
947 printk(KERN_INFO DRV_NAME "(%s) flags: "
948 "%s%s%s%s%s%s"
949 "%s%s%s%s%s%s%s\n"
950 ,
951 pci_name(pdev),
952
953 cap & (1 << 31) ? "64bit " : "",
954 cap & (1 << 30) ? "ncq " : "",
955 cap & (1 << 28) ? "ilck " : "",
956 cap & (1 << 27) ? "stag " : "",
957 cap & (1 << 26) ? "pm " : "",
958 cap & (1 << 25) ? "led " : "",
959
960 cap & (1 << 24) ? "clo " : "",
961 cap & (1 << 19) ? "nz " : "",
962 cap & (1 << 18) ? "only " : "",
963 cap & (1 << 17) ? "pmp " : "",
964 cap & (1 << 15) ? "pio " : "",
965 cap & (1 << 14) ? "slum " : "",
966 cap & (1 << 13) ? "part " : ""
967 );
968}
969
970static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
971{
972 static int printed_version;
973 struct ata_probe_ent *probe_ent = NULL;
974 struct ahci_host_priv *hpriv;
975 unsigned long base;
976 void *mmio_base;
977 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 978 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 979 int rc;
980
981 VPRINTK("ENTER\n");
982
983 if (!printed_version++)
984 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
985
986 rc = pci_enable_device(pdev);
987 if (rc)
988 return rc;
989
990 rc = pci_request_regions(pdev, DRV_NAME);
991 if (rc) {
992 pci_dev_busy = 1;
993 goto err_out;
994 }
995
907f4678
JG		 996 if (pci_enable_msi(pdev) == 0)
997 have_msi = 1;
998 else {
999 pci_intx(pdev, 1);
1000 have_msi = 0;
1001 }
1da177e4
LT		 1002
1003 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1004 if (probe_ent == NULL) {
1005 rc = -ENOMEM;
907f4678 1006 goto err_out_msi;
1da177e4
LT		 1007 }
1008
1009 memset(probe_ent, 0, sizeof(*probe_ent));
1010 probe_ent->dev = pci_dev_to_dev(pdev);
1011 INIT_LIST_HEAD(&probe_ent->node);
1012
1013 mmio_base = ioremap(pci_resource_start(pdev, AHCI_PCI_BAR),
1014 pci_resource_len(pdev, AHCI_PCI_BAR));
1015 if (mmio_base == NULL) {
1016 rc = -ENOMEM;
1017 goto err_out_free_ent;
1018 }
1019 base = (unsigned long) mmio_base;
1020
1021 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1022 if (!hpriv) {
1023 rc = -ENOMEM;
1024 goto err_out_iounmap;
1025 }
1026 memset(hpriv, 0, sizeof(*hpriv));
1027
1028 probe_ent->sht = ahci_port_info[board_idx].sht;
1029 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1030 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1031 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1032 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1033
1034 probe_ent->irq = pdev->irq;
1035 probe_ent->irq_flags = SA_SHIRQ;
1036 probe_ent->mmio_base = mmio_base;
1037 probe_ent->private_data = hpriv;
1038
4b0060f4
JG		 1039 if (have_msi)
1040 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1041
1da177e4
LT		 1042 /* initialize adapter */
1043 rc = ahci_host_init(probe_ent);
1044 if (rc)
1045 goto err_out_hpriv;
1046
1047 ahci_print_info(probe_ent);
1048
1049 /* FIXME: check ata_device_add return value */
1050 ata_device_add(probe_ent);
1051 kfree(probe_ent);
1052
1053 return 0;
1054
1055err_out_hpriv:
1056 kfree(hpriv);
1057err_out_iounmap:
1058 iounmap(mmio_base);
1059err_out_free_ent:
1060 kfree(probe_ent);
907f4678
JG		 1061err_out_msi:
1062 if (have_msi)
1063 pci_disable_msi(pdev);
1064 else
1065 pci_intx(pdev, 0);
1da177e4
LT		 1066 pci_release_regions(pdev);
1067err_out:
1068 if (!pci_dev_busy)
1069 pci_disable_device(pdev);
1070 return rc;
1071}
1072
907f4678
JG		 1073static void ahci_remove_one (struct pci_dev *pdev)
1074{
1075 struct device *dev = pci_dev_to_dev(pdev);
1076 struct ata_host_set *host_set = dev_get_drvdata(dev);
1077 struct ahci_host_priv *hpriv = host_set->private_data;
1078 struct ata_port *ap;
1079 unsigned int i;
1080 int have_msi;
1081
1082 for (i = 0; i < host_set->n_ports; i++) {
1083 ap = host_set->ports[i];
1084
1085 scsi_remove_host(ap->host);
1086 }
1087
4b0060f4 1088 have_msi = hpriv->flags & AHCI_FLAG_MSI;
907f4678 1089 free_irq(host_set->irq, host_set);
907f4678
JG		 1090
1091 for (i = 0; i < host_set->n_ports; i++) {
1092 ap = host_set->ports[i];
1093
1094 ata_scsi_release(ap->host);
1095 scsi_host_put(ap->host);
1096 }
1097
ead5de99
JG		 1098 host_set->ops->host_stop(host_set);
1099 kfree(host_set);
1100
907f4678
JG		 1101 if (have_msi)
1102 pci_disable_msi(pdev);
1103 else
1104 pci_intx(pdev, 0);
1105 pci_release_regions(pdev);
907f4678
JG		 1106 pci_disable_device(pdev);
1107 dev_set_drvdata(dev, NULL);
1108}
1da177e4
LT		 1109
1110static int __init ahci_init(void)
1111{
1112 return pci_module_init(&ahci_pci_driver);
1113}
1114
1115
1116static void __exit ahci_exit(void)
1117{
1118 pci_unregister_driver(&ahci_pci_driver);
1119}
1120
1121
1122MODULE_AUTHOR("Jeff Garzik");
1123MODULE_DESCRIPTION("AHCI SATA low-level driver");
1124MODULE_LICENSE("GPL");
1125MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1126
1127module_init(ahci_init);
1128module_exit(ahci_exit);
Clone of davem's net-next-2.6 tree