[net-next-2.6.git] / drivers / rtc / rtc-jz4740.c

/*
 *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
 *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
 *	 JZ4740 SoC RTC driver
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under  the terms of  the GNU General Public License as published by the
 *  Free Software Foundation;  either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define JZ_REG_RTC_CTRL		0x00
#define JZ_REG_RTC_SEC		0x04
#define JZ_REG_RTC_SEC_ALARM	0x08
#define JZ_REG_RTC_REGULATOR	0x0C
#define JZ_REG_RTC_HIBERNATE	0x20
#define JZ_REG_RTC_SCRATCHPAD	0x34

#define JZ_RTC_CTRL_WRDY	BIT(7)
#define JZ_RTC_CTRL_1HZ		BIT(6)
#define JZ_RTC_CTRL_1HZ_IRQ	BIT(5)
#define JZ_RTC_CTRL_AF		BIT(4)
#define JZ_RTC_CTRL_AF_IRQ	BIT(3)
#define JZ_RTC_CTRL_AE		BIT(2)
#define JZ_RTC_CTRL_ENABLE	BIT(0)

struct jz4740_rtc {
	struct resource *mem;
	void __iomem *base;

	struct rtc_device *rtc;

	unsigned int irq;

	spinlock_t lock;
};

static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
{
	return readl(rtc->base + reg);
}

static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
{
	uint32_t ctrl;
	int timeout = 1000;

	do {
		ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	} while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);

	return timeout ? 0 : -EIO;
}

static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
	uint32_t val)
{
	int ret;
	ret = jz4740_rtc_wait_write_ready(rtc);
	if (ret == 0)
		writel(val, rtc->base + reg);

	return ret;
}

static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
	bool set)
{
	int ret;
	unsigned long flags;
	uint32_t ctrl;

	spin_lock_irqsave(&rtc->lock, flags);

	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);

	/* Don't clear interrupt flags by accident */
	ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;

	if (set)
		ctrl |= mask;
	else
		ctrl &= ~mask;

	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);

	spin_unlock_irqrestore(&rtc->lock, flags);

	return ret;
}

static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	uint32_t secs, secs2;
	int timeout = 5;

	/* If the seconds register is read while it is updated, it can contain a
	 * bogus value. This can be avoided by making sure that two consecutive
	 * reads have the same value.
	 */
	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);

	while (secs != secs2 && --timeout) {
		secs = secs2;
		secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	}

	if (timeout == 0)
		return -EIO;

	rtc_time_to_tm(secs, time);

	return rtc_valid_tm(time);
}

static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);

	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
}

static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	uint32_t secs;
	uint32_t ctrl;

	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);

	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);

	alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
	alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);

	rtc_time_to_tm(secs, &alrm->time);

	return rtc_valid_tm(&alrm->time);
}

static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	int ret;
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	unsigned long secs;

	rtc_tm_to_time(&alrm->time, &secs);

	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
	if (!ret)
		ret = jz4740_rtc_ctrl_set_bits(rtc,
			JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);

	return ret;
}

static int jz4740_rtc_update_irq_enable(struct device *dev, unsigned int enable)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ, enable);
}

static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
}

static struct rtc_class_ops jz4740_rtc_ops = {
	.read_time	= jz4740_rtc_read_time,
	.set_mmss	= jz4740_rtc_set_mmss,
	.read_alarm	= jz4740_rtc_read_alarm,
	.set_alarm	= jz4740_rtc_set_alarm,
	.update_irq_enable = jz4740_rtc_update_irq_enable,
	.alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
};

static irqreturn_t jz4740_rtc_irq(int irq, void *data)
{
	struct jz4740_rtc *rtc = data;
	uint32_t ctrl;
	unsigned long events = 0;

	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);

	if (ctrl & JZ_RTC_CTRL_1HZ)
		events |= (RTC_UF | RTC_IRQF);

	if (ctrl & JZ_RTC_CTRL_AF)
		events |= (RTC_AF | RTC_IRQF);

	rtc_update_irq(rtc->rtc, 1, events);

	jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);

	return IRQ_HANDLED;
}

void jz4740_rtc_poweroff(struct device *dev)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
}
EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);

static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
{
	int ret;
	struct jz4740_rtc *rtc;
	uint32_t scratchpad;

	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
	if (!rtc)
		return -ENOMEM;

	rtc->irq = platform_get_irq(pdev, 0);
	if (rtc->irq < 0) {
		ret = -ENOENT;
		dev_err(&pdev->dev, "Failed to get platform irq\n");
		goto err_free;
	}

	rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!rtc->mem) {
		ret = -ENOENT;
		dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
		goto err_free;
	}

	rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
					pdev->name);
	if (!rtc->mem) {
		ret = -EBUSY;
		dev_err(&pdev->dev, "Failed to request mmio memory region\n");
		goto err_free;
	}

	rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
	if (!rtc->base) {
		ret = -EBUSY;
		dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
		goto err_release_mem_region;
	}

	spin_lock_init(&rtc->lock);

	platform_set_drvdata(pdev, rtc);

	device_init_wakeup(&pdev->dev, 1);

	rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
					THIS_MODULE);
	if (IS_ERR(rtc->rtc)) {
		ret = PTR_ERR(rtc->rtc);
		dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
		goto err_iounmap;
	}

	ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
				pdev->name, rtc);
	if (ret) {
		dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
		goto err_unregister_rtc;
	}

	scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
	if (scratchpad != 0x12345678) {
		ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
		ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
		if (ret) {
			dev_err(&pdev->dev, "Could not write write to RTC registers\n");
			goto err_free_irq;
		}
	}

	return 0;

err_free_irq:
	free_irq(rtc->irq, rtc);
err_unregister_rtc:
	rtc_device_unregister(rtc->rtc);
err_iounmap:
	platform_set_drvdata(pdev, NULL);
	iounmap(rtc->base);
err_release_mem_region:
	release_mem_region(rtc->mem->start, resource_size(rtc->mem));
err_free:
	kfree(rtc);

	return ret;
}

static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
{
	struct jz4740_rtc *rtc = platform_get_drvdata(pdev);

	free_irq(rtc->irq, rtc);

	rtc_device_unregister(rtc->rtc);

	iounmap(rtc->base);
	release_mem_region(rtc->mem->start, resource_size(rtc->mem));

	kfree(rtc);

	platform_set_drvdata(pdev, NULL);

	return 0;
}


#ifdef CONFIG_PM
static int jz4740_rtc_suspend(struct device *dev)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(rtc->irq);
	return 0;
}

static int jz4740_rtc_resume(struct device *dev)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(rtc->irq);
	return 0;
}

static const struct dev_pm_ops jz4740_pm_ops = {
	.suspend = jz4740_rtc_suspend,
	.resume  = jz4740_rtc_resume,
};
#define JZ4740_RTC_PM_OPS (&jz4740_pm_ops)

#else
#define JZ4740_RTC_PM_OPS NULL
#endif  /* CONFIG_PM */

struct platform_driver jz4740_rtc_driver = {
	.probe	 = jz4740_rtc_probe,
	.remove	 = __devexit_p(jz4740_rtc_remove),
	.driver	 = {
		.name  = "jz4740-rtc",
		.owner = THIS_MODULE,
		.pm    = JZ4740_RTC_PM_OPS,
	},
};

static int __init jz4740_rtc_init(void)
{
	return platform_driver_register(&jz4740_rtc_driver);
}
module_init(jz4740_rtc_init);

static void __exit jz4740_rtc_exit(void)
{
	platform_driver_unregister(&jz4740_rtc_driver);
}
module_exit(jz4740_rtc_exit);

MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
MODULE_ALIAS("platform:jz4740-rtc");
Commit	Line	Data
3bf0eea8 LPC	1	/*
3bf0eea8 LPC	2	* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
d0f744c8	3	* Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
3bf0eea8 LPC	4	* JZ4740 SoC RTC driver
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* You should have received a copy of the GNU General Public License along
	12	* with this program; if not, write to the Free Software Foundation, Inc.,
	13	* 675 Mass Ave, Cambridge, MA 02139, USA.
	14	*
	15	*/
	16
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/rtc.h>
	21	#include <linux/slab.h>
	22	#include <linux/spinlock.h>
	23
	24	#define JZ_REG_RTC_CTRL 0x00
	25	#define JZ_REG_RTC_SEC 0x04
	26	#define JZ_REG_RTC_SEC_ALARM 0x08
	27	#define JZ_REG_RTC_REGULATOR 0x0C
	28	#define JZ_REG_RTC_HIBERNATE 0x20
	29	#define JZ_REG_RTC_SCRATCHPAD 0x34
	30
	31	#define JZ_RTC_CTRL_WRDY BIT(7)
	32	#define JZ_RTC_CTRL_1HZ BIT(6)
	33	#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
	34	#define JZ_RTC_CTRL_AF BIT(4)
	35	#define JZ_RTC_CTRL_AF_IRQ BIT(3)
	36	#define JZ_RTC_CTRL_AE BIT(2)
	37	#define JZ_RTC_CTRL_ENABLE BIT(0)
	38
	39	struct jz4740_rtc {
	40	struct resource *mem;
	41	void __iomem *base;
	42
	43	struct rtc_device *rtc;
	44
	45	unsigned int irq;
	46
	47	spinlock_t lock;
	48	};
	49
	50	static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
	51	{
	52	return readl(rtc->base + reg);
	53	}
	54
	55	static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
	56	{
	57	uint32_t ctrl;
	58	int timeout = 1000;
	59
	60	do {
	61	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	62	} while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
	63
	64	return timeout ? 0 : -EIO;
	65	}
	66
	67	static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
68	uint32_t val)
69	{
70	int ret;
71	ret = jz4740_rtc_wait_write_ready(rtc);
72	if (ret == 0)
73	writel(val, rtc->base + reg);
74
75	return ret;
76	}
77
78	static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
79	bool set)
80	{
81	int ret;
82	unsigned long flags;
83	uint32_t ctrl;
84
85	spin_lock_irqsave(&rtc->lock, flags);
86
87	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
88
89	/* Don't clear interrupt flags by accident */
90	ctrl \|= JZ_RTC_CTRL_1HZ \| JZ_RTC_CTRL_AF;
91
92	if (set)
93	ctrl \|= mask;
94	else
95	ctrl &= ~mask;
96
97	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
98
99	spin_unlock_irqrestore(&rtc->lock, flags);
100
101	return ret;
102	}
103
104	static int jz4740_rtc_read_time(struct device dev, struct rtc_time time)
105	{
106	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
107	uint32_t secs, secs2;
108	int timeout = 5;
109
110	/* If the seconds register is read while it is updated, it can contain a
111	* bogus value. This can be avoided by making sure that two consecutive
112	* reads have the same value.
113	*/
114	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
115	secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
116
117	while (secs != secs2 && --timeout) {
118	secs = secs2;
119	secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
120	}
121
122	if (timeout == 0)
123	return -EIO;
124
125	rtc_time_to_tm(secs, time);
126
127	return rtc_valid_tm(time);
128	}
129
130	static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
131	{
132	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
133
134	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
135	}
136
137	static int jz4740_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
138	{
139	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
140	uint32_t secs;
141	uint32_t ctrl;
142
143	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
144
145	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
146
147	alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
148	alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
149
150	rtc_time_to_tm(secs, &alrm->time);
151
152	return rtc_valid_tm(&alrm->time);
153	}
154
155	static int jz4740_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
156	{
157	int ret;
158	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
159	unsigned long secs;
160
161	rtc_tm_to_time(&alrm->time, &secs);
162
163	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
164	if (!ret)
d0f744c8 PC	165	ret = jz4740_rtc_ctrl_set_bits(rtc,
d0f744c8 PC	166	JZ_RTC_CTRL_AE \| JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
3bf0eea8 LPC	167
	168	return ret;
	169	}
	170
	171	static int jz4740_rtc_update_irq_enable(struct device *dev, unsigned int enable)
	172	{
	173	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	174	return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ, enable);
	175	}
	176
	177	static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
	178	{
	179	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	180	return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
	181	}
	182
	183	static struct rtc_class_ops jz4740_rtc_ops = {
	184	.read_time = jz4740_rtc_read_time,
	185	.set_mmss = jz4740_rtc_set_mmss,
	186	.read_alarm = jz4740_rtc_read_alarm,
	187	.set_alarm = jz4740_rtc_set_alarm,
	188	.update_irq_enable = jz4740_rtc_update_irq_enable,
	189	.alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
	190	};
	191
	192	static irqreturn_t jz4740_rtc_irq(int irq, void *data)
	193	{
	194	struct jz4740_rtc *rtc = data;
	195	uint32_t ctrl;
	196	unsigned long events = 0;
	197
	198	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	199
	200	if (ctrl & JZ_RTC_CTRL_1HZ)
	201	events \|= (RTC_UF \| RTC_IRQF);
	202
	203	if (ctrl & JZ_RTC_CTRL_AF)
	204	events \|= (RTC_AF \| RTC_IRQF);
	205
	206	rtc_update_irq(rtc->rtc, 1, events);
	207
	208	jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ \| JZ_RTC_CTRL_AF, false);
	209
	210	return IRQ_HANDLED;
	211	}
	212
	213	void jz4740_rtc_poweroff(struct device *dev)
	214	{
	215	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	216	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
	217	}
	218	EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
	219
	220	static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
	221	{
	222	int ret;
	223	struct jz4740_rtc *rtc;
	224	uint32_t scratchpad;
	225
	226	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
	227	if (!rtc)
	228	return -ENOMEM;
	229
	230	rtc->irq = platform_get_irq(pdev, 0);
231	if (rtc->irq < 0) {
232	ret = -ENOENT;
233	dev_err(&pdev->dev, "Failed to get platform irq\n");
234	goto err_free;
235	}
236
237	rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
238	if (!rtc->mem) {
239	ret = -ENOENT;
240	dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
241	goto err_free;
242	}
243
244	rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
245	pdev->name);
246	if (!rtc->mem) {
247	ret = -EBUSY;
248	dev_err(&pdev->dev, "Failed to request mmio memory region\n");
249	goto err_free;
250	}
251
252	rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
253	if (!rtc->base) {
254	ret = -EBUSY;
255	dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
256	goto err_release_mem_region;
257	}
258
259	spin_lock_init(&rtc->lock);
260
261	platform_set_drvdata(pdev, rtc);
262
d0f744c8 PC	263	device_init_wakeup(&pdev->dev, 1);
d0f744c8 PC	264
3bf0eea8 LPC	265	rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
	266	THIS_MODULE);
	267	if (IS_ERR(rtc->rtc)) {
	268	ret = PTR_ERR(rtc->rtc);
	269	dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
	270	goto err_iounmap;
	271	}
	272
	273	ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
	274	pdev->name, rtc);
	275	if (ret) {
	276	dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
	277	goto err_unregister_rtc;
	278	}
	279
	280	scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
	281	if (scratchpad != 0x12345678) {
	282	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
	283	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
	284	if (ret) {
	285	dev_err(&pdev->dev, "Could not write write to RTC registers\n");
	286	goto err_free_irq;
	287	}
	288	}
	289
	290	return 0;
	291
	292	err_free_irq:
	293	free_irq(rtc->irq, rtc);
	294	err_unregister_rtc:
	295	rtc_device_unregister(rtc->rtc);
	296	err_iounmap:
	297	platform_set_drvdata(pdev, NULL);
	298	iounmap(rtc->base);
	299	err_release_mem_region:
	300	release_mem_region(rtc->mem->start, resource_size(rtc->mem));
	301	err_free:
	302	kfree(rtc);
	303
	304	return ret;
	305	}
	306
	307	static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
	308	{
	309	struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
	310
	311	free_irq(rtc->irq, rtc);
	312
	313	rtc_device_unregister(rtc->rtc);
	314
	315	iounmap(rtc->base);
	316	release_mem_region(rtc->mem->start, resource_size(rtc->mem));
	317
	318	kfree(rtc);
	319
	320	platform_set_drvdata(pdev, NULL);
	321
	322	return 0;
	323	}
	324
d0f744c8 PC	325
	326	#ifdef CONFIG_PM
	327	static int jz4740_rtc_suspend(struct device *dev)
	328	{
	329	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	330
	331	if (device_may_wakeup(dev))
	332	enable_irq_wake(rtc->irq);
	333	return 0;
	334	}
	335
	336	static int jz4740_rtc_resume(struct device *dev)
	337	{
	338	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	339
	340	if (device_may_wakeup(dev))
	341	disable_irq_wake(rtc->irq);
	342	return 0;
	343	}
	344
	345	static const struct dev_pm_ops jz4740_pm_ops = {
	346	.suspend = jz4740_rtc_suspend,
	347	.resume = jz4740_rtc_resume,
	348	};
	349	#define JZ4740_RTC_PM_OPS (&jz4740_pm_ops)
	350
	351	#else
	352	#define JZ4740_RTC_PM_OPS NULL
	353	#endif /* CONFIG_PM */
	354
3bf0eea8	355	struct platform_driver jz4740_rtc_driver = {
d0f744c8 PC	356	.probe = jz4740_rtc_probe,
	357	.remove = __devexit_p(jz4740_rtc_remove),
	358	.driver = {
	359	.name = "jz4740-rtc",
3bf0eea8	360	.owner = THIS_MODULE,
d0f744c8	361	.pm = JZ4740_RTC_PM_OPS,
3bf0eea8 LPC	362	},
	363	};
	364
	365	static int __init jz4740_rtc_init(void)
	366	{
	367	return platform_driver_register(&jz4740_rtc_driver);
	368	}
	369	module_init(jz4740_rtc_init);
	370
	371	static void __exit jz4740_rtc_exit(void)
	372	{
	373	platform_driver_unregister(&jz4740_rtc_driver);
	374	}
	375	module_exit(jz4740_rtc_exit);
	376
	377	MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
	378	MODULE_LICENSE("GPL");
	379	MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
	380	MODULE_ALIAS("platform:jz4740-rtc");