[net-next-2.6.git] / drivers / rtc / rtc-imxdi.c

/*
 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2010 Orex Computed Radiography
 */

/*
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/* based on rtc-mc13892.c */

/*
 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
 * to implement a Linux RTC. Times and alarms are truncated to seconds.
 * Since the RTC framework performs API locking via rtc->ops_lock the
 * only simultaneous accesses we need to deal with is updating DryIce
 * registers while servicing an alarm.
 *
 * Note that reading the DSR (DryIce Status Register) automatically clears
 * the WCF (Write Complete Flag). All DryIce writes are synchronized to the
 * LP (Low Power) domain and set the WCF upon completion. Writes to the
 * DIER (DryIce Interrupt Enable Register) are the only exception. These
 * occur at normal bus speeds and do not set WCF.  Periodic interrupts are
 * not supported by the hardware.
 */

#include <linux/io.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/workqueue.h>

/* DryIce Register Definitions */

#define DTCMR     0x00           /* Time Counter MSB Reg */
#define DTCLR     0x04           /* Time Counter LSB Reg */

#define DCAMR     0x08           /* Clock Alarm MSB Reg */
#define DCALR     0x0c           /* Clock Alarm LSB Reg */
#define DCAMR_UNSET  0xFFFFFFFF  /* doomsday - 1 sec */

#define DCR       0x10           /* Control Reg */
#define DCR_TCE   (1 << 3)       /* Time Counter Enable */

#define DSR       0x14           /* Status Reg */
#define DSR_WBF   (1 << 10)      /* Write Busy Flag */
#define DSR_WNF   (1 << 9)       /* Write Next Flag */
#define DSR_WCF   (1 << 8)       /* Write Complete Flag */
#define DSR_WEF   (1 << 7)       /* Write Error Flag */
#define DSR_CAF   (1 << 4)       /* Clock Alarm Flag */
#define DSR_NVF   (1 << 1)       /* Non-Valid Flag */
#define DSR_SVF   (1 << 0)       /* Security Violation Flag */

#define DIER      0x18           /* Interrupt Enable Reg */
#define DIER_WNIE (1 << 9)       /* Write Next Interrupt Enable */
#define DIER_WCIE (1 << 8)       /* Write Complete Interrupt Enable */
#define DIER_WEIE (1 << 7)       /* Write Error Interrupt Enable */
#define DIER_CAIE (1 << 4)       /* Clock Alarm Interrupt Enable */

/**
 * struct imxdi_dev - private imxdi rtc data
 * @pdev: pionter to platform dev
 * @rtc: pointer to rtc struct
 * @ioaddr: IO registers pointer
 * @irq: dryice normal interrupt
 * @clk: input reference clock
 * @dsr: copy of the DSR register
 * @irq_lock: interrupt enable register (DIER) lock
 * @write_wait: registers write complete queue
 * @write_mutex: serialize registers write
 * @work: schedule alarm work
 */
struct imxdi_dev {
	struct platform_device *pdev;
	struct rtc_device *rtc;
	void __iomem *ioaddr;
	int irq;
	struct clk *clk;
	u32 dsr;
	spinlock_t irq_lock;
	wait_queue_head_t write_wait;
	struct mutex write_mutex;
	struct work_struct work;
};

/*
 * enable a dryice interrupt
 */
static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
{
	unsigned long flags;

	spin_lock_irqsave(&imxdi->irq_lock, flags);
	__raw_writel(__raw_readl(imxdi->ioaddr + DIER) | intr,
			imxdi->ioaddr + DIER);
	spin_unlock_irqrestore(&imxdi->irq_lock, flags);
}

/*
 * disable a dryice interrupt
 */
static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
{
	unsigned long flags;

	spin_lock_irqsave(&imxdi->irq_lock, flags);
	__raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr,
			imxdi->ioaddr + DIER);
	spin_unlock_irqrestore(&imxdi->irq_lock, flags);
}

/*
 * This function attempts to clear the dryice write-error flag.
 *
 * A dryice write error is similar to a bus fault and should not occur in
 * normal operation.  Clearing the flag requires another write, so the root
 * cause of the problem may need to be fixed before the flag can be cleared.
 */
static void clear_write_error(struct imxdi_dev *imxdi)
{
	int cnt;

	dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");

	/* clear the write error flag */
	__raw_writel(DSR_WEF, imxdi->ioaddr + DSR);

	/* wait for it to take effect */
	for (cnt = 0; cnt < 1000; cnt++) {
		if ((__raw_readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
			return;
		udelay(10);
	}
	dev_err(&imxdi->pdev->dev,
			"ERROR: Cannot clear write-error flag!\n");
}

/*
 * Write a dryice register and wait until it completes.
 *
 * This function uses interrupts to determine when the
 * write has completed.
 */
static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
{
	int ret;
	int rc = 0;

	/* serialize register writes */
	mutex_lock(&imxdi->write_mutex);

	/* enable the write-complete interrupt */
	di_int_enable(imxdi, DIER_WCIE);

	imxdi->dsr = 0;

	/* do the register write */
	__raw_writel(val, imxdi->ioaddr + reg);

	/* wait for the write to finish */
	ret = wait_event_interruptible_timeout(imxdi->write_wait,
			imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));
	if (ret < 0) {
		rc = ret;
		goto out;
	} else if (ret == 0) {
		dev_warn(&imxdi->pdev->dev,
				"Write-wait timeout "
				"val = 0x%08x reg = 0x%08x\n", val, reg);
	}

	/* check for write error */
	if (imxdi->dsr & DSR_WEF) {
		clear_write_error(imxdi);
		rc = -EIO;
	}

out:
	mutex_unlock(&imxdi->write_mutex);

	return rc;
}

/*
 * read the seconds portion of the current time from the dryice time counter
 */
static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
	unsigned long now;

	now = __raw_readl(imxdi->ioaddr + DTCMR);
	rtc_time_to_tm(now, tm);

	return 0;
}

/*
 * set the seconds portion of dryice time counter and clear the
 * fractional part.
 */
static int dryice_rtc_set_mmss(struct device *dev, unsigned long secs)
{
	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
	int rc;

	/* zero the fractional part first */
	rc = di_write_wait(imxdi, 0, DTCLR);
	if (rc == 0)
		rc = di_write_wait(imxdi, secs, DTCMR);

	return rc;
}

static int dryice_rtc_alarm_irq_enable(struct device *dev,
		unsigned int enabled)
{
	struct imxdi_dev *imxdi = dev_get_drvdata(dev);

	if (enabled)
		di_int_enable(imxdi, DIER_CAIE);
	else
		di_int_disable(imxdi, DIER_CAIE);

	return 0;
}

/*
 * read the seconds portion of the alarm register.
 * the fractional part of the alarm register is always zero.
 */
static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
	u32 dcamr;

	dcamr = __raw_readl(imxdi->ioaddr + DCAMR);
	rtc_time_to_tm(dcamr, &alarm->time);

	/* alarm is enabled if the interrupt is enabled */
	alarm->enabled = (__raw_readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;

	/* don't allow the DSR read to mess up DSR_WCF */
	mutex_lock(&imxdi->write_mutex);

	/* alarm is pending if the alarm flag is set */
	alarm->pending = (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;

	mutex_unlock(&imxdi->write_mutex);

	return 0;
}

/*
 * set the seconds portion of dryice alarm register
 */
static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
	unsigned long now;
	unsigned long alarm_time;
	int rc;

	rc = rtc_tm_to_time(&alarm->time, &alarm_time);
	if (rc)
		return rc;

	/* don't allow setting alarm in the past */
	now = __raw_readl(imxdi->ioaddr + DTCMR);
	if (alarm_time < now)
		return -EINVAL;

	/* write the new alarm time */
	rc = di_write_wait(imxdi, (u32)alarm_time, DCAMR);
	if (rc)
		return rc;

	if (alarm->enabled)
		di_int_enable(imxdi, DIER_CAIE);  /* enable alarm intr */
	else
		di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */

	return 0;
}

static struct rtc_class_ops dryice_rtc_ops = {
	.read_time		= dryice_rtc_read_time,
	.set_mmss		= dryice_rtc_set_mmss,
	.alarm_irq_enable	= dryice_rtc_alarm_irq_enable,
	.read_alarm		= dryice_rtc_read_alarm,
	.set_alarm		= dryice_rtc_set_alarm,
};

/*
 * dryice "normal" interrupt handler
 */
static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
{
	struct imxdi_dev *imxdi = dev_id;
	u32 dsr, dier;
	irqreturn_t rc = IRQ_NONE;

	dier = __raw_readl(imxdi->ioaddr + DIER);

	/* handle write complete and write error cases */
	if ((dier & DIER_WCIE)) {
		/*If the write wait queue is empty then there is no pending
		  operations. It means the interrupt is for DryIce -Security.
		  IRQ must be returned as none.*/
		if (list_empty_careful(&imxdi->write_wait.task_list))
			return rc;

		/* DSR_WCF clears itself on DSR read */
		dsr = __raw_readl(imxdi->ioaddr + DSR);
		if ((dsr & (DSR_WCF | DSR_WEF))) {
			/* mask the interrupt */
			di_int_disable(imxdi, DIER_WCIE);

			/* save the dsr value for the wait queue */
			imxdi->dsr |= dsr;

			wake_up_interruptible(&imxdi->write_wait);
			rc = IRQ_HANDLED;
		}
	}

	/* handle the alarm case */
	if ((dier & DIER_CAIE)) {
		/* DSR_WCF clears itself on DSR read */
		dsr = __raw_readl(imxdi->ioaddr + DSR);
		if (dsr & DSR_CAF) {
			/* mask the interrupt */
			di_int_disable(imxdi, DIER_CAIE);

			/* finish alarm in user context */
			schedule_work(&imxdi->work);
			rc = IRQ_HANDLED;
		}
	}
	return rc;
}

/*
 * post the alarm event from user context so it can sleep
 * on the write completion.
 */
static void dryice_work(struct work_struct *work)
{
	struct imxdi_dev *imxdi = container_of(work,
			struct imxdi_dev, work);

	/* dismiss the interrupt (ignore error) */
	di_write_wait(imxdi, DSR_CAF, DSR);

	/* pass the alarm event to the rtc framework. */
	rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF);
}

/*
 * probe for dryice rtc device
 */
static int dryice_rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct imxdi_dev *imxdi;
	int rc;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
	if (!imxdi)
		return -ENOMEM;

	imxdi->pdev = pdev;

	if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
				pdev->name))
		return -EBUSY;

	imxdi->ioaddr = devm_ioremap(&pdev->dev, res->start,
			resource_size(res));
	if (imxdi->ioaddr == NULL)
		return -ENOMEM;

	imxdi->irq = platform_get_irq(pdev, 0);
	if (imxdi->irq < 0)
		return imxdi->irq;

	init_waitqueue_head(&imxdi->write_wait);

	INIT_WORK(&imxdi->work, dryice_work);

	mutex_init(&imxdi->write_mutex);

	imxdi->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(imxdi->clk))
		return PTR_ERR(imxdi->clk);
	clk_enable(imxdi->clk);

	/*
	 * Initialize dryice hardware
	 */

	/* mask all interrupts */
	__raw_writel(0, imxdi->ioaddr + DIER);

	rc = devm_request_irq(&pdev->dev, imxdi->irq, dryice_norm_irq,
			IRQF_SHARED, pdev->name, imxdi);
	if (rc) {
		dev_warn(&pdev->dev, "interrupt not available.\n");
		goto err;
	}

	/* put dryice into valid state */
	if (__raw_readl(imxdi->ioaddr + DSR) & DSR_NVF) {
		rc = di_write_wait(imxdi, DSR_NVF | DSR_SVF, DSR);
		if (rc)
			goto err;
	}

	/* initialize alarm */
	rc = di_write_wait(imxdi, DCAMR_UNSET, DCAMR);
	if (rc)
		goto err;
	rc = di_write_wait(imxdi, 0, DCALR);
	if (rc)
		goto err;

	/* clear alarm flag */
	if (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) {
		rc = di_write_wait(imxdi, DSR_CAF, DSR);
		if (rc)
			goto err;
	}

	/* the timer won't count if it has never been written to */
	if (__raw_readl(imxdi->ioaddr + DTCMR) == 0) {
		rc = di_write_wait(imxdi, 0, DTCMR);
		if (rc)
			goto err;
	}

	/* start keeping time */
	if (!(__raw_readl(imxdi->ioaddr + DCR) & DCR_TCE)) {
		rc = di_write_wait(imxdi,
				__raw_readl(imxdi->ioaddr + DCR) | DCR_TCE,
				DCR);
		if (rc)
			goto err;
	}

	platform_set_drvdata(pdev, imxdi);
	imxdi->rtc = rtc_device_register(pdev->name, &pdev->dev,
				  &dryice_rtc_ops, THIS_MODULE);
	if (IS_ERR(imxdi->rtc)) {
		rc = PTR_ERR(imxdi->rtc);
		goto err;
	}

	return 0;

err:
	clk_disable(imxdi->clk);
	clk_put(imxdi->clk);

	return rc;
}

static int __devexit dryice_rtc_remove(struct platform_device *pdev)
{
	struct imxdi_dev *imxdi = platform_get_drvdata(pdev);

	flush_work(&imxdi->work);

	/* mask all interrupts */
	__raw_writel(0, imxdi->ioaddr + DIER);

	rtc_device_unregister(imxdi->rtc);

	clk_disable(imxdi->clk);
	clk_put(imxdi->clk);

	return 0;
}

static struct platform_driver dryice_rtc_driver = {
	.driver = {
		   .name = "imxdi_rtc",
		   .owner = THIS_MODULE,
		   },
	.remove = __devexit_p(dryice_rtc_remove),
};

static int __init dryice_rtc_init(void)
{
	return platform_driver_probe(&dryice_rtc_driver, dryice_rtc_probe);
}

static void __exit dryice_rtc_exit(void)
{
	platform_driver_unregister(&dryice_rtc_driver);
}

module_init(dryice_rtc_init);
module_exit(dryice_rtc_exit);

MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
Commit	Line	Data
eba54546 BS	1	/*
	2	* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2010 Orex Computed Radiography
	4	*/
	5
	6	/*
	7	* The code contained herein is licensed under the GNU General Public
	8	* License. You may obtain a copy of the GNU General Public License
	9	* Version 2 or later at the following locations:
	10	*
	11	* http://www.opensource.org/licenses/gpl-license.html
	12	* http://www.gnu.org/copyleft/gpl.html
	13	*/
	14
	15	/* based on rtc-mc13892.c */
	16
	17	/*
	18	* This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
	19	* to implement a Linux RTC. Times and alarms are truncated to seconds.
	20	* Since the RTC framework performs API locking via rtc->ops_lock the
	21	* only simultaneous accesses we need to deal with is updating DryIce
	22	* registers while servicing an alarm.
	23	*
	24	* Note that reading the DSR (DryIce Status Register) automatically clears
	25	* the WCF (Write Complete Flag). All DryIce writes are synchronized to the
	26	* LP (Low Power) domain and set the WCF upon completion. Writes to the
	27	* DIER (DryIce Interrupt Enable Register) are the only exception. These
	28	* occur at normal bus speeds and do not set WCF. Periodic interrupts are
	29	* not supported by the hardware.
	30	*/
	31
	32	#include <linux/io.h>
	33	#include <linux/clk.h>
	34	#include <linux/delay.h>
	35	#include <linux/module.h>
	36	#include <linux/platform_device.h>
	37	#include <linux/rtc.h>
	38	#include <linux/workqueue.h>
	39
	40	/* DryIce Register Definitions */
	41
	42	#define DTCMR 0x00 /* Time Counter MSB Reg */
	43	#define DTCLR 0x04 /* Time Counter LSB Reg */
	44
	45	#define DCAMR 0x08 /* Clock Alarm MSB Reg */
	46	#define DCALR 0x0c /* Clock Alarm LSB Reg */
	47	#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
	48
	49	#define DCR 0x10 /* Control Reg */
	50	#define DCR_TCE (1 << 3) /* Time Counter Enable */
	51
	52	#define DSR 0x14 /* Status Reg */
	53	#define DSR_WBF (1 << 10) /* Write Busy Flag */
	54	#define DSR_WNF (1 << 9) /* Write Next Flag */
	55	#define DSR_WCF (1 << 8) /* Write Complete Flag */
	56	#define DSR_WEF (1 << 7) /* Write Error Flag */
	57	#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
	58	#define DSR_NVF (1 << 1) /* Non-Valid Flag */
	59	#define DSR_SVF (1 << 0) /* Security Violation Flag */
	60
	61	#define DIER 0x18 /* Interrupt Enable Reg */
	62	#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
	63	#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
	64	#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
65	#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
66
67	/**
68	* struct imxdi_dev - private imxdi rtc data
69	* @pdev: pionter to platform dev
70	* @rtc: pointer to rtc struct
71	* @ioaddr: IO registers pointer
72	* @irq: dryice normal interrupt
73	* @clk: input reference clock
74	* @dsr: copy of the DSR register
75	* @irq_lock: interrupt enable register (DIER) lock
76	* @write_wait: registers write complete queue
77	* @write_mutex: serialize registers write
78	* @work: schedule alarm work
79	*/
80	struct imxdi_dev {
81	struct platform_device *pdev;
82	struct rtc_device *rtc;
83	void __iomem *ioaddr;
84	int irq;
85	struct clk *clk;
86	u32 dsr;
87	spinlock_t irq_lock;
88	wait_queue_head_t write_wait;
89	struct mutex write_mutex;
90	struct work_struct work;
91	};
92
93	/*
94	* enable a dryice interrupt
95	*/
96	static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
97	{
98	unsigned long flags;
99
100	spin_lock_irqsave(&imxdi->irq_lock, flags);
101	__raw_writel(__raw_readl(imxdi->ioaddr + DIER) \| intr,
102	imxdi->ioaddr + DIER);
103	spin_unlock_irqrestore(&imxdi->irq_lock, flags);
104	}
105
106	/*
107	* disable a dryice interrupt
108	*/
109	static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
110	{
111	unsigned long flags;
112
113	spin_lock_irqsave(&imxdi->irq_lock, flags);
114	__raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr,
115	imxdi->ioaddr + DIER);
116	spin_unlock_irqrestore(&imxdi->irq_lock, flags);
117	}
118
119	/*
120	* This function attempts to clear the dryice write-error flag.
121	*
122	* A dryice write error is similar to a bus fault and should not occur in
123	* normal operation. Clearing the flag requires another write, so the root
124	* cause of the problem may need to be fixed before the flag can be cleared.
125	*/
126	static void clear_write_error(struct imxdi_dev *imxdi)
127	{
128	int cnt;
129
130	dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");
131
132	/* clear the write error flag */
133	__raw_writel(DSR_WEF, imxdi->ioaddr + DSR);
134
135	/* wait for it to take effect */
136	for (cnt = 0; cnt < 1000; cnt++) {
137	if ((__raw_readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
138	return;
139	udelay(10);
140	}
141	dev_err(&imxdi->pdev->dev,
142	"ERROR: Cannot clear write-error flag!\n");
143	}
144
145	/*
146	* Write a dryice register and wait until it completes.
147	*
148	* This function uses interrupts to determine when the
149	* write has completed.
150	*/
151	static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
152	{
153	int ret;
154	int rc = 0;
155
156	/* serialize register writes */
157	mutex_lock(&imxdi->write_mutex);
158
159	/* enable the write-complete interrupt */
160	di_int_enable(imxdi, DIER_WCIE);
161
162	imxdi->dsr = 0;
163
164	/* do the register write */
165	__raw_writel(val, imxdi->ioaddr + reg);
166
167	/* wait for the write to finish */
168	ret = wait_event_interruptible_timeout(imxdi->write_wait,
169	imxdi->dsr & (DSR_WCF \| DSR_WEF), msecs_to_jiffies(1));
170	if (ret < 0) {
171	rc = ret;
172	goto out;
173	} else if (ret == 0) {
174	dev_warn(&imxdi->pdev->dev,
175	"Write-wait timeout "
176	"val = 0x%08x reg = 0x%08x\n", val, reg);
177	}
178
179	/* check for write error */
180	if (imxdi->dsr & DSR_WEF) {
181	clear_write_error(imxdi);
182	rc = -EIO;
183	}
184
185	out:
186	mutex_unlock(&imxdi->write_mutex);
187
188	return rc;
189	}
190
191	/*
192	* read the seconds portion of the current time from the dryice time counter
193	*/
194	static int dryice_rtc_read_time(struct device dev, struct rtc_time tm)
195	{
196	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
197	unsigned long now;
198
199	now = __raw_readl(imxdi->ioaddr + DTCMR);
200	rtc_time_to_tm(now, tm);
201
202	return 0;
203	}
204
205	/*
206	* set the seconds portion of dryice time counter and clear the
207	* fractional part.
208	*/
209	static int dryice_rtc_set_mmss(struct device *dev, unsigned long secs)
210	{
211	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
212	int rc;
213
214	/* zero the fractional part first */
215	rc = di_write_wait(imxdi, 0, DTCLR);
216	if (rc == 0)
217	rc = di_write_wait(imxdi, secs, DTCMR);
218
219	return rc;
220	}
221
222	static int dryice_rtc_alarm_irq_enable(struct device *dev,
223	unsigned int enabled)
224	{
225	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
226
227	if (enabled)
228	di_int_enable(imxdi, DIER_CAIE);
229	else
230	di_int_disable(imxdi, DIER_CAIE);
231
232	return 0;
233	}
234
235	/*
236	* read the seconds portion of the alarm register.
237	* the fractional part of the alarm register is always zero.
238	*/
239	static int dryice_rtc_read_alarm(struct device dev, struct rtc_wkalrm alarm)
240	{
241	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
242	u32 dcamr;
243
244	dcamr = __raw_readl(imxdi->ioaddr + DCAMR);
245	rtc_time_to_tm(dcamr, &alarm->time);
246
247	/* alarm is enabled if the interrupt is enabled */
248	alarm->enabled = (__raw_readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;
249
250	/* don't allow the DSR read to mess up DSR_WCF */
251	mutex_lock(&imxdi->write_mutex);
252
253	/* alarm is pending if the alarm flag is set */
254	alarm->pending = (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
255
256	mutex_unlock(&imxdi->write_mutex);
257
258	return 0;
259	}
260
261	/*
262	* set the seconds portion of dryice alarm register
263	*/
264	static int dryice_rtc_set_alarm(struct device dev, struct rtc_wkalrm alarm)
265	{
266	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
267	unsigned long now;
268	unsigned long alarm_time;
269	int rc;
270
271	rc = rtc_tm_to_time(&alarm->time, &alarm_time);
272	if (rc)
273	return rc;
274
275	/* don't allow setting alarm in the past */
276	now = __raw_readl(imxdi->ioaddr + DTCMR);
277	if (alarm_time < now)
278	return -EINVAL;
279
280	/* write the new alarm time */
281	rc = di_write_wait(imxdi, (u32)alarm_time, DCAMR);
282	if (rc)
283	return rc;
284
285	if (alarm->enabled)
286	di_int_enable(imxdi, DIER_CAIE); /* enable alarm intr */
287	else
288	di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */
289
290	return 0;
291	}
292
293	static struct rtc_class_ops dryice_rtc_ops = {
294	.read_time = dryice_rtc_read_time,
295	.set_mmss = dryice_rtc_set_mmss,
296	.alarm_irq_enable = dryice_rtc_alarm_irq_enable,
297	.read_alarm = dryice_rtc_read_alarm,
298	.set_alarm = dryice_rtc_set_alarm,
299	};
300
301	/*
302	* dryice "normal" interrupt handler
303	*/
304	static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
305	{
306	struct imxdi_dev *imxdi = dev_id;
307	u32 dsr, dier;
308	irqreturn_t rc = IRQ_NONE;
309
310	dier = __raw_readl(imxdi->ioaddr + DIER);
311
312	/* handle write complete and write error cases */
313	if ((dier & DIER_WCIE)) {
314	/*If the write wait queue is empty then there is no pending
315	operations. It means the interrupt is for DryIce -Security.
316	IRQ must be returned as none.*/
317	if (list_empty_careful(&imxdi->write_wait.task_list))
318	return rc;
319
320	/* DSR_WCF clears itself on DSR read */
321	dsr = __raw_readl(imxdi->ioaddr + DSR);
322	if ((dsr & (DSR_WCF \| DSR_WEF))) {
323	/* mask the interrupt */
324	di_int_disable(imxdi, DIER_WCIE);
325
326	/* save the dsr value for the wait queue */
327	imxdi->dsr \|= dsr;
328
329	wake_up_interruptible(&imxdi->write_wait);
330	rc = IRQ_HANDLED;
331	}
332	}
333
334	/* handle the alarm case */
335	if ((dier & DIER_CAIE)) {
336	/* DSR_WCF clears itself on DSR read */
337	dsr = __raw_readl(imxdi->ioaddr + DSR);
338	if (dsr & DSR_CAF) {
339	/* mask the interrupt */
340	di_int_disable(imxdi, DIER_CAIE);
341
342	/* finish alarm in user context */
343	schedule_work(&imxdi->work);
344	rc = IRQ_HANDLED;
345	}
346	}
347	return rc;
348	}
349
350	/*
351	* post the alarm event from user context so it can sleep
352	* on the write completion.
353	*/
354	static void dryice_work(struct work_struct *work)
355	{
356	struct imxdi_dev *imxdi = container_of(work,
357	struct imxdi_dev, work);
358
359	/* dismiss the interrupt (ignore error) */
360	di_write_wait(imxdi, DSR_CAF, DSR);
361
362	/* pass the alarm event to the rtc framework. */
363	rtc_update_irq(imxdi->rtc, 1, RTC_AF \| RTC_IRQF);
364	}
365
366	/*
367	* probe for dryice rtc device
368	*/
369	static int dryice_rtc_probe(struct platform_device *pdev)
370	{
371	struct resource *res;
372	struct imxdi_dev *imxdi;
373	int rc;
374
375	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
376	if (!res)
377	return -ENODEV;
378
379	imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
380	if (!imxdi)
381	return -ENOMEM;
382
383	imxdi->pdev = pdev;
384
385	if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
386	pdev->name))
387	return -EBUSY;
388
389	imxdi->ioaddr = devm_ioremap(&pdev->dev, res->start,
390	resource_size(res));
391	if (imxdi->ioaddr == NULL)
392	return -ENOMEM;
393
394	imxdi->irq = platform_get_irq(pdev, 0);
395	if (imxdi->irq < 0)
396	return imxdi->irq;
397
398	init_waitqueue_head(&imxdi->write_wait);
399
400	INIT_WORK(&imxdi->work, dryice_work);
401
402	mutex_init(&imxdi->write_mutex);
403
404	imxdi->clk = clk_get(&pdev->dev, NULL);
405	if (IS_ERR(imxdi->clk))
406	return PTR_ERR(imxdi->clk);
407	clk_enable(imxdi->clk);
408
409	/*
410	* Initialize dryice hardware
411	*/
412
413	/* mask all interrupts */
414	__raw_writel(0, imxdi->ioaddr + DIER);
415
416	rc = devm_request_irq(&pdev->dev, imxdi->irq, dryice_norm_irq,
417	IRQF_SHARED, pdev->name, imxdi);
418	if (rc) {
419	dev_warn(&pdev->dev, "interrupt not available.\n");
420	goto err;
421	}
422
423	/* put dryice into valid state */
424	if (__raw_readl(imxdi->ioaddr + DSR) & DSR_NVF) {
425	rc = di_write_wait(imxdi, DSR_NVF \| DSR_SVF, DSR);
426	if (rc)
427	goto err;
428	}
429
430	/* initialize alarm */
431	rc = di_write_wait(imxdi, DCAMR_UNSET, DCAMR);
432	if (rc)
433	goto err;
434	rc = di_write_wait(imxdi, 0, DCALR);
435	if (rc)
436	goto err;
437
438	/* clear alarm flag */
439	if (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) {
440	rc = di_write_wait(imxdi, DSR_CAF, DSR);
441	if (rc)
442	goto err;
443	}
444
445	/* the timer won't count if it has never been written to */
446	if (__raw_readl(imxdi->ioaddr + DTCMR) == 0) {
447	rc = di_write_wait(imxdi, 0, DTCMR);
448	if (rc)
449	goto err;
450	}
451
452	/* start keeping time */
453	if (!(__raw_readl(imxdi->ioaddr + DCR) & DCR_TCE)) {
454	rc = di_write_wait(imxdi,
455	__raw_readl(imxdi->ioaddr + DCR) \| DCR_TCE,
456	DCR);
457	if (rc)
458	goto err;
459	}
460
461	platform_set_drvdata(pdev, imxdi);
462	imxdi->rtc = rtc_device_register(pdev->name, &pdev->dev,
463	&dryice_rtc_ops, THIS_MODULE);
464	if (IS_ERR(imxdi->rtc)) {
465	rc = PTR_ERR(imxdi->rtc);
466	goto err;
467	}
468
469	return 0;
470
471	err:
472	clk_disable(imxdi->clk);
473	clk_put(imxdi->clk);
474
475	return rc;
476	}
477
478	static int __devexit dryice_rtc_remove(struct platform_device *pdev)
479	{
480	struct imxdi_dev *imxdi = platform_get_drvdata(pdev);
481
482	flush_work(&imxdi->work);
483
484	/* mask all interrupts */
485	__raw_writel(0, imxdi->ioaddr + DIER);
486
487	rtc_device_unregister(imxdi->rtc);
488
489	clk_disable(imxdi->clk);
490	clk_put(imxdi->clk);
491
492	return 0;
493	}
494
495	static struct platform_driver dryice_rtc_driver = {
496	.driver = {
497	.name = "imxdi_rtc",
498	.owner = THIS_MODULE,
499	},
500	.remove = __devexit_p(dryice_rtc_remove),
501	};
502
503	static int __init dryice_rtc_init(void)
504	{
505	return platform_driver_probe(&dryice_rtc_driver, dryice_rtc_probe);
506	}
507
508	static void __exit dryice_rtc_exit(void)
509	{
510	platform_driver_unregister(&dryice_rtc_driver);
511	}
512
513	module_init(dryice_rtc_init);
514	module_exit(dryice_rtc_exit);
515
516	MODULE_AUTHOR("Freescale Semiconductor, Inc.");
517	MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
518	MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
519	MODULE_LICENSE("GPL");