[net-next-2.6.git] / drivers / rtc / rtc-bfin.c

/*
 * Blackfin On-Chip Real Time Clock Driver
 *  Supports BF52[257]/BF53[123]/BF53[467]/BF54[24789]
 *
 * Copyright 2004-2008 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

/* The biggest issue we deal with in this driver is that register writes are
 * synced to the RTC frequency of 1Hz.  So if you write to a register and
 * attempt to write again before the first write has completed, the new write
 * is simply discarded.  This can easily be troublesome if userspace disables
 * one event (say periodic) and then right after enables an event (say alarm).
 * Since all events are maintained in the same interrupt mask register, if
 * we wrote to it to disable the first event and then wrote to it again to
 * enable the second event, that second event would not be enabled as the
 * write would be discarded and things quickly fall apart.
 *
 * To keep this delay from significantly degrading performance (we, in theory,
 * would have to sleep for up to 1 second everytime we wanted to write a
 * register), we only check the write pending status before we start to issue
 * a new write.  We bank on the idea that it doesnt matter when the sync
 * happens so long as we don't attempt another write before it does.  The only
 * time userspace would take this penalty is when they try and do multiple
 * operations right after another ... but in this case, they need to take the
 * sync penalty, so we should be OK.
 *
 * Also note that the RTC_ISTAT register does not suffer this penalty; its
 * writes to clear status registers complete immediately.
 */

/* It may seem odd that there is no SWCNT code in here (which would be exposed
 * via the periodic interrupt event, or PIE).  Since the Blackfin RTC peripheral
 * runs in units of seconds (N/HZ) but the Linux framework runs in units of HZ
 * (2^N HZ), there is no point in keeping code that only provides 1 HZ PIEs.
 * The same exact behavior can be accomplished by using the update interrupt
 * event (UIE).  Maybe down the line the RTC peripheral will suck less in which
 * case we can re-introduce PIE support.
 */

#include <linux/bcd.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/seq_file.h>

#include <asm/blackfin.h>

#define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)

struct bfin_rtc {
	struct rtc_device *rtc_dev;
	struct rtc_time rtc_alarm;
	u16 rtc_wrote_regs;
};

/* Bit values for the ISTAT / ICTL registers */
#define RTC_ISTAT_WRITE_COMPLETE  0x8000
#define RTC_ISTAT_WRITE_PENDING   0x4000
#define RTC_ISTAT_ALARM_DAY       0x0040
#define RTC_ISTAT_24HR            0x0020
#define RTC_ISTAT_HOUR            0x0010
#define RTC_ISTAT_MIN             0x0008
#define RTC_ISTAT_SEC             0x0004
#define RTC_ISTAT_ALARM           0x0002
#define RTC_ISTAT_STOPWATCH       0x0001

/* Shift values for RTC_STAT register */
#define DAY_BITS_OFF    17
#define HOUR_BITS_OFF   12
#define MIN_BITS_OFF    6
#define SEC_BITS_OFF    0

/* Some helper functions to convert between the common RTC notion of time
 * and the internal Blackfin notion that is encoded in 32bits.
 */
static inline u32 rtc_time_to_bfin(unsigned long now)
{
	u32 sec  = (now % 60);
	u32 min  = (now % (60 * 60)) / 60;
	u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
	u32 days = (now / (60 * 60 * 24));
	return (sec  << SEC_BITS_OFF) +
	       (min  << MIN_BITS_OFF) +
	       (hour << HOUR_BITS_OFF) +
	       (days << DAY_BITS_OFF);
}
static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
{
	return (((rtc_bfin >> SEC_BITS_OFF)  & 0x003F)) +
	       (((rtc_bfin >> MIN_BITS_OFF)  & 0x003F) * 60) +
	       (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
	       (((rtc_bfin >> DAY_BITS_OFF)  & 0x7FFF) * 60 * 60 * 24);
}
static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
{
	rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
}

/**
 *	bfin_rtc_sync_pending - make sure pending writes have complete
 *
 * Wait for the previous write to a RTC register to complete.
 * Unfortunately, we can't sleep here as that introduces a race condition when
 * turning on interrupt events.  Consider this:
 *  - process sets alarm
 *  - process enables alarm
 *  - process sleeps while waiting for rtc write to sync
 *  - interrupt fires while process is sleeping
 *  - interrupt acks the event by writing to ISTAT
 *  - interrupt sets the WRITE PENDING bit
 *  - interrupt handler finishes
 *  - process wakes up, sees WRITE PENDING bit set, goes to sleep
 *  - interrupt fires while process is sleeping
 * If anyone can point out the obvious solution here, i'm listening :).  This
 * shouldn't be an issue on an SMP or preempt system as this function should
 * only be called with the rtc lock held.
 *
 * Other options:
 *  - disable PREN so the sync happens at 32.768kHZ ... but this changes the
 *    inc rate for all RTC registers from 1HZ to 32.768kHZ ...
 *  - use the write complete IRQ
 */
/*
static void bfin_rtc_sync_pending_polled(void)
{
	while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE))
		if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
			break;
	bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
}
*/
static DECLARE_COMPLETION(bfin_write_complete);
static void bfin_rtc_sync_pending(struct device *dev)
{
	dev_dbg_stamp(dev);
	while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
		wait_for_completion_timeout(&bfin_write_complete, HZ * 5);
	dev_dbg_stamp(dev);
}

/**
 *	bfin_rtc_reset - set RTC to sane/known state
 *
 * Initialize the RTC.  Enable pre-scaler to scale RTC clock
 * to 1Hz and clear interrupt/status registers.
 */
static void bfin_rtc_reset(struct device *dev, u16 rtc_ictl)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	dev_dbg_stamp(dev);
	bfin_rtc_sync_pending(dev);
	bfin_write_RTC_PREN(0x1);
	bfin_write_RTC_ICTL(rtc_ictl);
	bfin_write_RTC_ALARM(0);
	bfin_write_RTC_ISTAT(0xFFFF);
	rtc->rtc_wrote_regs = 0;
}

/**
 *	bfin_rtc_interrupt - handle interrupt from RTC
 *
 * Since we handle all RTC events here, we have to make sure the requested
 * interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT)
 * always gets updated regardless of the interrupt being enabled.  So when one
 * even we care about (e.g. stopwatch) goes off, we don't want to turn around
 * and say that other events have happened as well (e.g. second).  We do not
 * have to worry about pending writes to the RTC_ICTL register as interrupts
 * only fire if they are enabled in the RTC_ICTL register.
 */
static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
{
	struct device *dev = dev_id;
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	unsigned long events = 0;
	bool write_complete = false;
	u16 rtc_istat, rtc_ictl;

	dev_dbg_stamp(dev);

	rtc_istat = bfin_read_RTC_ISTAT();
	rtc_ictl = bfin_read_RTC_ICTL();

	if (rtc_istat & RTC_ISTAT_WRITE_COMPLETE) {
		bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
		write_complete = true;
		complete(&bfin_write_complete);
	}

	if (rtc_ictl & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) {
		if (rtc_istat & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) {
			bfin_write_RTC_ISTAT(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY);
			events |= RTC_AF | RTC_IRQF;
		}
	}

	if (rtc_ictl & RTC_ISTAT_SEC) {
		if (rtc_istat & RTC_ISTAT_SEC) {
			bfin_write_RTC_ISTAT(RTC_ISTAT_SEC);
			events |= RTC_UF | RTC_IRQF;
		}
	}

	if (events)
		rtc_update_irq(rtc->rtc_dev, 1, events);

	if (write_complete || events)
		return IRQ_HANDLED;
	else
		return IRQ_NONE;
}

static void bfin_rtc_int_set(u16 rtc_int)
{
	bfin_write_RTC_ISTAT(rtc_int);
	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | rtc_int);
}
static void bfin_rtc_int_clear(u16 rtc_int)
{
	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int);
}
static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc)
{
	/* Blackfin has different bits for whether the alarm is
	 * more than 24 hours away.
	 */
	bfin_rtc_int_set(rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY);
}
static int bfin_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	int ret = 0;

	dev_dbg_stamp(dev);

	bfin_rtc_sync_pending(dev);

	switch (cmd) {
	case RTC_UIE_ON:
		dev_dbg_stamp(dev);
		bfin_rtc_int_set(RTC_ISTAT_SEC);
		break;
	case RTC_UIE_OFF:
		dev_dbg_stamp(dev);
		bfin_rtc_int_clear(~RTC_ISTAT_SEC);
		break;

	case RTC_AIE_ON:
		dev_dbg_stamp(dev);
		bfin_rtc_int_set_alarm(rtc);
		break;
	case RTC_AIE_OFF:
		dev_dbg_stamp(dev);
		bfin_rtc_int_clear(~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
		break;

	default:
		dev_dbg_stamp(dev);
		ret = -ENOIOCTLCMD;
	}

	return ret;
}

static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);

	dev_dbg_stamp(dev);

	if (rtc->rtc_wrote_regs & 0x1)
		bfin_rtc_sync_pending(dev);

	rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);

	return 0;
}

static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	int ret;
	unsigned long now;

	dev_dbg_stamp(dev);

	ret = rtc_tm_to_time(tm, &now);
	if (ret == 0) {
		if (rtc->rtc_wrote_regs & 0x1)
			bfin_rtc_sync_pending(dev);
		bfin_write_RTC_STAT(rtc_time_to_bfin(now));
		rtc->rtc_wrote_regs = 0x1;
	}

	return ret;
}

static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	dev_dbg_stamp(dev);
	alrm->time = rtc->rtc_alarm;
	bfin_rtc_sync_pending(dev);
	alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
	return 0;
}

static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	unsigned long rtc_alarm;

	dev_dbg_stamp(dev);

	if (rtc_tm_to_time(&alrm->time, &rtc_alarm))
		return -EINVAL;

	rtc->rtc_alarm = alrm->time;

	bfin_rtc_sync_pending(dev);
	bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
	if (alrm->enabled)
		bfin_rtc_int_set_alarm(rtc);

	return 0;
}

static int bfin_rtc_proc(struct device *dev, struct seq_file *seq)
{
#define yesno(x) ((x) ? "yes" : "no")
	u16 ictl = bfin_read_RTC_ICTL();
	dev_dbg_stamp(dev);
	seq_printf(seq,
		"alarm_IRQ\t: %s\n"
		"wkalarm_IRQ\t: %s\n"
		"seconds_IRQ\t: %s\n",
		yesno(ictl & RTC_ISTAT_ALARM),
		yesno(ictl & RTC_ISTAT_ALARM_DAY),
		yesno(ictl & RTC_ISTAT_SEC));
	return 0;
#undef yesno
}

static struct rtc_class_ops bfin_rtc_ops = {
	.ioctl         = bfin_rtc_ioctl,
	.read_time     = bfin_rtc_read_time,
	.set_time      = bfin_rtc_set_time,
	.read_alarm    = bfin_rtc_read_alarm,
	.set_alarm     = bfin_rtc_set_alarm,
	.proc          = bfin_rtc_proc,
};

static int __devinit bfin_rtc_probe(struct platform_device *pdev)
{
	struct bfin_rtc *rtc;
	struct device *dev = &pdev->dev;
	int ret = 0;

	dev_dbg_stamp(dev);

	/* Allocate memory for our RTC struct */
	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
	if (unlikely(!rtc))
		return -ENOMEM;
	platform_set_drvdata(pdev, rtc);

	/* Grab the IRQ and init the hardware */
	ret = request_irq(IRQ_RTC, bfin_rtc_interrupt, IRQF_SHARED, pdev->name, dev);
	if (unlikely(ret))
		goto err;
	bfin_rtc_reset(dev, RTC_ISTAT_WRITE_COMPLETE);
	bfin_write_RTC_SWCNT(0);

	/* Register our RTC with the RTC framework */
	rtc->rtc_dev = rtc_device_register(pdev->name, dev, &bfin_rtc_ops, THIS_MODULE);
	if (unlikely(IS_ERR(rtc))) {
		ret = PTR_ERR(rtc->rtc_dev);
		goto err_irq;
	}

	device_init_wakeup(dev, 1);

	return 0;

 err_irq:
	free_irq(IRQ_RTC, dev);
 err:
	kfree(rtc);
	return ret;
}

static int __devexit bfin_rtc_remove(struct platform_device *pdev)
{
	struct bfin_rtc *rtc = platform_get_drvdata(pdev);
	struct device *dev = &pdev->dev;

	bfin_rtc_reset(dev, 0);
	free_irq(IRQ_RTC, dev);
	rtc_device_unregister(rtc->rtc_dev);
	platform_set_drvdata(pdev, NULL);
	kfree(rtc);

	return 0;
}

#ifdef CONFIG_PM
static int bfin_rtc_suspend(struct platform_device *pdev, pm_message_t state)
{
	if (device_may_wakeup(&pdev->dev)) {
		enable_irq_wake(IRQ_RTC);
		bfin_rtc_sync_pending(&pdev->dev);
	} else
		bfin_rtc_int_clear(-1);

	return 0;
}

static int bfin_rtc_resume(struct platform_device *pdev)
{
	if (device_may_wakeup(&pdev->dev))
		disable_irq_wake(IRQ_RTC);
	else
		bfin_write_RTC_ISTAT(-1);

	return 0;
}
#else
# define bfin_rtc_suspend NULL
# define bfin_rtc_resume  NULL
#endif

static struct platform_driver bfin_rtc_driver = {
	.driver		= {
		.name	= "rtc-bfin",
		.owner	= THIS_MODULE,
	},
	.probe		= bfin_rtc_probe,
	.remove		= __devexit_p(bfin_rtc_remove),
	.suspend	= bfin_rtc_suspend,
	.resume		= bfin_rtc_resume,
};

static int __init bfin_rtc_init(void)
{
	return platform_driver_register(&bfin_rtc_driver);
}

static void __exit bfin_rtc_exit(void)
{
	platform_driver_unregister(&bfin_rtc_driver);
}

module_init(bfin_rtc_init);
module_exit(bfin_rtc_exit);

MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:rtc-bfin");
Commit	Line	Data
8cc75c9a WB	1	/*
8cc75c9a WB	2	* Blackfin On-Chip Real Time Clock Driver
095b9d54	3	* Supports BF52[257]/BF53[123]/BF53[467]/BF54[24789]
8cc75c9a	4	*
813006f4	5	* Copyright 2004-2008 Analog Devices Inc.
8cc75c9a WB	6	*
	7	* Enter bugs at http://blackfin.uclinux.org/
	8	*
	9	* Licensed under the GPL-2 or later.
	10	*/
	11
	12	/* The biggest issue we deal with in this driver is that register writes are
	13	* synced to the RTC frequency of 1Hz. So if you write to a register and
	14	* attempt to write again before the first write has completed, the new write
	15	* is simply discarded. This can easily be troublesome if userspace disables
	16	* one event (say periodic) and then right after enables an event (say alarm).
	17	* Since all events are maintained in the same interrupt mask register, if
	18	* we wrote to it to disable the first event and then wrote to it again to
	19	* enable the second event, that second event would not be enabled as the
	20	* write would be discarded and things quickly fall apart.
	21	*
	22	* To keep this delay from significantly degrading performance (we, in theory,
	23	* would have to sleep for up to 1 second everytime we wanted to write a
	24	* register), we only check the write pending status before we start to issue
	25	* a new write. We bank on the idea that it doesnt matter when the sync
	26	* happens so long as we don't attempt another write before it does. The only
	27	* time userspace would take this penalty is when they try and do multiple
	28	* operations right after another ... but in this case, they need to take the
	29	* sync penalty, so we should be OK.
	30	*
	31	* Also note that the RTC_ISTAT register does not suffer this penalty; its
	32	* writes to clear status registers complete immediately.
	33	*/
	34
26cb8bb2 MF	35	/* It may seem odd that there is no SWCNT code in here (which would be exposed
	36	* via the periodic interrupt event, or PIE). Since the Blackfin RTC peripheral
	37	* runs in units of seconds (N/HZ) but the Linux framework runs in units of HZ
	38	* (2^N HZ), there is no point in keeping code that only provides 1 HZ PIEs.
	39	* The same exact behavior can be accomplished by using the update interrupt
	40	* event (UIE). Maybe down the line the RTC peripheral will suck less in which
	41	* case we can re-introduce PIE support.
	42	*/
	43
8cc75c9a	44	#include <linux/bcd.h>
095b9d54 MF	45	#include <linux/completion.h>
095b9d54 MF	46	#include <linux/delay.h>
8cc75c9a	47	#include <linux/init.h>
095b9d54 MF	48	#include <linux/interrupt.h>
	49	#include <linux/kernel.h>
	50	#include <linux/module.h>
8cc75c9a	51	#include <linux/platform_device.h>
095b9d54	52	#include <linux/rtc.h>
8cc75c9a	53	#include <linux/seq_file.h>
8cc75c9a WB	54
	55	#include <asm/blackfin.h>
	56
5438de44	57	#define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)
8cc75c9a WB	58
	59	struct bfin_rtc {
	60	struct rtc_device *rtc_dev;
	61	struct rtc_time rtc_alarm;
095b9d54	62	u16 rtc_wrote_regs;
8cc75c9a WB	63	};
	64
	65	/* Bit values for the ISTAT / ICTL registers */
	66	#define RTC_ISTAT_WRITE_COMPLETE 0x8000
	67	#define RTC_ISTAT_WRITE_PENDING 0x4000
	68	#define RTC_ISTAT_ALARM_DAY 0x0040
	69	#define RTC_ISTAT_24HR 0x0020
	70	#define RTC_ISTAT_HOUR 0x0010
	71	#define RTC_ISTAT_MIN 0x0008
	72	#define RTC_ISTAT_SEC 0x0004
	73	#define RTC_ISTAT_ALARM 0x0002
	74	#define RTC_ISTAT_STOPWATCH 0x0001
	75
	76	/* Shift values for RTC_STAT register */
	77	#define DAY_BITS_OFF 17
	78	#define HOUR_BITS_OFF 12
	79	#define MIN_BITS_OFF 6
	80	#define SEC_BITS_OFF 0
	81
	82	/* Some helper functions to convert between the common RTC notion of time
5c236343	83	* and the internal Blackfin notion that is encoded in 32bits.
8cc75c9a WB	84	*/
	85	static inline u32 rtc_time_to_bfin(unsigned long now)
	86	{
	87	u32 sec = (now % 60);
	88	u32 min = (now % (60 * 60)) / 60;
	89	u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
	90	u32 days = (now / (60 * 60 * 24));
	91	return (sec << SEC_BITS_OFF) +
	92	(min << MIN_BITS_OFF) +
	93	(hour << HOUR_BITS_OFF) +
	94	(days << DAY_BITS_OFF);
	95	}
	96	static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
	97	{
	98	return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) +
	99	(((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) +
	100	(((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
	101	(((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24);
	102	}
	103	static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
	104	{
	105	rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
	106	}
	107
095b9d54 MF	108	/**
	109	* bfin_rtc_sync_pending - make sure pending writes have complete
	110	*
	111	* Wait for the previous write to a RTC register to complete.
8cc75c9a WB	112	* Unfortunately, we can't sleep here as that introduces a race condition when
	113	* turning on interrupt events. Consider this:
	114	* - process sets alarm
	115	* - process enables alarm
	116	* - process sleeps while waiting for rtc write to sync
	117	* - interrupt fires while process is sleeping
	118	* - interrupt acks the event by writing to ISTAT
	119	* - interrupt sets the WRITE PENDING bit
	120	* - interrupt handler finishes
	121	* - process wakes up, sees WRITE PENDING bit set, goes to sleep
	122	* - interrupt fires while process is sleeping
	123	* If anyone can point out the obvious solution here, i'm listening :). This
	124	* shouldn't be an issue on an SMP or preempt system as this function should
	125	* only be called with the rtc lock held.
5c236343 MF	126	*
	127	* Other options:
	128	* - disable PREN so the sync happens at 32.768kHZ ... but this changes the
	129	* inc rate for all RTC registers from 1HZ to 32.768kHZ ...
	130	* - use the write complete IRQ
8cc75c9a	131	*/
095b9d54 MF	132	/*
095b9d54 MF	133	static void bfin_rtc_sync_pending_polled(void)
8cc75c9a	134	{
095b9d54	135	while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE))
8cc75c9a WB	136	if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
8cc75c9a WB	137	break;
8cc75c9a WB	138	bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
8cc75c9a WB	139	}
095b9d54 MF	140	*/
	141	static DECLARE_COMPLETION(bfin_write_complete);
	142	static void bfin_rtc_sync_pending(struct device *dev)
	143	{
	144	dev_dbg_stamp(dev);
	145	while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
	146	wait_for_completion_timeout(&bfin_write_complete, HZ * 5);
	147	dev_dbg_stamp(dev);
	148	}
8cc75c9a	149
095b9d54 MF	150	/**
	151	* bfin_rtc_reset - set RTC to sane/known state
	152	*
	153	* Initialize the RTC. Enable pre-scaler to scale RTC clock
	154	* to 1Hz and clear interrupt/status registers.
	155	*/
3b128fe0	156	static void bfin_rtc_reset(struct device *dev, u16 rtc_ictl)
8cc75c9a	157	{
5438de44	158	struct bfin_rtc *rtc = dev_get_drvdata(dev);
095b9d54 MF	159	dev_dbg_stamp(dev);
095b9d54 MF	160	bfin_rtc_sync_pending(dev);
8cc75c9a	161	bfin_write_RTC_PREN(0x1);
3b128fe0	162	bfin_write_RTC_ICTL(rtc_ictl);
8cc75c9a WB	163	bfin_write_RTC_ALARM(0);
8cc75c9a WB	164	bfin_write_RTC_ISTAT(0xFFFF);
095b9d54	165	rtc->rtc_wrote_regs = 0;
8cc75c9a WB	166	}
8cc75c9a WB	167
095b9d54 MF	168	/**
	169	* bfin_rtc_interrupt - handle interrupt from RTC
	170	*
	171	* Since we handle all RTC events here, we have to make sure the requested
	172	* interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT)
	173	* always gets updated regardless of the interrupt being enabled. So when one
	174	* even we care about (e.g. stopwatch) goes off, we don't want to turn around
	175	* and say that other events have happened as well (e.g. second). We do not
	176	* have to worry about pending writes to the RTC_ICTL register as interrupts
	177	* only fire if they are enabled in the RTC_ICTL register.
	178	*/
8cc75c9a WB	179	static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
8cc75c9a WB	180	{
d7827d88 MF	181	struct device *dev = dev_id;
d7827d88 MF	182	struct bfin_rtc *rtc = dev_get_drvdata(dev);
8cc75c9a	183	unsigned long events = 0;
095b9d54 MF	184	bool write_complete = false;
095b9d54 MF	185	u16 rtc_istat, rtc_ictl;
8cc75c9a	186
5438de44	187	dev_dbg_stamp(dev);
8cc75c9a	188
8cc75c9a	189	rtc_istat = bfin_read_RTC_ISTAT();
095b9d54	190	rtc_ictl = bfin_read_RTC_ICTL();
8cc75c9a	191
095b9d54 MF	192	if (rtc_istat & RTC_ISTAT_WRITE_COMPLETE) {
	193	bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
	194	write_complete = true;
	195	complete(&bfin_write_complete);
8cc75c9a WB	196	}
8cc75c9a WB	197
095b9d54 MF	198	if (rtc_ictl & (RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY)) {
	199	if (rtc_istat & (RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY)) {
	200	bfin_write_RTC_ISTAT(RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY);
	201	events \|= RTC_AF \| RTC_IRQF;
	202	}
8cc75c9a WB	203	}
8cc75c9a WB	204
095b9d54 MF	205	if (rtc_ictl & RTC_ISTAT_SEC) {
	206	if (rtc_istat & RTC_ISTAT_SEC) {
	207	bfin_write_RTC_ISTAT(RTC_ISTAT_SEC);
	208	events \|= RTC_UF \| RTC_IRQF;
	209	}
	210	}
8cc75c9a	211
095b9d54 MF	212	if (events)
095b9d54 MF	213	rtc_update_irq(rtc->rtc_dev, 1, events);
8cc75c9a	214
095b9d54 MF	215	if (write_complete \|\| events)
	216	return IRQ_HANDLED;
	217	else
	218	return IRQ_NONE;
8cc75c9a WB	219	}
8cc75c9a WB	220
605eb8b3	221	static void bfin_rtc_int_set(u16 rtc_int)
095b9d54 MF	222	{
	223	bfin_write_RTC_ISTAT(rtc_int);
	224	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() \| rtc_int);
	225	}
605eb8b3	226	static void bfin_rtc_int_clear(u16 rtc_int)
095b9d54 MF	227	{
	228	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int);
	229	}
	230	static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc)
	231	{
	232	/* Blackfin has different bits for whether the alarm is
	233	* more than 24 hours away.
	234	*/
605eb8b3	235	bfin_rtc_int_set(rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY);
095b9d54	236	}
8cc75c9a WB	237	static int bfin_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
	238	{
	239	struct bfin_rtc *rtc = dev_get_drvdata(dev);
095b9d54	240	int ret = 0;
8cc75c9a	241
5438de44	242	dev_dbg_stamp(dev);
8cc75c9a	243
095b9d54 MF	244	bfin_rtc_sync_pending(dev);
095b9d54 MF	245
8cc75c9a	246	switch (cmd) {
8cc75c9a	247	case RTC_UIE_ON:
5438de44	248	dev_dbg_stamp(dev);
605eb8b3	249	bfin_rtc_int_set(RTC_ISTAT_SEC);
095b9d54	250	break;
8cc75c9a	251	case RTC_UIE_OFF:
5438de44	252	dev_dbg_stamp(dev);
605eb8b3	253	bfin_rtc_int_clear(~RTC_ISTAT_SEC);
095b9d54	254	break;
8cc75c9a	255
095b9d54	256	case RTC_AIE_ON:
5438de44	257	dev_dbg_stamp(dev);
095b9d54 MF	258	bfin_rtc_int_set_alarm(rtc);
095b9d54 MF	259	break;
8cc75c9a	260	case RTC_AIE_OFF:
5438de44	261	dev_dbg_stamp(dev);
605eb8b3	262	bfin_rtc_int_clear(~(RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY));
095b9d54 MF	263	break;
	264
	265	default:
	266	dev_dbg_stamp(dev);
	267	ret = -ENOIOCTLCMD;
8cc75c9a WB	268	}
8cc75c9a WB	269
095b9d54	270	return ret;
8cc75c9a WB	271	}
	272
	273	static int bfin_rtc_read_time(struct device dev, struct rtc_time tm)
	274	{
	275	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	276
5438de44	277	dev_dbg_stamp(dev);
8cc75c9a	278
095b9d54 MF	279	if (rtc->rtc_wrote_regs & 0x1)
	280	bfin_rtc_sync_pending(dev);
	281
8cc75c9a	282	rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);
8cc75c9a WB	283
	284	return 0;
	285	}
	286
	287	static int bfin_rtc_set_time(struct device dev, struct rtc_time tm)
	288	{
	289	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	290	int ret;
	291	unsigned long now;
	292
5438de44	293	dev_dbg_stamp(dev);
8cc75c9a	294
8cc75c9a WB	295	ret = rtc_tm_to_time(tm, &now);
8cc75c9a WB	296	if (ret == 0) {
095b9d54 MF	297	if (rtc->rtc_wrote_regs & 0x1)
095b9d54 MF	298	bfin_rtc_sync_pending(dev);
8cc75c9a	299	bfin_write_RTC_STAT(rtc_time_to_bfin(now));
095b9d54	300	rtc->rtc_wrote_regs = 0x1;
8cc75c9a WB	301	}
8cc75c9a WB	302
8cc75c9a WB	303	return ret;
	304	}
	305
	306	static int bfin_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	307	{
	308	struct bfin_rtc *rtc = dev_get_drvdata(dev);
5438de44	309	dev_dbg_stamp(dev);
48c1a56b	310	alrm->time = rtc->rtc_alarm;
095b9d54	311	bfin_rtc_sync_pending(dev);
68db3047	312	alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY));
8cc75c9a WB	313	return 0;
	314	}
	315
	316	static int bfin_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	317	{
	318	struct bfin_rtc *rtc = dev_get_drvdata(dev);
095b9d54 MF	319	unsigned long rtc_alarm;
095b9d54 MF	320
5438de44	321	dev_dbg_stamp(dev);
095b9d54 MF	322
	323	if (rtc_tm_to_time(&alrm->time, &rtc_alarm))
	324	return -EINVAL;
	325
68db3047	326	rtc->rtc_alarm = alrm->time;
095b9d54 MF	327
	328	bfin_rtc_sync_pending(dev);
	329	bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
	330	if (alrm->enabled)
	331	bfin_rtc_int_set_alarm(rtc);
	332
8cc75c9a WB	333	return 0;
	334	}
	335
	336	static int bfin_rtc_proc(struct device dev, struct seq_file seq)
	337	{
64061160	338	#define yesno(x) ((x) ? "yes" : "no")
8cc75c9a	339	u16 ictl = bfin_read_RTC_ICTL();
5438de44	340	dev_dbg_stamp(dev);
64061160 MF	341	seq_printf(seq,
	342	"alarm_IRQ\t: %s\n"
	343	"wkalarm_IRQ\t: %s\n"
26cb8bb2	344	"seconds_IRQ\t: %s\n",
64061160 MF	345	yesno(ictl & RTC_ISTAT_ALARM),
64061160 MF	346	yesno(ictl & RTC_ISTAT_ALARM_DAY),
26cb8bb2	347	yesno(ictl & RTC_ISTAT_SEC));
8cc75c9a	348	return 0;
64061160	349	#undef yesno
8cc75c9a WB	350	}
8cc75c9a WB	351
8cc75c9a	352	static struct rtc_class_ops bfin_rtc_ops = {
8cc75c9a WB	353	.ioctl = bfin_rtc_ioctl,
	354	.read_time = bfin_rtc_read_time,
	355	.set_time = bfin_rtc_set_time,
	356	.read_alarm = bfin_rtc_read_alarm,
	357	.set_alarm = bfin_rtc_set_alarm,
	358	.proc = bfin_rtc_proc,
8cc75c9a WB	359	};
	360
	361	static int __devinit bfin_rtc_probe(struct platform_device *pdev)
	362	{
	363	struct bfin_rtc *rtc;
fe2e1cf8	364	struct device *dev = &pdev->dev;
8cc75c9a WB	365	int ret = 0;
8cc75c9a WB	366
fe2e1cf8	367	dev_dbg_stamp(dev);
8cc75c9a	368
fe2e1cf8	369	/* Allocate memory for our RTC struct */
8cc75c9a WB	370	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
	371	if (unlikely(!rtc))
	372	return -ENOMEM;
fe2e1cf8	373	platform_set_drvdata(pdev, rtc);
8cc75c9a	374
fe2e1cf8 MF	375	/* Grab the IRQ and init the hardware */
	376	ret = request_irq(IRQ_RTC, bfin_rtc_interrupt, IRQF_SHARED, pdev->name, dev);
	377	if (unlikely(ret))
8cc75c9a	378	goto err;
fe2e1cf8	379	bfin_rtc_reset(dev, RTC_ISTAT_WRITE_COMPLETE);
26cb8bb2	380	bfin_write_RTC_SWCNT(0);
8cc75c9a	381
fe2e1cf8 MF	382	/* Register our RTC with the RTC framework */
	383	rtc->rtc_dev = rtc_device_register(pdev->name, dev, &bfin_rtc_ops, THIS_MODULE);
	384	if (unlikely(IS_ERR(rtc))) {
	385	ret = PTR_ERR(rtc->rtc_dev);
	386	goto err_irq;
	387	}
8cc75c9a	388
fe2e1cf8	389	device_init_wakeup(dev, 1);
813006f4	390
8cc75c9a WB	391	return 0;
8cc75c9a WB	392
fe2e1cf8 MF	393	err_irq:
fe2e1cf8 MF	394	free_irq(IRQ_RTC, dev);
5c236343	395	err:
8cc75c9a WB	396	kfree(rtc);
	397	return ret;
	398	}
	399
	400	static int __devexit bfin_rtc_remove(struct platform_device *pdev)
	401	{
	402	struct bfin_rtc *rtc = platform_get_drvdata(pdev);
fe2e1cf8	403	struct device *dev = &pdev->dev;
8cc75c9a	404
fe2e1cf8 MF	405	bfin_rtc_reset(dev, 0);
fe2e1cf8 MF	406	free_irq(IRQ_RTC, dev);
8cc75c9a WB	407	rtc_device_unregister(rtc->rtc_dev);
	408	platform_set_drvdata(pdev, NULL);
	409	kfree(rtc);
	410
	411	return 0;
	412	}
	413
5aeb776d SZ	414	#ifdef CONFIG_PM
	415	static int bfin_rtc_suspend(struct platform_device *pdev, pm_message_t state)
	416	{
140fab14	417	if (device_may_wakeup(&pdev->dev)) {
813006f4	418	enable_irq_wake(IRQ_RTC);
140fab14 MF	419	bfin_rtc_sync_pending(&pdev->dev);
140fab14 MF	420	} else
605eb8b3	421	bfin_rtc_int_clear(-1);
813006f4	422
5aeb776d SZ	423	return 0;
	424	}
	425
	426	static int bfin_rtc_resume(struct platform_device *pdev)
	427	{
813006f4 MF	428	if (device_may_wakeup(&pdev->dev))
	429	disable_irq_wake(IRQ_RTC);
	430	else
	431	bfin_write_RTC_ISTAT(-1);
	432
5aeb776d SZ	433	return 0;
5aeb776d SZ	434	}
813006f4 MF	435	#else
	436	# define bfin_rtc_suspend NULL
	437	# define bfin_rtc_resume NULL
5aeb776d SZ	438	#endif
5aeb776d SZ	439
8cc75c9a WB	440	static struct platform_driver bfin_rtc_driver = {
	441	.driver = {
	442	.name = "rtc-bfin",
	443	.owner = THIS_MODULE,
	444	},
	445	.probe = bfin_rtc_probe,
	446	.remove = __devexit_p(bfin_rtc_remove),
5aeb776d SZ	447	.suspend = bfin_rtc_suspend,
5aeb776d SZ	448	.resume = bfin_rtc_resume,
8cc75c9a WB	449	};
	450
	451	static int __init bfin_rtc_init(void)
	452	{
8cc75c9a WB	453	return platform_driver_register(&bfin_rtc_driver);
	454	}
	455
	456	static void __exit bfin_rtc_exit(void)
	457	{
	458	platform_driver_unregister(&bfin_rtc_driver);
	459	}
	460
	461	module_init(bfin_rtc_init);
	462	module_exit(bfin_rtc_exit);
	463
	464	MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
	465	MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
	466	MODULE_LICENSE("GPL");
ad28a07b	467	MODULE_ALIAS("platform:rtc-bfin");