[net-next-2.6.git] / drivers / rtc / rtc-bfin.c

/*
 * Blackfin On-Chip Real Time Clock Driver
 *  Supports BF52[257]/BF53[123]/BF53[467]/BF54[24789]
 *
 * Copyright 2004-2007 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

/* The biggest issue we deal with in this driver is that register writes are
 * synced to the RTC frequency of 1Hz.  So if you write to a register and
 * attempt to write again before the first write has completed, the new write
 * is simply discarded.  This can easily be troublesome if userspace disables
 * one event (say periodic) and then right after enables an event (say alarm).
 * Since all events are maintained in the same interrupt mask register, if
 * we wrote to it to disable the first event and then wrote to it again to
 * enable the second event, that second event would not be enabled as the
 * write would be discarded and things quickly fall apart.
 *
 * To keep this delay from significantly degrading performance (we, in theory,
 * would have to sleep for up to 1 second everytime we wanted to write a
 * register), we only check the write pending status before we start to issue
 * a new write.  We bank on the idea that it doesnt matter when the sync
 * happens so long as we don't attempt another write before it does.  The only
 * time userspace would take this penalty is when they try and do multiple
 * operations right after another ... but in this case, they need to take the
 * sync penalty, so we should be OK.
 *
 * Also note that the RTC_ISTAT register does not suffer this penalty; its
 * writes to clear status registers complete immediately.
 */

#include <linux/bcd.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/seq_file.h>

#include <asm/blackfin.h>

#define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)

struct bfin_rtc {
	struct rtc_device *rtc_dev;
	struct rtc_time rtc_alarm;
	u16 rtc_wrote_regs;
};

/* Bit values for the ISTAT / ICTL registers */
#define RTC_ISTAT_WRITE_COMPLETE  0x8000
#define RTC_ISTAT_WRITE_PENDING   0x4000
#define RTC_ISTAT_ALARM_DAY       0x0040
#define RTC_ISTAT_24HR            0x0020
#define RTC_ISTAT_HOUR            0x0010
#define RTC_ISTAT_MIN             0x0008
#define RTC_ISTAT_SEC             0x0004
#define RTC_ISTAT_ALARM           0x0002
#define RTC_ISTAT_STOPWATCH       0x0001

/* Shift values for RTC_STAT register */
#define DAY_BITS_OFF    17
#define HOUR_BITS_OFF   12
#define MIN_BITS_OFF    6
#define SEC_BITS_OFF    0

/* Some helper functions to convert between the common RTC notion of time
 * and the internal Blackfin notion that is encoded in 32bits.
 */
static inline u32 rtc_time_to_bfin(unsigned long now)
{
	u32 sec  = (now % 60);
	u32 min  = (now % (60 * 60)) / 60;
	u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
	u32 days = (now / (60 * 60 * 24));
	return (sec  << SEC_BITS_OFF) +
	       (min  << MIN_BITS_OFF) +
	       (hour << HOUR_BITS_OFF) +
	       (days << DAY_BITS_OFF);
}
static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
{
	return (((rtc_bfin >> SEC_BITS_OFF)  & 0x003F)) +
	       (((rtc_bfin >> MIN_BITS_OFF)  & 0x003F) * 60) +
	       (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
	       (((rtc_bfin >> DAY_BITS_OFF)  & 0x7FFF) * 60 * 60 * 24);
}
static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
{
	rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
}

/**
 *	bfin_rtc_sync_pending - make sure pending writes have complete
 *
 * Wait for the previous write to a RTC register to complete.
 * Unfortunately, we can't sleep here as that introduces a race condition when
 * turning on interrupt events.  Consider this:
 *  - process sets alarm
 *  - process enables alarm
 *  - process sleeps while waiting for rtc write to sync
 *  - interrupt fires while process is sleeping
 *  - interrupt acks the event by writing to ISTAT
 *  - interrupt sets the WRITE PENDING bit
 *  - interrupt handler finishes
 *  - process wakes up, sees WRITE PENDING bit set, goes to sleep
 *  - interrupt fires while process is sleeping
 * If anyone can point out the obvious solution here, i'm listening :).  This
 * shouldn't be an issue on an SMP or preempt system as this function should
 * only be called with the rtc lock held.
 *
 * Other options:
 *  - disable PREN so the sync happens at 32.768kHZ ... but this changes the
 *    inc rate for all RTC registers from 1HZ to 32.768kHZ ...
 *  - use the write complete IRQ
 */
/*
static void bfin_rtc_sync_pending_polled(void)
{
	while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE))
		if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
			break;
	bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
}
*/
static DECLARE_COMPLETION(bfin_write_complete);
static void bfin_rtc_sync_pending(struct device *dev)
{
	dev_dbg_stamp(dev);
	while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
		wait_for_completion_timeout(&bfin_write_complete, HZ * 5);
	dev_dbg_stamp(dev);
}

/**
 *	bfin_rtc_reset - set RTC to sane/known state
 *
 * Initialize the RTC.  Enable pre-scaler to scale RTC clock
 * to 1Hz and clear interrupt/status registers.
 */
static void bfin_rtc_reset(struct device *dev)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	dev_dbg_stamp(dev);
	bfin_rtc_sync_pending(dev);
	bfin_write_RTC_PREN(0x1);
	bfin_write_RTC_ICTL(RTC_ISTAT_WRITE_COMPLETE);
	bfin_write_RTC_SWCNT(0);
	bfin_write_RTC_ALARM(0);
	bfin_write_RTC_ISTAT(0xFFFF);
	rtc->rtc_wrote_regs = 0;
}

/**
 *	bfin_rtc_interrupt - handle interrupt from RTC
 *
 * Since we handle all RTC events here, we have to make sure the requested
 * interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT)
 * always gets updated regardless of the interrupt being enabled.  So when one
 * even we care about (e.g. stopwatch) goes off, we don't want to turn around
 * and say that other events have happened as well (e.g. second).  We do not
 * have to worry about pending writes to the RTC_ICTL register as interrupts
 * only fire if they are enabled in the RTC_ICTL register.
 */
static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
{
	struct device *dev = dev_id;
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	unsigned long events = 0;
	bool write_complete = false;
	u16 rtc_istat, rtc_ictl;

	dev_dbg_stamp(dev);

	rtc_istat = bfin_read_RTC_ISTAT();
	rtc_ictl = bfin_read_RTC_ICTL();

	if (rtc_istat & RTC_ISTAT_WRITE_COMPLETE) {
		bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
		write_complete = true;
		complete(&bfin_write_complete);
	}

	if (rtc_ictl & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) {
		if (rtc_istat & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) {
			bfin_write_RTC_ISTAT(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY);
			events |= RTC_AF | RTC_IRQF;
		}
	}

	if (rtc_ictl & RTC_ISTAT_STOPWATCH) {
		if (rtc_istat & RTC_ISTAT_STOPWATCH) {
			bfin_write_RTC_ISTAT(RTC_ISTAT_STOPWATCH);
			events |= RTC_PF | RTC_IRQF;
			bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq);
		}
	}

	if (rtc_ictl & RTC_ISTAT_SEC) {
		if (rtc_istat & RTC_ISTAT_SEC) {
			bfin_write_RTC_ISTAT(RTC_ISTAT_SEC);
			events |= RTC_UF | RTC_IRQF;
		}
	}

	if (events)
		rtc_update_irq(rtc->rtc_dev, 1, events);

	if (write_complete || events)
		return IRQ_HANDLED;
	else
		return IRQ_NONE;
}

static int bfin_rtc_open(struct device *dev)
{
	int ret;

	dev_dbg_stamp(dev);

	ret = request_irq(IRQ_RTC, bfin_rtc_interrupt, IRQF_SHARED, to_platform_device(dev)->name, dev);
	if (!ret)
		bfin_rtc_reset(dev);

	return ret;
}

static void bfin_rtc_release(struct device *dev)
{
	dev_dbg_stamp(dev);
	bfin_rtc_reset(dev);
	free_irq(IRQ_RTC, dev);
}

static void bfin_rtc_int_set(struct bfin_rtc *rtc, u16 rtc_int)
{
	bfin_write_RTC_ISTAT(rtc_int);
	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | rtc_int);
}
static void bfin_rtc_int_clear(struct bfin_rtc *rtc, u16 rtc_int)
{
	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int);
}
static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc)
{
	/* Blackfin has different bits for whether the alarm is
	 * more than 24 hours away.
	 */
	bfin_rtc_int_set(rtc, (rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY));
}
static int bfin_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	int ret = 0;

	dev_dbg_stamp(dev);

	bfin_rtc_sync_pending(dev);

	switch (cmd) {
	case RTC_PIE_ON:
		dev_dbg_stamp(dev);
		bfin_rtc_int_set(rtc, RTC_ISTAT_STOPWATCH);
		bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq);
		break;
	case RTC_PIE_OFF:
		dev_dbg_stamp(dev);
		bfin_rtc_int_clear(rtc, ~RTC_ISTAT_STOPWATCH);
		break;

	case RTC_UIE_ON:
		dev_dbg_stamp(dev);
		bfin_rtc_int_set(rtc, RTC_ISTAT_SEC);
		break;
	case RTC_UIE_OFF:
		dev_dbg_stamp(dev);
		bfin_rtc_int_clear(rtc, ~RTC_ISTAT_SEC);
		break;

	case RTC_AIE_ON:
		dev_dbg_stamp(dev);
		bfin_rtc_int_set_alarm(rtc);
		break;
	case RTC_AIE_OFF:
		dev_dbg_stamp(dev);
		bfin_rtc_int_clear(rtc, ~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
		break;

	default:
		dev_dbg_stamp(dev);
		ret = -ENOIOCTLCMD;
	}

	return ret;
}

static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);

	dev_dbg_stamp(dev);

	if (rtc->rtc_wrote_regs & 0x1)
		bfin_rtc_sync_pending(dev);

	rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);

	return 0;
}

static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	int ret;
	unsigned long now;

	dev_dbg_stamp(dev);

	ret = rtc_tm_to_time(tm, &now);
	if (ret == 0) {
		if (rtc->rtc_wrote_regs & 0x1)
			bfin_rtc_sync_pending(dev);
		bfin_write_RTC_STAT(rtc_time_to_bfin(now));
		rtc->rtc_wrote_regs = 0x1;
	}

	return ret;
}

static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	dev_dbg_stamp(dev);
	alrm->time = rtc->rtc_alarm;
	bfin_rtc_sync_pending(dev);
	alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
	return 0;
}

static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	unsigned long rtc_alarm;

	dev_dbg_stamp(dev);

	if (rtc_tm_to_time(&alrm->time, &rtc_alarm))
		return -EINVAL;

	rtc->rtc_alarm = alrm->time;

	bfin_rtc_sync_pending(dev);
	bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
	if (alrm->enabled)
		bfin_rtc_int_set_alarm(rtc);

	return 0;
}

static int bfin_rtc_proc(struct device *dev, struct seq_file *seq)
{
#define yesno(x) ((x) ? "yes" : "no")
	u16 ictl = bfin_read_RTC_ICTL();
	dev_dbg_stamp(dev);
	seq_printf(seq,
		"alarm_IRQ\t: %s\n"
		"wkalarm_IRQ\t: %s\n"
		"seconds_IRQ\t: %s\n"
		"periodic_IRQ\t: %s\n",
		yesno(ictl & RTC_ISTAT_ALARM),
		yesno(ictl & RTC_ISTAT_ALARM_DAY),
		yesno(ictl & RTC_ISTAT_SEC),
		yesno(ictl & RTC_ISTAT_STOPWATCH));
	return 0;
#undef yesno
}

/**
 *	bfin_irq_set_freq - make sure hardware supports requested freq
 *	@dev: pointer to RTC device structure
 *	@freq: requested frequency rate
 *
 *	The Blackfin RTC can only generate periodic events at 1 per
 *	second (1 Hz), so reject any attempt at changing it.
 */
static int bfin_irq_set_freq(struct device *dev, int freq)
{
	dev_dbg_stamp(dev);
	return -ENOTTY;
}

static struct rtc_class_ops bfin_rtc_ops = {
	.open          = bfin_rtc_open,
	.release       = bfin_rtc_release,
	.ioctl         = bfin_rtc_ioctl,
	.read_time     = bfin_rtc_read_time,
	.set_time      = bfin_rtc_set_time,
	.read_alarm    = bfin_rtc_read_alarm,
	.set_alarm     = bfin_rtc_set_alarm,
	.proc          = bfin_rtc_proc,
	.irq_set_freq  = bfin_irq_set_freq,
};

static int __devinit bfin_rtc_probe(struct platform_device *pdev)
{
	struct bfin_rtc *rtc;
	int ret = 0;

	dev_dbg_stamp(&pdev->dev);

	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
	if (unlikely(!rtc))
		return -ENOMEM;

	rtc->rtc_dev = rtc_device_register(pdev->name, &pdev->dev, &bfin_rtc_ops, THIS_MODULE);
	if (unlikely(IS_ERR(rtc))) {
		ret = PTR_ERR(rtc->rtc_dev);
		goto err;
	}
	rtc->rtc_dev->irq_freq = 1;

	platform_set_drvdata(pdev, rtc);

	return 0;

 err:
	kfree(rtc);
	return ret;
}

static int __devexit bfin_rtc_remove(struct platform_device *pdev)
{
	struct bfin_rtc *rtc = platform_get_drvdata(pdev);

	rtc_device_unregister(rtc->rtc_dev);
	platform_set_drvdata(pdev, NULL);
	kfree(rtc);

	return 0;
}

static struct platform_driver bfin_rtc_driver = {
	.driver		= {
		.name	= "rtc-bfin",
		.owner	= THIS_MODULE,
	},
	.probe		= bfin_rtc_probe,
	.remove		= __devexit_p(bfin_rtc_remove),
};

static int __init bfin_rtc_init(void)
{
	return platform_driver_register(&bfin_rtc_driver);
}

static void __exit bfin_rtc_exit(void)
{
	platform_driver_unregister(&bfin_rtc_driver);
}

module_init(bfin_rtc_init);
module_exit(bfin_rtc_exit);

MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
8cc75c9a WB	1	/*
8cc75c9a WB	2	* Blackfin On-Chip Real Time Clock Driver
095b9d54	3	* Supports BF52[257]/BF53[123]/BF53[467]/BF54[24789]
8cc75c9a WB	4	*
	5	* Copyright 2004-2007 Analog Devices Inc.
	6	*
	7	* Enter bugs at http://blackfin.uclinux.org/
	8	*
	9	* Licensed under the GPL-2 or later.
	10	*/
	11
	12	/* The biggest issue we deal with in this driver is that register writes are
	13	* synced to the RTC frequency of 1Hz. So if you write to a register and
	14	* attempt to write again before the first write has completed, the new write
	15	* is simply discarded. This can easily be troublesome if userspace disables
	16	* one event (say periodic) and then right after enables an event (say alarm).
	17	* Since all events are maintained in the same interrupt mask register, if
	18	* we wrote to it to disable the first event and then wrote to it again to
	19	* enable the second event, that second event would not be enabled as the
	20	* write would be discarded and things quickly fall apart.
	21	*
	22	* To keep this delay from significantly degrading performance (we, in theory,
	23	* would have to sleep for up to 1 second everytime we wanted to write a
	24	* register), we only check the write pending status before we start to issue
	25	* a new write. We bank on the idea that it doesnt matter when the sync
	26	* happens so long as we don't attempt another write before it does. The only
	27	* time userspace would take this penalty is when they try and do multiple
	28	* operations right after another ... but in this case, they need to take the
	29	* sync penalty, so we should be OK.
	30	*
	31	* Also note that the RTC_ISTAT register does not suffer this penalty; its
	32	* writes to clear status registers complete immediately.
	33	*/
	34
8cc75c9a	35	#include <linux/bcd.h>
095b9d54 MF	36	#include <linux/completion.h>
095b9d54 MF	37	#include <linux/delay.h>
8cc75c9a	38	#include <linux/init.h>
095b9d54 MF	39	#include <linux/interrupt.h>
	40	#include <linux/kernel.h>
	41	#include <linux/module.h>
8cc75c9a	42	#include <linux/platform_device.h>
095b9d54	43	#include <linux/rtc.h>
8cc75c9a	44	#include <linux/seq_file.h>
8cc75c9a WB	45
	46	#include <asm/blackfin.h>
	47
5438de44	48	#define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)
8cc75c9a WB	49
	50	struct bfin_rtc {
	51	struct rtc_device *rtc_dev;
	52	struct rtc_time rtc_alarm;
095b9d54	53	u16 rtc_wrote_regs;
8cc75c9a WB	54	};
	55
	56	/* Bit values for the ISTAT / ICTL registers */
	57	#define RTC_ISTAT_WRITE_COMPLETE 0x8000
	58	#define RTC_ISTAT_WRITE_PENDING 0x4000
	59	#define RTC_ISTAT_ALARM_DAY 0x0040
	60	#define RTC_ISTAT_24HR 0x0020
	61	#define RTC_ISTAT_HOUR 0x0010
	62	#define RTC_ISTAT_MIN 0x0008
	63	#define RTC_ISTAT_SEC 0x0004
	64	#define RTC_ISTAT_ALARM 0x0002
	65	#define RTC_ISTAT_STOPWATCH 0x0001
	66
	67	/* Shift values for RTC_STAT register */
	68	#define DAY_BITS_OFF 17
	69	#define HOUR_BITS_OFF 12
	70	#define MIN_BITS_OFF 6
	71	#define SEC_BITS_OFF 0
	72
	73	/* Some helper functions to convert between the common RTC notion of time
5c236343	74	* and the internal Blackfin notion that is encoded in 32bits.
8cc75c9a WB	75	*/
	76	static inline u32 rtc_time_to_bfin(unsigned long now)
	77	{
	78	u32 sec = (now % 60);
	79	u32 min = (now % (60 * 60)) / 60;
	80	u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
	81	u32 days = (now / (60 * 60 * 24));
	82	return (sec << SEC_BITS_OFF) +
	83	(min << MIN_BITS_OFF) +
	84	(hour << HOUR_BITS_OFF) +
	85	(days << DAY_BITS_OFF);
	86	}
	87	static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
	88	{
	89	return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) +
	90	(((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) +
	91	(((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
	92	(((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24);
	93	}
	94	static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
	95	{
	96	rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
	97	}
	98
095b9d54 MF	99	/**
	100	* bfin_rtc_sync_pending - make sure pending writes have complete
	101	*
	102	* Wait for the previous write to a RTC register to complete.
8cc75c9a WB	103	* Unfortunately, we can't sleep here as that introduces a race condition when
	104	* turning on interrupt events. Consider this:
	105	* - process sets alarm
	106	* - process enables alarm
	107	* - process sleeps while waiting for rtc write to sync
	108	* - interrupt fires while process is sleeping
	109	* - interrupt acks the event by writing to ISTAT
	110	* - interrupt sets the WRITE PENDING bit
	111	* - interrupt handler finishes
	112	* - process wakes up, sees WRITE PENDING bit set, goes to sleep
	113	* - interrupt fires while process is sleeping
	114	* If anyone can point out the obvious solution here, i'm listening :). This
	115	* shouldn't be an issue on an SMP or preempt system as this function should
	116	* only be called with the rtc lock held.
5c236343 MF	117	*
	118	* Other options:
	119	* - disable PREN so the sync happens at 32.768kHZ ... but this changes the
	120	* inc rate for all RTC registers from 1HZ to 32.768kHZ ...
	121	* - use the write complete IRQ
8cc75c9a	122	*/
095b9d54 MF	123	/*
095b9d54 MF	124	static void bfin_rtc_sync_pending_polled(void)
8cc75c9a	125	{
095b9d54	126	while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE))
8cc75c9a WB	127	if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
8cc75c9a WB	128	break;
8cc75c9a WB	129	bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
8cc75c9a WB	130	}
095b9d54 MF	131	*/
	132	static DECLARE_COMPLETION(bfin_write_complete);
	133	static void bfin_rtc_sync_pending(struct device *dev)
	134	{
	135	dev_dbg_stamp(dev);
	136	while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
	137	wait_for_completion_timeout(&bfin_write_complete, HZ * 5);
	138	dev_dbg_stamp(dev);
	139	}
8cc75c9a	140
095b9d54 MF	141	/**
	142	* bfin_rtc_reset - set RTC to sane/known state
	143	*
	144	* Initialize the RTC. Enable pre-scaler to scale RTC clock
	145	* to 1Hz and clear interrupt/status registers.
	146	*/
	147	static void bfin_rtc_reset(struct device *dev)
8cc75c9a	148	{
5438de44	149	struct bfin_rtc *rtc = dev_get_drvdata(dev);
095b9d54 MF	150	dev_dbg_stamp(dev);
095b9d54 MF	151	bfin_rtc_sync_pending(dev);
8cc75c9a	152	bfin_write_RTC_PREN(0x1);
095b9d54	153	bfin_write_RTC_ICTL(RTC_ISTAT_WRITE_COMPLETE);
8cc75c9a WB	154	bfin_write_RTC_SWCNT(0);
	155	bfin_write_RTC_ALARM(0);
	156	bfin_write_RTC_ISTAT(0xFFFF);
095b9d54	157	rtc->rtc_wrote_regs = 0;
8cc75c9a WB	158	}
8cc75c9a WB	159
095b9d54 MF	160	/**
	161	* bfin_rtc_interrupt - handle interrupt from RTC
	162	*
	163	* Since we handle all RTC events here, we have to make sure the requested
	164	* interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT)
	165	* always gets updated regardless of the interrupt being enabled. So when one
	166	* even we care about (e.g. stopwatch) goes off, we don't want to turn around
	167	* and say that other events have happened as well (e.g. second). We do not
	168	* have to worry about pending writes to the RTC_ICTL register as interrupts
	169	* only fire if they are enabled in the RTC_ICTL register.
	170	*/
8cc75c9a WB	171	static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
8cc75c9a WB	172	{
d7827d88 MF	173	struct device *dev = dev_id;
d7827d88 MF	174	struct bfin_rtc *rtc = dev_get_drvdata(dev);
8cc75c9a	175	unsigned long events = 0;
095b9d54 MF	176	bool write_complete = false;
095b9d54 MF	177	u16 rtc_istat, rtc_ictl;
8cc75c9a	178
5438de44	179	dev_dbg_stamp(dev);
8cc75c9a	180
8cc75c9a	181	rtc_istat = bfin_read_RTC_ISTAT();
095b9d54	182	rtc_ictl = bfin_read_RTC_ICTL();
8cc75c9a	183
095b9d54 MF	184	if (rtc_istat & RTC_ISTAT_WRITE_COMPLETE) {
	185	bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
	186	write_complete = true;
	187	complete(&bfin_write_complete);
8cc75c9a WB	188	}
8cc75c9a WB	189
095b9d54 MF	190	if (rtc_ictl & (RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY)) {
	191	if (rtc_istat & (RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY)) {
	192	bfin_write_RTC_ISTAT(RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY);
	193	events \|= RTC_AF \| RTC_IRQF;
	194	}
8cc75c9a WB	195	}
8cc75c9a WB	196
095b9d54 MF	197	if (rtc_ictl & RTC_ISTAT_STOPWATCH) {
	198	if (rtc_istat & RTC_ISTAT_STOPWATCH) {
	199	bfin_write_RTC_ISTAT(RTC_ISTAT_STOPWATCH);
	200	events \|= RTC_PF \| RTC_IRQF;
	201	bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq);
	202	}
8cc75c9a WB	203	}
8cc75c9a WB	204
095b9d54 MF	205	if (rtc_ictl & RTC_ISTAT_SEC) {
	206	if (rtc_istat & RTC_ISTAT_SEC) {
	207	bfin_write_RTC_ISTAT(RTC_ISTAT_SEC);
	208	events \|= RTC_UF \| RTC_IRQF;
	209	}
	210	}
8cc75c9a	211
095b9d54 MF	212	if (events)
095b9d54 MF	213	rtc_update_irq(rtc->rtc_dev, 1, events);
8cc75c9a	214
095b9d54 MF	215	if (write_complete \|\| events)
	216	return IRQ_HANDLED;
	217	else
	218	return IRQ_NONE;
8cc75c9a WB	219	}
	220
	221	static int bfin_rtc_open(struct device *dev)
	222	{
8cc75c9a WB	223	int ret;
8cc75c9a WB	224
5438de44	225	dev_dbg_stamp(dev);
8cc75c9a	226
095b9d54 MF	227	ret = request_irq(IRQ_RTC, bfin_rtc_interrupt, IRQF_SHARED, to_platform_device(dev)->name, dev);
	228	if (!ret)
	229	bfin_rtc_reset(dev);
8cc75c9a WB	230
	231	return ret;
	232	}
	233
	234	static void bfin_rtc_release(struct device *dev)
	235	{
5438de44	236	dev_dbg_stamp(dev);
095b9d54	237	bfin_rtc_reset(dev);
8cc75c9a WB	238	free_irq(IRQ_RTC, dev);
	239	}
	240
095b9d54 MF	241	static void bfin_rtc_int_set(struct bfin_rtc *rtc, u16 rtc_int)
	242	{
	243	bfin_write_RTC_ISTAT(rtc_int);
	244	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() \| rtc_int);
	245	}
	246	static void bfin_rtc_int_clear(struct bfin_rtc *rtc, u16 rtc_int)
	247	{
	248	bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int);
	249	}
	250	static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc)
	251	{
	252	/* Blackfin has different bits for whether the alarm is
	253	* more than 24 hours away.
	254	*/
	255	bfin_rtc_int_set(rtc, (rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY));
	256	}
8cc75c9a WB	257	static int bfin_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
	258	{
	259	struct bfin_rtc *rtc = dev_get_drvdata(dev);
095b9d54	260	int ret = 0;
8cc75c9a	261
5438de44	262	dev_dbg_stamp(dev);
8cc75c9a	263
095b9d54 MF	264	bfin_rtc_sync_pending(dev);
095b9d54 MF	265
8cc75c9a WB	266	switch (cmd) {
8cc75c9a WB	267	case RTC_PIE_ON:
5438de44	268	dev_dbg_stamp(dev);
095b9d54	269	bfin_rtc_int_set(rtc, RTC_ISTAT_STOPWATCH);
8cc75c9a	270	bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq);
095b9d54	271	break;
8cc75c9a	272	case RTC_PIE_OFF:
5438de44	273	dev_dbg_stamp(dev);
095b9d54 MF	274	bfin_rtc_int_clear(rtc, ~RTC_ISTAT_STOPWATCH);
095b9d54 MF	275	break;
8cc75c9a WB	276
8cc75c9a WB	277	case RTC_UIE_ON:
5438de44	278	dev_dbg_stamp(dev);
095b9d54 MF	279	bfin_rtc_int_set(rtc, RTC_ISTAT_SEC);
095b9d54 MF	280	break;
8cc75c9a	281	case RTC_UIE_OFF:
5438de44	282	dev_dbg_stamp(dev);
095b9d54 MF	283	bfin_rtc_int_clear(rtc, ~RTC_ISTAT_SEC);
095b9d54 MF	284	break;
8cc75c9a	285
095b9d54	286	case RTC_AIE_ON:
5438de44	287	dev_dbg_stamp(dev);
095b9d54 MF	288	bfin_rtc_int_set_alarm(rtc);
095b9d54 MF	289	break;
8cc75c9a	290	case RTC_AIE_OFF:
5438de44	291	dev_dbg_stamp(dev);
095b9d54 MF	292	bfin_rtc_int_clear(rtc, ~(RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY));
	293	break;
	294
	295	default:
	296	dev_dbg_stamp(dev);
	297	ret = -ENOIOCTLCMD;
8cc75c9a WB	298	}
8cc75c9a WB	299
095b9d54	300	return ret;
8cc75c9a WB	301	}
	302
	303	static int bfin_rtc_read_time(struct device dev, struct rtc_time tm)
	304	{
	305	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	306
5438de44	307	dev_dbg_stamp(dev);
8cc75c9a	308
095b9d54 MF	309	if (rtc->rtc_wrote_regs & 0x1)
	310	bfin_rtc_sync_pending(dev);
	311
8cc75c9a	312	rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);
8cc75c9a WB	313
	314	return 0;
	315	}
	316
	317	static int bfin_rtc_set_time(struct device dev, struct rtc_time tm)
	318	{
	319	struct bfin_rtc *rtc = dev_get_drvdata(dev);
	320	int ret;
	321	unsigned long now;
	322
5438de44	323	dev_dbg_stamp(dev);
8cc75c9a	324
8cc75c9a WB	325	ret = rtc_tm_to_time(tm, &now);
8cc75c9a WB	326	if (ret == 0) {
095b9d54 MF	327	if (rtc->rtc_wrote_regs & 0x1)
095b9d54 MF	328	bfin_rtc_sync_pending(dev);
8cc75c9a	329	bfin_write_RTC_STAT(rtc_time_to_bfin(now));
095b9d54	330	rtc->rtc_wrote_regs = 0x1;
8cc75c9a WB	331	}
8cc75c9a WB	332
8cc75c9a WB	333	return ret;
	334	}
	335
	336	static int bfin_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	337	{
	338	struct bfin_rtc *rtc = dev_get_drvdata(dev);
5438de44	339	dev_dbg_stamp(dev);
48c1a56b	340	alrm->time = rtc->rtc_alarm;
095b9d54	341	bfin_rtc_sync_pending(dev);
68db3047	342	alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM \| RTC_ISTAT_ALARM_DAY));
8cc75c9a WB	343	return 0;
	344	}
	345
	346	static int bfin_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	347	{
	348	struct bfin_rtc *rtc = dev_get_drvdata(dev);
095b9d54 MF	349	unsigned long rtc_alarm;
095b9d54 MF	350
5438de44	351	dev_dbg_stamp(dev);
095b9d54 MF	352
	353	if (rtc_tm_to_time(&alrm->time, &rtc_alarm))
	354	return -EINVAL;
	355
68db3047	356	rtc->rtc_alarm = alrm->time;
095b9d54 MF	357
	358	bfin_rtc_sync_pending(dev);
	359	bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
	360	if (alrm->enabled)
	361	bfin_rtc_int_set_alarm(rtc);
	362
8cc75c9a WB	363	return 0;
	364	}
	365
	366	static int bfin_rtc_proc(struct device dev, struct seq_file seq)
	367	{
64061160	368	#define yesno(x) ((x) ? "yes" : "no")
8cc75c9a	369	u16 ictl = bfin_read_RTC_ICTL();
5438de44	370	dev_dbg_stamp(dev);
64061160 MF	371	seq_printf(seq,
	372	"alarm_IRQ\t: %s\n"
	373	"wkalarm_IRQ\t: %s\n"
	374	"seconds_IRQ\t: %s\n"
	375	"periodic_IRQ\t: %s\n",
	376	yesno(ictl & RTC_ISTAT_ALARM),
	377	yesno(ictl & RTC_ISTAT_ALARM_DAY),
	378	yesno(ictl & RTC_ISTAT_SEC),
	379	yesno(ictl & RTC_ISTAT_STOPWATCH));
8cc75c9a	380	return 0;
64061160	381	#undef yesno
8cc75c9a WB	382	}
8cc75c9a WB	383
5c236343 MF	384	/**
	385	* bfin_irq_set_freq - make sure hardware supports requested freq
	386	* @dev: pointer to RTC device structure
	387	* @freq: requested frequency rate
	388	*
	389	* The Blackfin RTC can only generate periodic events at 1 per
	390	* second (1 Hz), so reject any attempt at changing it.
	391	*/
8cc75c9a WB	392	static int bfin_irq_set_freq(struct device *dev, int freq)
8cc75c9a WB	393	{
5438de44	394	dev_dbg_stamp(dev);
5c236343	395	return -ENOTTY;
8cc75c9a WB	396	}
	397
	398	static struct rtc_class_ops bfin_rtc_ops = {
	399	.open = bfin_rtc_open,
	400	.release = bfin_rtc_release,
	401	.ioctl = bfin_rtc_ioctl,
	402	.read_time = bfin_rtc_read_time,
	403	.set_time = bfin_rtc_set_time,
	404	.read_alarm = bfin_rtc_read_alarm,
	405	.set_alarm = bfin_rtc_set_alarm,
	406	.proc = bfin_rtc_proc,
	407	.irq_set_freq = bfin_irq_set_freq,
	408	};
	409
	410	static int __devinit bfin_rtc_probe(struct platform_device *pdev)
	411	{
	412	struct bfin_rtc *rtc;
	413	int ret = 0;
	414
5438de44	415	dev_dbg_stamp(&pdev->dev);
8cc75c9a WB	416
	417	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
	418	if (unlikely(!rtc))
	419	return -ENOMEM;
	420
8cc75c9a WB	421	rtc->rtc_dev = rtc_device_register(pdev->name, &pdev->dev, &bfin_rtc_ops, THIS_MODULE);
	422	if (unlikely(IS_ERR(rtc))) {
	423	ret = PTR_ERR(rtc->rtc_dev);
	424	goto err;
	425	}
5c236343	426	rtc->rtc_dev->irq_freq = 1;
8cc75c9a WB	427
	428	platform_set_drvdata(pdev, rtc);
	429
	430	return 0;
	431
5c236343	432	err:
8cc75c9a WB	433	kfree(rtc);
	434	return ret;
	435	}
	436
	437	static int __devexit bfin_rtc_remove(struct platform_device *pdev)
	438	{
	439	struct bfin_rtc *rtc = platform_get_drvdata(pdev);
	440
	441	rtc_device_unregister(rtc->rtc_dev);
	442	platform_set_drvdata(pdev, NULL);
	443	kfree(rtc);
	444
	445	return 0;
	446	}
	447
	448	static struct platform_driver bfin_rtc_driver = {
	449	.driver = {
	450	.name = "rtc-bfin",
	451	.owner = THIS_MODULE,
	452	},
	453	.probe = bfin_rtc_probe,
	454	.remove = __devexit_p(bfin_rtc_remove),
	455	};
	456
	457	static int __init bfin_rtc_init(void)
	458	{
8cc75c9a WB	459	return platform_driver_register(&bfin_rtc_driver);
	460	}
	461
	462	static void __exit bfin_rtc_exit(void)
	463	{
	464	platform_driver_unregister(&bfin_rtc_driver);
	465	}
	466
	467	module_init(bfin_rtc_init);
	468	module_exit(bfin_rtc_exit);
	469
	470	MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
	471	MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
	472	MODULE_LICENSE("GPL");