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Commit | Line | Data |
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8cc75c9a WB |
1 | /* |
2 | * Blackfin On-Chip Real Time Clock Driver | |
095b9d54 | 3 | * Supports BF52[257]/BF53[123]/BF53[467]/BF54[24789] |
8cc75c9a | 4 | * |
813006f4 | 5 | * Copyright 2004-2008 Analog Devices Inc. |
8cc75c9a WB |
6 | * |
7 | * Enter bugs at http://blackfin.uclinux.org/ | |
8 | * | |
9 | * Licensed under the GPL-2 or later. | |
10 | */ | |
11 | ||
12 | /* The biggest issue we deal with in this driver is that register writes are | |
13 | * synced to the RTC frequency of 1Hz. So if you write to a register and | |
14 | * attempt to write again before the first write has completed, the new write | |
15 | * is simply discarded. This can easily be troublesome if userspace disables | |
16 | * one event (say periodic) and then right after enables an event (say alarm). | |
17 | * Since all events are maintained in the same interrupt mask register, if | |
18 | * we wrote to it to disable the first event and then wrote to it again to | |
19 | * enable the second event, that second event would not be enabled as the | |
20 | * write would be discarded and things quickly fall apart. | |
21 | * | |
22 | * To keep this delay from significantly degrading performance (we, in theory, | |
23 | * would have to sleep for up to 1 second everytime we wanted to write a | |
24 | * register), we only check the write pending status before we start to issue | |
25 | * a new write. We bank on the idea that it doesnt matter when the sync | |
26 | * happens so long as we don't attempt another write before it does. The only | |
27 | * time userspace would take this penalty is when they try and do multiple | |
28 | * operations right after another ... but in this case, they need to take the | |
29 | * sync penalty, so we should be OK. | |
30 | * | |
31 | * Also note that the RTC_ISTAT register does not suffer this penalty; its | |
32 | * writes to clear status registers complete immediately. | |
33 | */ | |
34 | ||
8cc75c9a | 35 | #include <linux/bcd.h> |
095b9d54 MF |
36 | #include <linux/completion.h> |
37 | #include <linux/delay.h> | |
8cc75c9a | 38 | #include <linux/init.h> |
095b9d54 MF |
39 | #include <linux/interrupt.h> |
40 | #include <linux/kernel.h> | |
41 | #include <linux/module.h> | |
8cc75c9a | 42 | #include <linux/platform_device.h> |
095b9d54 | 43 | #include <linux/rtc.h> |
8cc75c9a | 44 | #include <linux/seq_file.h> |
8cc75c9a WB |
45 | |
46 | #include <asm/blackfin.h> | |
47 | ||
5438de44 | 48 | #define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__) |
8cc75c9a WB |
49 | |
50 | struct bfin_rtc { | |
51 | struct rtc_device *rtc_dev; | |
52 | struct rtc_time rtc_alarm; | |
095b9d54 | 53 | u16 rtc_wrote_regs; |
8cc75c9a WB |
54 | }; |
55 | ||
56 | /* Bit values for the ISTAT / ICTL registers */ | |
57 | #define RTC_ISTAT_WRITE_COMPLETE 0x8000 | |
58 | #define RTC_ISTAT_WRITE_PENDING 0x4000 | |
59 | #define RTC_ISTAT_ALARM_DAY 0x0040 | |
60 | #define RTC_ISTAT_24HR 0x0020 | |
61 | #define RTC_ISTAT_HOUR 0x0010 | |
62 | #define RTC_ISTAT_MIN 0x0008 | |
63 | #define RTC_ISTAT_SEC 0x0004 | |
64 | #define RTC_ISTAT_ALARM 0x0002 | |
65 | #define RTC_ISTAT_STOPWATCH 0x0001 | |
66 | ||
67 | /* Shift values for RTC_STAT register */ | |
68 | #define DAY_BITS_OFF 17 | |
69 | #define HOUR_BITS_OFF 12 | |
70 | #define MIN_BITS_OFF 6 | |
71 | #define SEC_BITS_OFF 0 | |
72 | ||
73 | /* Some helper functions to convert between the common RTC notion of time | |
5c236343 | 74 | * and the internal Blackfin notion that is encoded in 32bits. |
8cc75c9a WB |
75 | */ |
76 | static inline u32 rtc_time_to_bfin(unsigned long now) | |
77 | { | |
78 | u32 sec = (now % 60); | |
79 | u32 min = (now % (60 * 60)) / 60; | |
80 | u32 hour = (now % (60 * 60 * 24)) / (60 * 60); | |
81 | u32 days = (now / (60 * 60 * 24)); | |
82 | return (sec << SEC_BITS_OFF) + | |
83 | (min << MIN_BITS_OFF) + | |
84 | (hour << HOUR_BITS_OFF) + | |
85 | (days << DAY_BITS_OFF); | |
86 | } | |
87 | static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin) | |
88 | { | |
89 | return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) + | |
90 | (((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) + | |
91 | (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) + | |
92 | (((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24); | |
93 | } | |
94 | static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm) | |
95 | { | |
96 | rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm); | |
97 | } | |
98 | ||
095b9d54 MF |
99 | /** |
100 | * bfin_rtc_sync_pending - make sure pending writes have complete | |
101 | * | |
102 | * Wait for the previous write to a RTC register to complete. | |
8cc75c9a WB |
103 | * Unfortunately, we can't sleep here as that introduces a race condition when |
104 | * turning on interrupt events. Consider this: | |
105 | * - process sets alarm | |
106 | * - process enables alarm | |
107 | * - process sleeps while waiting for rtc write to sync | |
108 | * - interrupt fires while process is sleeping | |
109 | * - interrupt acks the event by writing to ISTAT | |
110 | * - interrupt sets the WRITE PENDING bit | |
111 | * - interrupt handler finishes | |
112 | * - process wakes up, sees WRITE PENDING bit set, goes to sleep | |
113 | * - interrupt fires while process is sleeping | |
114 | * If anyone can point out the obvious solution here, i'm listening :). This | |
115 | * shouldn't be an issue on an SMP or preempt system as this function should | |
116 | * only be called with the rtc lock held. | |
5c236343 MF |
117 | * |
118 | * Other options: | |
119 | * - disable PREN so the sync happens at 32.768kHZ ... but this changes the | |
120 | * inc rate for all RTC registers from 1HZ to 32.768kHZ ... | |
121 | * - use the write complete IRQ | |
8cc75c9a | 122 | */ |
095b9d54 MF |
123 | /* |
124 | static void bfin_rtc_sync_pending_polled(void) | |
8cc75c9a | 125 | { |
095b9d54 | 126 | while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE)) |
8cc75c9a WB |
127 | if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)) |
128 | break; | |
8cc75c9a WB |
129 | bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE); |
130 | } | |
095b9d54 MF |
131 | */ |
132 | static DECLARE_COMPLETION(bfin_write_complete); | |
133 | static void bfin_rtc_sync_pending(struct device *dev) | |
134 | { | |
135 | dev_dbg_stamp(dev); | |
136 | while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING) | |
137 | wait_for_completion_timeout(&bfin_write_complete, HZ * 5); | |
138 | dev_dbg_stamp(dev); | |
139 | } | |
8cc75c9a | 140 | |
095b9d54 MF |
141 | /** |
142 | * bfin_rtc_reset - set RTC to sane/known state | |
143 | * | |
144 | * Initialize the RTC. Enable pre-scaler to scale RTC clock | |
145 | * to 1Hz and clear interrupt/status registers. | |
146 | */ | |
3b128fe0 | 147 | static void bfin_rtc_reset(struct device *dev, u16 rtc_ictl) |
8cc75c9a | 148 | { |
5438de44 | 149 | struct bfin_rtc *rtc = dev_get_drvdata(dev); |
095b9d54 MF |
150 | dev_dbg_stamp(dev); |
151 | bfin_rtc_sync_pending(dev); | |
8cc75c9a | 152 | bfin_write_RTC_PREN(0x1); |
3b128fe0 | 153 | bfin_write_RTC_ICTL(rtc_ictl); |
8cc75c9a WB |
154 | bfin_write_RTC_SWCNT(0); |
155 | bfin_write_RTC_ALARM(0); | |
156 | bfin_write_RTC_ISTAT(0xFFFF); | |
095b9d54 | 157 | rtc->rtc_wrote_regs = 0; |
8cc75c9a WB |
158 | } |
159 | ||
095b9d54 MF |
160 | /** |
161 | * bfin_rtc_interrupt - handle interrupt from RTC | |
162 | * | |
163 | * Since we handle all RTC events here, we have to make sure the requested | |
164 | * interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT) | |
165 | * always gets updated regardless of the interrupt being enabled. So when one | |
166 | * even we care about (e.g. stopwatch) goes off, we don't want to turn around | |
167 | * and say that other events have happened as well (e.g. second). We do not | |
168 | * have to worry about pending writes to the RTC_ICTL register as interrupts | |
169 | * only fire if they are enabled in the RTC_ICTL register. | |
170 | */ | |
8cc75c9a WB |
171 | static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id) |
172 | { | |
d7827d88 MF |
173 | struct device *dev = dev_id; |
174 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
8cc75c9a | 175 | unsigned long events = 0; |
095b9d54 MF |
176 | bool write_complete = false; |
177 | u16 rtc_istat, rtc_ictl; | |
8cc75c9a | 178 | |
5438de44 | 179 | dev_dbg_stamp(dev); |
8cc75c9a | 180 | |
8cc75c9a | 181 | rtc_istat = bfin_read_RTC_ISTAT(); |
095b9d54 | 182 | rtc_ictl = bfin_read_RTC_ICTL(); |
8cc75c9a | 183 | |
095b9d54 MF |
184 | if (rtc_istat & RTC_ISTAT_WRITE_COMPLETE) { |
185 | bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE); | |
186 | write_complete = true; | |
187 | complete(&bfin_write_complete); | |
8cc75c9a WB |
188 | } |
189 | ||
095b9d54 MF |
190 | if (rtc_ictl & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) { |
191 | if (rtc_istat & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) { | |
192 | bfin_write_RTC_ISTAT(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY); | |
193 | events |= RTC_AF | RTC_IRQF; | |
194 | } | |
8cc75c9a WB |
195 | } |
196 | ||
095b9d54 MF |
197 | if (rtc_ictl & RTC_ISTAT_STOPWATCH) { |
198 | if (rtc_istat & RTC_ISTAT_STOPWATCH) { | |
199 | bfin_write_RTC_ISTAT(RTC_ISTAT_STOPWATCH); | |
200 | events |= RTC_PF | RTC_IRQF; | |
201 | bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq); | |
202 | } | |
8cc75c9a WB |
203 | } |
204 | ||
095b9d54 MF |
205 | if (rtc_ictl & RTC_ISTAT_SEC) { |
206 | if (rtc_istat & RTC_ISTAT_SEC) { | |
207 | bfin_write_RTC_ISTAT(RTC_ISTAT_SEC); | |
208 | events |= RTC_UF | RTC_IRQF; | |
209 | } | |
210 | } | |
8cc75c9a | 211 | |
095b9d54 MF |
212 | if (events) |
213 | rtc_update_irq(rtc->rtc_dev, 1, events); | |
8cc75c9a | 214 | |
095b9d54 MF |
215 | if (write_complete || events) |
216 | return IRQ_HANDLED; | |
217 | else | |
218 | return IRQ_NONE; | |
8cc75c9a WB |
219 | } |
220 | ||
221 | static int bfin_rtc_open(struct device *dev) | |
222 | { | |
8cc75c9a WB |
223 | int ret; |
224 | ||
5438de44 | 225 | dev_dbg_stamp(dev); |
8cc75c9a | 226 | |
095b9d54 MF |
227 | ret = request_irq(IRQ_RTC, bfin_rtc_interrupt, IRQF_SHARED, to_platform_device(dev)->name, dev); |
228 | if (!ret) | |
3b128fe0 | 229 | bfin_rtc_reset(dev, RTC_ISTAT_WRITE_COMPLETE); |
8cc75c9a WB |
230 | |
231 | return ret; | |
232 | } | |
233 | ||
234 | static void bfin_rtc_release(struct device *dev) | |
235 | { | |
5438de44 | 236 | dev_dbg_stamp(dev); |
3b128fe0 | 237 | bfin_rtc_reset(dev, 0); |
8cc75c9a WB |
238 | free_irq(IRQ_RTC, dev); |
239 | } | |
240 | ||
605eb8b3 | 241 | static void bfin_rtc_int_set(u16 rtc_int) |
095b9d54 MF |
242 | { |
243 | bfin_write_RTC_ISTAT(rtc_int); | |
244 | bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | rtc_int); | |
245 | } | |
605eb8b3 | 246 | static void bfin_rtc_int_clear(u16 rtc_int) |
095b9d54 MF |
247 | { |
248 | bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int); | |
249 | } | |
250 | static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc) | |
251 | { | |
252 | /* Blackfin has different bits for whether the alarm is | |
253 | * more than 24 hours away. | |
254 | */ | |
605eb8b3 | 255 | bfin_rtc_int_set(rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY); |
095b9d54 | 256 | } |
8cc75c9a WB |
257 | static int bfin_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) |
258 | { | |
259 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
095b9d54 | 260 | int ret = 0; |
8cc75c9a | 261 | |
5438de44 | 262 | dev_dbg_stamp(dev); |
8cc75c9a | 263 | |
095b9d54 MF |
264 | bfin_rtc_sync_pending(dev); |
265 | ||
8cc75c9a | 266 | switch (cmd) { |
8cc75c9a | 267 | case RTC_UIE_ON: |
5438de44 | 268 | dev_dbg_stamp(dev); |
605eb8b3 | 269 | bfin_rtc_int_set(RTC_ISTAT_SEC); |
095b9d54 | 270 | break; |
8cc75c9a | 271 | case RTC_UIE_OFF: |
5438de44 | 272 | dev_dbg_stamp(dev); |
605eb8b3 | 273 | bfin_rtc_int_clear(~RTC_ISTAT_SEC); |
095b9d54 | 274 | break; |
8cc75c9a | 275 | |
095b9d54 | 276 | case RTC_AIE_ON: |
5438de44 | 277 | dev_dbg_stamp(dev); |
095b9d54 MF |
278 | bfin_rtc_int_set_alarm(rtc); |
279 | break; | |
8cc75c9a | 280 | case RTC_AIE_OFF: |
5438de44 | 281 | dev_dbg_stamp(dev); |
605eb8b3 | 282 | bfin_rtc_int_clear(~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)); |
095b9d54 MF |
283 | break; |
284 | ||
285 | default: | |
286 | dev_dbg_stamp(dev); | |
287 | ret = -ENOIOCTLCMD; | |
8cc75c9a WB |
288 | } |
289 | ||
095b9d54 | 290 | return ret; |
8cc75c9a WB |
291 | } |
292 | ||
293 | static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
294 | { | |
295 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
296 | ||
5438de44 | 297 | dev_dbg_stamp(dev); |
8cc75c9a | 298 | |
095b9d54 MF |
299 | if (rtc->rtc_wrote_regs & 0x1) |
300 | bfin_rtc_sync_pending(dev); | |
301 | ||
8cc75c9a | 302 | rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm); |
8cc75c9a WB |
303 | |
304 | return 0; | |
305 | } | |
306 | ||
307 | static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
308 | { | |
309 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
310 | int ret; | |
311 | unsigned long now; | |
312 | ||
5438de44 | 313 | dev_dbg_stamp(dev); |
8cc75c9a | 314 | |
8cc75c9a WB |
315 | ret = rtc_tm_to_time(tm, &now); |
316 | if (ret == 0) { | |
095b9d54 MF |
317 | if (rtc->rtc_wrote_regs & 0x1) |
318 | bfin_rtc_sync_pending(dev); | |
8cc75c9a | 319 | bfin_write_RTC_STAT(rtc_time_to_bfin(now)); |
095b9d54 | 320 | rtc->rtc_wrote_regs = 0x1; |
8cc75c9a WB |
321 | } |
322 | ||
8cc75c9a WB |
323 | return ret; |
324 | } | |
325 | ||
326 | static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
327 | { | |
328 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
5438de44 | 329 | dev_dbg_stamp(dev); |
48c1a56b | 330 | alrm->time = rtc->rtc_alarm; |
095b9d54 | 331 | bfin_rtc_sync_pending(dev); |
68db3047 | 332 | alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)); |
8cc75c9a WB |
333 | return 0; |
334 | } | |
335 | ||
336 | static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
337 | { | |
338 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
095b9d54 MF |
339 | unsigned long rtc_alarm; |
340 | ||
5438de44 | 341 | dev_dbg_stamp(dev); |
095b9d54 MF |
342 | |
343 | if (rtc_tm_to_time(&alrm->time, &rtc_alarm)) | |
344 | return -EINVAL; | |
345 | ||
68db3047 | 346 | rtc->rtc_alarm = alrm->time; |
095b9d54 MF |
347 | |
348 | bfin_rtc_sync_pending(dev); | |
349 | bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm)); | |
350 | if (alrm->enabled) | |
351 | bfin_rtc_int_set_alarm(rtc); | |
352 | ||
8cc75c9a WB |
353 | return 0; |
354 | } | |
355 | ||
356 | static int bfin_rtc_proc(struct device *dev, struct seq_file *seq) | |
357 | { | |
64061160 | 358 | #define yesno(x) ((x) ? "yes" : "no") |
8cc75c9a | 359 | u16 ictl = bfin_read_RTC_ICTL(); |
5438de44 | 360 | dev_dbg_stamp(dev); |
64061160 MF |
361 | seq_printf(seq, |
362 | "alarm_IRQ\t: %s\n" | |
363 | "wkalarm_IRQ\t: %s\n" | |
364 | "seconds_IRQ\t: %s\n" | |
365 | "periodic_IRQ\t: %s\n", | |
366 | yesno(ictl & RTC_ISTAT_ALARM), | |
367 | yesno(ictl & RTC_ISTAT_ALARM_DAY), | |
368 | yesno(ictl & RTC_ISTAT_SEC), | |
369 | yesno(ictl & RTC_ISTAT_STOPWATCH)); | |
8cc75c9a | 370 | return 0; |
64061160 | 371 | #undef yesno |
8cc75c9a WB |
372 | } |
373 | ||
e12af37d MF |
374 | static int bfin_irq_set_state(struct device *dev, int enabled) |
375 | { | |
376 | struct bfin_rtc *rtc = dev_get_drvdata(dev); | |
377 | ||
378 | dev_dbg_stamp(dev); | |
379 | ||
380 | bfin_rtc_sync_pending(dev); | |
381 | ||
382 | if (enabled) { | |
383 | bfin_rtc_int_set(RTC_ISTAT_STOPWATCH); | |
384 | bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq); | |
385 | } else | |
386 | bfin_rtc_int_clear(~RTC_ISTAT_STOPWATCH); | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
8cc75c9a WB |
391 | static struct rtc_class_ops bfin_rtc_ops = { |
392 | .open = bfin_rtc_open, | |
393 | .release = bfin_rtc_release, | |
394 | .ioctl = bfin_rtc_ioctl, | |
395 | .read_time = bfin_rtc_read_time, | |
396 | .set_time = bfin_rtc_set_time, | |
397 | .read_alarm = bfin_rtc_read_alarm, | |
398 | .set_alarm = bfin_rtc_set_alarm, | |
399 | .proc = bfin_rtc_proc, | |
e12af37d | 400 | .irq_set_state = bfin_irq_set_state, |
8cc75c9a WB |
401 | }; |
402 | ||
403 | static int __devinit bfin_rtc_probe(struct platform_device *pdev) | |
404 | { | |
405 | struct bfin_rtc *rtc; | |
406 | int ret = 0; | |
407 | ||
5438de44 | 408 | dev_dbg_stamp(&pdev->dev); |
8cc75c9a WB |
409 | |
410 | rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); | |
411 | if (unlikely(!rtc)) | |
412 | return -ENOMEM; | |
413 | ||
8cc75c9a | 414 | rtc->rtc_dev = rtc_device_register(pdev->name, &pdev->dev, &bfin_rtc_ops, THIS_MODULE); |
801678c5 | 415 | if (IS_ERR(rtc)) { |
8cc75c9a WB |
416 | ret = PTR_ERR(rtc->rtc_dev); |
417 | goto err; | |
418 | } | |
5c236343 | 419 | rtc->rtc_dev->irq_freq = 1; |
8cc75c9a WB |
420 | |
421 | platform_set_drvdata(pdev, rtc); | |
422 | ||
813006f4 MF |
423 | device_init_wakeup(&pdev->dev, 1); |
424 | ||
8cc75c9a WB |
425 | return 0; |
426 | ||
5c236343 | 427 | err: |
8cc75c9a WB |
428 | kfree(rtc); |
429 | return ret; | |
430 | } | |
431 | ||
432 | static int __devexit bfin_rtc_remove(struct platform_device *pdev) | |
433 | { | |
434 | struct bfin_rtc *rtc = platform_get_drvdata(pdev); | |
435 | ||
436 | rtc_device_unregister(rtc->rtc_dev); | |
437 | platform_set_drvdata(pdev, NULL); | |
438 | kfree(rtc); | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
5aeb776d SZ |
443 | #ifdef CONFIG_PM |
444 | static int bfin_rtc_suspend(struct platform_device *pdev, pm_message_t state) | |
445 | { | |
140fab14 | 446 | if (device_may_wakeup(&pdev->dev)) { |
813006f4 | 447 | enable_irq_wake(IRQ_RTC); |
140fab14 MF |
448 | bfin_rtc_sync_pending(&pdev->dev); |
449 | } else | |
605eb8b3 | 450 | bfin_rtc_int_clear(-1); |
813006f4 | 451 | |
5aeb776d SZ |
452 | return 0; |
453 | } | |
454 | ||
455 | static int bfin_rtc_resume(struct platform_device *pdev) | |
456 | { | |
813006f4 MF |
457 | if (device_may_wakeup(&pdev->dev)) |
458 | disable_irq_wake(IRQ_RTC); | |
459 | else | |
460 | bfin_write_RTC_ISTAT(-1); | |
461 | ||
5aeb776d SZ |
462 | return 0; |
463 | } | |
813006f4 MF |
464 | #else |
465 | # define bfin_rtc_suspend NULL | |
466 | # define bfin_rtc_resume NULL | |
5aeb776d SZ |
467 | #endif |
468 | ||
8cc75c9a WB |
469 | static struct platform_driver bfin_rtc_driver = { |
470 | .driver = { | |
471 | .name = "rtc-bfin", | |
472 | .owner = THIS_MODULE, | |
473 | }, | |
474 | .probe = bfin_rtc_probe, | |
475 | .remove = __devexit_p(bfin_rtc_remove), | |
5aeb776d SZ |
476 | .suspend = bfin_rtc_suspend, |
477 | .resume = bfin_rtc_resume, | |
8cc75c9a WB |
478 | }; |
479 | ||
480 | static int __init bfin_rtc_init(void) | |
481 | { | |
8cc75c9a WB |
482 | return platform_driver_register(&bfin_rtc_driver); |
483 | } | |
484 | ||
485 | static void __exit bfin_rtc_exit(void) | |
486 | { | |
487 | platform_driver_unregister(&bfin_rtc_driver); | |
488 | } | |
489 | ||
490 | module_init(bfin_rtc_init); | |
491 | module_exit(bfin_rtc_exit); | |
492 | ||
493 | MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver"); | |
494 | MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>"); | |
495 | MODULE_LICENSE("GPL"); | |
ad28a07b | 496 | MODULE_ALIAS("platform:rtc-bfin"); |