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Merge branch 'core-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[net-next-2.6.git] / drivers / regulator / wm8350-regulator.c
CommitLineData
da09155a
MB		 1/*
2 * wm8350.c -- Voltage and current regulation for the Wolfson WM8350 PMIC
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood
7 * linux@wolfsonmicro.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/bitops.h>
19#include <linux/err.h>
20#include <linux/i2c.h>
21#include <linux/mfd/wm8350/core.h>
22#include <linux/mfd/wm8350/pmic.h>
23#include <linux/platform_device.h>
24#include <linux/regulator/driver.h>
25#include <linux/regulator/machine.h>
26
221a7c7c
MB		 27/* Maximum value possible for VSEL */
28#define WM8350_DCDC_MAX_VSEL 0x66
29
da09155a
MB		 30/* Microamps */
31static const int isink_cur[] = {
32 4,
33 5,
34 6,
35 7,
36 8,
37 10,
38 11,
39 14,
40 16,
41 19,
42 23,
43 27,
44 32,
45 39,
46 46,
47 54,
48 65,
49 77,
50 92,
51 109,
52 130,
53 154,
54 183,
55 218,
56 259,
57 308,
58 367,
59 436,
60 518,
61 616,
62 733,
63 872,
64 1037,
65 1233,
66 1466,
67 1744,
68 2073,
69 2466,
70 2933,
71 3487,
72 4147,
73 4932,
74 5865,
75 6975,
76 8294,
77 9864,
78 11730,
79 13949,
80 16589,
81 19728,
82 23460,
83 27899,
84 33178,
85 39455,
86 46920,
87 55798,
88 66355,
89 78910,
90 93840,
91 111596,
92 132710,
93 157820,
94 187681,
95 223191
96};
97
98static int get_isink_val(int min_uA, int max_uA, u16 *setting)
99{
100 int i;
101
102 for (i = ARRAY_SIZE(isink_cur) - 1; i >= 0; i--) {
103 if (min_uA <= isink_cur[i] && max_uA >= isink_cur[i]) {
104 *setting = i;
105 return 0;
106 }
107 }
108 return -EINVAL;
109}
110
111static inline int wm8350_ldo_val_to_mvolts(unsigned int val)
112{
113 if (val < 16)
114 return (val * 50) + 900;
115 else
116 return ((val - 16) * 100) + 1800;
117
118}
119
120static inline unsigned int wm8350_ldo_mvolts_to_val(int mV)
121{
122 if (mV < 1800)
123 return (mV - 900) / 50;
124 else
125 return ((mV - 1800) / 100) + 16;
126}
127
128static inline int wm8350_dcdc_val_to_mvolts(unsigned int val)
129{
130 return (val * 25) + 850;
131}
132
133static inline unsigned int wm8350_dcdc_mvolts_to_val(int mV)
134{
135 return (mV - 850) / 25;
136}
137
138static int wm8350_isink_set_current(struct regulator_dev *rdev, int min_uA,
139 int max_uA)
140{
141 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
142 int isink = rdev_get_id(rdev);
143 u16 val, setting;
144 int ret;
145
146 ret = get_isink_val(min_uA, max_uA, &setting);
147 if (ret != 0)
148 return ret;
149
150 switch (isink) {
151 case WM8350_ISINK_A:
152 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
153 ~WM8350_CS1_ISEL_MASK;
154 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_A,
155 val | setting);
156 break;
157 case WM8350_ISINK_B:
158 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
159 ~WM8350_CS1_ISEL_MASK;
160 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_B,
161 val | setting);
162 break;
163 default:
164 return -EINVAL;
165 }
166
167 return 0;
168}
169
170static int wm8350_isink_get_current(struct regulator_dev *rdev)
171{
172 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
173 int isink = rdev_get_id(rdev);
174 u16 val;
175
176 switch (isink) {
177 case WM8350_ISINK_A:
178 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
179 WM8350_CS1_ISEL_MASK;
180 break;
181 case WM8350_ISINK_B:
182 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
183 WM8350_CS1_ISEL_MASK;
184 break;
185 default:
186 return 0;
187 }
188
189 return (isink_cur[val] + 50) / 100;
190}
191
192/* turn on ISINK followed by DCDC */
193static int wm8350_isink_enable(struct regulator_dev *rdev)
194{
195 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
196 int isink = rdev_get_id(rdev);
197
198 switch (isink) {
199 case WM8350_ISINK_A:
200 switch (wm8350->pmic.isink_A_dcdc) {
201 case WM8350_DCDC_2:
202 case WM8350_DCDC_5:
203 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
204 WM8350_CS1_ENA);
205 wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL,
206 WM8350_CS1_DRIVE);
207 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
208 1 << (wm8350->pmic.isink_A_dcdc -
209 WM8350_DCDC_1));
210 break;
211 default:
212 return -EINVAL;
213 }
214 break;
215 case WM8350_ISINK_B:
216 switch (wm8350->pmic.isink_B_dcdc) {
217 case WM8350_DCDC_2:
218 case WM8350_DCDC_5:
219 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
220 WM8350_CS2_ENA);
221 wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL,
222 WM8350_CS2_DRIVE);
223 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
224 1 << (wm8350->pmic.isink_B_dcdc -
225 WM8350_DCDC_1));
226 break;
227 default:
228 return -EINVAL;
229 }
230 break;
231 default:
232 return -EINVAL;
233 }
234 return 0;
235}
236
237static int wm8350_isink_disable(struct regulator_dev *rdev)
238{
239 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
240 int isink = rdev_get_id(rdev);
241
242 switch (isink) {
243 case WM8350_ISINK_A:
244 switch (wm8350->pmic.isink_A_dcdc) {
245 case WM8350_DCDC_2:
246 case WM8350_DCDC_5:
247 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
248 1 << (wm8350->pmic.isink_A_dcdc -
249 WM8350_DCDC_1));
250 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
251 WM8350_CS1_ENA);
252 break;
253 default:
254 return -EINVAL;
255 }
256 break;
257 case WM8350_ISINK_B:
258 switch (wm8350->pmic.isink_B_dcdc) {
259 case WM8350_DCDC_2:
260 case WM8350_DCDC_5:
261 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
262 1 << (wm8350->pmic.isink_B_dcdc -
263 WM8350_DCDC_1));
264 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
265 WM8350_CS2_ENA);
266 break;
267 default:
268 return -EINVAL;
269 }
270 break;
271 default:
272 return -EINVAL;
273 }
274 return 0;
275}
276
277static int wm8350_isink_is_enabled(struct regulator_dev *rdev)
278{
279 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
280 int isink = rdev_get_id(rdev);
281
282 switch (isink) {
283 case WM8350_ISINK_A:
284 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
285 0x8000;
286 case WM8350_ISINK_B:
287 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
288 0x8000;
289 }
290 return -EINVAL;
291}
292
75c8ac22
MB		 293static int wm8350_isink_enable_time(struct regulator_dev *rdev)
294{
295 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
296 int isink = rdev_get_id(rdev);
297 int reg;
298
299 switch (isink) {
300 case WM8350_ISINK_A:
301 reg = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL);
302 break;
303 case WM8350_ISINK_B:
304 reg = wm8350_reg_read(wm8350, WM8350_CSB_FLASH_CONTROL);
305 break;
306 default:
307 return -EINVAL;
308 }
309
310 if (reg & WM8350_CS1_FLASH_MODE) {
311 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
312 case 0:
313 return 0;
314 case 1:
315 return 1950;
316 case 2:
317 return 3910;
318 case 3:
319 return 7800;
320 }
321 } else {
322 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
323 case 0:
324 return 0;
325 case 1:
326 return 250000;
327 case 2:
328 return 500000;
329 case 3:
330 return 1000000;
331 }
332 }
333
334 return -EINVAL;
335}
336
337
da09155a
MB		 338int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
339 u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp,
340 u16 drive)
341{
342 switch (isink) {
343 case WM8350_ISINK_A:
344 wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL,
345 (mode ? WM8350_CS1_FLASH_MODE : 0) |
346 (trigger ? WM8350_CS1_TRIGSRC : 0) |
347 duration | on_ramp | off_ramp | drive);
348 break;
349 case WM8350_ISINK_B:
350 wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL,
351 (mode ? WM8350_CS2_FLASH_MODE : 0) |
352 (trigger ? WM8350_CS2_TRIGSRC : 0) |
353 duration | on_ramp | off_ramp | drive);
354 break;
355 default:
356 return -EINVAL;
357 }
358 return 0;
359}
360EXPORT_SYMBOL_GPL(wm8350_isink_set_flash);
361
362static int wm8350_dcdc_set_voltage(struct regulator_dev *rdev, int min_uV,
363 int max_uV)
364{
365 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
366 int volt_reg, dcdc = rdev_get_id(rdev), mV,
367 min_mV = min_uV / 1000, max_mV = max_uV / 1000;
368 u16 val;
369
370 if (min_mV < 850 || min_mV > 4025)
371 return -EINVAL;
372 if (max_mV < 850 || max_mV > 4025)
373 return -EINVAL;
374
375 /* step size is 25mV */
376 mV = (min_mV - 826) / 25;
377 if (wm8350_dcdc_val_to_mvolts(mV) > max_mV)
378 return -EINVAL;
379 BUG_ON(wm8350_dcdc_val_to_mvolts(mV) < min_mV);
380
381 switch (dcdc) {
382 case WM8350_DCDC_1:
383 volt_reg = WM8350_DCDC1_CONTROL;
384 break;
385 case WM8350_DCDC_3:
386 volt_reg = WM8350_DCDC3_CONTROL;
387 break;
388 case WM8350_DCDC_4:
389 volt_reg = WM8350_DCDC4_CONTROL;
390 break;
391 case WM8350_DCDC_6:
392 volt_reg = WM8350_DCDC6_CONTROL;
393 break;
394 case WM8350_DCDC_2:
395 case WM8350_DCDC_5:
396 default:
397 return -EINVAL;
398 }
399
400 /* all DCDCs have same mV bits */
401 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
402 wm8350_reg_write(wm8350, volt_reg, val | mV);
403 return 0;
404}
405
406static int wm8350_dcdc_get_voltage(struct regulator_dev *rdev)
407{
408 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
409 int volt_reg, dcdc = rdev_get_id(rdev);
410 u16 val;
411
412 switch (dcdc) {
413 case WM8350_DCDC_1:
414 volt_reg = WM8350_DCDC1_CONTROL;
415 break;
416 case WM8350_DCDC_3:
417 volt_reg = WM8350_DCDC3_CONTROL;
418 break;
419 case WM8350_DCDC_4:
420 volt_reg = WM8350_DCDC4_CONTROL;
421 break;
422 case WM8350_DCDC_6:
423 volt_reg = WM8350_DCDC6_CONTROL;
424 break;
425 case WM8350_DCDC_2:
426 case WM8350_DCDC_5:
427 default:
428 return -EINVAL;
429 }
430
431 /* all DCDCs have same mV bits */
432 val = wm8350_reg_read(wm8350, volt_reg) & WM8350_DC1_VSEL_MASK;
433 return wm8350_dcdc_val_to_mvolts(val) * 1000;
434}
435
221a7c7c
MB		 436static int wm8350_dcdc_list_voltage(struct regulator_dev *rdev,
437 unsigned selector)
438{
439 if (selector > WM8350_DCDC_MAX_VSEL)
440 return -EINVAL;
441 return wm8350_dcdc_val_to_mvolts(selector) * 1000;
442}
443
da09155a
MB		 444static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
445{
446 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
447 int volt_reg, mV = uV / 1000, dcdc = rdev_get_id(rdev);
448 u16 val;
449
450 dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, mV);
451
452 if (mV && (mV < 850 || mV > 4025)) {
453 dev_err(wm8350->dev,
454 "DCDC%d suspend voltage %d mV out of range\n",
455 dcdc, mV);
456 return -EINVAL;
457 }
458 if (mV == 0)
459 mV = 850;
460
461 switch (dcdc) {
462 case WM8350_DCDC_1:
463 volt_reg = WM8350_DCDC1_LOW_POWER;
464 break;
465 case WM8350_DCDC_3:
466 volt_reg = WM8350_DCDC3_LOW_POWER;
467 break;
468 case WM8350_DCDC_4:
469 volt_reg = WM8350_DCDC4_LOW_POWER;
470 break;
471 case WM8350_DCDC_6:
472 volt_reg = WM8350_DCDC6_LOW_POWER;
473 break;
474 case WM8350_DCDC_2:
475 case WM8350_DCDC_5:
476 default:
477 return -EINVAL;
478 }
479
480 /* all DCDCs have same mV bits */
481 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
482 wm8350_reg_write(wm8350, volt_reg,
483 val | wm8350_dcdc_mvolts_to_val(mV));
484 return 0;
485}
486
487static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
488{
489 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
490 int dcdc = rdev_get_id(rdev);
491 u16 val;
492
493 switch (dcdc) {
494 case WM8350_DCDC_1:
495 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
496 & ~WM8350_DCDC_HIB_MODE_MASK;
497 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
498 wm8350->pmic.dcdc1_hib_mode);
499 break;
500 case WM8350_DCDC_3:
501 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
502 & ~WM8350_DCDC_HIB_MODE_MASK;
503 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
504 wm8350->pmic.dcdc3_hib_mode);
505 break;
506 case WM8350_DCDC_4:
507 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
508 & ~WM8350_DCDC_HIB_MODE_MASK;
509 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
510 wm8350->pmic.dcdc4_hib_mode);
511 break;
512 case WM8350_DCDC_6:
513 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
514 & ~WM8350_DCDC_HIB_MODE_MASK;
515 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
516 wm8350->pmic.dcdc6_hib_mode);
517 break;
518 case WM8350_DCDC_2:
519 case WM8350_DCDC_5:
520 default:
521 return -EINVAL;
522 }
523
524 return 0;
525}
526
527static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev)
528{
529 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
530 int dcdc = rdev_get_id(rdev);
531 u16 val;
532
533 switch (dcdc) {
534 case WM8350_DCDC_1:
535 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
536 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
537 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
538 WM8350_DCDC_HIB_MODE_DIS);
539 break;
540 case WM8350_DCDC_3:
541 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
542 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
543 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
544 WM8350_DCDC_HIB_MODE_DIS);
545 break;
546 case WM8350_DCDC_4:
547 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
548 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
549 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
550 WM8350_DCDC_HIB_MODE_DIS);
551 break;
552 case WM8350_DCDC_6:
553 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
554 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
555 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
556 WM8350_DCDC_HIB_MODE_DIS);
557 break;
558 case WM8350_DCDC_2:
559 case WM8350_DCDC_5:
560 default:
561 return -EINVAL;
562 }
563
564 return 0;
565}
566
567static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev)
568{
569 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
570 int dcdc = rdev_get_id(rdev);
571 u16 val;
572
573 switch (dcdc) {
574 case WM8350_DCDC_2:
575 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
576 & ~WM8350_DC2_HIB_MODE_MASK;
577 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
578 WM8350_DC2_HIB_MODE_ACTIVE);
579 break;
580 case WM8350_DCDC_5:
581 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
582 & ~WM8350_DC2_HIB_MODE_MASK;
583 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
584 WM8350_DC5_HIB_MODE_ACTIVE);
585 break;
586 default:
587 return -EINVAL;
588 }
589 return 0;
590}
591
592static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
593{
594 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
595 int dcdc = rdev_get_id(rdev);
596 u16 val;
597
598 switch (dcdc) {
599 case WM8350_DCDC_2:
600 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
601 & ~WM8350_DC2_HIB_MODE_MASK;
602 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
603 WM8350_DC2_HIB_MODE_DISABLE);
604 break;
605 case WM8350_DCDC_5:
606 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
607 & ~WM8350_DC2_HIB_MODE_MASK;
608 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
609 WM8350_DC2_HIB_MODE_DISABLE);
610 break;
611 default:
612 return -EINVAL;
613 }
614 return 0;
615}
616
617static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev,
618 unsigned int mode)
619{
620 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
621 int dcdc = rdev_get_id(rdev);
622 u16 *hib_mode;
623
624 switch (dcdc) {
625 case WM8350_DCDC_1:
626 hib_mode = &wm8350->pmic.dcdc1_hib_mode;
627 break;
628 case WM8350_DCDC_3:
629 hib_mode = &wm8350->pmic.dcdc3_hib_mode;
630 break;
631 case WM8350_DCDC_4:
632 hib_mode = &wm8350->pmic.dcdc4_hib_mode;
633 break;
634 case WM8350_DCDC_6:
635 hib_mode = &wm8350->pmic.dcdc6_hib_mode;
636 break;
637 case WM8350_DCDC_2:
638 case WM8350_DCDC_5:
639 default:
640 return -EINVAL;
641 }
642
643 switch (mode) {
644 case REGULATOR_MODE_NORMAL:
645 *hib_mode = WM8350_DCDC_HIB_MODE_IMAGE;
646 break;
647 case REGULATOR_MODE_IDLE:
648 *hib_mode = WM8350_DCDC_HIB_MODE_STANDBY;
649 break;
650 case REGULATOR_MODE_STANDBY:
651 *hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM;
652 break;
653 default:
654 return -EINVAL;
655 }
656
657 return 0;
658}
659
660static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
661{
662 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
663 int volt_reg, mV = uV / 1000, ldo = rdev_get_id(rdev);
664 u16 val;
665
666 dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, mV);
667
668 if (mV < 900 || mV > 3300) {
669 dev_err(wm8350->dev, "LDO%d voltage %d mV out of range\n",
670 ldo, mV);
671 return -EINVAL;
672 }
673
674 switch (ldo) {
675 case WM8350_LDO_1:
676 volt_reg = WM8350_LDO1_LOW_POWER;
677 break;
678 case WM8350_LDO_2:
679 volt_reg = WM8350_LDO2_LOW_POWER;
680 break;
681 case WM8350_LDO_3:
682 volt_reg = WM8350_LDO3_LOW_POWER;
683 break;
684 case WM8350_LDO_4:
685 volt_reg = WM8350_LDO4_LOW_POWER;
686 break;
687 default:
688 return -EINVAL;
689 }
690
691 /* all LDOs have same mV bits */
692 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
693 wm8350_reg_write(wm8350, volt_reg,
694 val | wm8350_ldo_mvolts_to_val(mV));
695 return 0;
696}
697
698static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev)
699{
700 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
701 int volt_reg, ldo = rdev_get_id(rdev);
702 u16 val;
703
704 switch (ldo) {
705 case WM8350_LDO_1:
706 volt_reg = WM8350_LDO1_LOW_POWER;
707 break;
708 case WM8350_LDO_2:
709 volt_reg = WM8350_LDO2_LOW_POWER;
710 break;
711 case WM8350_LDO_3:
712 volt_reg = WM8350_LDO3_LOW_POWER;
713 break;
714 case WM8350_LDO_4:
715 volt_reg = WM8350_LDO4_LOW_POWER;
716 break;
717 default:
718 return -EINVAL;
719 }
720
721 /* all LDOs have same mV bits */
722 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
723 wm8350_reg_write(wm8350, volt_reg, val);
724 return 0;
725}
726
727static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev)
728{
729 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
730 int volt_reg, ldo = rdev_get_id(rdev);
731 u16 val;
732
733 switch (ldo) {
734 case WM8350_LDO_1:
735 volt_reg = WM8350_LDO1_LOW_POWER;
736 break;
737 case WM8350_LDO_2:
738 volt_reg = WM8350_LDO2_LOW_POWER;
739 break;
740 case WM8350_LDO_3:
741 volt_reg = WM8350_LDO3_LOW_POWER;
742 break;
743 case WM8350_LDO_4:
744 volt_reg = WM8350_LDO4_LOW_POWER;
745 break;
746 default:
747 return -EINVAL;
748 }
749
750 /* all LDOs have same mV bits */
751 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
752 wm8350_reg_write(wm8350, volt_reg, WM8350_LDO1_HIB_MODE_DIS);
753 return 0;
754}
755
756static int wm8350_ldo_set_voltage(struct regulator_dev *rdev, int min_uV,
757 int max_uV)
758{
759 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
760 int volt_reg, ldo = rdev_get_id(rdev), mV, min_mV = min_uV / 1000,
761 max_mV = max_uV / 1000;
762 u16 val;
763
764 if (min_mV < 900 || min_mV > 3300)
765 return -EINVAL;
766 if (max_mV < 900 || max_mV > 3300)
767 return -EINVAL;
768
769 if (min_mV < 1800) {
770 /* step size is 50mV < 1800mV */
771 mV = (min_mV - 851) / 50;
772 if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
773 return -EINVAL;
774 BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
775 } else {
776 /* step size is 100mV > 1800mV */
777 mV = ((min_mV - 1701) / 100) + 16;
778 if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
779 return -EINVAL;
780 BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
781 }
782
783 switch (ldo) {
784 case WM8350_LDO_1:
785 volt_reg = WM8350_LDO1_CONTROL;
786 break;
787 case WM8350_LDO_2:
788 volt_reg = WM8350_LDO2_CONTROL;
789 break;
790 case WM8350_LDO_3:
791 volt_reg = WM8350_LDO3_CONTROL;
792 break;
793 case WM8350_LDO_4:
794 volt_reg = WM8350_LDO4_CONTROL;
795 break;
796 default:
797 return -EINVAL;
798 }
799
800 /* all LDOs have same mV bits */
801 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
802 wm8350_reg_write(wm8350, volt_reg, val | mV);
803 return 0;
804}
805
806static int wm8350_ldo_get_voltage(struct regulator_dev *rdev)
807{
808 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
809 int volt_reg, ldo = rdev_get_id(rdev);
810 u16 val;
811
812 switch (ldo) {
813 case WM8350_LDO_1:
814 volt_reg = WM8350_LDO1_CONTROL;
815 break;
816 case WM8350_LDO_2:
817 volt_reg = WM8350_LDO2_CONTROL;
818 break;
819 case WM8350_LDO_3:
820 volt_reg = WM8350_LDO3_CONTROL;
821 break;
822 case WM8350_LDO_4:
823 volt_reg = WM8350_LDO4_CONTROL;
824 break;
825 default:
826 return -EINVAL;
827 }
828
829 /* all LDOs have same mV bits */
830 val = wm8350_reg_read(wm8350, volt_reg) & WM8350_LDO1_VSEL_MASK;
831 return wm8350_ldo_val_to_mvolts(val) * 1000;
832}
833
221a7c7c
MB		 834static int wm8350_ldo_list_voltage(struct regulator_dev *rdev,
835 unsigned selector)
836{
837 if (selector > WM8350_LDO1_VSEL_MASK)
838 return -EINVAL;
839 return wm8350_ldo_val_to_mvolts(selector) * 1000;
840}
841
da09155a
MB		 842int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
843 u16 stop, u16 fault)
844{
845 int slot_reg;
846 u16 val;
847
848 dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
849 __func__, dcdc, start, stop);
850
851 /* slot valid ? */
852 if (start > 15 || stop > 15)
853 return -EINVAL;
854
855 switch (dcdc) {
856 case WM8350_DCDC_1:
857 slot_reg = WM8350_DCDC1_TIMEOUTS;
858 break;
859 case WM8350_DCDC_2:
860 slot_reg = WM8350_DCDC2_TIMEOUTS;
861 break;
862 case WM8350_DCDC_3:
863 slot_reg = WM8350_DCDC3_TIMEOUTS;
864 break;
865 case WM8350_DCDC_4:
866 slot_reg = WM8350_DCDC4_TIMEOUTS;
867 break;
868 case WM8350_DCDC_5:
869 slot_reg = WM8350_DCDC5_TIMEOUTS;
870 break;
871 case WM8350_DCDC_6:
872 slot_reg = WM8350_DCDC6_TIMEOUTS;
873 break;
874 default:
875 return -EINVAL;
876 }
877
878 val = wm8350_reg_read(wm8350, slot_reg) &
879 ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
880 WM8350_DC1_ERRACT_MASK);
881 wm8350_reg_write(wm8350, slot_reg,
882 val | (start << WM8350_DC1_ENSLOT_SHIFT) |
883 (stop << WM8350_DC1_SDSLOT_SHIFT) |
884 (fault << WM8350_DC1_ERRACT_SHIFT));
885
886 return 0;
887}
888EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot);
889
890int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop)
891{
892 int slot_reg;
893 u16 val;
894
895 dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
896 __func__, ldo, start, stop);
897
898 /* slot valid ? */
899 if (start > 15 || stop > 15)
900 return -EINVAL;
901
902 switch (ldo) {
903 case WM8350_LDO_1:
904 slot_reg = WM8350_LDO1_TIMEOUTS;
905 break;
906 case WM8350_LDO_2:
907 slot_reg = WM8350_LDO2_TIMEOUTS;
908 break;
909 case WM8350_LDO_3:
910 slot_reg = WM8350_LDO3_TIMEOUTS;
911 break;
912 case WM8350_LDO_4:
913 slot_reg = WM8350_LDO4_TIMEOUTS;
914 break;
915 default:
916 return -EINVAL;
917 }
918
919 val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK;
920 wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6)));
921 return 0;
922}
923EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot);
924
925int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
926 u16 ilim, u16 ramp, u16 feedback)
927{
928 u16 val;
929
930 dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc,
931 mode ? "normal" : "boost", ilim ? "low" : "normal");
932
933 switch (dcdc) {
934 case WM8350_DCDC_2:
935 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
936 & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK |
937 WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK);
938 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
939 (mode << WM8350_DC2_MODE_SHIFT) |
940 (ilim << WM8350_DC2_ILIM_SHIFT) |
941 (ramp << WM8350_DC2_RMP_SHIFT) |
942 (feedback << WM8350_DC2_FBSRC_SHIFT));
943 break;
944 case WM8350_DCDC_5:
945 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
946 & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK |
947 WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK);
948 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
949 (mode << WM8350_DC5_MODE_SHIFT) |
950 (ilim << WM8350_DC5_ILIM_SHIFT) |
951 (ramp << WM8350_DC5_RMP_SHIFT) |
952 (feedback << WM8350_DC5_FBSRC_SHIFT));
953 break;
954 default:
955 return -EINVAL;
956 }
957
958 return 0;
959}
960EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode);
961
962static int wm8350_dcdc_enable(struct regulator_dev *rdev)
963{
964 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
965 int dcdc = rdev_get_id(rdev);
966 u16 shift;
967
968 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
969 return -EINVAL;
970
971 shift = dcdc - WM8350_DCDC_1;
972 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
973 return 0;
974}
975
976static int wm8350_dcdc_disable(struct regulator_dev *rdev)
977{
978 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
979 int dcdc = rdev_get_id(rdev);
980 u16 shift;
981
982 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
983 return -EINVAL;
984
985 shift = dcdc - WM8350_DCDC_1;
986 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
987
988 return 0;
989}
990
991static int wm8350_ldo_enable(struct regulator_dev *rdev)
992{
993 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
994 int ldo = rdev_get_id(rdev);
995 u16 shift;
996
997 if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
998 return -EINVAL;
999
1000 shift = (ldo - WM8350_LDO_1) + 8;
1001 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
1002 return 0;
1003}
1004
1005static int wm8350_ldo_disable(struct regulator_dev *rdev)
1006{
1007 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1008 int ldo = rdev_get_id(rdev);
1009 u16 shift;
1010
1011 if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
1012 return -EINVAL;
1013
1014 shift = (ldo - WM8350_LDO_1) + 8;
1015 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
1016 return 0;
1017}
1018
1019static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable)
1020{
1021 int reg = 0, ret;
1022
1023 switch (dcdc) {
1024 case WM8350_DCDC_1:
1025 reg = WM8350_DCDC1_FORCE_PWM;
1026 break;
1027 case WM8350_DCDC_3:
1028 reg = WM8350_DCDC3_FORCE_PWM;
1029 break;
1030 case WM8350_DCDC_4:
1031 reg = WM8350_DCDC4_FORCE_PWM;
1032 break;
1033 case WM8350_DCDC_6:
1034 reg = WM8350_DCDC6_FORCE_PWM;
1035 break;
1036 default:
1037 return -EINVAL;
1038 }
1039
1040 if (enable)
1041 ret = wm8350_set_bits(wm8350, reg,
1042 WM8350_DCDC1_FORCE_PWM_ENA);
1043 else
1044 ret = wm8350_clear_bits(wm8350, reg,
1045 WM8350_DCDC1_FORCE_PWM_ENA);
1046 return ret;
1047}
1048
1049static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
1050{
1051 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1052 int dcdc = rdev_get_id(rdev);
1053 u16 val;
1054
1055 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
1056 return -EINVAL;
1057
1058 if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
1059 return -EINVAL;
1060
1061 val = 1 << (dcdc - WM8350_DCDC_1);
1062
1063 switch (mode) {
1064 case REGULATOR_MODE_FAST:
1065 /* force continuous mode */
1066 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1067 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1068 force_continuous_enable(wm8350, dcdc, 1);
1069 break;
1070 case REGULATOR_MODE_NORMAL:
1071 /* active / pulse skipping */
1072 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1073 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1074 force_continuous_enable(wm8350, dcdc, 0);
1075 break;
1076 case REGULATOR_MODE_IDLE:
1077 /* standby mode */
1078 force_continuous_enable(wm8350, dcdc, 0);
1079 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1080 wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1081 break;
1082 case REGULATOR_MODE_STANDBY:
1083 /* LDO mode */
1084 force_continuous_enable(wm8350, dcdc, 0);
1085 wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1086 break;
1087 }
1088
1089 return 0;
1090}
1091
1092static unsigned int wm8350_dcdc_get_mode(struct regulator_dev *rdev)
1093{
1094 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1095 int dcdc = rdev_get_id(rdev);
1096 u16 mask, sleep, active, force;
1097 int mode = REGULATOR_MODE_NORMAL;
33f301af 1098 int reg;
da09155a 1099
33f301af
MB		 1100 switch (dcdc) {
1101 case WM8350_DCDC_1:
1102 reg = WM8350_DCDC1_FORCE_PWM;
1103 break;
1104 case WM8350_DCDC_3:
1105 reg = WM8350_DCDC3_FORCE_PWM;
1106 break;
1107 case WM8350_DCDC_4:
1108 reg = WM8350_DCDC4_FORCE_PWM;
1109 break;
1110 case WM8350_DCDC_6:
1111 reg = WM8350_DCDC6_FORCE_PWM;
1112 break;
1113 default:
da09155a 1114 return -EINVAL;
33f301af 1115 }
da09155a
MB		 1116
1117 mask = 1 << (dcdc - WM8350_DCDC_1);
1118 active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask;
33f301af 1119 force = wm8350_reg_read(wm8350, reg) & WM8350_DCDC1_FORCE_PWM_ENA;
da09155a 1120 sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask;
33f301af 1121
da09155a
MB		 1122 dev_dbg(wm8350->dev, "mask %x active %x sleep %x force %x",
1123 mask, active, sleep, force);
1124
1125 if (active && !sleep) {
1126 if (force)
1127 mode = REGULATOR_MODE_FAST;
1128 else
1129 mode = REGULATOR_MODE_NORMAL;
1130 } else if (!active && !sleep)
1131 mode = REGULATOR_MODE_IDLE;
8ecee36a 1132 else if (sleep)
da09155a
MB		 1133 mode = REGULATOR_MODE_STANDBY;
1134
1135 return mode;
1136}
1137
1138static unsigned int wm8350_ldo_get_mode(struct regulator_dev *rdev)
1139{
1140 return REGULATOR_MODE_NORMAL;
1141}
1142
1143struct wm8350_dcdc_efficiency {
1144 int uA_load_min;
1145 int uA_load_max;
1146 unsigned int mode;
1147};
1148
1149static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = {
1150 {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */
1151 {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */
1152 {100000, 1000000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
1153 {-1, -1, REGULATOR_MODE_NORMAL},
1154};
1155
1156static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = {
1157 {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */
1158 {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */
1159 {100000, 800000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
1160 {-1, -1, REGULATOR_MODE_NORMAL},
1161};
1162
1163static unsigned int get_mode(int uA, const struct wm8350_dcdc_efficiency *eff)
1164{
1165 int i = 0;
1166
1167 while (eff[i].uA_load_min != -1) {
1168 if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max)
1169 return eff[i].mode;
1170 }
1171 return REGULATOR_MODE_NORMAL;
1172}
1173
1174/* Query the regulator for it's most efficient mode @ uV,uA
1175 * WM8350 regulator efficiency is pretty similar over
1176 * different input and output uV.
1177 */
1178static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator_dev *rdev,
1179 int input_uV, int output_uV,
1180 int output_uA)
1181{
1182 int dcdc = rdev_get_id(rdev), mode;
1183
1184 switch (dcdc) {
1185 case WM8350_DCDC_1:
1186 case WM8350_DCDC_6:
1187 mode = get_mode(output_uA, dcdc1_6_efficiency);
1188 break;
1189 case WM8350_DCDC_3:
1190 case WM8350_DCDC_4:
1191 mode = get_mode(output_uA, dcdc3_4_efficiency);
1192 break;
1193 default:
1194 mode = REGULATOR_MODE_NORMAL;
1195 break;
1196 }
1197 return mode;
1198}
1199
1200static int wm8350_dcdc_is_enabled(struct regulator_dev *rdev)
1201{
1202 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1203 int dcdc = rdev_get_id(rdev), shift;
1204
1205 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
1206 return -EINVAL;
1207
1208 shift = dcdc - WM8350_DCDC_1;
1209 return wm8350_reg_read(wm8350, WM8350_DCDC_LDO_REQUESTED)
1210 & (1 << shift);
1211}
1212
1213static int wm8350_ldo_is_enabled(struct regulator_dev *rdev)
1214{
1215 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1216 int ldo = rdev_get_id(rdev), shift;
1217
1218 if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
1219 return -EINVAL;
1220
1221 shift = (ldo - WM8350_LDO_1) + 8;
1222 return wm8350_reg_read(wm8350, WM8350_DCDC_LDO_REQUESTED)
1223 & (1 << shift);
1224}
1225
1226static struct regulator_ops wm8350_dcdc_ops = {
1227 .set_voltage = wm8350_dcdc_set_voltage,
1228 .get_voltage = wm8350_dcdc_get_voltage,
221a7c7c 1229 .list_voltage = wm8350_dcdc_list_voltage,
da09155a
MB		 1230 .enable = wm8350_dcdc_enable,
1231 .disable = wm8350_dcdc_disable,
1232 .get_mode = wm8350_dcdc_get_mode,
1233 .set_mode = wm8350_dcdc_set_mode,
1234 .get_optimum_mode = wm8350_dcdc_get_optimum_mode,
1235 .is_enabled = wm8350_dcdc_is_enabled,
1236 .set_suspend_voltage = wm8350_dcdc_set_suspend_voltage,
1237 .set_suspend_enable = wm8350_dcdc_set_suspend_enable,
1238 .set_suspend_disable = wm8350_dcdc_set_suspend_disable,
1239 .set_suspend_mode = wm8350_dcdc_set_suspend_mode,
1240};
1241
1242static struct regulator_ops wm8350_dcdc2_5_ops = {
1243 .enable = wm8350_dcdc_enable,
1244 .disable = wm8350_dcdc_disable,
1245 .is_enabled = wm8350_dcdc_is_enabled,
1246 .set_suspend_enable = wm8350_dcdc25_set_suspend_enable,
1247 .set_suspend_disable = wm8350_dcdc25_set_suspend_disable,
1248};
1249
1250static struct regulator_ops wm8350_ldo_ops = {
1251 .set_voltage = wm8350_ldo_set_voltage,
1252 .get_voltage = wm8350_ldo_get_voltage,
221a7c7c 1253 .list_voltage = wm8350_ldo_list_voltage,
da09155a
MB		 1254 .enable = wm8350_ldo_enable,
1255 .disable = wm8350_ldo_disable,
1256 .is_enabled = wm8350_ldo_is_enabled,
1257 .get_mode = wm8350_ldo_get_mode,
1258 .set_suspend_voltage = wm8350_ldo_set_suspend_voltage,
1259 .set_suspend_enable = wm8350_ldo_set_suspend_enable,
1260 .set_suspend_disable = wm8350_ldo_set_suspend_disable,
1261};
1262
1263static struct regulator_ops wm8350_isink_ops = {
1264 .set_current_limit = wm8350_isink_set_current,
1265 .get_current_limit = wm8350_isink_get_current,
1266 .enable = wm8350_isink_enable,
1267 .disable = wm8350_isink_disable,
1268 .is_enabled = wm8350_isink_is_enabled,
75c8ac22 1269 .enable_time = wm8350_isink_enable_time,
da09155a
MB		 1270};
1271
1272static struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = {
1273 {
1274 .name = "DCDC1",
1275 .id = WM8350_DCDC_1,
1276 .ops = &wm8350_dcdc_ops,
1277 .irq = WM8350_IRQ_UV_DC1,
1278 .type = REGULATOR_VOLTAGE,
221a7c7c 1279 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
da09155a
MB		 1280 .owner = THIS_MODULE,
1281 },
1282 {
1283 .name = "DCDC2",
1284 .id = WM8350_DCDC_2,
1285 .ops = &wm8350_dcdc2_5_ops,
1286 .irq = WM8350_IRQ_UV_DC2,
1287 .type = REGULATOR_VOLTAGE,
1288 .owner = THIS_MODULE,
1289 },
1290 {
1291 .name = "DCDC3",
1292 .id = WM8350_DCDC_3,
1293 .ops = &wm8350_dcdc_ops,
1294 .irq = WM8350_IRQ_UV_DC3,
1295 .type = REGULATOR_VOLTAGE,
221a7c7c 1296 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
da09155a
MB		 1297 .owner = THIS_MODULE,
1298 },
1299 {
1300 .name = "DCDC4",
1301 .id = WM8350_DCDC_4,
1302 .ops = &wm8350_dcdc_ops,
1303 .irq = WM8350_IRQ_UV_DC4,
1304 .type = REGULATOR_VOLTAGE,
221a7c7c 1305 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
da09155a
MB		 1306 .owner = THIS_MODULE,
1307 },
1308 {
1309 .name = "DCDC5",
1310 .id = WM8350_DCDC_5,
1311 .ops = &wm8350_dcdc2_5_ops,
1312 .irq = WM8350_IRQ_UV_DC5,
1313 .type = REGULATOR_VOLTAGE,
1314 .owner = THIS_MODULE,
1315 },
1316 {
1317 .name = "DCDC6",
1318 .id = WM8350_DCDC_6,
1319 .ops = &wm8350_dcdc_ops,
1320 .irq = WM8350_IRQ_UV_DC6,
1321 .type = REGULATOR_VOLTAGE,
221a7c7c 1322 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
da09155a
MB		 1323 .owner = THIS_MODULE,
1324 },
1325 {
1326 .name = "LDO1",
1327 .id = WM8350_LDO_1,
1328 .ops = &wm8350_ldo_ops,
1329 .irq = WM8350_IRQ_UV_LDO1,
1330 .type = REGULATOR_VOLTAGE,
221a7c7c 1331 .n_voltages = WM8350_LDO1_VSEL_MASK + 1,
da09155a
MB		 1332 .owner = THIS_MODULE,
1333 },
1334 {
1335 .name = "LDO2",
1336 .id = WM8350_LDO_2,
1337 .ops = &wm8350_ldo_ops,
1338 .irq = WM8350_IRQ_UV_LDO2,
1339 .type = REGULATOR_VOLTAGE,
221a7c7c 1340 .n_voltages = WM8350_LDO2_VSEL_MASK + 1,
da09155a
MB		 1341 .owner = THIS_MODULE,
1342 },
1343 {
1344 .name = "LDO3",
1345 .id = WM8350_LDO_3,
1346 .ops = &wm8350_ldo_ops,
1347 .irq = WM8350_IRQ_UV_LDO3,
1348 .type = REGULATOR_VOLTAGE,
221a7c7c 1349 .n_voltages = WM8350_LDO3_VSEL_MASK + 1,
da09155a
MB		 1350 .owner = THIS_MODULE,
1351 },
1352 {
1353 .name = "LDO4",
1354 .id = WM8350_LDO_4,
1355 .ops = &wm8350_ldo_ops,
1356 .irq = WM8350_IRQ_UV_LDO4,
1357 .type = REGULATOR_VOLTAGE,
221a7c7c 1358 .n_voltages = WM8350_LDO4_VSEL_MASK + 1,
da09155a
MB		 1359 .owner = THIS_MODULE,
1360 },
1361 {
1362 .name = "ISINKA",
1363 .id = WM8350_ISINK_A,
1364 .ops = &wm8350_isink_ops,
1365 .irq = WM8350_IRQ_CS1,
1366 .type = REGULATOR_CURRENT,
1367 .owner = THIS_MODULE,
1368 },
1369 {
1370 .name = "ISINKB",
1371 .id = WM8350_ISINK_B,
1372 .ops = &wm8350_isink_ops,
1373 .irq = WM8350_IRQ_CS2,
1374 .type = REGULATOR_CURRENT,
1375 .owner = THIS_MODULE,
1376 },
1377};
1378
5a65edbc 1379static irqreturn_t pmic_uv_handler(int irq, void *data)
da09155a
MB		 1380{
1381 struct regulator_dev *rdev = (struct regulator_dev *)data;
5a65edbc 1382 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
da09155a 1383
b136fb44 1384 mutex_lock(&rdev->mutex);
da09155a
MB		 1385 if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2)
1386 regulator_notifier_call_chain(rdev,
1387 REGULATOR_EVENT_REGULATION_OUT,
1388 wm8350);
1389 else
1390 regulator_notifier_call_chain(rdev,
1391 REGULATOR_EVENT_UNDER_VOLTAGE,
1392 wm8350);
b136fb44 1393 mutex_unlock(&rdev->mutex);
5a65edbc
MB		 1394
1395 return IRQ_HANDLED;
da09155a
MB		 1396}
1397
1398static int wm8350_regulator_probe(struct platform_device *pdev)
1399{
1400 struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev);
1401 struct regulator_dev *rdev;
1402 int ret;
1403 u16 val;
1404
1405 if (pdev->id < WM8350_DCDC_1 || pdev->id > WM8350_ISINK_B)
1406 return -ENODEV;
1407
1408 /* do any regulatior specific init */
1409 switch (pdev->id) {
1410 case WM8350_DCDC_1:
1411 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
1412 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1413 break;
1414 case WM8350_DCDC_3:
1415 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
1416 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1417 break;
1418 case WM8350_DCDC_4:
1419 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
1420 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1421 break;
1422 case WM8350_DCDC_6:
1423 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
1424 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1425 break;
1426 }
1427
da09155a
MB		 1428 /* register regulator */
1429 rdev = regulator_register(&wm8350_reg[pdev->id], &pdev->dev,
0527100f 1430 pdev->dev.platform_data,
da09155a
MB		 1431 dev_get_drvdata(&pdev->dev));
1432 if (IS_ERR(rdev)) {
1433 dev_err(&pdev->dev, "failed to register %s\n",
1434 wm8350_reg[pdev->id].name);
1435 return PTR_ERR(rdev);
1436 }
1437
1438 /* register regulator IRQ */
1439 ret = wm8350_register_irq(wm8350, wm8350_reg[pdev->id].irq,
5a65edbc 1440 pmic_uv_handler, 0, "UV", rdev);
da09155a
MB		 1441 if (ret < 0) {
1442 regulator_unregister(rdev);
1443 dev_err(&pdev->dev, "failed to register regulator %s IRQ\n",
1444 wm8350_reg[pdev->id].name);
1445 return ret;
1446 }
1447
da09155a
MB		 1448 return 0;
1449}
1450
1451static int wm8350_regulator_remove(struct platform_device *pdev)
1452{
1453 struct regulator_dev *rdev = platform_get_drvdata(pdev);
1454 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1455
f99344fc 1456 wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq, rdev);
da09155a
MB		 1457
1458 regulator_unregister(rdev);
1459
1460 return 0;
1461}
1462
1463int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
1464 struct regulator_init_data *initdata)
1465{
1466 struct platform_device *pdev;
1467 int ret;
4dee4d44
RK		 1468 if (reg < 0 || reg >= NUM_WM8350_REGULATORS)
1469 return -EINVAL;
da09155a
MB		 1470
1471 if (wm8350->pmic.pdev[reg])
1472 return -EBUSY;
1473
645524a9
MB		 1474 if (reg >= WM8350_DCDC_1 && reg <= WM8350_DCDC_6 &&
1475 reg > wm8350->pmic.max_dcdc)
1476 return -ENODEV;
1477 if (reg >= WM8350_ISINK_A && reg <= WM8350_ISINK_B &&
1478 reg > wm8350->pmic.max_isink)
1479 return -ENODEV;
1480
da09155a
MB		 1481 pdev = platform_device_alloc("wm8350-regulator", reg);
1482 if (!pdev)
1483 return -ENOMEM;
1484
1485 wm8350->pmic.pdev[reg] = pdev;
1486
1487 initdata->driver_data = wm8350;
1488
1489 pdev->dev.platform_data = initdata;
1490 pdev->dev.parent = wm8350->dev;
1491 platform_set_drvdata(pdev, wm8350);
1492
1493 ret = platform_device_add(pdev);
1494
1495 if (ret != 0) {
1496 dev_err(wm8350->dev, "Failed to register regulator %d: %d\n",
1497 reg, ret);
e9a1c512 1498 platform_device_put(pdev);
da09155a
MB		 1499 wm8350->pmic.pdev[reg] = NULL;
1500 }
1501
1502 return ret;
1503}
1504EXPORT_SYMBOL_GPL(wm8350_register_regulator);
1505
0081e802
MB		 1506/**
1507 * wm8350_register_led - Register a WM8350 LED output
1508 *
1509 * @param wm8350 The WM8350 device to configure.
1510 * @param lednum LED device index to create.
1511 * @param dcdc The DCDC to use for the LED.
1512 * @param isink The ISINK to use for the LED.
1513 * @param pdata Configuration for the LED.
1514 *
1515 * The WM8350 supports the use of an ISINK together with a DCDC to
1516 * provide a power-efficient LED driver. This function registers the
1517 * regulators and instantiates the platform device for a LED. The
1518 * operating modes for the LED regulators must be configured using
1519 * wm8350_isink_set_flash(), wm8350_dcdc25_set_mode() and
1520 * wm8350_dcdc_set_slot() prior to calling this function.
1521 */
1522int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
1523 struct wm8350_led_platform_data *pdata)
1524{
1525 struct wm8350_led *led;
1526 struct platform_device *pdev;
1527 int ret;
1528
8dd2c9e3 1529 if (lednum >= ARRAY_SIZE(wm8350->pmic.led) || lednum < 0) {
0081e802
MB		 1530 dev_err(wm8350->dev, "Invalid LED index %d\n", lednum);
1531 return -ENODEV;
1532 }
1533
1534 led = &wm8350->pmic.led[lednum];
1535
1536 if (led->pdev) {
1537 dev_err(wm8350->dev, "LED %d already allocated\n", lednum);
1538 return -EINVAL;
1539 }
1540
1541 pdev = platform_device_alloc("wm8350-led", lednum);
1542 if (pdev == NULL) {
1543 dev_err(wm8350->dev, "Failed to allocate LED %d\n", lednum);
1544 return -ENOMEM;
1545 }
1546
1547 led->isink_consumer.dev = &pdev->dev;
1548 led->isink_consumer.supply = "led_isink";
1549 led->isink_init.num_consumer_supplies = 1;
1550 led->isink_init.consumer_supplies = &led->isink_consumer;
1551 led->isink_init.constraints.min_uA = 0;
1552 led->isink_init.constraints.max_uA = pdata->max_uA;
a2fad9bf
MB		 1553 led->isink_init.constraints.valid_ops_mask
1554 = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS;
0081e802
MB		 1555 led->isink_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1556 ret = wm8350_register_regulator(wm8350, isink, &led->isink_init);
1557 if (ret != 0) {
1558 platform_device_put(pdev);
1559 return ret;
1560 }
1561
1562 led->dcdc_consumer.dev = &pdev->dev;
1563 led->dcdc_consumer.supply = "led_vcc";
1564 led->dcdc_init.num_consumer_supplies = 1;
1565 led->dcdc_init.consumer_supplies = &led->dcdc_consumer;
1566 led->dcdc_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
a2fad9bf 1567 led->dcdc_init.constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
0081e802
MB		 1568 ret = wm8350_register_regulator(wm8350, dcdc, &led->dcdc_init);
1569 if (ret != 0) {
1570 platform_device_put(pdev);
1571 return ret;
1572 }
1573
1574 switch (isink) {
1575 case WM8350_ISINK_A:
1576 wm8350->pmic.isink_A_dcdc = dcdc;
1577 break;
1578 case WM8350_ISINK_B:
1579 wm8350->pmic.isink_B_dcdc = dcdc;
1580 break;
1581 }
1582
1583 pdev->dev.platform_data = pdata;
1584 pdev->dev.parent = wm8350->dev;
1585 ret = platform_device_add(pdev);
1586 if (ret != 0) {
1587 dev_err(wm8350->dev, "Failed to register LED %d: %d\n",
1588 lednum, ret);
1589 platform_device_put(pdev);
1590 return ret;
1591 }
1592
1593 led->pdev = pdev;
1594
1595 return 0;
1596}
1597EXPORT_SYMBOL_GPL(wm8350_register_led);
1598
da09155a
MB		 1599static struct platform_driver wm8350_regulator_driver = {
1600 .probe = wm8350_regulator_probe,
1601 .remove = wm8350_regulator_remove,
1602 .driver = {
1603 .name = "wm8350-regulator",
1604 },
1605};
1606
1607static int __init wm8350_regulator_init(void)
1608{
1609 return platform_driver_register(&wm8350_regulator_driver);
1610}
1611subsys_initcall(wm8350_regulator_init);
1612
1613static void __exit wm8350_regulator_exit(void)
1614{
1615 platform_driver_unregister(&wm8350_regulator_driver);
1616}
1617module_exit(wm8350_regulator_exit);
1618
1619/* Module information */
1620MODULE_AUTHOR("Liam Girdwood");
1621MODULE_DESCRIPTION("WM8350 voltage and current regulator driver");
1622MODULE_LICENSE("GPL");
38c53c89 1623MODULE_ALIAS("platform:wm8350-regulator");
Clone of davem's net-next-2.6 tree