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fa16a5c1 1/*
c4aa6f31 2 * twl-regulator.c -- support regulators in twl4030/twl6030 family chips
fa16a5c1
DB
3 *
4 * Copyright (C) 2008 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/err.h>
53b8a9d9 15#include <linux/delay.h>
fa16a5c1
DB
16#include <linux/platform_device.h>
17#include <linux/regulator/driver.h>
18#include <linux/regulator/machine.h>
b07682b6 19#include <linux/i2c/twl.h>
fa16a5c1
DB
20
21
22/*
c4aa6f31 23 * The TWL4030/TW5030/TPS659x0/TWL6030 family chips include power management, a
fa16a5c1
DB
24 * USB OTG transceiver, an RTC, ADC, PWM, and lots more. Some versions
25 * include an audio codec, battery charger, and more voltage regulators.
26 * These chips are often used in OMAP-based systems.
27 *
28 * This driver implements software-based resource control for various
29 * voltage regulators. This is usually augmented with state machine
30 * based control.
31 */
32
33struct twlreg_info {
34 /* start of regulator's PM_RECEIVER control register bank */
35 u8 base;
36
c4aa6f31 37 /* twl resource ID, for resource control state machine */
fa16a5c1
DB
38 u8 id;
39
40 /* voltage in mV = table[VSEL]; table_len must be a power-of-two */
41 u8 table_len;
42 const u16 *table;
43
045f972f
JKS
44 /* regulator specific turn-on delay */
45 u16 delay;
46
47 /* State REMAP default configuration */
48 u8 remap;
49
fa16a5c1
DB
50 /* chip constraints on regulator behavior */
51 u16 min_mV;
3e3d3be7 52 u16 max_mV;
fa16a5c1
DB
53
54 /* used by regulator core */
55 struct regulator_desc desc;
56};
57
58
59/* LDO control registers ... offset is from the base of its register bank.
60 * The first three registers of all power resource banks help hardware to
61 * manage the various resource groups.
62 */
441a4505 63/* Common offset in TWL4030/6030 */
fa16a5c1 64#define VREG_GRP 0
441a4505 65/* TWL4030 register offsets */
fa16a5c1
DB
66#define VREG_TYPE 1
67#define VREG_REMAP 2
68#define VREG_DEDICATED 3 /* LDO control */
441a4505
RN
69/* TWL6030 register offsets */
70#define VREG_TRANS 1
71#define VREG_STATE 2
72#define VREG_VOLTAGE 3
73/* TWL6030 Misc register offsets */
74#define VREG_BC_ALL 1
75#define VREG_BC_REF 2
76#define VREG_BC_PROC 3
77#define VREG_BC_CLK_RST 4
fa16a5c1
DB
78
79static inline int
441a4505 80twlreg_read(struct twlreg_info *info, unsigned slave_subgp, unsigned offset)
fa16a5c1
DB
81{
82 u8 value;
83 int status;
84
441a4505 85 status = twl_i2c_read_u8(slave_subgp,
fa16a5c1
DB
86 &value, info->base + offset);
87 return (status < 0) ? status : value;
88}
89
90static inline int
441a4505
RN
91twlreg_write(struct twlreg_info *info, unsigned slave_subgp, unsigned offset,
92 u8 value)
fa16a5c1 93{
441a4505 94 return twl_i2c_write_u8(slave_subgp,
fa16a5c1
DB
95 value, info->base + offset);
96}
97
98/*----------------------------------------------------------------------*/
99
100/* generic power resource operations, which work on all regulators */
101
c4aa6f31 102static int twlreg_grp(struct regulator_dev *rdev)
fa16a5c1 103{
441a4505
RN
104 return twlreg_read(rdev_get_drvdata(rdev), TWL_MODULE_PM_RECEIVER,
105 VREG_GRP);
fa16a5c1
DB
106}
107
108/*
109 * Enable/disable regulators by joining/leaving the P1 (processor) group.
110 * We assume nobody else is updating the DEV_GRP registers.
111 */
441a4505
RN
112/* definition for 4030 family */
113#define P3_GRP_4030 BIT(7) /* "peripherals" */
114#define P2_GRP_4030 BIT(6) /* secondary processor, modem, etc */
115#define P1_GRP_4030 BIT(5) /* CPU/Linux */
116/* definition for 6030 family */
117#define P3_GRP_6030 BIT(2) /* secondary processor, modem, etc */
118#define P2_GRP_6030 BIT(1) /* "peripherals" */
119#define P1_GRP_6030 BIT(0) /* CPU/Linux */
fa16a5c1 120
c4aa6f31 121static int twlreg_is_enabled(struct regulator_dev *rdev)
fa16a5c1 122{
c4aa6f31 123 int state = twlreg_grp(rdev);
fa16a5c1
DB
124
125 if (state < 0)
126 return state;
127
441a4505
RN
128 if (twl_class_is_4030())
129 state &= P1_GRP_4030;
130 else
131 state &= P1_GRP_6030;
132 return state;
fa16a5c1
DB
133}
134
c4aa6f31 135static int twlreg_enable(struct regulator_dev *rdev)
fa16a5c1
DB
136{
137 struct twlreg_info *info = rdev_get_drvdata(rdev);
138 int grp;
53b8a9d9 139 int ret;
fa16a5c1 140
441a4505 141 grp = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_GRP);
fa16a5c1
DB
142 if (grp < 0)
143 return grp;
144
441a4505
RN
145 if (twl_class_is_4030())
146 grp |= P1_GRP_4030;
147 else
148 grp |= P1_GRP_6030;
149
53b8a9d9
JKS
150 ret = twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_GRP, grp);
151
152 udelay(info->delay);
153
154 return ret;
fa16a5c1
DB
155}
156
c4aa6f31 157static int twlreg_disable(struct regulator_dev *rdev)
fa16a5c1
DB
158{
159 struct twlreg_info *info = rdev_get_drvdata(rdev);
160 int grp;
161
441a4505 162 grp = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_GRP);
fa16a5c1
DB
163 if (grp < 0)
164 return grp;
165
441a4505 166 if (twl_class_is_4030())
cf9836f4 167 grp &= ~(P1_GRP_4030 | P2_GRP_4030 | P3_GRP_4030);
441a4505 168 else
cf9836f4 169 grp &= ~(P1_GRP_6030 | P2_GRP_6030 | P3_GRP_6030);
441a4505
RN
170
171 return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_GRP, grp);
fa16a5c1
DB
172}
173
c4aa6f31 174static int twlreg_get_status(struct regulator_dev *rdev)
fa16a5c1 175{
c4aa6f31 176 int state = twlreg_grp(rdev);
fa16a5c1 177
441a4505
RN
178 if (twl_class_is_6030())
179 return 0; /* FIXME return for 6030 regulator */
180
fa16a5c1
DB
181 if (state < 0)
182 return state;
183 state &= 0x0f;
184
185 /* assume state != WARM_RESET; we'd not be running... */
186 if (!state)
187 return REGULATOR_STATUS_OFF;
188 return (state & BIT(3))
189 ? REGULATOR_STATUS_NORMAL
190 : REGULATOR_STATUS_STANDBY;
191}
192
c4aa6f31 193static int twlreg_set_mode(struct regulator_dev *rdev, unsigned mode)
fa16a5c1
DB
194{
195 struct twlreg_info *info = rdev_get_drvdata(rdev);
196 unsigned message;
197 int status;
198
441a4505
RN
199 if (twl_class_is_6030())
200 return 0; /* FIXME return for 6030 regulator */
201
fa16a5c1
DB
202 /* We can only set the mode through state machine commands... */
203 switch (mode) {
204 case REGULATOR_MODE_NORMAL:
205 message = MSG_SINGULAR(DEV_GRP_P1, info->id, RES_STATE_ACTIVE);
206 break;
207 case REGULATOR_MODE_STANDBY:
208 message = MSG_SINGULAR(DEV_GRP_P1, info->id, RES_STATE_SLEEP);
209 break;
210 default:
211 return -EINVAL;
212 }
213
214 /* Ensure the resource is associated with some group */
c4aa6f31 215 status = twlreg_grp(rdev);
fa16a5c1
DB
216 if (status < 0)
217 return status;
441a4505 218 if (!(status & (P3_GRP_4030 | P2_GRP_4030 | P1_GRP_4030)))
fa16a5c1
DB
219 return -EACCES;
220
c4aa6f31 221 status = twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
fa16a5c1
DB
222 message >> 8, 0x15 /* PB_WORD_MSB */ );
223 if (status >= 0)
224 return status;
225
c4aa6f31 226 return twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
fa16a5c1
DB
227 message, 0x16 /* PB_WORD_LSB */ );
228}
229
230/*----------------------------------------------------------------------*/
231
232/*
233 * Support for adjustable-voltage LDOs uses a four bit (or less) voltage
234 * select field in its control register. We use tables indexed by VSEL
235 * to record voltages in milliVolts. (Accuracy is about three percent.)
236 *
237 * Note that VSEL values for VAUX2 changed in twl5030 and newer silicon;
238 * currently handled by listing two slightly different VAUX2 regulators,
239 * only one of which will be configured.
240 *
241 * VSEL values documented as "TI cannot support these values" are flagged
242 * in these tables as UNSUP() values; we normally won't assign them.
d6bb69cf
AH
243 *
244 * VAUX3 at 3V is incorrectly listed in some TI manuals as unsupported.
245 * TI are revising the twl5030/tps659x0 specs to support that 3.0V setting.
fa16a5c1
DB
246 */
247#ifdef CONFIG_TWL4030_ALLOW_UNSUPPORTED
248#define UNSUP_MASK 0x0000
249#else
250#define UNSUP_MASK 0x8000
251#endif
252
253#define UNSUP(x) (UNSUP_MASK | (x))
254#define IS_UNSUP(x) (UNSUP_MASK & (x))
255#define LDO_MV(x) (~UNSUP_MASK & (x))
256
257
258static const u16 VAUX1_VSEL_table[] = {
259 UNSUP(1500), UNSUP(1800), 2500, 2800,
260 3000, 3000, 3000, 3000,
261};
262static const u16 VAUX2_4030_VSEL_table[] = {
263 UNSUP(1000), UNSUP(1000), UNSUP(1200), 1300,
264 1500, 1800, UNSUP(1850), 2500,
265 UNSUP(2600), 2800, UNSUP(2850), UNSUP(3000),
266 UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150),
267};
268static const u16 VAUX2_VSEL_table[] = {
269 1700, 1700, 1900, 1300,
270 1500, 1800, 2000, 2500,
271 2100, 2800, 2200, 2300,
272 2400, 2400, 2400, 2400,
273};
274static const u16 VAUX3_VSEL_table[] = {
275 1500, 1800, 2500, 2800,
d6bb69cf 276 3000, 3000, 3000, 3000,
fa16a5c1
DB
277};
278static const u16 VAUX4_VSEL_table[] = {
279 700, 1000, 1200, UNSUP(1300),
280 1500, 1800, UNSUP(1850), 2500,
1897e742
DB
281 UNSUP(2600), 2800, UNSUP(2850), UNSUP(3000),
282 UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150),
fa16a5c1
DB
283};
284static const u16 VMMC1_VSEL_table[] = {
285 1850, 2850, 3000, 3150,
286};
287static const u16 VMMC2_VSEL_table[] = {
288 UNSUP(1000), UNSUP(1000), UNSUP(1200), UNSUP(1300),
289 UNSUP(1500), UNSUP(1800), 1850, UNSUP(2500),
290 2600, 2800, 2850, 3000,
291 3150, 3150, 3150, 3150,
292};
293static const u16 VPLL1_VSEL_table[] = {
294 1000, 1200, 1300, 1800,
295 UNSUP(2800), UNSUP(3000), UNSUP(3000), UNSUP(3000),
296};
297static const u16 VPLL2_VSEL_table[] = {
298 700, 1000, 1200, 1300,
299 UNSUP(1500), 1800, UNSUP(1850), UNSUP(2500),
300 UNSUP(2600), UNSUP(2800), UNSUP(2850), UNSUP(3000),
301 UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150),
302};
303static const u16 VSIM_VSEL_table[] = {
304 UNSUP(1000), UNSUP(1200), UNSUP(1300), 1800,
305 2800, 3000, 3000, 3000,
306};
307static const u16 VDAC_VSEL_table[] = {
308 1200, 1300, 1800, 1800,
309};
07fc493f
JKS
310static const u16 VDD1_VSEL_table[] = {
311 800, 1450,
312};
313static const u16 VDD2_VSEL_table[] = {
314 800, 1450, 1500,
315};
316static const u16 VIO_VSEL_table[] = {
317 1800, 1850,
318};
319static const u16 VINTANA2_VSEL_table[] = {
320 2500, 2750,
321};
fa16a5c1 322
3e3d3be7 323static int twl4030ldo_list_voltage(struct regulator_dev *rdev, unsigned index)
66b659e6
DB
324{
325 struct twlreg_info *info = rdev_get_drvdata(rdev);
326 int mV = info->table[index];
327
328 return IS_UNSUP(mV) ? 0 : (LDO_MV(mV) * 1000);
329}
330
fa16a5c1 331static int
3e3d3be7 332twl4030ldo_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV)
fa16a5c1
DB
333{
334 struct twlreg_info *info = rdev_get_drvdata(rdev);
335 int vsel;
336
337 for (vsel = 0; vsel < info->table_len; vsel++) {
338 int mV = info->table[vsel];
339 int uV;
340
341 if (IS_UNSUP(mV))
342 continue;
343 uV = LDO_MV(mV) * 1000;
344
66b659e6
DB
345 /* REVISIT for VAUX2, first match may not be best/lowest */
346
fa16a5c1
DB
347 /* use the first in-range value */
348 if (min_uV <= uV && uV <= max_uV)
441a4505
RN
349 return twlreg_write(info, TWL_MODULE_PM_RECEIVER,
350 VREG_VOLTAGE, vsel);
fa16a5c1
DB
351 }
352
353 return -EDOM;
354}
355
3e3d3be7 356static int twl4030ldo_get_voltage(struct regulator_dev *rdev)
fa16a5c1
DB
357{
358 struct twlreg_info *info = rdev_get_drvdata(rdev);
441a4505
RN
359 int vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER,
360 VREG_VOLTAGE);
fa16a5c1
DB
361
362 if (vsel < 0)
363 return vsel;
364
365 vsel &= info->table_len - 1;
366 return LDO_MV(info->table[vsel]) * 1000;
367}
368
3e3d3be7
RN
369static struct regulator_ops twl4030ldo_ops = {
370 .list_voltage = twl4030ldo_list_voltage,
66b659e6 371
3e3d3be7
RN
372 .set_voltage = twl4030ldo_set_voltage,
373 .get_voltage = twl4030ldo_get_voltage,
374
375 .enable = twlreg_enable,
376 .disable = twlreg_disable,
377 .is_enabled = twlreg_is_enabled,
378
379 .set_mode = twlreg_set_mode,
380
381 .get_status = twlreg_get_status,
382};
383
384static int twl6030ldo_list_voltage(struct regulator_dev *rdev, unsigned index)
385{
386 struct twlreg_info *info = rdev_get_drvdata(rdev);
387
388 return ((info->min_mV + (index * 100)) * 1000);
389}
390
391static int
392twl6030ldo_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV)
393{
394 struct twlreg_info *info = rdev_get_drvdata(rdev);
395 int vsel;
396
397 if ((min_uV/1000 < info->min_mV) || (max_uV/1000 > info->max_mV))
398 return -EDOM;
399
400 /*
401 * Use the below formula to calculate vsel
402 * mV = 1000mv + 100mv * (vsel - 1)
403 */
404 vsel = (min_uV/1000 - 1000)/100 + 1;
405 return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE, vsel);
406
407}
408
409static int twl6030ldo_get_voltage(struct regulator_dev *rdev)
410{
411 struct twlreg_info *info = rdev_get_drvdata(rdev);
412 int vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER,
413 VREG_VOLTAGE);
414
415 if (vsel < 0)
416 return vsel;
417
418 /*
419 * Use the below formula to calculate vsel
420 * mV = 1000mv + 100mv * (vsel - 1)
421 */
422 return (1000 + (100 * (vsel - 1))) * 1000;
423}
424
425static struct regulator_ops twl6030ldo_ops = {
426 .list_voltage = twl6030ldo_list_voltage,
427
428 .set_voltage = twl6030ldo_set_voltage,
429 .get_voltage = twl6030ldo_get_voltage,
fa16a5c1 430
c4aa6f31
RN
431 .enable = twlreg_enable,
432 .disable = twlreg_disable,
433 .is_enabled = twlreg_is_enabled,
fa16a5c1 434
c4aa6f31 435 .set_mode = twlreg_set_mode,
fa16a5c1 436
c4aa6f31 437 .get_status = twlreg_get_status,
fa16a5c1
DB
438};
439
440/*----------------------------------------------------------------------*/
441
442/*
443 * Fixed voltage LDOs don't have a VSEL field to update.
444 */
c4aa6f31 445static int twlfixed_list_voltage(struct regulator_dev *rdev, unsigned index)
66b659e6
DB
446{
447 struct twlreg_info *info = rdev_get_drvdata(rdev);
448
449 return info->min_mV * 1000;
450}
451
c4aa6f31 452static int twlfixed_get_voltage(struct regulator_dev *rdev)
fa16a5c1
DB
453{
454 struct twlreg_info *info = rdev_get_drvdata(rdev);
455
456 return info->min_mV * 1000;
457}
458
c4aa6f31
RN
459static struct regulator_ops twlfixed_ops = {
460 .list_voltage = twlfixed_list_voltage,
66b659e6 461
c4aa6f31 462 .get_voltage = twlfixed_get_voltage,
fa16a5c1 463
c4aa6f31
RN
464 .enable = twlreg_enable,
465 .disable = twlreg_disable,
466 .is_enabled = twlreg_is_enabled,
fa16a5c1 467
c4aa6f31 468 .set_mode = twlreg_set_mode,
fa16a5c1 469
c4aa6f31 470 .get_status = twlreg_get_status,
fa16a5c1
DB
471};
472
473/*----------------------------------------------------------------------*/
474
045f972f
JKS
475#define TWL4030_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \
476 remap_conf) \
477 TWL_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \
478 remap_conf, TWL4030)
045f972f
JKS
479#define TWL6030_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \
480 remap_conf) \
481 TWL_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \
482 remap_conf, TWL6030)
483
3e3d3be7 484#define TWL4030_ADJUSTABLE_LDO(label, offset, num, turnon_delay, remap_conf) { \
fa16a5c1
DB
485 .base = offset, \
486 .id = num, \
487 .table_len = ARRAY_SIZE(label##_VSEL_table), \
488 .table = label##_VSEL_table, \
045f972f
JKS
489 .delay = turnon_delay, \
490 .remap = remap_conf, \
fa16a5c1
DB
491 .desc = { \
492 .name = #label, \
3e3d3be7 493 .id = TWL4030_REG_##label, \
66b659e6 494 .n_voltages = ARRAY_SIZE(label##_VSEL_table), \
3e3d3be7
RN
495 .ops = &twl4030ldo_ops, \
496 .type = REGULATOR_VOLTAGE, \
497 .owner = THIS_MODULE, \
498 }, \
499 }
500
501#define TWL6030_ADJUSTABLE_LDO(label, offset, min_mVolts, max_mVolts, num, \
502 remap_conf) { \
503 .base = offset, \
504 .id = num, \
505 .min_mV = min_mVolts, \
506 .max_mV = max_mVolts, \
507 .remap = remap_conf, \
508 .desc = { \
509 .name = #label, \
510 .id = TWL6030_REG_##label, \
511 .n_voltages = (max_mVolts - min_mVolts)/100, \
512 .ops = &twl6030ldo_ops, \
fa16a5c1
DB
513 .type = REGULATOR_VOLTAGE, \
514 .owner = THIS_MODULE, \
515 }, \
516 }
517
3e3d3be7 518
045f972f
JKS
519#define TWL_FIXED_LDO(label, offset, mVolts, num, turnon_delay, remap_conf, \
520 family) { \
fa16a5c1
DB
521 .base = offset, \
522 .id = num, \
523 .min_mV = mVolts, \
045f972f
JKS
524 .delay = turnon_delay, \
525 .remap = remap_conf, \
fa16a5c1
DB
526 .desc = { \
527 .name = #label, \
c4aa6f31 528 .id = family##_REG_##label, \
66b659e6 529 .n_voltages = 1, \
c4aa6f31 530 .ops = &twlfixed_ops, \
fa16a5c1
DB
531 .type = REGULATOR_VOLTAGE, \
532 .owner = THIS_MODULE, \
533 }, \
534 }
535
536/*
537 * We list regulators here if systems need some level of
538 * software control over them after boot.
539 */
c4aa6f31 540static struct twlreg_info twl_regs[] = {
045f972f
JKS
541 TWL4030_ADJUSTABLE_LDO(VAUX1, 0x17, 1, 100, 0x08),
542 TWL4030_ADJUSTABLE_LDO(VAUX2_4030, 0x1b, 2, 100, 0x08),
543 TWL4030_ADJUSTABLE_LDO(VAUX2, 0x1b, 2, 100, 0x08),
544 TWL4030_ADJUSTABLE_LDO(VAUX3, 0x1f, 3, 100, 0x08),
545 TWL4030_ADJUSTABLE_LDO(VAUX4, 0x23, 4, 100, 0x08),
546 TWL4030_ADJUSTABLE_LDO(VMMC1, 0x27, 5, 100, 0x08),
547 TWL4030_ADJUSTABLE_LDO(VMMC2, 0x2b, 6, 100, 0x08),
548 TWL4030_ADJUSTABLE_LDO(VPLL1, 0x2f, 7, 100, 0x00),
549 TWL4030_ADJUSTABLE_LDO(VPLL2, 0x33, 8, 100, 0x08),
550 TWL4030_ADJUSTABLE_LDO(VSIM, 0x37, 9, 100, 0x00),
551 TWL4030_ADJUSTABLE_LDO(VDAC, 0x3b, 10, 100, 0x08),
552 TWL4030_FIXED_LDO(VINTANA1, 0x3f, 1500, 11, 100, 0x08),
553 TWL4030_ADJUSTABLE_LDO(VINTANA2, 0x43, 12, 100, 0x08),
554 TWL4030_FIXED_LDO(VINTDIG, 0x47, 1500, 13, 100, 0x08),
555 TWL4030_ADJUSTABLE_LDO(VIO, 0x4b, 14, 1000, 0x08),
556 TWL4030_ADJUSTABLE_LDO(VDD1, 0x55, 15, 1000, 0x08),
557 TWL4030_ADJUSTABLE_LDO(VDD2, 0x63, 16, 1000, 0x08),
558 TWL4030_FIXED_LDO(VUSB1V5, 0x71, 1500, 17, 100, 0x08),
559 TWL4030_FIXED_LDO(VUSB1V8, 0x74, 1800, 18, 100, 0x08),
560 TWL4030_FIXED_LDO(VUSB3V1, 0x77, 3100, 19, 150, 0x08),
fa16a5c1 561 /* VUSBCP is managed *only* by the USB subchip */
441a4505
RN
562
563 /* 6030 REG with base as PMC Slave Misc : 0x0030 */
045f972f
JKS
564 /* Turnon-delay and remap configuration values for 6030 are not
565 verified since the specification is not public */
3e3d3be7
RN
566 TWL6030_ADJUSTABLE_LDO(VAUX1_6030, 0x54, 1000, 3300, 1, 0x21),
567 TWL6030_ADJUSTABLE_LDO(VAUX2_6030, 0x58, 1000, 3300, 2, 0x21),
568 TWL6030_ADJUSTABLE_LDO(VAUX3_6030, 0x5c, 1000, 3300, 3, 0x21),
569 TWL6030_ADJUSTABLE_LDO(VMMC, 0x68, 1000, 3300, 4, 0x21),
570 TWL6030_ADJUSTABLE_LDO(VPP, 0x6c, 1000, 3300, 5, 0x21),
571 TWL6030_ADJUSTABLE_LDO(VUSIM, 0x74, 1000, 3300, 7, 0x21),
2ebcf632
RN
572 TWL6030_FIXED_LDO(VANA, 0x50, 2100, 15, 0, 0x21),
573 TWL6030_FIXED_LDO(VCXIO, 0x60, 1800, 16, 0, 0x21),
574 TWL6030_FIXED_LDO(VDAC, 0x64, 1800, 17, 0, 0x21),
575 TWL6030_FIXED_LDO(VUSB, 0x70, 3300, 18, 0, 0x21)
fa16a5c1
DB
576};
577
24c29020 578static int __devinit twlreg_probe(struct platform_device *pdev)
fa16a5c1
DB
579{
580 int i;
581 struct twlreg_info *info;
582 struct regulator_init_data *initdata;
583 struct regulation_constraints *c;
584 struct regulator_dev *rdev;
fa16a5c1 585
c4aa6f31
RN
586 for (i = 0, info = NULL; i < ARRAY_SIZE(twl_regs); i++) {
587 if (twl_regs[i].desc.id != pdev->id)
fa16a5c1 588 continue;
c4aa6f31 589 info = twl_regs + i;
fa16a5c1
DB
590 break;
591 }
592 if (!info)
593 return -ENODEV;
594
595 initdata = pdev->dev.platform_data;
596 if (!initdata)
597 return -EINVAL;
598
599 /* Constrain board-specific capabilities according to what
600 * this driver and the chip itself can actually do.
601 */
602 c = &initdata->constraints;
fa16a5c1
DB
603 c->valid_modes_mask &= REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY;
604 c->valid_ops_mask &= REGULATOR_CHANGE_VOLTAGE
605 | REGULATOR_CHANGE_MODE
606 | REGULATOR_CHANGE_STATUS;
205e5cd3
JKS
607 switch (pdev->id) {
608 case TWL4030_REG_VIO:
609 case TWL4030_REG_VDD1:
610 case TWL4030_REG_VDD2:
611 case TWL4030_REG_VPLL1:
612 case TWL4030_REG_VINTANA1:
613 case TWL4030_REG_VINTANA2:
614 case TWL4030_REG_VINTDIG:
615 c->always_on = true;
616 break;
617 default:
618 break;
619 }
fa16a5c1
DB
620
621 rdev = regulator_register(&info->desc, &pdev->dev, initdata, info);
622 if (IS_ERR(rdev)) {
623 dev_err(&pdev->dev, "can't register %s, %ld\n",
624 info->desc.name, PTR_ERR(rdev));
625 return PTR_ERR(rdev);
626 }
627 platform_set_drvdata(pdev, rdev);
628
30010fa5
JKS
629 twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_REMAP,
630 info->remap);
631
fa16a5c1
DB
632 /* NOTE: many regulators support short-circuit IRQs (presentable
633 * as REGULATOR_OVER_CURRENT notifications?) configured via:
634 * - SC_CONFIG
635 * - SC_DETECT1 (vintana2, vmmc1/2, vaux1/2/3/4)
636 * - SC_DETECT2 (vusb, vdac, vio, vdd1/2, vpll2)
637 * - IT_CONFIG
638 */
639
640 return 0;
641}
642
c4aa6f31 643static int __devexit twlreg_remove(struct platform_device *pdev)
fa16a5c1
DB
644{
645 regulator_unregister(platform_get_drvdata(pdev));
646 return 0;
647}
648
c4aa6f31 649MODULE_ALIAS("platform:twl_reg");
fa16a5c1 650
c4aa6f31
RN
651static struct platform_driver twlreg_driver = {
652 .probe = twlreg_probe,
653 .remove = __devexit_p(twlreg_remove),
fa16a5c1 654 /* NOTE: short name, to work around driver model truncation of
c4aa6f31 655 * "twl_regulator.12" (and friends) to "twl_regulator.1".
fa16a5c1 656 */
c4aa6f31 657 .driver.name = "twl_reg",
fa16a5c1
DB
658 .driver.owner = THIS_MODULE,
659};
660
c4aa6f31 661static int __init twlreg_init(void)
fa16a5c1 662{
c4aa6f31 663 return platform_driver_register(&twlreg_driver);
fa16a5c1 664}
c4aa6f31 665subsys_initcall(twlreg_init);
fa16a5c1 666
c4aa6f31 667static void __exit twlreg_exit(void)
fa16a5c1 668{
c4aa6f31 669 platform_driver_unregister(&twlreg_driver);
fa16a5c1 670}
c4aa6f31 671module_exit(twlreg_exit)
fa16a5c1 672
c4aa6f31 673MODULE_DESCRIPTION("TWL regulator driver");
fa16a5c1 674MODULE_LICENSE("GPL");