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[net-next-2.6.git] / drivers / pci / quirks.c
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1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
bc56b9e0 24#include "pci.h"
1da177e4 25
bd8481e1
DT		 26/* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
29 */
30static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
31{
32 dev->broken_parity_status = 1; /* This device gives false positives */
33}
34DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
35DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
36
1da177e4
LT		 37/* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
39static void __devinit quirk_passive_release(struct pci_dev *dev)
40{
41 struct pci_dev *d = NULL;
42 unsigned char dlc;
43
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
47 pci_read_config_byte(d, 0x82, &dlc);
48 if (!(dlc & 1<<1)) {
49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
50 dlc |= 1<<1;
51 pci_write_config_byte(d, 0x82, dlc);
52 }
53 }
54}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
56
57/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
58 but VIA don't answer queries. If you happen to have good contacts at VIA
59 ask them for me please -- Alan
60
61 This appears to be BIOS not version dependent. So presumably there is a
62 chipset level fix */
63int isa_dma_bridge_buggy; /* Exported */
64
65static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
66{
67 if (!isa_dma_bridge_buggy) {
68 isa_dma_bridge_buggy=1;
69 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
70 }
71}
72 /*
73 * Its not totally clear which chipsets are the problematic ones
74 * We know 82C586 and 82C596 variants are affected.
75 */
76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
77DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
78DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
83
84int pci_pci_problems;
85
86/*
87 * Chipsets where PCI->PCI transfers vanish or hang
88 */
89static void __devinit quirk_nopcipci(struct pci_dev *dev)
90{
91 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
92 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
93 pci_pci_problems |= PCIPCI_FAIL;
94 }
95}
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
98
99/*
100 * Triton requires workarounds to be used by the drivers
101 */
102static void __devinit quirk_triton(struct pci_dev *dev)
103{
104 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
105 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
106 pci_pci_problems |= PCIPCI_TRITON;
107 }
108}
109DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
111DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
112DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
113
114/*
115 * VIA Apollo KT133 needs PCI latency patch
116 * Made according to a windows driver based patch by George E. Breese
117 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
118 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
119 * the info on which Mr Breese based his work.
120 *
121 * Updated based on further information from the site and also on
122 * information provided by VIA
123 */
124static void __devinit quirk_vialatency(struct pci_dev *dev)
125{
126 struct pci_dev *p;
127 u8 rev;
128 u8 busarb;
129 /* Ok we have a potential problem chipset here. Now see if we have
130 a buggy southbridge */
131
132 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
133 if (p!=NULL) {
134 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
135 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
136 /* Check for buggy part revisions */
137 if (rev < 0x40 || rev > 0x42)
138 goto exit;
139 } else {
140 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
141 if (p==NULL) /* No problem parts */
142 goto exit;
143 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
144 /* Check for buggy part revisions */
145 if (rev < 0x10 || rev > 0x12)
146 goto exit;
147 }
148
149 /*
150 * Ok we have the problem. Now set the PCI master grant to
151 * occur every master grant. The apparent bug is that under high
152 * PCI load (quite common in Linux of course) you can get data
153 * loss when the CPU is held off the bus for 3 bus master requests
154 * This happens to include the IDE controllers....
155 *
156 * VIA only apply this fix when an SB Live! is present but under
157 * both Linux and Windows this isnt enough, and we have seen
158 * corruption without SB Live! but with things like 3 UDMA IDE
159 * controllers. So we ignore that bit of the VIA recommendation..
160 */
161
162 pci_read_config_byte(dev, 0x76, &busarb);
163 /* Set bit 4 and bi 5 of byte 76 to 0x01
164 "Master priority rotation on every PCI master grant */
165 busarb &= ~(1<<5);
166 busarb |= (1<<4);
167 pci_write_config_byte(dev, 0x76, busarb);
168 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
169exit:
170 pci_dev_put(p);
171}
172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
174DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
175
176/*
177 * VIA Apollo VP3 needs ETBF on BT848/878
178 */
179static void __devinit quirk_viaetbf(struct pci_dev *dev)
180{
181 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
182 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
183 pci_pci_problems |= PCIPCI_VIAETBF;
184 }
185}
186DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
187
188static void __devinit quirk_vsfx(struct pci_dev *dev)
189{
190 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
191 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
192 pci_pci_problems |= PCIPCI_VSFX;
193 }
194}
195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
196
197/*
198 * Ali Magik requires workarounds to be used by the drivers
199 * that DMA to AGP space. Latency must be set to 0xA and triton
200 * workaround applied too
201 * [Info kindly provided by ALi]
202 */
203static void __init quirk_alimagik(struct pci_dev *dev)
204{
205 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
206 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
207 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
208 }
209}
210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
212
213/*
214 * Natoma has some interesting boundary conditions with Zoran stuff
215 * at least
216 */
217static void __devinit quirk_natoma(struct pci_dev *dev)
218{
219 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
220 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
221 pci_pci_problems |= PCIPCI_NATOMA;
222 }
223}
224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
228DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
229DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
230
231/*
232 * This chip can cause PCI parity errors if config register 0xA0 is read
233 * while DMAs are occurring.
234 */
235static void __devinit quirk_citrine(struct pci_dev *dev)
236{
237 dev->cfg_size = 0xA0;
238}
239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
240
241/*
242 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
243 * If it's needed, re-allocate the region.
244 */
245static void __devinit quirk_s3_64M(struct pci_dev *dev)
246{
247 struct resource *r = &dev->resource[0];
248
249 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
250 r->start = 0;
251 r->end = 0x3ffffff;
252 }
253}
254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
255DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
256
6693e74a
LT		 257static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
258 unsigned size, int nr, const char *name)
1da177e4
LT		 259{
260 region &= ~(size-1);
261 if (region) {
085ae41f 262 struct pci_bus_region bus_region;
1da177e4
LT		 263 struct resource *res = dev->resource + nr;
264
265 res->name = pci_name(dev);
266 res->start = region;
267 res->end = region + size - 1;
268 res->flags = IORESOURCE_IO;
085ae41f
DM		 269
270 /* Convert from PCI bus to resource space. */
271 bus_region.start = res->start;
272 bus_region.end = res->end;
273 pcibios_bus_to_resource(dev, res, &bus_region);
274
1da177e4 275 pci_claim_resource(dev, nr);
6693e74a 276 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 277 }
278}
279
280/*
281 * ATI Northbridge setups MCE the processor if you even
282 * read somewhere between 0x3b0->0x3bb or read 0x3d3
283 */
284static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
285{
286 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
287 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
288 request_region(0x3b0, 0x0C, "RadeonIGP");
289 request_region(0x3d3, 0x01, "RadeonIGP");
290}
291DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
292
293/*
294 * Let's make the southbridge information explicit instead
295 * of having to worry about people probing the ACPI areas,
296 * for example.. (Yes, it happens, and if you read the wrong
297 * ACPI register it will put the machine to sleep with no
298 * way of waking it up again. Bummer).
299 *
300 * ALI M7101: Two IO regions pointed to by words at
301 * 0xE0 (64 bytes of ACPI registers)
302 * 0xE2 (32 bytes of SMB registers)
303 */
304static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
305{
306 u16 region;
307
308 pci_read_config_word(dev, 0xE0, &region);
6693e74a 309 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 310 pci_read_config_word(dev, 0xE2, &region);
6693e74a 311 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4
LT		 312}
313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
314
6693e74a
LT		 315static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
316{
317 u32 devres;
318 u32 mask, size, base;
319
320 pci_read_config_dword(dev, port, &devres);
321 if ((devres & enable) != enable)
322 return;
323 mask = (devres >> 16) & 15;
324 base = devres & 0xffff;
325 size = 16;
326 for (;;) {
327 unsigned bit = size >> 1;
328 if ((bit & mask) == bit)
329 break;
330 size = bit;
331 }
332 /*
333 * For now we only print it out. Eventually we'll want to
334 * reserve it (at least if it's in the 0x1000+ range), but
335 * let's get enough confirmation reports first.
336 */
337 base &= -size;
338 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
339}
340
341static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
342{
343 u32 devres;
344 u32 mask, size, base;
345
346 pci_read_config_dword(dev, port, &devres);
347 if ((devres & enable) != enable)
348 return;
349 base = devres & 0xffff0000;
350 mask = (devres & 0x3f) << 16;
351 size = 128 << 16;
352 for (;;) {
353 unsigned bit = size >> 1;
354 if ((bit & mask) == bit)
355 break;
356 size = bit;
357 }
358 /*
359 * For now we only print it out. Eventually we'll want to
360 * reserve it, but let's get enough confirmation reports first.
361 */
362 base &= -size;
363 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
364}
365
1da177e4
LT		 366/*
367 * PIIX4 ACPI: Two IO regions pointed to by longwords at
368 * 0x40 (64 bytes of ACPI registers)
08db2a70 369 * 0x90 (16 bytes of SMB registers)
6693e74a 370 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 371 */
372static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
373{
6693e74a 374 u32 region, res_a;
1da177e4
LT		 375
376 pci_read_config_dword(dev, 0x40, &region);
6693e74a 377 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 378 pci_read_config_dword(dev, 0x90, &region);
08db2a70 379 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 380
381 /* Device resource A has enables for some of the other ones */
382 pci_read_config_dword(dev, 0x5c, &res_a);
383
384 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
385 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
386
387 /* Device resource D is just bitfields for static resources */
388
389 /* Device 12 enabled? */
390 if (res_a & (1 << 29)) {
391 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
392 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
393 }
394 /* Device 13 enabled? */
395 if (res_a & (1 << 30)) {
396 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
397 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
398 }
399 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
400 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4
LT		 401}
402DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
c6764664 403DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi );
1da177e4
LT		 404
405/*
406 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
407 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
408 * 0x58 (64 bytes of GPIO I/O space)
409 */
410static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
411{
412 u32 region;
413
414 pci_read_config_dword(dev, 0x40, &region);
6693e74a 415 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 416
417 pci_read_config_dword(dev, 0x58, &region);
6693e74a 418 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4
LT		 419}
420DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
422DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
424DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
425DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
426DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
428DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
3aa8c4fe 429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
1da177e4 430
2cea752f
RM		 431static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
432{
433 u32 region;
434
435 pci_read_config_dword(dev, 0x40, &region);
436 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
437
438 pci_read_config_dword(dev, 0x48, &region);
439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
440}
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
442
1da177e4
LT		 443/*
444 * VIA ACPI: One IO region pointed to by longword at
445 * 0x48 or 0x20 (256 bytes of ACPI registers)
446 */
447static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
448{
449 u8 rev;
450 u32 region;
451
452 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
453 if (rev & 0x10) {
454 pci_read_config_dword(dev, 0x48, &region);
455 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 456 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 457 }
458}
459DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
460
461/*
462 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
463 * 0x48 (256 bytes of ACPI registers)
464 * 0x70 (128 bytes of hardware monitoring register)
465 * 0x90 (16 bytes of SMB registers)
466 */
467static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
468{
469 u16 hm;
470 u32 smb;
471
472 quirk_vt82c586_acpi(dev);
473
474 pci_read_config_word(dev, 0x70, &hm);
475 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 476 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 477
478 pci_read_config_dword(dev, 0x90, &smb);
479 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 480 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4
LT		 481}
482DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
483
6d85f29b
IK		 484/*
485 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
486 * 0x88 (128 bytes of power management registers)
487 * 0xd0 (16 bytes of SMB registers)
488 */
489static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
490{
491 u16 pm, smb;
492
493 pci_read_config_word(dev, 0x88, &pm);
494 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 495 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 496
497 pci_read_config_word(dev, 0xd0, &smb);
498 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 499 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 500}
501DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
502
1da177e4
LT		 503
504#ifdef CONFIG_X86_IO_APIC
505
506#include <asm/io_apic.h>
507
508/*
509 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
510 * devices to the external APIC.
511 *
512 * TODO: When we have device-specific interrupt routers,
513 * this code will go away from quirks.
514 */
515static void __devinit quirk_via_ioapic(struct pci_dev *dev)
516{
517 u8 tmp;
518
519 if (nr_ioapics < 1)
520 tmp = 0; /* nothing routed to external APIC */
521 else
522 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
523
524 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
525 tmp == 0 ? "Disa" : "Ena");
526
527 /* Offset 0x58: External APIC IRQ output control */
528 pci_write_config_byte (dev, 0x58, tmp);
529}
530DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
531
a1740913
KW		 532/*
533 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
534 * This leads to doubled level interrupt rates.
535 * Set this bit to get rid of cycle wastage.
536 * Otherwise uncritical.
537 */
538static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
539{
540 u8 misc_control2;
541#define BYPASS_APIC_DEASSERT 8
542
543 pci_read_config_byte(dev, 0x5B, &misc_control2);
544 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
545 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
546 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
547 }
548}
549DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
550
1da177e4
LT		 551/*
552 * The AMD io apic can hang the box when an apic irq is masked.
553 * We check all revs >= B0 (yet not in the pre production!) as the bug
554 * is currently marked NoFix
555 *
556 * We have multiple reports of hangs with this chipset that went away with
557 * noapic specified. For the moment we assume its the errata. We may be wrong
558 * of course. However the advice is demonstrably good even if so..
559 */
560static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
561{
562 u8 rev;
563
564 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
565 if (rev >= 0x02) {
566 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
567 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
568 }
569}
570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
571
572static void __init quirk_ioapic_rmw(struct pci_dev *dev)
573{
574 if (dev->devfn == 0 && dev->bus->number == 0)
575 sis_apic_bug = 1;
576}
577DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
578
579int pci_msi_quirk;
580
581#define AMD8131_revA0 0x01
582#define AMD8131_revB0 0x11
583#define AMD8131_MISC 0x40
584#define AMD8131_NIOAMODE_BIT 0
585static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
586{
587 unsigned char revid, tmp;
588
6e325a62
MT		 589 if (dev->subordinate) {
590 printk(KERN_WARNING "PCI: MSI quirk detected. "
591 "PCI_BUS_FLAGS_NO_MSI set for subordinate bus.\n");
592 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
593 }
1da177e4
LT		 594
595 if (nr_ioapics == 0)
596 return;
597
598 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
599 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
600 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
601 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
602 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
603 pci_write_config_byte( dev, AMD8131_MISC, tmp);
604 }
605}
5da594b1 606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
1da177e4 607
1e062767
NS		 608static void __init quirk_svw_msi(struct pci_dev *dev)
609{
610 pci_msi_quirk = 1;
611 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
612}
613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi );
1da177e4
LT		 614#endif /* CONFIG_X86_IO_APIC */
615
616
1da177e4
LT		 617/*
618 * FIXME: it is questionable that quirk_via_acpi
619 * is needed. It shows up as an ISA bridge, and does not
620 * support the PCI_INTERRUPT_LINE register at all. Therefore
621 * it seems like setting the pci_dev's 'irq' to the
622 * value of the ACPI SCI interrupt is only done for convenience.
623 * -jgarzik
624 */
625static void __devinit quirk_via_acpi(struct pci_dev *d)
626{
627 /*
628 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
629 */
630 u8 irq;
631 pci_read_config_byte(d, 0x42, &irq);
632 irq &= 0xf;
633 if (irq && (irq != 2))
634 d->irq = irq;
635}
636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
638
93cffffa
BH		 639/*
640 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
641 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
642 * when written, it makes an internal connection to the PIC.
643 * For these devices, this register is defined to be 4 bits wide.
644 * Normally this is fine. However for IO-APIC motherboards, or
645 * non-x86 architectures (yes Via exists on PPC among other places),
646 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
647 * interrupts delivered properly.
a7b862f6
CW		 648 *
649 * Some of the on-chip devices are actually '586 devices' so they are
650 * listed here.
93cffffa
BH		 651 */
652static void quirk_via_irq(struct pci_dev *dev)
25be5e6c
LB		 653{
654 u8 irq, new_irq;
655
25be5e6c
LB		 656 new_irq = dev->irq & 0xf;
657 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
658 if (new_irq != irq) {
75cf7456 659 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n",
25be5e6c
LB		 660 pci_name(dev), irq, new_irq);
661 udelay(15); /* unknown if delay really needed */
662 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
663 }
664}
a7b862f6
CW		 665DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_via_irq);
666DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, quirk_via_irq);
667DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irq);
668DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_irq);
75cf7456
CW		 669DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq);
670DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq);
671DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq);
25be5e6c 672
1da177e4
LT		 673/*
674 * VIA VT82C598 has its device ID settable and many BIOSes
675 * set it to the ID of VT82C597 for backward compatibility.
676 * We need to switch it off to be able to recognize the real
677 * type of the chip.
678 */
679static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
680{
681 pci_write_config_byte(dev, 0xfc, 0);
682 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
683}
684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
685
709cf5ea
MG		 686#ifdef CONFIG_ACPI_SLEEP
687
688/*
689 * Some VIA systems boot with the abnormal status flag set. This can cause
690 * the BIOS to re-POST the system on resume rather than passing control
691 * back to the OS. Clear the flag on boot
692 */
693static void __devinit quirk_via_abnormal_poweroff(struct pci_dev *dev)
694{
695 u32 reg;
696
697 acpi_hw_register_read(ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_STATUS,
698 &reg);
699
700 if (reg & 0x800) {
701 printk("Clearing abnormal poweroff flag\n");
702 acpi_hw_register_write(ACPI_MTX_DO_NOT_LOCK,
703 ACPI_REGISTER_PM1_STATUS,
704 (u16)0x800);
705 }
706}
707
708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_abnormal_poweroff);
709DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_abnormal_poweroff);
710
711#endif
712
1da177e4
LT		 713/*
714 * CardBus controllers have a legacy base address that enables them
715 * to respond as i82365 pcmcia controllers. We don't want them to
716 * do this even if the Linux CardBus driver is not loaded, because
717 * the Linux i82365 driver does not (and should not) handle CardBus.
718 */
719static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
720{
721 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
722 return;
723 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
724}
725DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
726
727/*
728 * Following the PCI ordering rules is optional on the AMD762. I'm not
729 * sure what the designers were smoking but let's not inhale...
730 *
731 * To be fair to AMD, it follows the spec by default, its BIOS people
732 * who turn it off!
733 */
734static void __devinit quirk_amd_ordering(struct pci_dev *dev)
735{
736 u32 pcic;
737 pci_read_config_dword(dev, 0x4C, &pcic);
738 if ((pcic&6)!=6) {
739 pcic |= 6;
740 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
741 pci_write_config_dword(dev, 0x4C, pcic);
742 pci_read_config_dword(dev, 0x84, &pcic);
743 pcic |= (1<<23); /* Required in this mode */
744 pci_write_config_dword(dev, 0x84, pcic);
745 }
746}
747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
748
749/*
750 * DreamWorks provided workaround for Dunord I-3000 problem
751 *
752 * This card decodes and responds to addresses not apparently
753 * assigned to it. We force a larger allocation to ensure that
754 * nothing gets put too close to it.
755 */
756static void __devinit quirk_dunord ( struct pci_dev * dev )
757{
758 struct resource *r = &dev->resource [1];
759 r->start = 0;
760 r->end = 0xffffff;
761}
762DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
763
764/*
765 * i82380FB mobile docking controller: its PCI-to-PCI bridge
766 * is subtractive decoding (transparent), and does indicate this
767 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
768 * instead of 0x01.
769 */
770static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
771{
772 dev->transparent = 1;
773}
774DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
775DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
776
777/*
778 * Common misconfiguration of the MediaGX/Geode PCI master that will
779 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
780 * datasheets found at http://www.national.com/ds/GX for info on what
781 * these bits do. <christer@weinigel.se>
782 */
783static void __init quirk_mediagx_master(struct pci_dev *dev)
784{
785 u8 reg;
786 pci_read_config_byte(dev, 0x41, &reg);
787 if (reg & 2) {
788 reg &= ~2;
789 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
790 pci_write_config_byte(dev, 0x41, reg);
791 }
792}
793DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
794
795/*
796 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
797 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
798 * secondary channels respectively). If the device reports Compatible mode
799 * but does use BAR0-3 for address decoding, we assume that firmware has
800 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
801 * Exceptions (if they exist) must be handled in chip/architecture specific
802 * fixups.
803 *
804 * Note: for non x86 people. You may need an arch specific quirk to handle
805 * moving IDE devices to native mode as well. Some plug in card devices power
806 * up in compatible mode and assume the BIOS will adjust them.
807 *
808 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
809 * we do now ? We don't want is pci_enable_device to come along
810 * and assign new resources. Both approaches work for that.
811 */
812static void __devinit quirk_ide_bases(struct pci_dev *dev)
813{
814 struct resource *res;
815 int first_bar = 2, last_bar = 0;
816
817 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
818 return;
819
820 res = &dev->resource[0];
821
822 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
823 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
824 res[0].start = res[0].end = res[0].flags = 0;
825 res[1].start = res[1].end = res[1].flags = 0;
826 first_bar = 0;
827 last_bar = 1;
828 }
829
830 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
831 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
832 res[2].start = res[2].end = res[2].flags = 0;
833 res[3].start = res[3].end = res[3].flags = 0;
834 last_bar = 3;
835 }
836
837 if (!last_bar)
838 return;
839
840 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
841 first_bar, last_bar, pci_name(dev));
842}
843DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
844
845/*
846 * Ensure C0 rev restreaming is off. This is normally done by
847 * the BIOS but in the odd case it is not the results are corruption
848 * hence the presence of a Linux check
849 */
850static void __init quirk_disable_pxb(struct pci_dev *pdev)
851{
852 u16 config;
853 u8 rev;
854
855 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
856 if (rev != 0x04) /* Only C0 requires this */
857 return;
858 pci_read_config_word(pdev, 0x40, &config);
859 if (config & (1<<6)) {
860 config &= ~(1<<6);
861 pci_write_config_word(pdev, 0x40, config);
862 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
863 }
864}
865DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
866
1da177e4
LT		 867
868/*
869 * Serverworks CSB5 IDE does not fully support native mode
870 */
871static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
872{
873 u8 prog;
874 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
875 if (prog & 5) {
876 prog &= ~5;
877 pdev->class &= ~5;
878 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
879 /* need to re-assign BARs for compat mode */
880 quirk_ide_bases(pdev);
881 }
882}
883DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
884
885/*
886 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
887 */
888static void __init quirk_ide_samemode(struct pci_dev *pdev)
889{
890 u8 prog;
891
892 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
893
894 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
895 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
896 prog &= ~5;
897 pdev->class &= ~5;
898 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
899 /* need to re-assign BARs for compat mode */
900 quirk_ide_bases(pdev);
901 }
902}
903DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
904
905/* This was originally an Alpha specific thing, but it really fits here.
906 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
907 */
908static void __init quirk_eisa_bridge(struct pci_dev *dev)
909{
910 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
911}
912DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
913
7daa0c4f
JG		 914/*
915 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
916 * when a PCI-Soundcard is added. The BIOS only gives Options
917 * "Disabled" and "AUTO". This Quirk Sets the corresponding
918 * Register-Value to enable the Soundcard.
bd91fde9
CW		 919 *
920 * FIXME: Presently this quirk will run on anything that has an 8237
921 * which isn't correct, we need to check DMI tables or something in
922 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
923 * runs everywhere at present we suppress the printk output in most
924 * irrelevant cases.
7daa0c4f
JG		 925 */
926static void __init k8t_sound_hostbridge(struct pci_dev *dev)
927{
928 unsigned char val;
929
7daa0c4f
JG		 930 pci_read_config_byte(dev, 0x50, &val);
931 if (val == 0x88 || val == 0xc8) {
bd91fde9
CW		 932 /* Assume it's probably a MSI-K8T-Neo2Fir */
933 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
7daa0c4f
JG		 934 pci_write_config_byte(dev, 0x50, val & (~0x40));
935
936 /* Verify the Change for Status output */
937 pci_read_config_byte(dev, 0x50, &val);
938 if (val & 0x40)
bd91fde9 939 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
7daa0c4f 940 else
bd91fde9 941 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n");
7daa0c4f 942 }
7daa0c4f
JG		 943}
944DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
945
ce007ea5 946#ifndef CONFIG_ACPI_SLEEP
1da177e4
LT		 947/*
948 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
949 * is not activated. The myth is that Asus said that they do not want the
950 * users to be irritated by just another PCI Device in the Win98 device
951 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
952 * package 2.7.0 for details)
953 *
954 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
955 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
956 * becomes necessary to do this tweak in two steps -- I've chosen the Host
957 * bridge as trigger.
ce007ea5
CDH		 958 *
959 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram
960 * will cause thermal management to break down, and causing machine to
961 * overheat.
1da177e4 962 */
ce007ea5 963static int __initdata asus_hides_smbus;
1da177e4
LT		 964
965static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
966{
967 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
968 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
969 switch(dev->subsystem_device) {
a00db371 970 case 0x8025: /* P4B-LX */
1da177e4
LT		 971 case 0x8070: /* P4B */
972 case 0x8088: /* P4B533 */
973 case 0x1626: /* L3C notebook */
974 asus_hides_smbus = 1;
975 }
976 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
977 switch(dev->subsystem_device) {
978 case 0x80b1: /* P4GE-V */
979 case 0x80b2: /* P4PE */
980 case 0x8093: /* P4B533-V */
981 asus_hides_smbus = 1;
982 }
983 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
984 switch(dev->subsystem_device) {
985 case 0x8030: /* P4T533 */
986 asus_hides_smbus = 1;
987 }
988 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
989 switch (dev->subsystem_device) {
990 case 0x8070: /* P4G8X Deluxe */
991 asus_hides_smbus = 1;
992 }
993 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
994 switch (dev->subsystem_device) {
995 case 0x1751: /* M2N notebook */
996 case 0x1821: /* M5N notebook */
997 asus_hides_smbus = 1;
998 }
999 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1000 switch (dev->subsystem_device) {
1001 case 0x184b: /* W1N notebook */
1002 case 0x186a: /* M6Ne notebook */
1003 asus_hides_smbus = 1;
1004 }
acc06632
RM		 1005 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1006 switch (dev->subsystem_device) {
1007 case 0x1882: /* M6V notebook */
2d1e1c75 1008 case 0x1977: /* A6VA notebook */
acc06632
RM		 1009 asus_hides_smbus = 1;
1010 }
1011 }
1da177e4
LT		 1012 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1013 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1014 switch(dev->subsystem_device) {
1015 case 0x088C: /* HP Compaq nc8000 */
1016 case 0x0890: /* HP Compaq nc6000 */
1017 asus_hides_smbus = 1;
1018 }
1019 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1020 switch (dev->subsystem_device) {
1021 case 0x12bc: /* HP D330L */
e3b1bd57 1022 case 0x12bd: /* HP D530 */
1da177e4
LT		 1023 asus_hides_smbus = 1;
1024 }
3c0a654e 1025 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1026 switch (dev->subsystem_device) {
1027 case 0x099c: /* HP Compaq nx6110 */
1028 asus_hides_smbus = 1;
1029 }
1030 }
1da177e4
LT		 1031 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
1032 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1033 switch(dev->subsystem_device) {
1034 case 0x0001: /* Toshiba Satellite A40 */
1035 asus_hides_smbus = 1;
1036 }
e96e2f14
DG		 1037 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1038 switch(dev->subsystem_device) {
1039 case 0x0001: /* Toshiba Tecra M2 */
1040 asus_hides_smbus = 1;
1041 }
1da177e4
LT		 1042 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1043 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1044 switch(dev->subsystem_device) {
1045 case 0xC00C: /* Samsung P35 notebook */
1046 asus_hides_smbus = 1;
1047 }
c87f883e
RIZ		 1048 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1049 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1050 switch(dev->subsystem_device) {
1051 case 0x0058: /* Compaq Evo N620c */
1052 asus_hides_smbus = 1;
1053 }
1da177e4
LT		 1054 }
1055}
1056DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1057DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1058DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1060DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
1061DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1062DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
acc06632 1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1da177e4
LT		 1064
1065static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
1066{
1067 u16 val;
1068
1069 if (likely(!asus_hides_smbus))
1070 return;
1071
1072 pci_read_config_word(dev, 0xF2, &val);
1073 if (val & 0x8) {
1074 pci_write_config_word(dev, 0xF2, val & (~0x8));
1075 pci_read_config_word(dev, 0xF2, &val);
1076 if (val & 0x8)
1077 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1078 else
1079 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1080 }
1081}
1082DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1083DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1084DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1085DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1086DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
2d1e1c75 1087DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc );
1da177e4 1088
acc06632
RM		 1089static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1090{
1091 u32 val, rcba;
1092 void __iomem *base;
1093
1094 if (likely(!asus_hides_smbus))
1095 return;
1096 pci_read_config_dword(dev, 0xF0, &rcba);
1097 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1098 if (base == NULL) return;
1099 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1100 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1101 iounmap(base);
1102 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1103}
1104DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1105
ce007ea5
CDH		 1106#endif
1107
1da177e4
LT		 1108/*
1109 * SiS 96x south bridge: BIOS typically hides SMBus device...
1110 */
1111static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
1112{
1113 u8 val = 0;
1114 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1115 pci_read_config_byte(dev, 0x77, &val);
1116 pci_write_config_byte(dev, 0x77, val & ~0x10);
1117 pci_read_config_byte(dev, 0x77, &val);
1118}
1119
1da177e4
LT		 1120/*
1121 * ... This is further complicated by the fact that some SiS96x south
1122 * bridges pretend to be 85C503/5513 instead. In that case see if we
1123 * spotted a compatible north bridge to make sure.
1124 * (pci_find_device doesn't work yet)
1125 *
1126 * We can also enable the sis96x bit in the discovery register..
1127 */
1128static int __devinitdata sis_96x_compatible = 0;
1129
1130#define SIS_DETECT_REGISTER 0x40
1131
1132static void __init quirk_sis_503(struct pci_dev *dev)
1133{
1134 u8 reg;
1135 u16 devid;
1136
1137 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1138 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1139 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1140 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1141 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1142 return;
1143 }
1144
1145 /* Make people aware that we changed the config.. */
1146 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1147
1148 /*
1149 * Ok, it now shows up as a 96x.. The 96x quirks are after
1150 * the 503 quirk in the quirk table, so they'll automatically
1151 * run and enable things like the SMBus device
1152 */
1153 dev->device = devid;
1154}
1155
1156static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1157{
1158 sis_96x_compatible = 1;
1159}
1160DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1161DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1162DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1163DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1164DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1165DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1166
1167DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
e5548e96
BJD		 1168/*
1169 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1170 * and MC97 modem controller are disabled when a second PCI soundcard is
1171 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1172 * -- bjd
1173 */
1174static void __init asus_hides_ac97_lpc(struct pci_dev *dev)
1175{
1176 u8 val;
1177 int asus_hides_ac97 = 0;
1178
1179 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1180 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1181 asus_hides_ac97 = 1;
1182 }
1183
1184 if (!asus_hides_ac97)
1185 return;
1186
1187 pci_read_config_byte(dev, 0x50, &val);
1188 if (val & 0xc0) {
1189 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1190 pci_read_config_byte(dev, 0x50, &val);
1191 if (val & 0xc0)
1192 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1193 else
1194 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1195 }
1196}
1197DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1198
1da177e4
LT		 1199
1200DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1201DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1202DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1203DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1204
15e0c694
AC		 1205#if defined(CONFIG_SCSI_SATA) || defined(CONFIG_SCSI_SATA_MODULE)
1206
1207/*
1208 * If we are using libata we can drive this chip properly but must
1209 * do this early on to make the additional device appear during
1210 * the PCI scanning.
1211 */
1212
1213static void __devinit quirk_jmicron_dualfn(struct pci_dev *pdev)
1214{
1215 u32 conf;
1216 u8 hdr;
1217
1218 /* Only poke fn 0 */
1219 if (PCI_FUNC(pdev->devfn))
1220 return;
1221
1222 switch(pdev->device) {
1223 case PCI_DEVICE_ID_JMICRON_JMB365:
1224 case PCI_DEVICE_ID_JMICRON_JMB366:
1225 /* Redirect IDE second PATA port to the right spot */
1226 pci_read_config_dword(pdev, 0x80, &conf);
1227 conf |= (1 << 24);
1228 /* Fall through */
1229 pci_write_config_dword(pdev, 0x80, conf);
1230 case PCI_DEVICE_ID_JMICRON_JMB361:
1231 case PCI_DEVICE_ID_JMICRON_JMB363:
1232 pci_read_config_dword(pdev, 0x40, &conf);
1233 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1234 /* Set the class codes correctly and then direct IDE 0 */
1235 conf &= ~0x000F0200; /* Clear bit 9 and 16-19 */
1236 conf |= 0x00C20002; /* Set bit 1, 17, 22, 23 */
1237 pci_write_config_dword(pdev, 0x40, conf);
1238
1239 /* Reconfigure so that the PCI scanner discovers the
1240 device is now multifunction */
1241
1242 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1243 pdev->hdr_type = hdr & 0x7f;
1244 pdev->multifunction = !!(hdr & 0x80);
1245
1246 break;
1247 }
1248}
1249
1250DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);
1251
1252#endif
1253
1da177e4
LT		 1254#ifdef CONFIG_X86_IO_APIC
1255static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1256{
1257 int i;
1258
1259 if ((pdev->class >> 8) != 0xff00)
1260 return;
1261
1262 /* the first BAR is the location of the IO APIC...we must
1263 * not touch this (and it's already covered by the fixmap), so
1264 * forcibly insert it into the resource tree */
1265 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1266 insert_resource(&iomem_resource, &pdev->resource[0]);
1267
1268 /* The next five BARs all seem to be rubbish, so just clean
1269 * them out */
1270 for (i=1; i < 6; i++) {
1271 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1272 }
1273
1274}
1275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1276#endif
1277
2bd0fa3b
JB		 1278enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 };
1279/* Defaults to combined */
1280static enum ide_combined_type combined_mode;
1281
1282static int __init combined_setup(char *str)
1283{
1284 if (!strncmp(str, "ide", 3))
1285 combined_mode = IDE;
1286 else if (!strncmp(str, "libata", 6))
1287 combined_mode = LIBATA;
1288 else /* "combined" or anything else defaults to old behavior */
1289 combined_mode = COMBINED;
1290
1291 return 1;
1292}
1293__setup("combined_mode=", combined_setup);
1294
cc675230 1295#ifdef CONFIG_SCSI_SATA_INTEL_COMBINED
1da177e4
LT		 1296static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1297{
1298 u8 prog, comb, tmp;
1299 int ich = 0;
1300
1301 /*
1302 * Narrow down to Intel SATA PCI devices.
1303 */
1304 switch (pdev->device) {
1305 /* PCI ids taken from drivers/scsi/ata_piix.c */
1306 case 0x24d1:
1307 case 0x24df:
1308 case 0x25a3:
1309 case 0x25b0:
1310 ich = 5;
1311 break;
1312 case 0x2651:
1313 case 0x2652:
1314 case 0x2653:
c368ca4e 1315 case 0x2680: /* ESB2 */
1da177e4
LT		 1316 ich = 6;
1317 break;
1318 case 0x27c0:
1319 case 0x27c4:
1320 ich = 7;
1321 break;
012b265f
JG		 1322 case 0x2828: /* ICH8M */
1323 ich = 8;
1324 break;
1da177e4
LT		 1325 default:
1326 /* we do not handle this PCI device */
1327 return;
1328 }
1329
1330 /*
1331 * Read combined mode register.
1332 */
1333 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1334
1335 if (ich == 5) {
1336 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1337 if (tmp == 0x4) /* bits 10x */
1338 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1339 else if (tmp == 0x6) /* bits 11x */
1340 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1341 else
1342 return; /* not in combined mode */
1343 } else {
012b265f 1344 WARN_ON((ich != 6) && (ich != 7) && (ich != 8));
1da177e4
LT		 1345 tmp &= 0x3; /* interesting bits 1:0 */
1346 if (tmp & (1 << 0))
1347 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1348 else if (tmp & (1 << 1))
1349 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1350 else
1351 return; /* not in combined mode */
1352 }
1353
1354 /*
1355 * Read programming interface register.
1356 * (Tells us if it's legacy or native mode)
1357 */
1358 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1359
1360 /* if SATA port is in native mode, we're ok. */
1361 if (prog & comb)
1362 return;
1363
2bd0fa3b
JB		 1364 /* Don't reserve any so the IDE driver can get them (but only if
1365 * combined_mode=ide).
1366 */
1367 if (combined_mode == IDE)
1368 return;
1369
1370 /* Grab them both for libata if combined_mode=libata. */
1371 if (combined_mode == LIBATA) {
1372 request_region(0x1f0, 8, "libata"); /* port 0 */
1373 request_region(0x170, 8, "libata"); /* port 1 */
1374 return;
1375 }
1376
1da177e4
LT		 1377 /* SATA port is in legacy mode. Reserve port so that
1378 * IDE driver does not attempt to use it. If request_region
1379 * fails, it will be obvious at boot time, so we don't bother
1380 * checking return values.
1381 */
1382 if (comb == (1 << 0))
1383 request_region(0x1f0, 8, "libata"); /* port 0 */
1384 else
1385 request_region(0x170, 8, "libata"); /* port 1 */
1386}
1387DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
cc675230 1388#endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */
1da177e4
LT		 1389
1390
1391int pcie_mch_quirk;
1392
1393static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1394{
1395 pcie_mch_quirk = 1;
1396}
1397DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1398DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1399DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1400
4602b88d
KA		 1401
1402/*
1403 * It's possible for the MSI to get corrupted if shpc and acpi
1404 * are used together on certain PXH-based systems.
1405 */
1406static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1407{
1408 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1409 PCI_CAP_ID_MSI);
1410 dev->no_msi = 1;
1411
1412 printk(KERN_WARNING "PCI: PXH quirk detected, "
1413 "disabling MSI for SHPC device\n");
1414}
1415DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1416DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1417DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1418DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1419DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1420
ffadcc2f
KCA		 1421/*
1422 * Some Intel PCI Express chipsets have trouble with downstream
1423 * device power management.
1424 */
1425static void quirk_intel_pcie_pm(struct pci_dev * dev)
1426{
1427 pci_pm_d3_delay = 120;
1428 dev->no_d1d2 = 1;
1429}
1430
1431DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1432DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1433DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1434DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1435DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1436DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1437DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1438DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1439DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1440DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1441DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1442DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1446DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1447DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1448DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1449DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1450DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1451DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1452
c408a379
KA		 1453/*
1454 * Fixup the cardbus bridges on the IBM Dock II docking station
1455 */
1456static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev)
1457{
1458 u32 val;
1459
1460 /*
1461 * tie the 2 interrupt pins to INTA, and configure the
1462 * multifunction routing register to handle this.
1463 */
1464 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) &&
1465 (dev->subsystem_device == 0x0148)) {
1466 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge "
1467 "applying quirk\n");
1468 pci_read_config_dword(dev, 0x8c, &val);
1469 val = ((val & 0xffffff00) | 0x1002);
1470 pci_write_config_dword(dev, 0x8c, val);
1471 pci_read_config_dword(dev, 0x80, &val);
1472 val = ((val & 0x00ffff00) | 0x2864c077);
1473 pci_write_config_dword(dev, 0x80, val);
1474 }
1475}
1476
1477DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420,
1478 quirk_ibm_dock2_cardbus);
1479
1da177e4
LT		 1480static void __devinit quirk_netmos(struct pci_dev *dev)
1481{
1482 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1483 unsigned int num_serial = dev->subsystem_device & 0xf;
1484
1485 /*
1486 * These Netmos parts are multiport serial devices with optional
1487 * parallel ports. Even when parallel ports are present, they
1488 * are identified as class SERIAL, which means the serial driver
1489 * will claim them. To prevent this, mark them as class OTHER.
1490 * These combo devices should be claimed by parport_serial.
1491 *
1492 * The subdevice ID is of the form 0x00PS, where <P> is the number
1493 * of parallel ports and <S> is the number of serial ports.
1494 */
1495 switch (dev->device) {
1496 case PCI_DEVICE_ID_NETMOS_9735:
1497 case PCI_DEVICE_ID_NETMOS_9745:
1498 case PCI_DEVICE_ID_NETMOS_9835:
1499 case PCI_DEVICE_ID_NETMOS_9845:
1500 case PCI_DEVICE_ID_NETMOS_9855:
1501 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1502 num_parallel) {
1503 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1504 "%u serial); changing class SERIAL to OTHER "
1505 "(use parport_serial)\n",
1506 dev->device, num_parallel, num_serial);
1507 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1508 (dev->class & 0xff);
1509 }
1510 }
1511}
1512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1513
a5312e28
IK		 1514
1515static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1516{
1517 /* rev 1 ncr53c810 chips don't set the class at all which means
1518 * they don't get their resources remapped. Fix that here.
1519 */
1520
1521 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1522 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1523 dev->class = PCI_CLASS_STORAGE_SCSI;
1524 }
1525}
1526DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1527
1528
1da177e4
LT		 1529static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1530{
1531 while (f < end) {
1532 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1533 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1534 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1535 f->hook(dev);
1536 }
1537 f++;
1538 }
1539}
1540
1541extern struct pci_fixup __start_pci_fixups_early[];
1542extern struct pci_fixup __end_pci_fixups_early[];
1543extern struct pci_fixup __start_pci_fixups_header[];
1544extern struct pci_fixup __end_pci_fixups_header[];
1545extern struct pci_fixup __start_pci_fixups_final[];
1546extern struct pci_fixup __end_pci_fixups_final[];
1547extern struct pci_fixup __start_pci_fixups_enable[];
1548extern struct pci_fixup __end_pci_fixups_enable[];
1549
1550
1551void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1552{
1553 struct pci_fixup *start, *end;
1554
1555 switch(pass) {
1556 case pci_fixup_early:
1557 start = __start_pci_fixups_early;
1558 end = __end_pci_fixups_early;
1559 break;
1560
1561 case pci_fixup_header:
1562 start = __start_pci_fixups_header;
1563 end = __end_pci_fixups_header;
1564 break;
1565
1566 case pci_fixup_final:
1567 start = __start_pci_fixups_final;
1568 end = __end_pci_fixups_final;
1569 break;
1570
1571 case pci_fixup_enable:
1572 start = __start_pci_fixups_enable;
1573 end = __end_pci_fixups_enable;
1574 break;
1575
1576 default:
1577 /* stupid compiler warning, you would think with an enum... */
1578 return;
1579 }
1580 pci_do_fixups(dev, start, end);
1581}
1582
9d265124
DY		 1583/* Enable 1k I/O space granularity on the Intel P64H2 */
1584static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1585{
1586 u16 en1k;
1587 u8 io_base_lo, io_limit_lo;
1588 unsigned long base, limit;
1589 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1590
1591 pci_read_config_word(dev, 0x40, &en1k);
1592
1593 if (en1k & 0x200) {
1594 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1595
1596 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1597 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1598 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1599 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1600
1601 if (base <= limit) {
1602 res->start = base;
1603 res->end = limit + 0x3ff;
1604 }
1605 }
1606}
1607DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1608
cf34a8e0
BG		 1609/* Under some circumstances, AER is not linked with extended capabilities.
1610 * Force it to be linked by setting the corresponding control bit in the
1611 * config space.
1612 */
1613static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1614{
1615 uint8_t b;
1616 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1617 if (!(b & 0x20)) {
1618 pci_write_config_byte(dev, 0xf41, b | 0x20);
1619 printk(KERN_INFO
1620 "PCI: Linking AER extended capability on %s\n",
1621 pci_name(dev));
1622 }
1623 }
1624}
1625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1626 quirk_nvidia_ck804_pcie_aer_ext_cap);
1627
1da177e4
LT		 1628EXPORT_SYMBOL(pcie_mch_quirk);
1629#ifdef CONFIG_HOTPLUG
1630EXPORT_SYMBOL(pci_fixup_device);
1631#endif
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