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Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes...
[net-next-2.6.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
9f23ed3b 24#include <linux/kallsyms.h>
75e07fc3 25#include <linux/dmi.h>
649426ef 26#include <linux/pci-aspm.h>
32a9a682 27#include <linux/ioport.h>
93177a74 28#include <asm/dma.h> /* isa_dma_bridge_buggy */
bc56b9e0 29#include "pci.h"
1da177e4 30
32a9a682 31/*
0cdbe30f
YS		 32 * This quirk function disables memory decoding and releases memory resources
33 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
32a9a682
YS		 34 * It also rounds up size to specified alignment.
35 * Later on, the kernel will assign page-aligned memory resource back
0cdbe30f 36 * to the device.
32a9a682
YS		 37 */
38static void __devinit quirk_resource_alignment(struct pci_dev *dev)
39{
40 int i;
41 struct resource *r;
42 resource_size_t align, size;
0cdbe30f 43 u16 command;
32a9a682
YS		 44
45 if (!pci_is_reassigndev(dev))
46 return;
47
48 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
49 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
50 dev_warn(&dev->dev,
51 "Can't reassign resources to host bridge.\n");
52 return;
53 }
54
0cdbe30f
YS		 55 dev_info(&dev->dev,
56 "Disabling memory decoding and releasing memory resources.\n");
57 pci_read_config_word(dev, PCI_COMMAND, &command);
58 command &= ~PCI_COMMAND_MEMORY;
59 pci_write_config_word(dev, PCI_COMMAND, command);
32a9a682
YS		 60
61 align = pci_specified_resource_alignment(dev);
62 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
63 r = &dev->resource[i];
64 if (!(r->flags & IORESOURCE_MEM))
65 continue;
66 size = resource_size(r);
67 if (size < align) {
68 size = align;
69 dev_info(&dev->dev,
70 "Rounding up size of resource #%d to %#llx.\n",
71 i, (unsigned long long)size);
72 }
73 r->end = size - 1;
74 r->start = 0;
75 }
76 /* Need to disable bridge's resource window,
77 * to enable the kernel to reassign new resource
78 * window later on.
79 */
80 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
81 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
82 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
83 r = &dev->resource[i];
84 if (!(r->flags & IORESOURCE_MEM))
85 continue;
86 r->end = resource_size(r) - 1;
87 r->start = 0;
88 }
89 pci_disable_bridge_window(dev);
90 }
91}
92DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
93
253d2e54
JP		 94/*
95 * Decoding should be disabled for a PCI device during BAR sizing to avoid
96 * conflict. But doing so may cause problems on host bridge and perhaps other
97 * key system devices. For devices that need to have mmio decoding always-on,
98 * we need to set the dev->mmio_always_on bit.
99 */
100static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
101{
102 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
103 dev->mmio_always_on = 1;
104}
105DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on);
106
bd8481e1
DT		 107/* The Mellanox Tavor device gives false positive parity errors
108 * Mark this device with a broken_parity_status, to allow
109 * PCI scanning code to "skip" this now blacklisted device.
110 */
111static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
112{
113 dev->broken_parity_status = 1; /* This device gives false positives */
114}
115DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
117
1da177e4
LT		 118/* Deal with broken BIOS'es that neglect to enable passive release,
119 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 120static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 121{
122 struct pci_dev *d = NULL;
123 unsigned char dlc;
124
125 /* We have to make sure a particular bit is set in the PIIX3
126 ISA bridge, so we have to go out and find it. */
127 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
128 pci_read_config_byte(d, 0x82, &dlc);
129 if (!(dlc & 1<<1)) {
999da9fd 130 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 131 dlc |= 1<<1;
132 pci_write_config_byte(d, 0x82, dlc);
133 }
134 }
135}
652c538e
AM		 136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
137DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4
LT		 138
139/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
140 but VIA don't answer queries. If you happen to have good contacts at VIA
141 ask them for me please -- Alan
142
143 This appears to be BIOS not version dependent. So presumably there is a
144 chipset level fix */
1da177e4
LT		 145
146static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
147{
148 if (!isa_dma_bridge_buggy) {
149 isa_dma_bridge_buggy=1;
f0fda801 150 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 151 }
152}
153 /*
154 * Its not totally clear which chipsets are the problematic ones
155 * We know 82C586 and 82C596 variants are affected.
156 */
652c538e
AM		 157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4 164
4731fdcf
LB		 165/*
166 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
167 * for some HT machines to use C4 w/o hanging.
168 */
169static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
170{
171 u32 pmbase;
172 u16 pm1a;
173
174 pci_read_config_dword(dev, 0x40, &pmbase);
175 pmbase = pmbase & 0xff80;
176 pm1a = inw(pmbase);
177
178 if (pm1a & 0x10) {
179 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
180 outw(0x10, pmbase);
181 }
182}
183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
184
1da177e4
LT		 185/*
186 * Chipsets where PCI->PCI transfers vanish or hang
187 */
188static void __devinit quirk_nopcipci(struct pci_dev *dev)
189{
190 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
f0fda801 191 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 192 pci_pci_problems |= PCIPCI_FAIL;
193 }
194}
652c538e
AM		 195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5
AC		 197
198static void __devinit quirk_nopciamd(struct pci_dev *dev)
199{
200 u8 rev;
201 pci_read_config_byte(dev, 0x08, &rev);
202 if (rev == 0x13) {
203 /* Erratum 24 */
f0fda801 204 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 205 pci_pci_problems |= PCIAGP_FAIL;
206 }
207}
652c538e 208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4
LT		 209
210/*
211 * Triton requires workarounds to be used by the drivers
212 */
213static void __devinit quirk_triton(struct pci_dev *dev)
214{
215 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
f0fda801 216 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 217 pci_pci_problems |= PCIPCI_TRITON;
218 }
219}
652c538e
AM		 220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 224
225/*
226 * VIA Apollo KT133 needs PCI latency patch
227 * Made according to a windows driver based patch by George E. Breese
228 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
631dd1a8 229 * and http://www.georgebreese.com/net/software/#PCI
1da177e4
LT		 230 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
231 * the info on which Mr Breese based his work.
232 *
233 * Updated based on further information from the site and also on
234 * information provided by VIA
235 */
1597cacb 236static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 237{
238 struct pci_dev *p;
1da177e4
LT		 239 u8 busarb;
240 /* Ok we have a potential problem chipset here. Now see if we have
241 a buggy southbridge */
242
243 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
244 if (p!=NULL) {
1da177e4
LT		 245 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
246 /* Check for buggy part revisions */
2b1afa87 247 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 248 goto exit;
249 } else {
250 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
251 if (p==NULL) /* No problem parts */
252 goto exit;
1da177e4 253 /* Check for buggy part revisions */
2b1afa87 254 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 255 goto exit;
256 }
257
258 /*
259 * Ok we have the problem. Now set the PCI master grant to
260 * occur every master grant. The apparent bug is that under high
261 * PCI load (quite common in Linux of course) you can get data
262 * loss when the CPU is held off the bus for 3 bus master requests
263 * This happens to include the IDE controllers....
264 *
265 * VIA only apply this fix when an SB Live! is present but under
266 * both Linux and Windows this isnt enough, and we have seen
267 * corruption without SB Live! but with things like 3 UDMA IDE
268 * controllers. So we ignore that bit of the VIA recommendation..
269 */
270
271 pci_read_config_byte(dev, 0x76, &busarb);
272 /* Set bit 4 and bi 5 of byte 76 to 0x01
273 "Master priority rotation on every PCI master grant */
274 busarb &= ~(1<<5);
275 busarb |= (1<<4);
276 pci_write_config_byte(dev, 0x76, busarb);
f0fda801 277 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 278exit:
279 pci_dev_put(p);
280}
652c538e
AM		 281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
283DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 284/* Must restore this on a resume from RAM */
652c538e
AM		 285DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
286DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
287DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4
LT		 288
289/*
290 * VIA Apollo VP3 needs ETBF on BT848/878
291 */
292static void __devinit quirk_viaetbf(struct pci_dev *dev)
293{
294 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
f0fda801 295 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 296 pci_pci_problems |= PCIPCI_VIAETBF;
297 }
298}
652c538e 299DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4
LT		 300
301static void __devinit quirk_vsfx(struct pci_dev *dev)
302{
303 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
f0fda801 304 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 305 pci_pci_problems |= PCIPCI_VSFX;
306 }
307}
652c538e 308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 309
310/*
311 * Ali Magik requires workarounds to be used by the drivers
312 * that DMA to AGP space. Latency must be set to 0xA and triton
313 * workaround applied too
314 * [Info kindly provided by ALi]
315 */
316static void __init quirk_alimagik(struct pci_dev *dev)
317{
318 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
f0fda801 319 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 320 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
321 }
322}
652c538e
AM		 323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4
LT		 325
326/*
327 * Natoma has some interesting boundary conditions with Zoran stuff
328 * at least
329 */
330static void __devinit quirk_natoma(struct pci_dev *dev)
331{
332 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
f0fda801 333 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 334 pci_pci_problems |= PCIPCI_NATOMA;
335 }
336}
652c538e
AM		 337DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
339DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
342DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 343
344/*
345 * This chip can cause PCI parity errors if config register 0xA0 is read
346 * while DMAs are occurring.
347 */
348static void __devinit quirk_citrine(struct pci_dev *dev)
349{
350 dev->cfg_size = 0xA0;
351}
652c538e 352DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4
LT		 353
354/*
355 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
356 * If it's needed, re-allocate the region.
357 */
358static void __devinit quirk_s3_64M(struct pci_dev *dev)
359{
360 struct resource *r = &dev->resource[0];
361
362 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
363 r->start = 0;
364 r->end = 0x3ffffff;
365 }
366}
652c538e
AM		 367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 369
73d2eaac
AS		 370/*
371 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
372 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
373 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
374 * (which conflicts w/ BAR1's memory range).
375 */
376static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
377{
378 if (pci_resource_len(dev, 0) != 8) {
379 struct resource *res = &dev->resource[0];
380 res->end = res->start + 8 - 1;
381 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
382 "(incorrect header); workaround applied.\n");
383 }
384}
385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
386
6693e74a
LT		 387static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
388 unsigned size, int nr, const char *name)
1da177e4
LT		 389{
390 region &= ~(size-1);
391 if (region) {
085ae41f 392 struct pci_bus_region bus_region;
1da177e4
LT		 393 struct resource *res = dev->resource + nr;
394
395 res->name = pci_name(dev);
396 res->start = region;
397 res->end = region + size - 1;
398 res->flags = IORESOURCE_IO;
085ae41f
DM		 399
400 /* Convert from PCI bus to resource space. */
401 bus_region.start = res->start;
402 bus_region.end = res->end;
403 pcibios_bus_to_resource(dev, res, &bus_region);
404
f967a443
BH		 405 if (pci_claim_resource(dev, nr) == 0)
406 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
407 res, name);
1da177e4
LT		 408 }
409}
410
411/*
412 * ATI Northbridge setups MCE the processor if you even
413 * read somewhere between 0x3b0->0x3bb or read 0x3d3
414 */
415static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
416{
f0fda801 417 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 418 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
419 request_region(0x3b0, 0x0C, "RadeonIGP");
420 request_region(0x3d3, 0x01, "RadeonIGP");
421}
652c538e 422DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4
LT		 423
424/*
425 * Let's make the southbridge information explicit instead
426 * of having to worry about people probing the ACPI areas,
427 * for example.. (Yes, it happens, and if you read the wrong
428 * ACPI register it will put the machine to sleep with no
429 * way of waking it up again. Bummer).
430 *
431 * ALI M7101: Two IO regions pointed to by words at
432 * 0xE0 (64 bytes of ACPI registers)
433 * 0xE2 (32 bytes of SMB registers)
434 */
435static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
436{
437 u16 region;
438
439 pci_read_config_word(dev, 0xE0, &region);
6693e74a 440 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 441 pci_read_config_word(dev, 0xE2, &region);
6693e74a 442 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 443}
652c538e 444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 445
6693e74a
LT		 446static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
447{
448 u32 devres;
449 u32 mask, size, base;
450
451 pci_read_config_dword(dev, port, &devres);
452 if ((devres & enable) != enable)
453 return;
454 mask = (devres >> 16) & 15;
455 base = devres & 0xffff;
456 size = 16;
457 for (;;) {
458 unsigned bit = size >> 1;
459 if ((bit & mask) == bit)
460 break;
461 size = bit;
462 }
463 /*
464 * For now we only print it out. Eventually we'll want to
465 * reserve it (at least if it's in the 0x1000+ range), but
466 * let's get enough confirmation reports first.
467 */
468 base &= -size;
f0fda801 469 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 470}
471
472static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
473{
474 u32 devres;
475 u32 mask, size, base;
476
477 pci_read_config_dword(dev, port, &devres);
478 if ((devres & enable) != enable)
479 return;
480 base = devres & 0xffff0000;
481 mask = (devres & 0x3f) << 16;
482 size = 128 << 16;
483 for (;;) {
484 unsigned bit = size >> 1;
485 if ((bit & mask) == bit)
486 break;
487 size = bit;
488 }
489 /*
490 * For now we only print it out. Eventually we'll want to
491 * reserve it, but let's get enough confirmation reports first.
492 */
493 base &= -size;
f0fda801 494 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 495}
496
1da177e4
LT		 497/*
498 * PIIX4 ACPI: Two IO regions pointed to by longwords at
499 * 0x40 (64 bytes of ACPI registers)
08db2a70 500 * 0x90 (16 bytes of SMB registers)
6693e74a 501 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 502 */
503static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
504{
6693e74a 505 u32 region, res_a;
1da177e4
LT		 506
507 pci_read_config_dword(dev, 0x40, &region);
6693e74a 508 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 509 pci_read_config_dword(dev, 0x90, &region);
08db2a70 510 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 511
512 /* Device resource A has enables for some of the other ones */
513 pci_read_config_dword(dev, 0x5c, &res_a);
514
515 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
516 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
517
518 /* Device resource D is just bitfields for static resources */
519
520 /* Device 12 enabled? */
521 if (res_a & (1 << 29)) {
522 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
523 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
524 }
525 /* Device 13 enabled? */
526 if (res_a & (1 << 30)) {
527 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
528 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
529 }
530 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
531 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 532}
652c538e
AM		 533DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
534DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4
LT		 535
536/*
537 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
538 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
539 * 0x58 (64 bytes of GPIO I/O space)
540 */
541static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
542{
543 u32 region;
544
545 pci_read_config_dword(dev, 0x40, &region);
6693e74a 546 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 547
548 pci_read_config_dword(dev, 0x58, &region);
6693e74a 549 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4 550}
652c538e
AM		 551DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
552DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
553DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
554DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
555DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
556DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
557DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
558DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
559DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
560DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 561
894886e5 562static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
2cea752f
RM		 563{
564 u32 region;
565
566 pci_read_config_dword(dev, 0x40, &region);
567 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
568
569 pci_read_config_dword(dev, 0x48, &region);
570 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
571}
894886e5
LT		 572
573static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
574{
575 u32 val;
576 u32 size, base;
577
578 pci_read_config_dword(dev, reg, &val);
579
580 /* Enabled? */
581 if (!(val & 1))
582 return;
583 base = val & 0xfffc;
584 if (dynsize) {
585 /*
586 * This is not correct. It is 16, 32 or 64 bytes depending on
587 * register D31:F0:ADh bits 5:4.
588 *
589 * But this gets us at least _part_ of it.
590 */
591 size = 16;
592 } else {
593 size = 128;
594 }
595 base &= ~(size-1);
596
597 /* Just print it out for now. We should reserve it after more debugging */
598 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
599}
600
601static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
602{
603 /* Shared ACPI/GPIO decode with all ICH6+ */
604 ich6_lpc_acpi_gpio(dev);
605
606 /* ICH6-specific generic IO decode */
607 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
608 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
609}
610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
611DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
612
613static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
614{
615 u32 val;
616 u32 mask, base;
617
618 pci_read_config_dword(dev, reg, &val);
619
620 /* Enabled? */
621 if (!(val & 1))
622 return;
623
624 /*
625 * IO base in bits 15:2, mask in bits 23:18, both
626 * are dword-based
627 */
628 base = val & 0xfffc;
629 mask = (val >> 16) & 0xfc;
630 mask |= 3;
631
632 /* Just print it out for now. We should reserve it after more debugging */
633 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
634}
635
636/* ICH7-10 has the same common LPC generic IO decode registers */
637static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
638{
639 /* We share the common ACPI/DPIO decode with ICH6 */
640 ich6_lpc_acpi_gpio(dev);
641
642 /* And have 4 ICH7+ generic decodes */
643 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
644 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
645 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
646 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
647}
648DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
649DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
650DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
651DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
652DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
653DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
654DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
655DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
656DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
657DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
659DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
660DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
2cea752f 661
1da177e4
LT		 662/*
663 * VIA ACPI: One IO region pointed to by longword at
664 * 0x48 or 0x20 (256 bytes of ACPI registers)
665 */
666static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
667{
1da177e4
LT		 668 u32 region;
669
651472fb 670 if (dev->revision & 0x10) {
1da177e4
LT		 671 pci_read_config_dword(dev, 0x48, &region);
672 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 673 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 674 }
675}
652c538e 676DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 677
678/*
679 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
680 * 0x48 (256 bytes of ACPI registers)
681 * 0x70 (128 bytes of hardware monitoring register)
682 * 0x90 (16 bytes of SMB registers)
683 */
684static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
685{
686 u16 hm;
687 u32 smb;
688
689 quirk_vt82c586_acpi(dev);
690
691 pci_read_config_word(dev, 0x70, &hm);
692 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 693 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 694
695 pci_read_config_dword(dev, 0x90, &smb);
696 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 697 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4 698}
652c538e 699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 700
6d85f29b
IK		 701/*
702 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
703 * 0x88 (128 bytes of power management registers)
704 * 0xd0 (16 bytes of SMB registers)
705 */
706static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
707{
708 u16 pm, smb;
709
710 pci_read_config_word(dev, 0x88, &pm);
711 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 712 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 713
714 pci_read_config_word(dev, 0xd0, &smb);
715 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 716 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 717}
718DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
719
1f56f4a2
GB		 720/*
721 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
722 * Disable fast back-to-back on the secondary bus segment
723 */
724static void __devinit quirk_xio2000a(struct pci_dev *dev)
725{
726 struct pci_dev *pdev;
727 u16 command;
728
729 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
730 "secondary bus fast back-to-back transfers disabled\n");
731 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
732 pci_read_config_word(pdev, PCI_COMMAND, &command);
733 if (command & PCI_COMMAND_FAST_BACK)
734 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
735 }
736}
737DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
738 quirk_xio2000a);
1da177e4
LT		 739
740#ifdef CONFIG_X86_IO_APIC
741
742#include <asm/io_apic.h>
743
744/*
745 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
746 * devices to the external APIC.
747 *
748 * TODO: When we have device-specific interrupt routers,
749 * this code will go away from quirks.
750 */
1597cacb 751static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 752{
753 u8 tmp;
754
755 if (nr_ioapics < 1)
756 tmp = 0; /* nothing routed to external APIC */
757 else
758 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
759
f0fda801 760 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 761 tmp == 0 ? "Disa" : "Ena");
762
763 /* Offset 0x58: External APIC IRQ output control */
764 pci_write_config_byte (dev, 0x58, tmp);
765}
652c538e 766DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 767DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 768
a1740913
KW		 769/*
770 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
771 * This leads to doubled level interrupt rates.
772 * Set this bit to get rid of cycle wastage.
773 * Otherwise uncritical.
774 */
1597cacb 775static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 776{
777 u8 misc_control2;
778#define BYPASS_APIC_DEASSERT 8
779
780 pci_read_config_byte(dev, 0x5B, &misc_control2);
781 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
f0fda801 782 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 783 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
784 }
785}
786DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 787DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 788
1da177e4
LT		 789/*
790 * The AMD io apic can hang the box when an apic irq is masked.
791 * We check all revs >= B0 (yet not in the pre production!) as the bug
792 * is currently marked NoFix
793 *
794 * We have multiple reports of hangs with this chipset that went away with
236561e5 795 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 796 * of course. However the advice is demonstrably good even if so..
797 */
798static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
799{
44c10138 800 if (dev->revision >= 0x02) {
f0fda801 801 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
802 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 803 }
804}
652c538e 805DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4
LT		 806
807static void __init quirk_ioapic_rmw(struct pci_dev *dev)
808{
809 if (dev->devfn == 0 && dev->bus->number == 0)
810 sis_apic_bug = 1;
811}
652c538e 812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
1da177e4
LT		 813#endif /* CONFIG_X86_IO_APIC */
814
d556ad4b
PO		 815/*
816 * Some settings of MMRBC can lead to data corruption so block changes.
817 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
818 */
819static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
820{
aa288d4d 821 if (dev->subordinate && dev->revision <= 0x12) {
f0fda801 822 dev_info(&dev->dev, "AMD8131 rev %x detected; "
823 "disabling PCI-X MMRBC\n", dev->revision);
d556ad4b
PO		 824 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
825 }
826}
827DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 828
1da177e4
LT		 829/*
830 * FIXME: it is questionable that quirk_via_acpi
831 * is needed. It shows up as an ISA bridge, and does not
832 * support the PCI_INTERRUPT_LINE register at all. Therefore
833 * it seems like setting the pci_dev's 'irq' to the
834 * value of the ACPI SCI interrupt is only done for convenience.
835 * -jgarzik
836 */
837static void __devinit quirk_via_acpi(struct pci_dev *d)
838{
839 /*
840 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
841 */
842 u8 irq;
843 pci_read_config_byte(d, 0x42, &irq);
844 irq &= 0xf;
845 if (irq && (irq != 2))
846 d->irq = irq;
847}
652c538e
AM		 848DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
849DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 850
09d6029f
DD		 851
852/*
1597cacb 853 * VIA bridges which have VLink
09d6029f 854 */
1597cacb 855
c06bb5d4
JD		 856static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
857
858static void quirk_via_bridge(struct pci_dev *dev)
859{
860 /* See what bridge we have and find the device ranges */
861 switch (dev->device) {
862 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 863 /* The VT82C686 is special, it attaches to PCI and can have
864 any device number. All its subdevices are functions of
865 that single device. */
866 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
867 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 868 break;
869 case PCI_DEVICE_ID_VIA_8237:
870 case PCI_DEVICE_ID_VIA_8237A:
871 via_vlink_dev_lo = 15;
872 break;
873 case PCI_DEVICE_ID_VIA_8235:
874 via_vlink_dev_lo = 16;
875 break;
876 case PCI_DEVICE_ID_VIA_8231:
877 case PCI_DEVICE_ID_VIA_8233_0:
878 case PCI_DEVICE_ID_VIA_8233A:
879 case PCI_DEVICE_ID_VIA_8233C_0:
880 via_vlink_dev_lo = 17;
881 break;
882 }
883}
884DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
888DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
889DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
890DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
891DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 892
1597cacb
AC		 893/**
894 * quirk_via_vlink - VIA VLink IRQ number update
895 * @dev: PCI device
896 *
897 * If the device we are dealing with is on a PIC IRQ we need to
898 * ensure that the IRQ line register which usually is not relevant
899 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 900 * to the right place.
901 * We only do this on systems where a VIA south bridge was detected,
902 * and only for VIA devices on the motherboard (see quirk_via_bridge
903 * above).
1597cacb
AC		 904 */
905
906static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 907{
908 u8 irq, new_irq;
909
c06bb5d4
JD		 910 /* Check if we have VLink at all */
911 if (via_vlink_dev_lo == -1)
09d6029f
DD		 912 return;
913
914 new_irq = dev->irq;
915
916 /* Don't quirk interrupts outside the legacy IRQ range */
917 if (!new_irq || new_irq > 15)
918 return;
919
1597cacb 920 /* Internal device ? */
c06bb5d4
JD		 921 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
922 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 923 return;
924
925 /* This is an internal VLink device on a PIC interrupt. The BIOS
926 ought to have set this but may not have, so we redo it */
927
25be5e6c
LB		 928 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
929 if (new_irq != irq) {
f0fda801 930 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
931 irq, new_irq);
25be5e6c
LB		 932 udelay(15); /* unknown if delay really needed */
933 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
934 }
935}
1597cacb 936DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 937
1da177e4
LT		 938/*
939 * VIA VT82C598 has its device ID settable and many BIOSes
940 * set it to the ID of VT82C597 for backward compatibility.
941 * We need to switch it off to be able to recognize the real
942 * type of the chip.
943 */
944static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
945{
946 pci_write_config_byte(dev, 0xfc, 0);
947 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
948}
652c538e 949DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 950
951/*
952 * CardBus controllers have a legacy base address that enables them
953 * to respond as i82365 pcmcia controllers. We don't want them to
954 * do this even if the Linux CardBus driver is not loaded, because
955 * the Linux i82365 driver does not (and should not) handle CardBus.
956 */
1597cacb 957static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4
LT		 958{
959 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
960 return;
961 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
962}
963DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
e1a2a51e 964DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1da177e4
LT		 965
966/*
967 * Following the PCI ordering rules is optional on the AMD762. I'm not
968 * sure what the designers were smoking but let's not inhale...
969 *
970 * To be fair to AMD, it follows the spec by default, its BIOS people
971 * who turn it off!
972 */
1597cacb 973static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 974{
975 u32 pcic;
976 pci_read_config_dword(dev, 0x4C, &pcic);
977 if ((pcic&6)!=6) {
978 pcic |= 6;
f0fda801 979 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 980 pci_write_config_dword(dev, 0x4C, pcic);
981 pci_read_config_dword(dev, 0x84, &pcic);
982 pcic |= (1<<23); /* Required in this mode */
983 pci_write_config_dword(dev, 0x84, pcic);
984 }
985}
652c538e 986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 987DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 988
989/*
990 * DreamWorks provided workaround for Dunord I-3000 problem
991 *
992 * This card decodes and responds to addresses not apparently
993 * assigned to it. We force a larger allocation to ensure that
994 * nothing gets put too close to it.
995 */
996static void __devinit quirk_dunord ( struct pci_dev * dev )
997{
998 struct resource *r = &dev->resource [1];
999 r->start = 0;
1000 r->end = 0xffffff;
1001}
652c538e 1002DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 1003
1004/*
1005 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1006 * is subtractive decoding (transparent), and does indicate this
1007 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1008 * instead of 0x01.
1009 */
1010static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
1011{
1012 dev->transparent = 1;
1013}
652c538e
AM		 1014DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1015DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 1016
1017/*
1018 * Common misconfiguration of the MediaGX/Geode PCI master that will
1019 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
631dd1a8 1020 * datasheets found at http://www.national.com/analog for info on what
1da177e4
LT		 1021 * these bits do. <christer@weinigel.se>
1022 */
1597cacb 1023static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 1024{
1025 u8 reg;
1026 pci_read_config_byte(dev, 0x41, &reg);
1027 if (reg & 2) {
1028 reg &= ~2;
f0fda801 1029 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1da177e4
LT		 1030 pci_write_config_byte(dev, 0x41, reg);
1031 }
1032}
652c538e
AM		 1033DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1034DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 1035
1da177e4
LT		 1036/*
1037 * Ensure C0 rev restreaming is off. This is normally done by
1038 * the BIOS but in the odd case it is not the results are corruption
1039 * hence the presence of a Linux check
1040 */
1597cacb 1041static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 1042{
1043 u16 config;
1da177e4 1044
44c10138 1045 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 1046 return;
1047 pci_read_config_word(pdev, 0x40, &config);
1048 if (config & (1<<6)) {
1049 config &= ~(1<<6);
1050 pci_write_config_word(pdev, 0x40, config);
f0fda801 1051 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 1052 }
1053}
652c538e 1054DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 1055DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 1056
05a7d22b 1057static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 1058{
5deab536 1059 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
05a7d22b 1060 u8 tmp;
ab17443a 1061
05a7d22b
CC		 1062 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1063 if (tmp == 0x01) {
ab17443a
CH		 1064 pci_read_config_byte(pdev, 0x40, &tmp);
1065 pci_write_config_byte(pdev, 0x40, tmp|1);
1066 pci_write_config_byte(pdev, 0x9, 1);
1067 pci_write_config_byte(pdev, 0xa, 6);
1068 pci_write_config_byte(pdev, 0x40, tmp);
1069
c9f89475 1070 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
05a7d22b 1071 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
ab17443a
CH		 1072 }
1073}
05a7d22b 1074DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 1075DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 1076DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 1077DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
5deab536
SH		 1078DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1079DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
ab17443a 1080
1da177e4
LT		 1081/*
1082 * Serverworks CSB5 IDE does not fully support native mode
1083 */
1084static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1085{
1086 u8 prog;
1087 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1088 if (prog & 5) {
1089 prog &= ~5;
1090 pdev->class &= ~5;
1091 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 1092 /* PCI layer will sort out resources */
1da177e4
LT		 1093 }
1094}
652c538e 1095DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4
LT		 1096
1097/*
1098 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1099 */
1100static void __init quirk_ide_samemode(struct pci_dev *pdev)
1101{
1102 u8 prog;
1103
1104 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1105
1106 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
f0fda801 1107 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 1108 prog &= ~5;
1109 pdev->class &= ~5;
1110 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 1111 }
1112}
368c73d4 1113DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4 1114
979b1791
AC		 1115/*
1116 * Some ATA devices break if put into D3
1117 */
1118
1119static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1120{
1121 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1122 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1123 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1124}
1125DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1126DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
7a661c6f
AC		 1127/* ALi loses some register settings that we cannot then restore */
1128DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1129/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1130 occur when mode detecting */
1131DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
979b1791 1132
1da177e4
LT		 1133/* This was originally an Alpha specific thing, but it really fits here.
1134 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1135 */
1136static void __init quirk_eisa_bridge(struct pci_dev *dev)
1137{
1138 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1139}
652c538e 1140DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4 1141
7daa0c4f 1142
1da177e4
LT		 1143/*
1144 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1145 * is not activated. The myth is that Asus said that they do not want the
1146 * users to be irritated by just another PCI Device in the Win98 device
1147 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1148 * package 2.7.0 for details)
1149 *
1150 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1151 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 1152 * becomes necessary to do this tweak in two steps -- the chosen trigger
1153 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 1154 *
1155 * Note that we used to unhide the SMBus that way on Toshiba laptops
1156 * (Satellite A40 and Tecra M2) but then found that the thermal management
1157 * was done by SMM code, which could cause unsynchronized concurrent
1158 * accesses to the SMBus registers, with potentially bad effects. Thus you
1159 * should be very careful when adding new entries: if SMM is accessing the
1160 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 1161 *
1162 * Likewise, many recent laptops use ACPI for thermal management. If the
1163 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1164 * natively, and keeping the SMBus hidden is the right thing to do. If you
1165 * are about to add an entry in the table below, please first disassemble
1166 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 1167 */
9d24a81e 1168static int asus_hides_smbus;
1da177e4
LT		 1169
1170static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1171{
1172 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1173 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1174 switch(dev->subsystem_device) {
a00db371 1175 case 0x8025: /* P4B-LX */
1da177e4
LT		 1176 case 0x8070: /* P4B */
1177 case 0x8088: /* P4B533 */
1178 case 0x1626: /* L3C notebook */
1179 asus_hides_smbus = 1;
1180 }
2f2d39d2 1181 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 1182 switch(dev->subsystem_device) {
1183 case 0x80b1: /* P4GE-V */
1184 case 0x80b2: /* P4PE */
1185 case 0x8093: /* P4B533-V */
1186 asus_hides_smbus = 1;
1187 }
2f2d39d2 1188 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 1189 switch(dev->subsystem_device) {
1190 case 0x8030: /* P4T533 */
1191 asus_hides_smbus = 1;
1192 }
2f2d39d2 1193 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 1194 switch (dev->subsystem_device) {
1195 case 0x8070: /* P4G8X Deluxe */
1196 asus_hides_smbus = 1;
1197 }
2f2d39d2 1198 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 1199 switch (dev->subsystem_device) {
1200 case 0x80c9: /* PU-DLS */
1201 asus_hides_smbus = 1;
1202 }
2f2d39d2 1203 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 1204 switch (dev->subsystem_device) {
1205 case 0x1751: /* M2N notebook */
1206 case 0x1821: /* M5N notebook */
4096ed0f 1207 case 0x1897: /* A6L notebook */
1da177e4
LT		 1208 asus_hides_smbus = 1;
1209 }
2f2d39d2 1210 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1211 switch (dev->subsystem_device) {
1212 case 0x184b: /* W1N notebook */
1213 case 0x186a: /* M6Ne notebook */
1214 asus_hides_smbus = 1;
1215 }
2f2d39d2 1216 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1217 switch (dev->subsystem_device) {
1218 case 0x80f2: /* P4P800-X */
1219 asus_hides_smbus = 1;
1220 }
2f2d39d2 1221 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
RM		 1222 switch (dev->subsystem_device) {
1223 case 0x1882: /* M6V notebook */
2d1e1c75 1224 case 0x1977: /* A6VA notebook */
acc06632
RM		 1225 asus_hides_smbus = 1;
1226 }
1da177e4
LT		 1227 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1228 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1229 switch(dev->subsystem_device) {
1230 case 0x088C: /* HP Compaq nc8000 */
1231 case 0x0890: /* HP Compaq nc6000 */
1232 asus_hides_smbus = 1;
1233 }
2f2d39d2 1234 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1235 switch (dev->subsystem_device) {
1236 case 0x12bc: /* HP D330L */
e3b1bd57 1237 case 0x12bd: /* HP D530 */
74c57428 1238 case 0x006a: /* HP Compaq nx9500 */
1da177e4
LT		 1239 asus_hides_smbus = 1;
1240 }
677cc644
JD		 1241 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1242 switch (dev->subsystem_device) {
1243 case 0x12bf: /* HP xw4100 */
1244 asus_hides_smbus = 1;
1245 }
1da177e4
LT		 1246 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1247 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1248 switch(dev->subsystem_device) {
1249 case 0xC00C: /* Samsung P35 notebook */
1250 asus_hides_smbus = 1;
1251 }
c87f883e
RIZ		 1252 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1253 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1254 switch(dev->subsystem_device) {
1255 case 0x0058: /* Compaq Evo N620c */
1256 asus_hides_smbus = 1;
1257 }
d7698edc 1258 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1259 switch(dev->subsystem_device) {
1260 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1261 /* Motherboard doesn't have Host bridge
1262 * subvendor/subdevice IDs, therefore checking
1263 * its on-board VGA controller */
1264 asus_hides_smbus = 1;
1265 }
8293b0f6 1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
10260d9a
JD		 1267 switch(dev->subsystem_device) {
1268 case 0x00b8: /* Compaq Evo D510 CMT */
1269 case 0x00b9: /* Compaq Evo D510 SFF */
6b5096e4 1270 case 0x00ba: /* Compaq Evo D510 USDT */
8293b0f6
DS		 1271 /* Motherboard doesn't have Host bridge
1272 * subvendor/subdevice IDs and on-board VGA
1273 * controller is disabled if an AGP card is
1274 * inserted, therefore checking USB UHCI
1275 * Controller #1 */
10260d9a
JD		 1276 asus_hides_smbus = 1;
1277 }
27e46859
KH		 1278 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1279 switch (dev->subsystem_device) {
1280 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1281 /* Motherboard doesn't have host bridge
1282 * subvendor/subdevice IDs, therefore checking
1283 * its on-board VGA controller */
1284 asus_hides_smbus = 1;
1285 }
1da177e4
LT		 1286 }
1287}
652c538e
AM		 1288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1290DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1293DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1295DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1296DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1297DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1298
1299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
8293b0f6 1300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
27e46859 1301DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
d7698edc 1302
1597cacb 1303static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1304{
1305 u16 val;
1306
1307 if (likely(!asus_hides_smbus))
1308 return;
1309
1310 pci_read_config_word(dev, 0xF2, &val);
1311 if (val & 0x8) {
1312 pci_write_config_word(dev, 0xF2, val & (~0x8));
1313 pci_read_config_word(dev, 0xF2, &val);
1314 if (val & 0x8)
f0fda801 1315 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1da177e4 1316 else
f0fda801 1317 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1318 }
1319}
652c538e
AM		 1320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1327DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1328DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1329DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1330DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1331DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1332DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1333DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1334
e1a2a51e
RW		 1335/* It appears we just have one such device. If not, we have a warning */
1336static void __iomem *asus_rcba_base;
1337static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1338{
e1a2a51e 1339 u32 rcba;
acc06632
RM		 1340
1341 if (likely(!asus_hides_smbus))
1342 return;
e1a2a51e
RW		 1343 WARN_ON(asus_rcba_base);
1344
acc06632 1345 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1346 /* use bits 31:14, 16 kB aligned */
1347 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1348 if (asus_rcba_base == NULL)
1349 return;
1350}
1351
1352static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1353{
1354 u32 val;
1355
1356 if (likely(!asus_hides_smbus || !asus_rcba_base))
1357 return;
1358 /* read the Function Disable register, dword mode only */
1359 val = readl(asus_rcba_base + 0x3418);
1360 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1361}
1362
1363static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1364{
1365 if (likely(!asus_hides_smbus || !asus_rcba_base))
1366 return;
1367 iounmap(asus_rcba_base);
1368 asus_rcba_base = NULL;
f0fda801 1369 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1370}
e1a2a51e
RW		 1371
1372static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1373{
1374 asus_hides_smbus_lpc_ich6_suspend(dev);
1375 asus_hides_smbus_lpc_ich6_resume_early(dev);
1376 asus_hides_smbus_lpc_ich6_resume(dev);
1377}
652c538e 1378DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1379DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1380DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1381DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1382
1da177e4
LT		 1383/*
1384 * SiS 96x south bridge: BIOS typically hides SMBus device...
1385 */
1597cacb 1386static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1387{
1388 u8 val = 0;
1da177e4 1389 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1390 if (val & 0x10) {
f0fda801 1391 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1392 pci_write_config_byte(dev, 0x77, val & ~0x10);
1393 }
1da177e4 1394}
652c538e
AM		 1395DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1396DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1397DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1398DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1399DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1400DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1401DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1402DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1403
1da177e4
LT		 1404/*
1405 * ... This is further complicated by the fact that some SiS96x south
1406 * bridges pretend to be 85C503/5513 instead. In that case see if we
1407 * spotted a compatible north bridge to make sure.
1408 * (pci_find_device doesn't work yet)
1409 *
1410 * We can also enable the sis96x bit in the discovery register..
1411 */
1da177e4
LT		 1412#define SIS_DETECT_REGISTER 0x40
1413
1597cacb 1414static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1415{
1416 u8 reg;
1417 u16 devid;
1418
1419 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1420 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1421 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1422 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1423 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1424 return;
1425 }
1426
1da177e4 1427 /*
2f5c33b3
MH		 1428 * Ok, it now shows up as a 96x.. run the 96x quirk by
1429 * hand in case it has already been processed.
1430 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1431 */
1432 dev->device = devid;
2f5c33b3 1433 quirk_sis_96x_smbus(dev);
1da177e4 1434}
652c538e 1435DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1436DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1437
1da177e4 1438
e5548e96
BJD		 1439/*
1440 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1441 * and MC97 modem controller are disabled when a second PCI soundcard is
1442 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1443 * -- bjd
1444 */
1597cacb 1445static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1446{
1447 u8 val;
1448 int asus_hides_ac97 = 0;
1449
1450 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1451 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1452 asus_hides_ac97 = 1;
1453 }
1454
1455 if (!asus_hides_ac97)
1456 return;
1457
1458 pci_read_config_byte(dev, 0x50, &val);
1459 if (val & 0xc0) {
1460 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1461 pci_read_config_byte(dev, 0x50, &val);
1462 if (val & 0xc0)
f0fda801 1463 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
e5548e96 1464 else
f0fda801 1465 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1466 }
1467}
652c538e 1468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1469DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1470
77967052 1471#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1472
1473/*
1474 * If we are using libata we can drive this chip properly but must
1475 * do this early on to make the additional device appear during
1476 * the PCI scanning.
1477 */
5ee2ae7f 1478static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1479{
e34bb370 1480 u32 conf1, conf5, class;
15e0c694
AC		 1481 u8 hdr;
1482
1483 /* Only poke fn 0 */
1484 if (PCI_FUNC(pdev->devfn))
1485 return;
1486
5ee2ae7f
TH		 1487 pci_read_config_dword(pdev, 0x40, &conf1);
1488 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1489
5ee2ae7f
TH		 1490 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1491 conf5 &= ~(1 << 24); /* Clear bit 24 */
1492
1493 switch (pdev->device) {
4daedcfe
TH		 1494 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1495 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
5b6ae5ba 1496 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
5ee2ae7f
TH		 1497 /* The controller should be in single function ahci mode */
1498 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1499 break;
1500
1501 case PCI_DEVICE_ID_JMICRON_JMB365:
1502 case PCI_DEVICE_ID_JMICRON_JMB366:
1503 /* Redirect IDE second PATA port to the right spot */
1504 conf5 |= (1 << 24);
1505 /* Fall through */
1506 case PCI_DEVICE_ID_JMICRON_JMB361:
1507 case PCI_DEVICE_ID_JMICRON_JMB363:
5b6ae5ba 1508 case PCI_DEVICE_ID_JMICRON_JMB369:
5ee2ae7f
TH		 1509 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1510 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1511 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1512 break;
1513
1514 case PCI_DEVICE_ID_JMICRON_JMB368:
1515 /* The controller should be in single function IDE mode */
1516 conf1 |= 0x00C00000; /* Set 22, 23 */
1517 break;
15e0c694 1518 }
5ee2ae7f
TH		 1519
1520 pci_write_config_dword(pdev, 0x40, conf1);
1521 pci_write_config_dword(pdev, 0x80, conf5);
1522
1523 /* Update pdev accordingly */
1524 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1525 pdev->hdr_type = hdr & 0x7f;
1526 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1527
1528 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1529 pdev->class = class >> 8;
15e0c694 1530}
5ee2ae7f
TH		 1531DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1532DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1533DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
5ee2ae7f 1534DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1535DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
5ee2ae7f
TH		 1536DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1537DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1538DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1539DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
e1a2a51e
RW		 1540DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1541DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1542DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
e1a2a51e 1543DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1544DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
e1a2a51e
RW		 1545DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1546DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1547DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1548DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
15e0c694
AC		 1549
1550#endif
1551
1da177e4
LT		 1552#ifdef CONFIG_X86_IO_APIC
1553static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1554{
1555 int i;
1556
1557 if ((pdev->class >> 8) != 0xff00)
1558 return;
1559
1560 /* the first BAR is the location of the IO APIC...we must
1561 * not touch this (and it's already covered by the fixmap), so
1562 * forcibly insert it into the resource tree */
1563 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1564 insert_resource(&iomem_resource, &pdev->resource[0]);
1565
1566 /* The next five BARs all seem to be rubbish, so just clean
1567 * them out */
1568 for (i=1; i < 6; i++) {
1569 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1570 }
1571
1572}
652c538e 1573DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1574#endif
1575
1da177e4
LT		 1576static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1577{
0ba379ec
EB		 1578 pci_msi_off(pdev);
1579 pdev->no_msi = 1;
1da177e4 1580}
652c538e
AM		 1581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1583DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1584
4602b88d
KA		 1585
1586/*
1587 * It's possible for the MSI to get corrupted if shpc and acpi
1588 * are used together on certain PXH-based systems.
1589 */
1590static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1591{
f5f2b131 1592 pci_msi_off(dev);
4602b88d 1593 dev->no_msi = 1;
f0fda801 1594 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1595}
1596DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1597DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1598DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1599DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1600DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1601
ffadcc2f
KCA		 1602/*
1603 * Some Intel PCI Express chipsets have trouble with downstream
1604 * device power management.
1605 */
1606static void quirk_intel_pcie_pm(struct pci_dev * dev)
1607{
1608 pci_pm_d3_delay = 120;
1609 dev->no_d1d2 = 1;
1610}
1611
1612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1621DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1622DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1627DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1630DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1632DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1633
426b3b8d 1634#ifdef CONFIG_X86_IO_APIC
e1d3a908
SA		 1635/*
1636 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1637 * remap the original interrupt in the linux kernel to the boot interrupt, so
1638 * that a PCI device's interrupt handler is installed on the boot interrupt
1639 * line instead.
1640 */
1641static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1642{
41b9eb26 1643 if (noioapicquirk || noioapicreroute)
e1d3a908
SA		 1644 return;
1645
1646 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
fdcdaf6c
BH		 1647 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1648 dev->vendor, dev->device);
e1d3a908 1649}
88d1dce3
OD		 1650DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1652DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1658DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1659DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1660DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1661DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1662DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1663DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1664DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1665DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
e1d3a908 1666
426b3b8d
SA		 1667/*
1668 * On some chipsets we can disable the generation of legacy INTx boot
1669 * interrupts.
1670 */
1671
1672/*
1673 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1674 * 300641-004US, section 5.7.3.
1675 */
1676#define INTEL_6300_IOAPIC_ABAR 0x40
1677#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1678
1679static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1680{
1681 u16 pci_config_word;
1682
1683 if (noioapicquirk)
1684 return;
1685
1686 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1687 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1688 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1689
fdcdaf6c
BH		 1690 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1691 dev->vendor, dev->device);
426b3b8d 1692}
88d1dce3
OD		 1693DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1694DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
77251188
OD		 1695
1696/*
1697 * disable boot interrupts on HT-1000
1698 */
1699#define BC_HT1000_FEATURE_REG 0x64
1700#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1701#define BC_HT1000_MAP_IDX 0xC00
1702#define BC_HT1000_MAP_DATA 0xC01
1703
1704static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1705{
1706 u32 pci_config_dword;
1707 u8 irq;
1708
1709 if (noioapicquirk)
1710 return;
1711
1712 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1713 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1714 BC_HT1000_PIC_REGS_ENABLE);
1715
1716 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1717 outb(irq, BC_HT1000_MAP_IDX);
1718 outb(0x00, BC_HT1000_MAP_DATA);
1719 }
1720
1721 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1722
fdcdaf6c
BH		 1723 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1724 dev->vendor, dev->device);
77251188 1725}
88d1dce3
OD		 1726DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1727DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
542622da
OD		 1728
1729/*
1730 * disable boot interrupts on AMD and ATI chipsets
1731 */
1732/*
1733 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1734 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1735 * (due to an erratum).
1736 */
1737#define AMD_813X_MISC 0x40
1738#define AMD_813X_NOIOAMODE (1<<0)
4fd8bdc5 1739#define AMD_813X_REV_B1 0x12
bbe19443 1740#define AMD_813X_REV_B2 0x13
542622da
OD		 1741
1742static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1743{
1744 u32 pci_config_dword;
1745
1746 if (noioapicquirk)
1747 return;
4fd8bdc5
SA		 1748 if ((dev->revision == AMD_813X_REV_B1) ||
1749 (dev->revision == AMD_813X_REV_B2))
bbe19443 1750 return;
542622da
OD		 1751
1752 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1753 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1754 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1755
fdcdaf6c
BH		 1756 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1757 dev->vendor, dev->device);
542622da 1758}
4fd8bdc5
SA		 1759DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1760DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1761DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1762DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
542622da
OD		 1763
1764#define AMD_8111_PCI_IRQ_ROUTING 0x56
1765
1766static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1767{
1768 u16 pci_config_word;
1769
1770 if (noioapicquirk)
1771 return;
1772
1773 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1774 if (!pci_config_word) {
fdcdaf6c
BH		 1775 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1776 "already disabled\n", dev->vendor, dev->device);
542622da
OD		 1777 return;
1778 }
1779 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
fdcdaf6c
BH		 1780 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1781 dev->vendor, dev->device);
542622da 1782}
88d1dce3
OD		 1783DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1784DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
426b3b8d
SA		 1785#endif /* CONFIG_X86_IO_APIC */
1786
33dced2e
SS		 1787/*
1788 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1789 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1790 * Re-allocate the region if needed...
1791 */
1792static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1793{
1794 struct resource *r = &dev->resource[0];
1795
1796 if (r->start & 0x8) {
1797 r->start = 0;
1798 r->end = 0xf;
1799 }
1800}
1801DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1802 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1803 quirk_tc86c001_ide);
1804
1da177e4
LT		 1805static void __devinit quirk_netmos(struct pci_dev *dev)
1806{
1807 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1808 unsigned int num_serial = dev->subsystem_device & 0xf;
1809
1810 /*
1811 * These Netmos parts are multiport serial devices with optional
1812 * parallel ports. Even when parallel ports are present, they
1813 * are identified as class SERIAL, which means the serial driver
1814 * will claim them. To prevent this, mark them as class OTHER.
1815 * These combo devices should be claimed by parport_serial.
1816 *
1817 * The subdevice ID is of the form 0x00PS, where <P> is the number
1818 * of parallel ports and <S> is the number of serial ports.
1819 */
1820 switch (dev->device) {
4c9c1686
JS		 1821 case PCI_DEVICE_ID_NETMOS_9835:
1822 /* Well, this rule doesn't hold for the following 9835 device */
1823 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1824 dev->subsystem_device == 0x0299)
1825 return;
1da177e4
LT		 1826 case PCI_DEVICE_ID_NETMOS_9735:
1827 case PCI_DEVICE_ID_NETMOS_9745:
1da177e4
LT		 1828 case PCI_DEVICE_ID_NETMOS_9845:
1829 case PCI_DEVICE_ID_NETMOS_9855:
1830 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1831 num_parallel) {
f0fda801 1832 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1da177e4
LT		 1833 "%u serial); changing class SERIAL to OTHER "
1834 "(use parport_serial)\n",
1835 dev->device, num_parallel, num_serial);
1836 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1837 (dev->class & 0xff);
1838 }
1839 }
1840}
1841DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1842
16a74744
BH		 1843static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1844{
e64aeccb 1845 u16 command, pmcsr;
16a74744
BH		 1846 u8 __iomem *csr;
1847 u8 cmd_hi;
e64aeccb 1848 int pm;
16a74744
BH		 1849
1850 switch (dev->device) {
1851 /* PCI IDs taken from drivers/net/e100.c */
1852 case 0x1029:
1853 case 0x1030 ... 0x1034:
1854 case 0x1038 ... 0x103E:
1855 case 0x1050 ... 0x1057:
1856 case 0x1059:
1857 case 0x1064 ... 0x106B:
1858 case 0x1091 ... 0x1095:
1859 case 0x1209:
1860 case 0x1229:
1861 case 0x2449:
1862 case 0x2459:
1863 case 0x245D:
1864 case 0x27DC:
1865 break;
1866 default:
1867 return;
1868 }
1869
1870 /*
1871 * Some firmware hands off the e100 with interrupts enabled,
1872 * which can cause a flood of interrupts if packets are
1873 * received before the driver attaches to the device. So
1874 * disable all e100 interrupts here. The driver will
1875 * re-enable them when it's ready.
1876 */
1877 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 1878
1bef7dc0 1879 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 1880 return;
1881
e64aeccb
IK		 1882 /*
1883 * Check that the device is in the D0 power state. If it's not,
1884 * there is no point to look any further.
1885 */
1886 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1887 if (pm) {
1888 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1889 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1890 return;
1891 }
1892
1bef7dc0
BH		 1893 /* Convert from PCI bus to resource space. */
1894 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 1895 if (!csr) {
f0fda801 1896 dev_warn(&dev->dev, "Can't map e100 registers\n");
16a74744
BH		 1897 return;
1898 }
1899
1900 cmd_hi = readb(csr + 3);
1901 if (cmd_hi == 0) {
f0fda801 1902 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1903 "disabling\n");
16a74744
BH		 1904 writeb(1, csr + 3);
1905 }
1906
1907 iounmap(csr);
1908}
4e68fc97 1909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28 1910
649426ef
AD		 1911/*
1912 * The 82575 and 82598 may experience data corruption issues when transitioning
1913 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1914 */
1915static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1916{
1917 dev_info(&dev->dev, "Disabling L0s\n");
1918 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1919}
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1923DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1924DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1925DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1926DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1927DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1928DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1932DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1933DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1934
a5312e28
IK		 1935static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1936{
1937 /* rev 1 ncr53c810 chips don't set the class at all which means
1938 * they don't get their resources remapped. Fix that here.
1939 */
1940
1941 if (dev->class == PCI_CLASS_NOT_DEFINED) {
f0fda801 1942 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
a5312e28
IK		 1943 dev->class = PCI_CLASS_STORAGE_SCSI;
1944 }
1945}
1946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1947
9d265124
DY		 1948/* Enable 1k I/O space granularity on the Intel P64H2 */
1949static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1950{
1951 u16 en1k;
1952 u8 io_base_lo, io_limit_lo;
1953 unsigned long base, limit;
1954 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1955
1956 pci_read_config_word(dev, 0x40, &en1k);
1957
1958 if (en1k & 0x200) {
f0fda801 1959 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
9d265124
DY		 1960
1961 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1962 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1963 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1964 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1965
1966 if (base <= limit) {
1967 res->start = base;
1968 res->end = limit + 0x3ff;
1969 }
1970 }
1971}
1972DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1973
15a260d5
DY		 1974/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1975 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1976 * in drivers/pci/setup-bus.c
1977 */
1978static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1979{
1980 u16 en1k, iobl_adr, iobl_adr_1k;
1981 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1982
1983 pci_read_config_word(dev, 0x40, &en1k);
1984
1985 if (en1k & 0x200) {
1986 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1987
1988 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1989
1990 if (iobl_adr != iobl_adr_1k) {
f0fda801 1991 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
15a260d5
DY		 1992 iobl_adr,iobl_adr_1k);
1993 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1994 }
1995 }
1996}
1997DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1998
cf34a8e0
BG		 1999/* Under some circumstances, AER is not linked with extended capabilities.
2000 * Force it to be linked by setting the corresponding control bit in the
2001 * config space.
2002 */
1597cacb 2003static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 2004{
2005 uint8_t b;
2006 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2007 if (!(b & 0x20)) {
2008 pci_write_config_byte(dev, 0xf41, b | 0x20);
f0fda801 2009 dev_info(&dev->dev,
2010 "Linking AER extended capability\n");
cf34a8e0
BG		 2011 }
2012 }
2013}
2014DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2015 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 2016DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 2017 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 2018
53a9bf42
TY		 2019static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2020{
2021 /*
2022 * Disable PCI Bus Parking and PCI Master read caching on CX700
2023 * which causes unspecified timing errors with a VT6212L on the PCI
ca846392
TY		 2024 * bus leading to USB2.0 packet loss.
2025 *
2026 * This quirk is only enabled if a second (on the external PCI bus)
2027 * VT6212L is found -- the CX700 core itself also contains a USB
2028 * host controller with the same PCI ID as the VT6212L.
53a9bf42
TY		 2029 */
2030
ca846392
TY		 2031 /* Count VT6212L instances */
2032 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2033 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
53a9bf42 2034 uint8_t b;
ca846392
TY		 2035
2036 /* p should contain the first (internal) VT6212L -- see if we have
2037 an external one by searching again */
2038 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2039 if (!p)
2040 return;
2041 pci_dev_put(p);
2042
53a9bf42
TY		 2043 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2044 if (b & 0x40) {
2045 /* Turn off PCI Bus Parking */
2046 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2047
bc043274
TY		 2048 dev_info(&dev->dev,
2049 "Disabling VIA CX700 PCI parking\n");
2050 }
2051 }
2052
2053 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2054 if (b != 0) {
53a9bf42
TY		 2055 /* Turn off PCI Master read caching */
2056 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 2057
2058 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 2059 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 2060
2061 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 2062 pci_write_config_byte(dev, 0x77, 0x0);
2063
d6505a52 2064 dev_info(&dev->dev,
bc043274 2065 "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 2066 }
2067 }
2068}
ca846392 2069DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
53a9bf42 2070
99cb233d
BL		 2071/*
2072 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2073 * VPD end tag will hang the device. This problem was initially
2074 * observed when a vpd entry was created in sysfs
2075 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2076 * will dump 32k of data. Reading a full 32k will cause an access
2077 * beyond the VPD end tag causing the device to hang. Once the device
2078 * is hung, the bnx2 driver will not be able to reset the device.
2079 * We believe that it is legal to read beyond the end tag and
2080 * therefore the solution is to limit the read/write length.
2081 */
2082static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2083{
9d82d8ea 2084 /*
35405f25
DH		 2085 * Only disable the VPD capability for 5706, 5706S, 5708,
2086 * 5708S and 5709 rev. A
9d82d8ea 2087 */
99cb233d 2088 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
35405f25 2089 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
99cb233d 2090 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
9d82d8ea 2091 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
99cb233d
BL		 2092 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2093 (dev->revision & 0xf0) == 0x0)) {
2094 if (dev->vpd)
2095 dev->vpd->len = 0x80;
2096 }
2097}
2098
bffadffd
YZ		 2099DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2100 PCI_DEVICE_ID_NX2_5706,
2101 quirk_brcm_570x_limit_vpd);
2102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2103 PCI_DEVICE_ID_NX2_5706S,
2104 quirk_brcm_570x_limit_vpd);
2105DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2106 PCI_DEVICE_ID_NX2_5708,
2107 quirk_brcm_570x_limit_vpd);
2108DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2109 PCI_DEVICE_ID_NX2_5708S,
2110 quirk_brcm_570x_limit_vpd);
2111DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2112 PCI_DEVICE_ID_NX2_5709,
2113 quirk_brcm_570x_limit_vpd);
2114DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2115 PCI_DEVICE_ID_NX2_5709S,
2116 quirk_brcm_570x_limit_vpd);
99cb233d 2117
26c56dc0
MM		 2118/* Originally in EDAC sources for i82875P:
2119 * Intel tells BIOS developers to hide device 6 which
2120 * configures the overflow device access containing
2121 * the DRBs - this is where we expose device 6.
2122 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2123 */
2124static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2125{
2126 u8 reg;
2127
2128 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2129 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2130 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2131 }
2132}
2133
2134DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2135 quirk_unhide_mch_dev6);
2136DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2137 quirk_unhide_mch_dev6);
2138
2139
3f79e107 2140#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 2141/* Some chipsets do not support MSI. We cannot easily rely on setting
2142 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2143 * some other busses controlled by the chipset even if Linux is not
2144 * aware of it. Instead of setting the flag on all busses in the
2145 * machine, simply disable MSI globally.
3f79e107 2146 */
ebdf7d39 2147static void __init quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 2148{
88187dfa 2149 pci_no_msi();
f0fda801 2150 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
3f79e107 2151}
ebdf7d39
TH		 2152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2154DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
66d715c9 2155DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
184b812f 2156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
162dedd3 2157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
549e1561 2158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
3f79e107
BG		 2159
2160/* Disable MSI on chipsets that are known to not support it */
2161static void __devinit quirk_disable_msi(struct pci_dev *dev)
2162{
2163 if (dev->subordinate) {
f0fda801 2164 dev_warn(&dev->dev, "MSI quirk detected; "
2165 "subordinate MSI disabled\n");
3f79e107
BG		 2166 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2167 }
2168}
2169DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
134b3450 2170DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
9313ff45 2171DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
6397c75c 2172
aff61369
CL		 2173/*
2174 * The APC bridge device in AMD 780 family northbridges has some random
2175 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2176 * we use the possible vendor/device IDs of the host bridge for the
2177 * declared quirk, and search for the APC bridge by slot number.
2178 */
2179static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2180{
2181 struct pci_dev *apc_bridge;
2182
2183 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2184 if (apc_bridge) {
2185 if (apc_bridge->device == 0x9602)
2186 quirk_disable_msi(apc_bridge);
2187 pci_dev_put(apc_bridge);
2188 }
2189}
2190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2191DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2192
6397c75c
BG		 2193/* Go through the list of Hypertransport capabilities and
2194 * return 1 if a HT MSI capability is found and enabled */
2195static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2196{
7a380507
ME		 2197 int pos, ttl = 48;
2198
2199 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2200 while (pos && ttl--) {
2201 u8 flags;
2202
2203 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2204 &flags) == 0)
2205 {
f0fda801 2206 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
7a380507 2207 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 2208 "enabled" : "disabled");
7a380507 2209 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 2210 }
7a380507
ME		 2211
2212 pos = pci_find_next_ht_capability(dev, pos,
2213 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 2214 }
2215 return 0;
2216}
2217
2218/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2219static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2220{
2221 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
f0fda801 2222 dev_warn(&dev->dev, "MSI quirk detected; "
2223 "subordinate MSI disabled\n");
6397c75c
BG		 2224 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2225 }
2226}
2227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2228 quirk_msi_ht_cap);
6bae1d96 2229
6397c75c
BG		 2230/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2231 * MSI are supported if the MSI capability set in any of these mappings.
2232 */
2233static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2234{
2235 struct pci_dev *pdev;
2236
2237 if (!dev->subordinate)
2238 return;
2239
2240 /* check HT MSI cap on this chipset and the root one.
2241 * a single one having MSI is enough to be sure that MSI are supported.
2242 */
11f242f0 2243 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 2244 if (!pdev)
2245 return;
0c875c28 2246 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
f0fda801 2247 dev_warn(&dev->dev, "MSI quirk detected; "
2248 "subordinate MSI disabled\n");
6397c75c
BG		 2249 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2250 }
11f242f0 2251 pci_dev_put(pdev);
6397c75c
BG		 2252}
2253DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2254 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 2255
415b6d0e
BH		 2256/* Force enable MSI mapping capability on HT bridges */
2257static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2258{
2259 int pos, ttl = 48;
2260
2261 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2262 while (pos && ttl--) {
2263 u8 flags;
2264
2265 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2266 &flags) == 0) {
2267 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2268
2269 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2270 flags | HT_MSI_FLAGS_ENABLE);
2271 }
2272 pos = pci_find_next_ht_capability(dev, pos,
2273 HT_CAPTYPE_MSI_MAPPING);
2274 }
2275}
415b6d0e
BH		 2276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2277 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2278 ht_enable_msi_mapping);
9dc625e7 2279
e0ae4f55
YL		 2280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2281 ht_enable_msi_mapping);
2282
e4146bb9 2283/* The P5N32-SLI motherboards from Asus have a problem with msi
75e07fc3
AP		 2284 * for the MCP55 NIC. It is not yet determined whether the msi problem
2285 * also affects other devices. As for now, turn off msi for this device.
2286 */
2287static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2288{
e4146bb9
BH		 2289 if (dmi_name_in_vendors("P5N32-SLI PREMIUM") ||
2290 dmi_name_in_vendors("P5N32-E SLI")) {
75e07fc3 2291 dev_info(&dev->dev,
e4146bb9 2292 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
75e07fc3
AP		 2293 dev->no_msi = 1;
2294 }
2295}
2296DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2297 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2298 nvenet_msi_disable);
2299
66db60ea
NH		 2300/*
2301 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2302 * config register. This register controls the routing of legacy interrupts
2303 * from devices that route through the MCP55. If this register is misprogramed
2304 * interrupts are only sent to the bsp, unlike conventional systems where the
2305 * irq is broadxast to all online cpus. Not having this register set
2306 * properly prevents kdump from booting up properly, so lets make sure that
2307 * we have it set correctly.
2308 * Note this is an undocumented register.
2309 */
2310static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2311{
2312 u32 cfg;
2313
2314 pci_read_config_dword(dev, 0x74, &cfg);
2315
2316 if (cfg & ((1 << 2) | (1 << 15))) {
2317 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2318 cfg &= ~((1 << 2) | (1 << 15));
2319 pci_write_config_dword(dev, 0x74, cfg);
2320 }
2321}
2322
2323DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2324 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2325 nvbridge_check_legacy_irq_routing);
2326
2327DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2328 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2329 nvbridge_check_legacy_irq_routing);
2330
de745306
YL		 2331static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2332{
2333 int pos, ttl = 48;
2334 int found = 0;
2335
2336 /* check if there is HT MSI cap or enabled on this device */
2337 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2338 while (pos && ttl--) {
2339 u8 flags;
2340
2341 if (found < 1)
2342 found = 1;
2343 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2344 &flags) == 0) {
2345 if (flags & HT_MSI_FLAGS_ENABLE) {
2346 if (found < 2) {
2347 found = 2;
2348 break;
2349 }
2350 }
2351 }
2352 pos = pci_find_next_ht_capability(dev, pos,
2353 HT_CAPTYPE_MSI_MAPPING);
2354 }
2355
2356 return found;
2357}
2358
2359static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2360{
2361 struct pci_dev *dev;
2362 int pos;
2363 int i, dev_no;
2364 int found = 0;
2365
2366 dev_no = host_bridge->devfn >> 3;
2367 for (i = dev_no + 1; i < 0x20; i++) {
2368 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2369 if (!dev)
2370 continue;
2371
2372 /* found next host bridge ?*/
2373 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2374 if (pos != 0) {
2375 pci_dev_put(dev);
2376 break;
2377 }
2378
2379 if (ht_check_msi_mapping(dev)) {
2380 found = 1;
2381 pci_dev_put(dev);
2382 break;
2383 }
2384 pci_dev_put(dev);
2385 }
2386
2387 return found;
2388}
2389
eeafda70
YL		 2390#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2391#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2392
2393static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2394{
2395 int pos, ctrl_off;
2396 int end = 0;
2397 u16 flags, ctrl;
2398
2399 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2400
2401 if (!pos)
2402 goto out;
2403
2404 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2405
2406 ctrl_off = ((flags >> 10) & 1) ?
2407 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2408 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2409
2410 if (ctrl & (1 << 6))
2411 end = 1;
2412
2413out:
2414 return end;
2415}
2416
1dec6b05 2417static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2418{
2419 struct pci_dev *host_bridge;
1dec6b05
YL		 2420 int pos;
2421 int i, dev_no;
2422 int found = 0;
2423
2424 dev_no = dev->devfn >> 3;
2425 for (i = dev_no; i >= 0; i--) {
2426 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2427 if (!host_bridge)
2428 continue;
2429
2430 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2431 if (pos != 0) {
2432 found = 1;
2433 break;
2434 }
2435 pci_dev_put(host_bridge);
2436 }
2437
2438 if (!found)
2439 return;
2440
eeafda70
YL		 2441 /* don't enable end_device/host_bridge with leaf directly here */
2442 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2443 host_bridge_with_leaf(host_bridge))
de745306
YL		 2444 goto out;
2445
1dec6b05
YL		 2446 /* root did that ! */
2447 if (msi_ht_cap_enabled(host_bridge))
2448 goto out;
2449
2450 ht_enable_msi_mapping(dev);
2451
2452out:
2453 pci_dev_put(host_bridge);
2454}
2455
2456static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2457{
2458 int pos, ttl = 48;
2459
2460 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2461 while (pos && ttl--) {
2462 u8 flags;
2463
2464 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2465 &flags) == 0) {
6a958d5b 2466 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
1dec6b05
YL		 2467
2468 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2469 flags & ~HT_MSI_FLAGS_ENABLE);
2470 }
2471 pos = pci_find_next_ht_capability(dev, pos,
2472 HT_CAPTYPE_MSI_MAPPING);
2473 }
2474}
2475
de745306 2476static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
1dec6b05
YL		 2477{
2478 struct pci_dev *host_bridge;
2479 int pos;
2480 int found;
2481
3d2a5318
RW		 2482 if (!pci_msi_enabled())
2483 return;
2484
1dec6b05
YL		 2485 /* check if there is HT MSI cap or enabled on this device */
2486 found = ht_check_msi_mapping(dev);
2487
2488 /* no HT MSI CAP */
2489 if (found == 0)
2490 return;
9dc625e7
PC		 2491
2492 /*
2493 * HT MSI mapping should be disabled on devices that are below
2494 * a non-Hypertransport host bridge. Locate the host bridge...
2495 */
2496 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2497 if (host_bridge == NULL) {
2498 dev_warn(&dev->dev,
2499 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2500 return;
2501 }
2502
2503 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2504 if (pos != 0) {
2505 /* Host bridge is to HT */
1dec6b05
YL		 2506 if (found == 1) {
2507 /* it is not enabled, try to enable it */
de745306
YL		 2508 if (all)
2509 ht_enable_msi_mapping(dev);
2510 else
2511 nv_ht_enable_msi_mapping(dev);
1dec6b05 2512 }
9dc625e7
PC		 2513 return;
2514 }
2515
1dec6b05
YL		 2516 /* HT MSI is not enabled */
2517 if (found == 1)
2518 return;
9dc625e7 2519
1dec6b05
YL		 2520 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2521 ht_disable_msi_mapping(dev);
9dc625e7 2522}
de745306
YL		 2523
2524static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2525{
2526 return __nv_msi_ht_cap_quirk(dev, 1);
2527}
2528
2529static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2530{
2531 return __nv_msi_ht_cap_quirk(dev, 0);
2532}
2533
2534DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
6dab62ee 2535DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
de745306
YL		 2536
2537DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
6dab62ee 2538DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
9dc625e7 2539
ba698ad4
DM		 2540static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2541{
2542 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2543}
4600c9d7
SH		 2544static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2545{
2546 struct pci_dev *p;
2547
2548 /* SB700 MSI issue will be fixed at HW level from revision A21,
2549 * we need check PCI REVISION ID of SMBus controller to get SB700
2550 * revision.
2551 */
2552 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2553 NULL);
2554 if (!p)
2555 return;
2556
2557 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2558 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2559 pci_dev_put(p);
2560}
ba698ad4
DM		 2561DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2562 PCI_DEVICE_ID_TIGON3_5780,
2563 quirk_msi_intx_disable_bug);
2564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2565 PCI_DEVICE_ID_TIGON3_5780S,
2566 quirk_msi_intx_disable_bug);
2567DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2568 PCI_DEVICE_ID_TIGON3_5714,
2569 quirk_msi_intx_disable_bug);
2570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2571 PCI_DEVICE_ID_TIGON3_5714S,
2572 quirk_msi_intx_disable_bug);
2573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2574 PCI_DEVICE_ID_TIGON3_5715,
2575 quirk_msi_intx_disable_bug);
2576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2577 PCI_DEVICE_ID_TIGON3_5715S,
2578 quirk_msi_intx_disable_bug);
2579
bc38b411 2580DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 2581 quirk_msi_intx_disable_ati_bug);
bc38b411 2582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 2583 quirk_msi_intx_disable_ati_bug);
bc38b411 2584DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 2585 quirk_msi_intx_disable_ati_bug);
bc38b411 2586DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 2587 quirk_msi_intx_disable_ati_bug);
bc38b411 2588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 2589 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 2590
2591DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2592 quirk_msi_intx_disable_bug);
2593DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2594 quirk_msi_intx_disable_bug);
2595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2596 quirk_msi_intx_disable_bug);
2597
3f79e107 2598#endif /* CONFIG_PCI_MSI */
3d137310 2599
7eb93b17
YZ		 2600#ifdef CONFIG_PCI_IOV
2601
2602/*
2603 * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
2604 * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
2605 * old Flash Memory Space.
2606 */
2607static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2608{
2609 int pos, flags;
2610 u32 bar, start, size;
2611
2612 if (PAGE_SIZE > 0x10000)
2613 return;
2614
2615 flags = pci_resource_flags(dev, 0);
2616 if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2617 PCI_BASE_ADDRESS_SPACE_MEMORY ||
2618 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2619 PCI_BASE_ADDRESS_MEM_TYPE_32)
2620 return;
2621
2622 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2623 if (!pos)
2624 return;
2625
2626 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2627 if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2628 return;
2629
2630 start = pci_resource_start(dev, 1);
2631 size = pci_resource_len(dev, 1);
2632 if (!start || size != 0x400000 || start & (size - 1))
2633 return;
2634
2635 pci_resource_flags(dev, 1) = 0;
2636 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2637 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2638 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2639
2640 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2641}
2642DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
dcb4ea2e
AD		 2645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
2646DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
6f1186be 2647DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
7a0deb6b 2648DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1518, quirk_i82576_sriov);
7eb93b17
YZ		 2649
2650#endif /* CONFIG_PCI_IOV */
2651
3322340a
FR		 2652/* Allow manual resource allocation for PCI hotplug bridges
2653 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2654 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2655 * kernel fails to allocate resources when hotplug device is
2656 * inserted and PCI bus is rescanned.
2657 */
2658static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2659{
2660 dev->is_hotplug_bridge = 1;
2661}
2662
2663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2664
03cd8f7e
ML		 2665/*
2666 * This is a quirk for the Ricoh MMC controller found as a part of
2667 * some mulifunction chips.
2668
2669 * This is very similiar and based on the ricoh_mmc driver written by
2670 * Philip Langdale. Thank you for these magic sequences.
2671 *
2672 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2673 * and one or both of cardbus or firewire.
2674 *
2675 * It happens that they implement SD and MMC
2676 * support as separate controllers (and PCI functions). The linux SDHCI
2677 * driver supports MMC cards but the chip detects MMC cards in hardware
2678 * and directs them to the MMC controller - so the SDHCI driver never sees
2679 * them.
2680 *
2681 * To get around this, we must disable the useless MMC controller.
2682 * At that point, the SDHCI controller will start seeing them
2683 * It seems to be the case that the relevant PCI registers to deactivate the
2684 * MMC controller live on PCI function 0, which might be the cardbus controller
2685 * or the firewire controller, depending on the particular chip in question
2686 *
2687 * This has to be done early, because as soon as we disable the MMC controller
2688 * other pci functions shift up one level, e.g. function #2 becomes function
2689 * #1, and this will confuse the pci core.
2690 */
2691
2692#ifdef CONFIG_MMC_RICOH_MMC
2693static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2694{
2695 /* disable via cardbus interface */
2696 u8 write_enable;
2697 u8 write_target;
2698 u8 disable;
2699
2700 /* disable must be done via function #0 */
2701 if (PCI_FUNC(dev->devfn))
2702 return;
2703
2704 pci_read_config_byte(dev, 0xB7, &disable);
2705 if (disable & 0x02)
2706 return;
2707
2708 pci_read_config_byte(dev, 0x8E, &write_enable);
2709 pci_write_config_byte(dev, 0x8E, 0xAA);
2710 pci_read_config_byte(dev, 0x8D, &write_target);
2711 pci_write_config_byte(dev, 0x8D, 0xB7);
2712 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2713 pci_write_config_byte(dev, 0x8E, write_enable);
2714 pci_write_config_byte(dev, 0x8D, write_target);
2715
2716 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2717 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2718}
2719DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2720DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2721
2722static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2723{
2724 /* disable via firewire interface */
2725 u8 write_enable;
2726 u8 disable;
2727
2728 /* disable must be done via function #0 */
2729 if (PCI_FUNC(dev->devfn))
2730 return;
2731
2732 pci_read_config_byte(dev, 0xCB, &disable);
2733
2734 if (disable & 0x02)
2735 return;
2736
2737 pci_read_config_byte(dev, 0xCA, &write_enable);
2738 pci_write_config_byte(dev, 0xCA, 0x57);
2739 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2740 pci_write_config_byte(dev, 0xCA, write_enable);
2741
2742 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2743 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2744}
2745DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2746DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2747#endif /*CONFIG_MMC_RICOH_MMC*/
2748
2749
bfb0f330
JB		 2750static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2751 struct pci_fixup *end)
3d137310
TP		 2752{
2753 while (f < end) {
2754 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
bfb0f330 2755 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
c9bbb4ab 2756 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
3d137310
TP		 2757 f->hook(dev);
2758 }
2759 f++;
2760 }
2761}
2762
2763extern struct pci_fixup __start_pci_fixups_early[];
2764extern struct pci_fixup __end_pci_fixups_early[];
2765extern struct pci_fixup __start_pci_fixups_header[];
2766extern struct pci_fixup __end_pci_fixups_header[];
2767extern struct pci_fixup __start_pci_fixups_final[];
2768extern struct pci_fixup __end_pci_fixups_final[];
2769extern struct pci_fixup __start_pci_fixups_enable[];
2770extern struct pci_fixup __end_pci_fixups_enable[];
2771extern struct pci_fixup __start_pci_fixups_resume[];
2772extern struct pci_fixup __end_pci_fixups_resume[];
2773extern struct pci_fixup __start_pci_fixups_resume_early[];
2774extern struct pci_fixup __end_pci_fixups_resume_early[];
2775extern struct pci_fixup __start_pci_fixups_suspend[];
2776extern struct pci_fixup __end_pci_fixups_suspend[];
2777
2778
2779void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2780{
2781 struct pci_fixup *start, *end;
2782
2783 switch(pass) {
2784 case pci_fixup_early:
2785 start = __start_pci_fixups_early;
2786 end = __end_pci_fixups_early;
2787 break;
2788
2789 case pci_fixup_header:
2790 start = __start_pci_fixups_header;
2791 end = __end_pci_fixups_header;
2792 break;
2793
2794 case pci_fixup_final:
2795 start = __start_pci_fixups_final;
2796 end = __end_pci_fixups_final;
2797 break;
2798
2799 case pci_fixup_enable:
2800 start = __start_pci_fixups_enable;
2801 end = __end_pci_fixups_enable;
2802 break;
2803
2804 case pci_fixup_resume:
2805 start = __start_pci_fixups_resume;
2806 end = __end_pci_fixups_resume;
2807 break;
2808
2809 case pci_fixup_resume_early:
2810 start = __start_pci_fixups_resume_early;
2811 end = __end_pci_fixups_resume_early;
2812 break;
2813
2814 case pci_fixup_suspend:
2815 start = __start_pci_fixups_suspend;
2816 end = __end_pci_fixups_suspend;
2817 break;
2818
2819 default:
2820 /* stupid compiler warning, you would think with an enum... */
2821 return;
2822 }
2823 pci_do_fixups(dev, start, end);
2824}
93177a74 2825EXPORT_SYMBOL(pci_fixup_device);
8d86fb2c 2826
00010268 2827static int __init pci_apply_final_quirks(void)
8d86fb2c
DW		 2828{
2829 struct pci_dev *dev = NULL;
ac1aa47b
JB		 2830 u8 cls = 0;
2831 u8 tmp;
2832
2833 if (pci_cache_line_size)
2834 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
2835 pci_cache_line_size << 2);
8d86fb2c 2836
4e344b1c 2837 for_each_pci_dev(dev) {
8d86fb2c 2838 pci_fixup_device(pci_fixup_final, dev);
ac1aa47b
JB		 2839 /*
2840 * If arch hasn't set it explicitly yet, use the CLS
2841 * value shared by all PCI devices. If there's a
2842 * mismatch, fall back to the default value.
2843 */
2844 if (!pci_cache_line_size) {
2845 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
2846 if (!cls)
2847 cls = tmp;
2848 if (!tmp || cls == tmp)
2849 continue;
2850
2851 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
2852 "using %u bytes\n", cls << 2, tmp << 2,
2853 pci_dfl_cache_line_size << 2);
2854 pci_cache_line_size = pci_dfl_cache_line_size;
2855 }
2856 }
2857 if (!pci_cache_line_size) {
2858 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
2859 cls << 2, pci_dfl_cache_line_size << 2);
2820f333 2860 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
8d86fb2c
DW		 2861 }
2862
2863 return 0;
2864}
2865
cf6f3bf7 2866fs_initcall_sync(pci_apply_final_quirks);
b9c3b266
DC		 2867
2868/*
2869 * Followings are device-specific reset methods which can be used to
2870 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
2871 * not available.
2872 */
aeb30016
DC		 2873static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
2874{
2875 int pos;
2876
2877 /* only implement PCI_CLASS_SERIAL_USB at present */
2878 if (dev->class == PCI_CLASS_SERIAL_USB) {
2879 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
2880 if (!pos)
2881 return -ENOTTY;
2882
2883 if (probe)
2884 return 0;
2885
2886 pci_write_config_byte(dev, pos + 0x4, 1);
2887 msleep(100);
2888
2889 return 0;
2890 } else {
2891 return -ENOTTY;
2892 }
2893}
2894
c763e7b5
DC		 2895static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
2896{
2897 int pos;
2898
2899 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2900 if (!pos)
2901 return -ENOTTY;
2902
2903 if (probe)
2904 return 0;
2905
2906 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2907 PCI_EXP_DEVCTL_BCR_FLR);
2908 msleep(100);
2909
2910 return 0;
2911}
2912
2913#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
2914
5b889bf2 2915static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
c763e7b5
DC		 2916 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
2917 reset_intel_82599_sfp_virtfn },
aeb30016
DC		 2918 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2919 reset_intel_generic_dev },
b9c3b266
DC		 2920 { 0 }
2921};
5b889bf2
RW		 2922
2923int pci_dev_specific_reset(struct pci_dev *dev, int probe)
2924{
df9d1e8a 2925 const struct pci_dev_reset_methods *i;
5b889bf2
RW		 2926
2927 for (i = pci_dev_reset_methods; i->reset; i++) {
2928 if ((i->vendor == dev->vendor ||
2929 i->vendor == (u16)PCI_ANY_ID) &&
2930 (i->device == dev->device ||
2931 i->device == (u16)PCI_ANY_ID))
2932 return i->reset(dev, probe);
2933 }
2934
2935 return -ENOTTY;
2936}
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