git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| 28eb5f27 RW |
1 | /* |
| 2 | * PCIe Port Native Services Support, ACPI-Related Part | |
| 3 | * | |
| 4 | * Copyright (C) 2010 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc. | |
| 5 | * | |
| 6 | * This file is subject to the terms and conditions of the GNU General Public | |
| 7 | * License V2. See the file "COPYING" in the main directory of this archive | |
| 8 | * for more details. | |
| 9 | */ | |
| 10 | ||
| 11 | #include <linux/pci.h> | |
| 12 | #include <linux/kernel.h> | |
| 13 | #include <linux/errno.h> | |
| 14 | #include <linux/acpi.h> | |
| 15 | #include <linux/pci-acpi.h> | |
| 16 | #include <linux/pcieport_if.h> | |
| 17 | ||
| 18 | #include "aer/aerdrv.h" | |
| 19 | #include "../pci.h" | |
| 20 | ||
| 21 | /** | |
| 22 | * pcie_port_acpi_setup - Request the BIOS to release control of PCIe services. | |
| 23 | * @port: PCIe Port service for a root port or event collector. | |
| 24 | * @srv_mask: Bit mask of services that can be enabled for @port. | |
| 25 | * | |
| 26 | * Invoked when @port is identified as a PCIe port device. To avoid conflicts | |
| 27 | * with the BIOS PCIe port native services support requires the BIOS to yield | |
| 28 | * control of these services to the kernel. The mask of services that the BIOS | |
| 29 | * allows to be enabled for @port is written to @srv_mask. | |
| 30 | * | |
| 31 | * NOTE: It turns out that we cannot do that for individual port services | |
| 32 | * separately, because that would make some systems work incorrectly. | |
| 33 | */ | |
| 34 | int pcie_port_acpi_setup(struct pci_dev *port, int *srv_mask) | |
| 35 | { | |
| 36 | acpi_status status; | |
| 37 | acpi_handle handle; | |
| 38 | u32 flags; | |
| 39 | ||
| 40 | if (acpi_pci_disabled) | |
| 41 | return 0; | |
| 42 | ||
| 43 | handle = acpi_find_root_bridge_handle(port); | |
| 44 | if (!handle) | |
| 45 | return -EINVAL; | |
| 46 | ||
| 47 | flags = OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL | |
| 48 | | OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | |
| 49 | | OSC_PCI_EXPRESS_PME_CONTROL; | |
| 50 | ||
| 51 | if (pci_aer_available()) { | |
| b22c3d82 | 52 | if (aer_acpi_firmware_first()) |
| 28eb5f27 RW |
53 | dev_dbg(&port->dev, "PCIe errors handled by BIOS.\n"); |
| 54 | else | |
| 55 | flags |= OSC_PCI_EXPRESS_AER_CONTROL; | |
| 56 | } | |
| 57 | ||
| 58 | status = acpi_pci_osc_control_set(handle, &flags, | |
| 59 | OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL); | |
| 60 | if (ACPI_FAILURE(status)) { | |
| 61 | dev_dbg(&port->dev, "ACPI _OSC request failed (code %d)\n", | |
| 62 | status); | |
| 63 | return -ENODEV; | |
| 64 | } | |
| 65 | ||
| 66 | dev_info(&port->dev, "ACPI _OSC control granted for 0x%02x\n", flags); | |
| 67 | ||
| 68 | *srv_mask = PCIE_PORT_SERVICE_VC; | |
| 69 | if (flags & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL) | |
| 70 | *srv_mask |= PCIE_PORT_SERVICE_HP; | |
| 71 | if (flags & OSC_PCI_EXPRESS_PME_CONTROL) | |
| 72 | *srv_mask |= PCIE_PORT_SERVICE_PME; | |
| 73 | if (flags & OSC_PCI_EXPRESS_AER_CONTROL) | |
| 74 | *srv_mask |= PCIE_PORT_SERVICE_AER; | |
| 75 | ||
| 76 | return 0; | |
| 77 | } |