[net-next-2.6.git] / drivers / pci / pci.h

#ifndef DRIVERS_PCI_H
#define DRIVERS_PCI_H

#include <linux/workqueue.h>

#define PCI_CFG_SPACE_SIZE	256
#define PCI_CFG_SPACE_EXP_SIZE	4096

/* Functions internal to the PCI core code */

extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env);
extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
#ifndef CONFIG_DMI
static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
{ return; }
static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
{ return; }
#else
extern void pci_create_firmware_label_files(struct pci_dev *pdev);
extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
#endif
extern void pci_cleanup_rom(struct pci_dev *dev);
#ifdef HAVE_PCI_MMAP
extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
			 struct vm_area_struct *vma);
#endif
int pci_probe_reset_function(struct pci_dev *dev);

/**
 * struct pci_platform_pm_ops - Firmware PM callbacks
 *
 * @is_manageable: returns 'true' if given device is power manageable by the
 *                 platform firmware
 *
 * @set_state: invokes the platform firmware to set the device's power state
 *
 * @choose_state: returns PCI power state of given device preferred by the
 *                platform; to be used during system-wide transitions from a
 *                sleeping state to the working state and vice versa
 *
 * @can_wakeup: returns 'true' if given device is capable of waking up the
 *              system from a sleeping state
 *
 * @sleep_wake: enables/disables the system wake up capability of given device
 *
 * @run_wake: enables/disables the platform to generate run-time wake-up events
 *		for given device (the device's wake-up capability has to be
 *		enabled by @sleep_wake for this feature to work)
 *
 * If given platform is generally capable of power managing PCI devices, all of
 * these callbacks are mandatory.
 */
struct pci_platform_pm_ops {
	bool (*is_manageable)(struct pci_dev *dev);
	int (*set_state)(struct pci_dev *dev, pci_power_t state);
	pci_power_t (*choose_state)(struct pci_dev *dev);
	bool (*can_wakeup)(struct pci_dev *dev);
	int (*sleep_wake)(struct pci_dev *dev, bool enable);
	int (*run_wake)(struct pci_dev *dev, bool enable);
};

extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
extern void pci_disable_enabled_device(struct pci_dev *dev);
extern int pci_finish_runtime_suspend(struct pci_dev *dev);
extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
extern void pci_pm_init(struct pci_dev *dev);
extern void platform_pci_wakeup_init(struct pci_dev *dev);
extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);

static inline bool pci_is_bridge(struct pci_dev *pci_dev)
{
	return !!(pci_dev->subordinate);
}

extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);

struct pci_vpd_ops {
	ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
	ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
	void (*release)(struct pci_dev *dev);
};

struct pci_vpd {
	unsigned int len;
	const struct pci_vpd_ops *ops;
	struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
};

extern int pci_vpd_pci22_init(struct pci_dev *dev);
static inline void pci_vpd_release(struct pci_dev *dev)
{
	if (dev->vpd)
		dev->vpd->ops->release(dev);
}

/* PCI /proc functions */
#ifdef CONFIG_PROC_FS
extern int pci_proc_attach_device(struct pci_dev *dev);
extern int pci_proc_detach_device(struct pci_dev *dev);
extern int pci_proc_detach_bus(struct pci_bus *bus);
#else
static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
#endif

/* Functions for PCI Hotplug drivers to use */
extern unsigned int pci_do_scan_bus(struct pci_bus *bus);

#ifdef HAVE_PCI_LEGACY
extern void pci_create_legacy_files(struct pci_bus *bus);
extern void pci_remove_legacy_files(struct pci_bus *bus);
#else
static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
#endif

/* Lock for read/write access to pci device and bus lists */
extern struct rw_semaphore pci_bus_sem;

extern unsigned int pci_pm_d3_delay;

#ifdef CONFIG_PCI_MSI
void pci_no_msi(void);
extern void pci_msi_init_pci_dev(struct pci_dev *dev);
#else
static inline void pci_no_msi(void) { }
static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
#endif

#ifdef CONFIG_PCIEAER
void pci_no_aer(void);
bool pci_aer_available(void);
#else
static inline void pci_no_aer(void) { }
static inline bool pci_aer_available(void) { return false; }
#endif

static inline int pci_no_d1d2(struct pci_dev *dev)
{
	unsigned int parent_dstates = 0;

	if (dev->bus->self)
		parent_dstates = dev->bus->self->no_d1d2;
	return (dev->no_d1d2 || parent_dstates);

}
extern struct device_attribute pci_dev_attrs[];
extern struct device_attribute dev_attr_cpuaffinity;
extern struct device_attribute dev_attr_cpulistaffinity;
#ifdef CONFIG_HOTPLUG
extern struct bus_attribute pci_bus_attrs[];
#else
#define pci_bus_attrs	NULL
#endif


/**
 * pci_match_one_device - Tell if a PCI device structure has a matching
 *                        PCI device id structure
 * @id: single PCI device id structure to match
 * @dev: the PCI device structure to match against
 *
 * Returns the matching pci_device_id structure or %NULL if there is no match.
 */
static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
{
	if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
	    (id->device == PCI_ANY_ID || id->device == dev->device) &&
	    (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
	    (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
	    !((id->class ^ dev->class) & id->class_mask))
		return id;
	return NULL;
}

struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);

/* PCI slot sysfs helper code */
#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)

extern struct kset *pci_slots_kset;

struct pci_slot_attribute {
	struct attribute attr;
	ssize_t (*show)(struct pci_slot *, char *);
	ssize_t (*store)(struct pci_slot *, const char *, size_t);
};
#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)

enum pci_bar_type {
	pci_bar_unknown,	/* Standard PCI BAR probe */
	pci_bar_io,		/* An io port BAR */
	pci_bar_mem32,		/* A 32-bit memory BAR */
	pci_bar_mem64,		/* A 64-bit memory BAR */
};

extern int pci_setup_device(struct pci_dev *dev);
extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
				struct resource *res, unsigned int reg);
extern int pci_resource_bar(struct pci_dev *dev, int resno,
			    enum pci_bar_type *type);
extern int pci_bus_add_child(struct pci_bus *bus);
extern void pci_enable_ari(struct pci_dev *dev);
/**
 * pci_ari_enabled - query ARI forwarding status
 * @bus: the PCI bus
 *
 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
 */
static inline int pci_ari_enabled(struct pci_bus *bus)
{
	return bus->self && bus->self->ari_enabled;
}

#ifdef CONFIG_PCI_QUIRKS
extern int pci_is_reassigndev(struct pci_dev *dev);
resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
extern void pci_disable_bridge_window(struct pci_dev *dev);
#endif

/* Single Root I/O Virtualization */
struct pci_sriov {
	int pos;		/* capability position */
	int nres;		/* number of resources */
	u32 cap;		/* SR-IOV Capabilities */
	u16 ctrl;		/* SR-IOV Control */
	u16 total;		/* total VFs associated with the PF */
	u16 initial;		/* initial VFs associated with the PF */
	u16 nr_virtfn;		/* number of VFs available */
	u16 offset;		/* first VF Routing ID offset */
	u16 stride;		/* following VF stride */
	u32 pgsz;		/* page size for BAR alignment */
	u8 link;		/* Function Dependency Link */
	struct pci_dev *dev;	/* lowest numbered PF */
	struct pci_dev *self;	/* this PF */
	struct mutex lock;	/* lock for VF bus */
	struct work_struct mtask; /* VF Migration task */
	u8 __iomem *mstate;	/* VF Migration State Array */
};

/* Address Translation Service */
struct pci_ats {
	int pos;	/* capability position */
	int stu;	/* Smallest Translation Unit */
	int qdep;	/* Invalidate Queue Depth */
	int ref_cnt;	/* Physical Function reference count */
	unsigned int is_enabled:1;	/* Enable bit is set */
};

#ifdef CONFIG_PCI_IOV
extern int pci_iov_init(struct pci_dev *dev);
extern void pci_iov_release(struct pci_dev *dev);
extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				enum pci_bar_type *type);
extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
						    int resno);
extern void pci_restore_iov_state(struct pci_dev *dev);
extern int pci_iov_bus_range(struct pci_bus *bus);

extern int pci_enable_ats(struct pci_dev *dev, int ps);
extern void pci_disable_ats(struct pci_dev *dev);
extern int pci_ats_queue_depth(struct pci_dev *dev);
/**
 * pci_ats_enabled - query the ATS status
 * @dev: the PCI device
 *
 * Returns 1 if ATS capability is enabled, or 0 if not.
 */
static inline int pci_ats_enabled(struct pci_dev *dev)
{
	return dev->ats && dev->ats->is_enabled;
}
#else
static inline int pci_iov_init(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline void pci_iov_release(struct pci_dev *dev)

{
}
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				       enum pci_bar_type *type)
{
	return 0;
}
static inline void pci_restore_iov_state(struct pci_dev *dev)
{
}
static inline int pci_iov_bus_range(struct pci_bus *bus)
{
	return 0;
}

static inline int pci_enable_ats(struct pci_dev *dev, int ps)
{
	return -ENODEV;
}
static inline void pci_disable_ats(struct pci_dev *dev)
{
}
static inline int pci_ats_queue_depth(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline int pci_ats_enabled(struct pci_dev *dev)
{
	return 0;
}
#endif /* CONFIG_PCI_IOV */

static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
					 struct resource *res)
{
#ifdef CONFIG_PCI_IOV
	int resno = res - dev->resource;

	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		return pci_sriov_resource_alignment(dev, resno);
#endif
	return resource_alignment(res);
}

extern void pci_enable_acs(struct pci_dev *dev);

struct pci_dev_reset_methods {
	u16 vendor;
	u16 device;
	int (*reset)(struct pci_dev *dev, int probe);
};

#ifdef CONFIG_PCI_QUIRKS
extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
#else
static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
	return -ENOTTY;
}
#endif

#endif /* DRIVERS_PCI_H */
Commit	Line	Data
557848c3 ZY	1	#ifndef DRIVERS_PCI_H
	2	#define DRIVERS_PCI_H
	3
74bb1bcc YZ	4	#include <linux/workqueue.h>
74bb1bcc YZ	5
557848c3 ZY	6	#define PCI_CFG_SPACE_SIZE 256
	7	#define PCI_CFG_SPACE_EXP_SIZE 4096
	8
1da177e4 LT	9	/* Functions internal to the PCI core code */
1da177e4 LT	10
7eff2e7a	11	extern int pci_uevent(struct device dev, struct kobj_uevent_env env);
1da177e4 LT	12	extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
1da177e4 LT	13	extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
911e1c9b N	14	#ifndef CONFIG_DMI
911e1c9b N	15	static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
b879743f	16	{ return; }
911e1c9b	17	static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
b879743f	18	{ return; }
911e1c9b N	19	#else
	20	extern void pci_create_firmware_label_files(struct pci_dev *pdev);
	21	extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
	22	#endif
1da177e4	23	extern void pci_cleanup_rom(struct pci_dev *dev);
9eff02e2 JB	24	#ifdef HAVE_PCI_MMAP
	25	extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
	26	struct vm_area_struct *vma);
	27	#endif
711d5779	28	int pci_probe_reset_function(struct pci_dev *dev);
ce5ccdef	29
961d9120	30	/**
b33bfdef	31	* struct pci_platform_pm_ops - Firmware PM callbacks
961d9120	32	*
b33bfdef RD	33	* @is_manageable: returns 'true' if given device is power manageable by the
b33bfdef RD	34	* platform firmware
961d9120	35	*
b33bfdef	36	* @set_state: invokes the platform firmware to set the device's power state
961d9120	37	*
b33bfdef RD	38	* @choose_state: returns PCI power state of given device preferred by the
	39	* platform; to be used during system-wide transitions from a
	40	* sleeping state to the working state and vice versa
961d9120	41	*
b33bfdef RD	42	* @can_wakeup: returns 'true' if given device is capable of waking up the
b33bfdef RD	43	* system from a sleeping state
eb9d0fe4	44	*
b33bfdef	45	* @sleep_wake: enables/disables the system wake up capability of given device
eb9d0fe4	46	*
b67ea761 RW	47	* @run_wake: enables/disables the platform to generate run-time wake-up events
	48	* for given device (the device's wake-up capability has to be
	49	* enabled by @sleep_wake for this feature to work)
	50	*
961d9120 RW	51	* If given platform is generally capable of power managing PCI devices, all of
	52	* these callbacks are mandatory.
	53	*/
	54	struct pci_platform_pm_ops {
	55	bool (is_manageable)(struct pci_dev dev);
	56	int (set_state)(struct pci_dev dev, pci_power_t state);
	57	pci_power_t (choose_state)(struct pci_dev dev);
eb9d0fe4 RW	58	bool (can_wakeup)(struct pci_dev dev);
eb9d0fe4 RW	59	int (sleep_wake)(struct pci_dev dev, bool enable);
b67ea761	60	int (run_wake)(struct pci_dev dev, bool enable);
961d9120 RW	61	};
	62
	63	extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
73410429	64	extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
fa58d305	65	extern void pci_disable_enabled_device(struct pci_dev *dev);
6cbf8214	66	extern int pci_finish_runtime_suspend(struct pci_dev *dev);
b67ea761	67	extern int __pci_pme_wakeup(struct pci_dev dev, void ign);
eb9d0fe4	68	extern void pci_pm_init(struct pci_dev *dev);
eb9c39d0	69	extern void platform_pci_wakeup_init(struct pci_dev *dev);
63f4898a	70	extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
aa8c6c93 RW	71
	72	static inline bool pci_is_bridge(struct pci_dev *pci_dev)
	73	{
	74	return !!(pci_dev->subordinate);
	75	}
0f64474b	76
e04b0ea2 BK	77	extern int pci_user_read_config_byte(struct pci_dev dev, int where, u8 val);
	78	extern int pci_user_read_config_word(struct pci_dev dev, int where, u16 val);
	79	extern int pci_user_read_config_dword(struct pci_dev dev, int where, u32 val);
	80	extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
	81	extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
	82	extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
	83
94e61088	84	struct pci_vpd_ops {
287d19ce SH	85	ssize_t (read)(struct pci_dev dev, loff_t pos, size_t count, void *buf);
287d19ce SH	86	ssize_t (write)(struct pci_dev dev, loff_t pos, size_t count, const void *buf);
94e61088 BH	87	void (release)(struct pci_dev dev);
	88	};
	89
	90	struct pci_vpd {
99cb233d	91	unsigned int len;
287d19ce	92	const struct pci_vpd_ops *ops;
94e61088 BH	93	struct bin_attribute attr; / descriptor for sysfs VPD entry */
	94	};
	95
	96	extern int pci_vpd_pci22_init(struct pci_dev *dev);
	97	static inline void pci_vpd_release(struct pci_dev *dev)
	98	{
	99	if (dev->vpd)
	100	dev->vpd->ops->release(dev);
	101	}
	102
1da177e4 LT	103	/* PCI /proc functions */
	104	#ifdef CONFIG_PROC_FS
	105	extern int pci_proc_attach_device(struct pci_dev *dev);
	106	extern int pci_proc_detach_device(struct pci_dev *dev);
1da177e4 LT	107	extern int pci_proc_detach_bus(struct pci_bus *bus);
	108	#else
	109	static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
	110	static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
1da177e4 LT	111	static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
	112	#endif
	113
	114	/* Functions for PCI Hotplug drivers to use */
1da177e4	115	extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
1da177e4	116
f19aeb1f BH	117	#ifdef HAVE_PCI_LEGACY
f19aeb1f BH	118	extern void pci_create_legacy_files(struct pci_bus *bus);
1da177e4	119	extern void pci_remove_legacy_files(struct pci_bus *bus);
f19aeb1f BH	120	#else
	121	static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
	122	static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
	123	#endif
1da177e4 LT	124
1da177e4 LT	125	/* Lock for read/write access to pci device and bus lists */
d71374da	126	extern struct rw_semaphore pci_bus_sem;
1da177e4	127
ffadcc2f	128	extern unsigned int pci_pm_d3_delay;
88187dfa	129
4b47b0ee	130	#ifdef CONFIG_PCI_MSI
309e57df	131	void pci_no_msi(void);
4aa9bc95	132	extern void pci_msi_init_pci_dev(struct pci_dev *dev);
4b47b0ee	133	#else
309e57df	134	static inline void pci_no_msi(void) { }
4aa9bc95	135	static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
4b47b0ee	136	#endif
8fed4b65	137
7f785763 RD	138	#ifdef CONFIG_PCIEAER
7f785763 RD	139	void pci_no_aer(void);
f1a7bfaf	140	bool pci_aer_available(void);
7f785763 RD	141	#else
7f785763 RD	142	static inline void pci_no_aer(void) { }
f1a7bfaf	143	static inline bool pci_aer_available(void) { return false; }
7f785763 RD	144	#endif
7f785763 RD	145
ffadcc2f KCA	146	static inline int pci_no_d1d2(struct pci_dev *dev)
	147	{
	148	unsigned int parent_dstates = 0;
4b47b0ee	149
ffadcc2f KCA	150	if (dev->bus->self)
	151	parent_dstates = dev->bus->self->no_d1d2;
	152	return (dev->no_d1d2 \|\| parent_dstates);
	153
	154	}
1da177e4	155	extern struct device_attribute pci_dev_attrs[];
fd7d1ced	156	extern struct device_attribute dev_attr_cpuaffinity;
93ff68a5	157	extern struct device_attribute dev_attr_cpulistaffinity;
705b1aaa AC	158	#ifdef CONFIG_HOTPLUG
	159	extern struct bus_attribute pci_bus_attrs[];
	160	#else
	161	#define pci_bus_attrs NULL
	162	#endif
	163
1da177e4 LT	164
	165	/**
	166	* pci_match_one_device - Tell if a PCI device structure has a matching
	167	* PCI device id structure
	168	* @id: single PCI device id structure to match
	169	* @dev: the PCI device structure to match against
367b09fe	170	*
1da177e4 LT	171	* Returns the matching pci_device_id structure or %NULL if there is no match.
	172	*/
	173	static inline const struct pci_device_id *
	174	pci_match_one_device(const struct pci_device_id id, const struct pci_dev dev)
	175	{
	176	if ((id->vendor == PCI_ANY_ID \|\| id->vendor == dev->vendor) &&
	177	(id->device == PCI_ANY_ID \|\| id->device == dev->device) &&
	178	(id->subvendor == PCI_ANY_ID \|\| id->subvendor == dev->subsystem_vendor) &&
	179	(id->subdevice == PCI_ANY_ID \|\| id->subdevice == dev->subsystem_device) &&
	180	!((id->class ^ dev->class) & id->class_mask))
	181	return id;
	182	return NULL;
	183	}
	184
994a65e2	185	struct pci_dev pci_find_upstream_pcie_bridge(struct pci_dev pdev);
f46753c5 AC	186
	187	/* PCI slot sysfs helper code */
	188	#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
	189
	190	extern struct kset *pci_slots_kset;
	191
	192	struct pci_slot_attribute {
	193	struct attribute attr;
	194	ssize_t (show)(struct pci_slot , char *);
	195	ssize_t (store)(struct pci_slot , const char *, size_t);
	196	};
	197	#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
	198
0b400c7e YZ	199	enum pci_bar_type {
	200	pci_bar_unknown, /* Standard PCI BAR probe */
	201	pci_bar_io, /* An io port BAR */
	202	pci_bar_mem32, /* A 32-bit memory BAR */
	203	pci_bar_mem64, /* A 64-bit memory BAR */
	204	};
	205
480b93b7	206	extern int pci_setup_device(struct pci_dev *dev);
0b400c7e YZ	207	extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
0b400c7e YZ	208	struct resource *res, unsigned int reg);
613e7ed6 YZ	209	extern int pci_resource_bar(struct pci_dev *dev, int resno,
613e7ed6 YZ	210	enum pci_bar_type *type);
876e501a	211	extern int pci_bus_add_child(struct pci_bus *bus);
58c3a727 YZ	212	extern void pci_enable_ari(struct pci_dev *dev);
	213	/**
	214	* pci_ari_enabled - query ARI forwarding status
6a49d812	215	* @bus: the PCI bus
58c3a727 YZ	216	*
	217	* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
	218	*/
6a49d812	219	static inline int pci_ari_enabled(struct pci_bus *bus)
58c3a727	220	{
6a49d812	221	return bus->self && bus->self->ari_enabled;
58c3a727 YZ	222	}
58c3a727 YZ	223
32a9a682 YS	224	#ifdef CONFIG_PCI_QUIRKS
	225	extern int pci_is_reassigndev(struct pci_dev *dev);
	226	resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
	227	extern void pci_disable_bridge_window(struct pci_dev *dev);
	228	#endif
	229
d1b054da YZ	230	/* Single Root I/O Virtualization */
	231	struct pci_sriov {
	232	int pos; /* capability position */
	233	int nres; /* number of resources */
	234	u32 cap; /* SR-IOV Capabilities */
	235	u16 ctrl; /* SR-IOV Control */
	236	u16 total; /* total VFs associated with the PF */
dd7cc44d YZ	237	u16 initial; /* initial VFs associated with the PF */
dd7cc44d YZ	238	u16 nr_virtfn; /* number of VFs available */
d1b054da YZ	239	u16 offset; /* first VF Routing ID offset */
	240	u16 stride; /* following VF stride */
	241	u32 pgsz; /* page size for BAR alignment */
	242	u8 link; /* Function Dependency Link */
	243	struct pci_dev dev; / lowest numbered PF */
	244	struct pci_dev self; / this PF */
	245	struct mutex lock; /* lock for VF bus */
74bb1bcc YZ	246	struct work_struct mtask; /* VF Migration task */
74bb1bcc YZ	247	u8 __iomem mstate; / VF Migration State Array */
d1b054da YZ	248	};
d1b054da YZ	249
302b4215 YZ	250	/* Address Translation Service */
	251	struct pci_ats {
	252	int pos; /* capability position */
	253	int stu; /* Smallest Translation Unit */
	254	int qdep; /* Invalidate Queue Depth */
e277d2fc	255	int ref_cnt; /* Physical Function reference count */
8356dda2	256	unsigned int is_enabled:1; /* Enable bit is set */
302b4215 YZ	257	};
302b4215 YZ	258
d1b054da YZ	259	#ifdef CONFIG_PCI_IOV
	260	extern int pci_iov_init(struct pci_dev *dev);
	261	extern void pci_iov_release(struct pci_dev *dev);
	262	extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	263	enum pci_bar_type *type);
0e52247a CM	264	extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
0e52247a CM	265	int resno);
8c5cdb6a	266	extern void pci_restore_iov_state(struct pci_dev *dev);
a28724b0	267	extern int pci_iov_bus_range(struct pci_bus *bus);
302b4215 YZ	268
	269	extern int pci_enable_ats(struct pci_dev *dev, int ps);
	270	extern void pci_disable_ats(struct pci_dev *dev);
	271	extern int pci_ats_queue_depth(struct pci_dev *dev);
	272	/**
	273	* pci_ats_enabled - query the ATS status
	274	* @dev: the PCI device
	275	*
	276	* Returns 1 if ATS capability is enabled, or 0 if not.
	277	*/
	278	static inline int pci_ats_enabled(struct pci_dev *dev)
	279	{
e277d2fc	280	return dev->ats && dev->ats->is_enabled;
302b4215	281	}
d1b054da YZ	282	#else
	283	static inline int pci_iov_init(struct pci_dev *dev)
	284	{
	285	return -ENODEV;
	286	}
	287	static inline void pci_iov_release(struct pci_dev *dev)
	288
	289	{
	290	}
	291	static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	292	enum pci_bar_type *type)
	293	{
	294	return 0;
	295	}
8c5cdb6a YZ	296	static inline void pci_restore_iov_state(struct pci_dev *dev)
	297	{
	298	}
a28724b0 YZ	299	static inline int pci_iov_bus_range(struct pci_bus *bus)
	300	{
	301	return 0;
	302	}
302b4215 YZ	303
	304	static inline int pci_enable_ats(struct pci_dev *dev, int ps)
	305	{
	306	return -ENODEV;
	307	}
	308	static inline void pci_disable_ats(struct pci_dev *dev)
	309	{
	310	}
	311	static inline int pci_ats_queue_depth(struct pci_dev *dev)
	312	{
	313	return -ENODEV;
	314	}
	315	static inline int pci_ats_enabled(struct pci_dev *dev)
	316	{
	317	return 0;
	318	}
d1b054da YZ	319	#endif /* CONFIG_PCI_IOV */
d1b054da YZ	320
0e52247a	321	static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
6faf17f6 CW	322	struct resource *res)
	323	{
	324	#ifdef CONFIG_PCI_IOV
	325	int resno = res - dev->resource;
	326
	327	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	328	return pci_sriov_resource_alignment(dev, resno);
	329	#endif
	330	return resource_alignment(res);
	331	}
	332
ae21ee65 AK	333	extern void pci_enable_acs(struct pci_dev *dev);
ae21ee65 AK	334
b9c3b266 DC	335	struct pci_dev_reset_methods {
	336	u16 vendor;
	337	u16 device;
	338	int (reset)(struct pci_dev dev, int probe);
	339	};
	340
93177a74	341	#ifdef CONFIG_PCI_QUIRKS
5b889bf2	342	extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
93177a74 RW	343	#else
	344	static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
	345	{
	346	return -ENOTTY;
	347	}
	348	#endif
b9c3b266	349
557848c3	350	#endif /* DRIVERS_PCI_H */