[net-next-2.6.git] / drivers / pci / pci.h

#ifndef DRIVERS_PCI_H
#define DRIVERS_PCI_H

#include <linux/workqueue.h>

#define PCI_CFG_SPACE_SIZE	256
#define PCI_CFG_SPACE_EXP_SIZE	4096

/* Functions internal to the PCI core code */

extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env);
extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
extern void pci_cleanup_rom(struct pci_dev *dev);
#ifdef HAVE_PCI_MMAP
extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
			 struct vm_area_struct *vma);
#endif
int pci_probe_reset_function(struct pci_dev *dev);

/**
 * struct pci_platform_pm_ops - Firmware PM callbacks
 *
 * @is_manageable: returns 'true' if given device is power manageable by the
 *                 platform firmware
 *
 * @set_state: invokes the platform firmware to set the device's power state
 *
 * @choose_state: returns PCI power state of given device preferred by the
 *                platform; to be used during system-wide transitions from a
 *                sleeping state to the working state and vice versa
 *
 * @can_wakeup: returns 'true' if given device is capable of waking up the
 *              system from a sleeping state
 *
 * @sleep_wake: enables/disables the system wake up capability of given device
 *
 * @run_wake: enables/disables the platform to generate run-time wake-up events
 *		for given device (the device's wake-up capability has to be
 *		enabled by @sleep_wake for this feature to work)
 *
 * If given platform is generally capable of power managing PCI devices, all of
 * these callbacks are mandatory.
 */
struct pci_platform_pm_ops {
	bool (*is_manageable)(struct pci_dev *dev);
	int (*set_state)(struct pci_dev *dev, pci_power_t state);
	pci_power_t (*choose_state)(struct pci_dev *dev);
	bool (*can_wakeup)(struct pci_dev *dev);
	int (*sleep_wake)(struct pci_dev *dev, bool enable);
	int (*run_wake)(struct pci_dev *dev, bool enable);
};

extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
extern void pci_disable_enabled_device(struct pci_dev *dev);
extern bool pci_check_pme_status(struct pci_dev *dev);
extern int pci_finish_runtime_suspend(struct pci_dev *dev);
extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
extern void pci_pme_wakeup_bus(struct pci_bus *bus);
extern void pci_pm_init(struct pci_dev *dev);
extern void platform_pci_wakeup_init(struct pci_dev *dev);
extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);

static inline bool pci_is_bridge(struct pci_dev *pci_dev)
{
	return !!(pci_dev->subordinate);
}

extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);

struct pci_vpd_ops {
	ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
	ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
	void (*release)(struct pci_dev *dev);
};

struct pci_vpd {
	unsigned int len;
	const struct pci_vpd_ops *ops;
	struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
};

extern int pci_vpd_pci22_init(struct pci_dev *dev);
static inline void pci_vpd_release(struct pci_dev *dev)
{
	if (dev->vpd)
		dev->vpd->ops->release(dev);
}

/* PCI /proc functions */
#ifdef CONFIG_PROC_FS
extern int pci_proc_attach_device(struct pci_dev *dev);
extern int pci_proc_detach_device(struct pci_dev *dev);
extern int pci_proc_detach_bus(struct pci_bus *bus);
#else
static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
#endif

/* Functions for PCI Hotplug drivers to use */
extern unsigned int pci_do_scan_bus(struct pci_bus *bus);

#ifdef HAVE_PCI_LEGACY
extern void pci_create_legacy_files(struct pci_bus *bus);
extern void pci_remove_legacy_files(struct pci_bus *bus);
#else
static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
#endif

/* Lock for read/write access to pci device and bus lists */
extern struct rw_semaphore pci_bus_sem;

extern unsigned int pci_pm_d3_delay;

#ifdef CONFIG_PCI_MSI
void pci_no_msi(void);
extern void pci_msi_init_pci_dev(struct pci_dev *dev);
#else
static inline void pci_no_msi(void) { }
static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
#endif

#ifdef CONFIG_PCIEAER
void pci_no_aer(void);
#else
static inline void pci_no_aer(void) { }
#endif

static inline int pci_no_d1d2(struct pci_dev *dev)
{
	unsigned int parent_dstates = 0;

	if (dev->bus->self)
		parent_dstates = dev->bus->self->no_d1d2;
	return (dev->no_d1d2 || parent_dstates);

}
extern struct device_attribute pci_dev_attrs[];
extern struct device_attribute dev_attr_cpuaffinity;
extern struct device_attribute dev_attr_cpulistaffinity;
#ifdef CONFIG_HOTPLUG
extern struct bus_attribute pci_bus_attrs[];
#else
#define pci_bus_attrs	NULL
#endif


/**
 * pci_match_one_device - Tell if a PCI device structure has a matching
 *                        PCI device id structure
 * @id: single PCI device id structure to match
 * @dev: the PCI device structure to match against
 *
 * Returns the matching pci_device_id structure or %NULL if there is no match.
 */
static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
{
	if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
	    (id->device == PCI_ANY_ID || id->device == dev->device) &&
	    (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
	    (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
	    !((id->class ^ dev->class) & id->class_mask))
		return id;
	return NULL;
}

struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);

/* PCI slot sysfs helper code */
#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)

extern struct kset *pci_slots_kset;

struct pci_slot_attribute {
	struct attribute attr;
	ssize_t (*show)(struct pci_slot *, char *);
	ssize_t (*store)(struct pci_slot *, const char *, size_t);
};
#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)

enum pci_bar_type {
	pci_bar_unknown,	/* Standard PCI BAR probe */
	pci_bar_io,		/* An io port BAR */
	pci_bar_mem32,		/* A 32-bit memory BAR */
	pci_bar_mem64,		/* A 64-bit memory BAR */
};

extern int pci_setup_device(struct pci_dev *dev);
extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
				struct resource *res, unsigned int reg);
extern int pci_resource_bar(struct pci_dev *dev, int resno,
			    enum pci_bar_type *type);
extern int pci_bus_add_child(struct pci_bus *bus);
extern void pci_enable_ari(struct pci_dev *dev);
/**
 * pci_ari_enabled - query ARI forwarding status
 * @bus: the PCI bus
 *
 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
 */
static inline int pci_ari_enabled(struct pci_bus *bus)
{
	return bus->self && bus->self->ari_enabled;
}

#ifdef CONFIG_PCI_QUIRKS
extern int pci_is_reassigndev(struct pci_dev *dev);
resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
extern void pci_disable_bridge_window(struct pci_dev *dev);
#endif

/* Single Root I/O Virtualization */
struct pci_sriov {
	int pos;		/* capability position */
	int nres;		/* number of resources */
	u32 cap;		/* SR-IOV Capabilities */
	u16 ctrl;		/* SR-IOV Control */
	u16 total;		/* total VFs associated with the PF */
	u16 initial;		/* initial VFs associated with the PF */
	u16 nr_virtfn;		/* number of VFs available */
	u16 offset;		/* first VF Routing ID offset */
	u16 stride;		/* following VF stride */
	u32 pgsz;		/* page size for BAR alignment */
	u8 link;		/* Function Dependency Link */
	struct pci_dev *dev;	/* lowest numbered PF */
	struct pci_dev *self;	/* this PF */
	struct mutex lock;	/* lock for VF bus */
	struct work_struct mtask; /* VF Migration task */
	u8 __iomem *mstate;	/* VF Migration State Array */
};

/* Address Translation Service */
struct pci_ats {
	int pos;	/* capability position */
	int stu;	/* Smallest Translation Unit */
	int qdep;	/* Invalidate Queue Depth */
	int ref_cnt;	/* Physical Function reference count */
	int is_enabled:1;	/* Enable bit is set */
};

#ifdef CONFIG_PCI_IOV
extern int pci_iov_init(struct pci_dev *dev);
extern void pci_iov_release(struct pci_dev *dev);
extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				enum pci_bar_type *type);
extern int pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
extern void pci_restore_iov_state(struct pci_dev *dev);
extern int pci_iov_bus_range(struct pci_bus *bus);

extern int pci_enable_ats(struct pci_dev *dev, int ps);
extern void pci_disable_ats(struct pci_dev *dev);
extern int pci_ats_queue_depth(struct pci_dev *dev);
/**
 * pci_ats_enabled - query the ATS status
 * @dev: the PCI device
 *
 * Returns 1 if ATS capability is enabled, or 0 if not.
 */
static inline int pci_ats_enabled(struct pci_dev *dev)
{
	return dev->ats && dev->ats->is_enabled;
}
#else
static inline int pci_iov_init(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline void pci_iov_release(struct pci_dev *dev)

{
}
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				       enum pci_bar_type *type)
{
	return 0;
}
static inline void pci_restore_iov_state(struct pci_dev *dev)
{
}
static inline int pci_iov_bus_range(struct pci_bus *bus)
{
	return 0;
}

static inline int pci_enable_ats(struct pci_dev *dev, int ps)
{
	return -ENODEV;
}
static inline void pci_disable_ats(struct pci_dev *dev)
{
}
static inline int pci_ats_queue_depth(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline int pci_ats_enabled(struct pci_dev *dev)
{
	return 0;
}
#endif /* CONFIG_PCI_IOV */

static inline int pci_resource_alignment(struct pci_dev *dev,
					 struct resource *res)
{
#ifdef CONFIG_PCI_IOV
	int resno = res - dev->resource;

	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		return pci_sriov_resource_alignment(dev, resno);
#endif
	return resource_alignment(res);
}

extern void pci_enable_acs(struct pci_dev *dev);

struct pci_dev_reset_methods {
	u16 vendor;
	u16 device;
	int (*reset)(struct pci_dev *dev, int probe);
};

#ifdef CONFIG_PCI_QUIRKS
extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
#else
static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
	return -ENOTTY;
}
#endif

#endif /* DRIVERS_PCI_H */
Commit	Line	Data
557848c3 ZY	1	#ifndef DRIVERS_PCI_H
	2	#define DRIVERS_PCI_H
	3
74bb1bcc YZ	4	#include <linux/workqueue.h>
74bb1bcc YZ	5
557848c3 ZY	6	#define PCI_CFG_SPACE_SIZE 256
	7	#define PCI_CFG_SPACE_EXP_SIZE 4096
	8
1da177e4 LT	9	/* Functions internal to the PCI core code */
1da177e4 LT	10
7eff2e7a	11	extern int pci_uevent(struct device dev, struct kobj_uevent_env env);
1da177e4 LT	12	extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
	13	extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
	14	extern void pci_cleanup_rom(struct pci_dev *dev);
9eff02e2 JB	15	#ifdef HAVE_PCI_MMAP
	16	extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
	17	struct vm_area_struct *vma);
	18	#endif
711d5779	19	int pci_probe_reset_function(struct pci_dev *dev);
ce5ccdef	20
961d9120	21	/**
b33bfdef	22	* struct pci_platform_pm_ops - Firmware PM callbacks
961d9120	23	*
b33bfdef RD	24	* @is_manageable: returns 'true' if given device is power manageable by the
b33bfdef RD	25	* platform firmware
961d9120	26	*
b33bfdef	27	* @set_state: invokes the platform firmware to set the device's power state
961d9120	28	*
b33bfdef RD	29	* @choose_state: returns PCI power state of given device preferred by the
	30	* platform; to be used during system-wide transitions from a
	31	* sleeping state to the working state and vice versa
961d9120	32	*
b33bfdef RD	33	* @can_wakeup: returns 'true' if given device is capable of waking up the
b33bfdef RD	34	* system from a sleeping state
eb9d0fe4	35	*
b33bfdef	36	* @sleep_wake: enables/disables the system wake up capability of given device
eb9d0fe4	37	*
b67ea761 RW	38	* @run_wake: enables/disables the platform to generate run-time wake-up events
	39	* for given device (the device's wake-up capability has to be
	40	* enabled by @sleep_wake for this feature to work)
	41	*
961d9120 RW	42	* If given platform is generally capable of power managing PCI devices, all of
	43	* these callbacks are mandatory.
	44	*/
	45	struct pci_platform_pm_ops {
	46	bool (is_manageable)(struct pci_dev dev);
	47	int (set_state)(struct pci_dev dev, pci_power_t state);
	48	pci_power_t (choose_state)(struct pci_dev dev);
eb9d0fe4 RW	49	bool (can_wakeup)(struct pci_dev dev);
eb9d0fe4 RW	50	int (sleep_wake)(struct pci_dev dev, bool enable);
b67ea761	51	int (run_wake)(struct pci_dev dev, bool enable);
961d9120 RW	52	};
	53
	54	extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
73410429	55	extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
fa58d305	56	extern void pci_disable_enabled_device(struct pci_dev *dev);
58ff4633	57	extern bool pci_check_pme_status(struct pci_dev *dev);
6cbf8214	58	extern int pci_finish_runtime_suspend(struct pci_dev *dev);
b67ea761 RW	59	extern int __pci_pme_wakeup(struct pci_dev dev, void ign);
b67ea761 RW	60	extern void pci_pme_wakeup_bus(struct pci_bus *bus);
eb9d0fe4	61	extern void pci_pm_init(struct pci_dev *dev);
eb9c39d0	62	extern void platform_pci_wakeup_init(struct pci_dev *dev);
63f4898a	63	extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
aa8c6c93 RW	64
	65	static inline bool pci_is_bridge(struct pci_dev *pci_dev)
	66	{
	67	return !!(pci_dev->subordinate);
	68	}
0f64474b	69
e04b0ea2 BK	70	extern int pci_user_read_config_byte(struct pci_dev dev, int where, u8 val);
	71	extern int pci_user_read_config_word(struct pci_dev dev, int where, u16 val);
	72	extern int pci_user_read_config_dword(struct pci_dev dev, int where, u32 val);
	73	extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
	74	extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
	75	extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
	76
94e61088	77	struct pci_vpd_ops {
287d19ce SH	78	ssize_t (read)(struct pci_dev dev, loff_t pos, size_t count, void *buf);
287d19ce SH	79	ssize_t (write)(struct pci_dev dev, loff_t pos, size_t count, const void *buf);
94e61088 BH	80	void (release)(struct pci_dev dev);
	81	};
	82
	83	struct pci_vpd {
99cb233d	84	unsigned int len;
287d19ce	85	const struct pci_vpd_ops *ops;
94e61088 BH	86	struct bin_attribute attr; / descriptor for sysfs VPD entry */
	87	};
	88
	89	extern int pci_vpd_pci22_init(struct pci_dev *dev);
	90	static inline void pci_vpd_release(struct pci_dev *dev)
	91	{
	92	if (dev->vpd)
	93	dev->vpd->ops->release(dev);
	94	}
	95
1da177e4 LT	96	/* PCI /proc functions */
	97	#ifdef CONFIG_PROC_FS
	98	extern int pci_proc_attach_device(struct pci_dev *dev);
	99	extern int pci_proc_detach_device(struct pci_dev *dev);
1da177e4 LT	100	extern int pci_proc_detach_bus(struct pci_bus *bus);
	101	#else
	102	static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
	103	static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
1da177e4 LT	104	static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
	105	#endif
	106
	107	/* Functions for PCI Hotplug drivers to use */
1da177e4	108	extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
1da177e4	109
f19aeb1f BH	110	#ifdef HAVE_PCI_LEGACY
f19aeb1f BH	111	extern void pci_create_legacy_files(struct pci_bus *bus);
1da177e4	112	extern void pci_remove_legacy_files(struct pci_bus *bus);
f19aeb1f BH	113	#else
	114	static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
	115	static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
	116	#endif
1da177e4 LT	117
1da177e4 LT	118	/* Lock for read/write access to pci device and bus lists */
d71374da	119	extern struct rw_semaphore pci_bus_sem;
1da177e4	120
ffadcc2f	121	extern unsigned int pci_pm_d3_delay;
88187dfa	122
4b47b0ee	123	#ifdef CONFIG_PCI_MSI
309e57df	124	void pci_no_msi(void);
4aa9bc95	125	extern void pci_msi_init_pci_dev(struct pci_dev *dev);
4b47b0ee	126	#else
309e57df	127	static inline void pci_no_msi(void) { }
4aa9bc95	128	static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
4b47b0ee	129	#endif
8fed4b65	130
7f785763 RD	131	#ifdef CONFIG_PCIEAER
	132	void pci_no_aer(void);
	133	#else
	134	static inline void pci_no_aer(void) { }
	135	#endif
	136
ffadcc2f KCA	137	static inline int pci_no_d1d2(struct pci_dev *dev)
	138	{
	139	unsigned int parent_dstates = 0;
4b47b0ee	140
ffadcc2f KCA	141	if (dev->bus->self)
	142	parent_dstates = dev->bus->self->no_d1d2;
	143	return (dev->no_d1d2 \|\| parent_dstates);
	144
	145	}
1da177e4	146	extern struct device_attribute pci_dev_attrs[];
fd7d1ced	147	extern struct device_attribute dev_attr_cpuaffinity;
93ff68a5	148	extern struct device_attribute dev_attr_cpulistaffinity;
705b1aaa AC	149	#ifdef CONFIG_HOTPLUG
	150	extern struct bus_attribute pci_bus_attrs[];
	151	#else
	152	#define pci_bus_attrs NULL
	153	#endif
	154
1da177e4 LT	155
	156	/**
	157	* pci_match_one_device - Tell if a PCI device structure has a matching
	158	* PCI device id structure
	159	* @id: single PCI device id structure to match
	160	* @dev: the PCI device structure to match against
367b09fe	161	*
1da177e4 LT	162	* Returns the matching pci_device_id structure or %NULL if there is no match.
	163	*/
	164	static inline const struct pci_device_id *
	165	pci_match_one_device(const struct pci_device_id id, const struct pci_dev dev)
	166	{
	167	if ((id->vendor == PCI_ANY_ID \|\| id->vendor == dev->vendor) &&
	168	(id->device == PCI_ANY_ID \|\| id->device == dev->device) &&
	169	(id->subvendor == PCI_ANY_ID \|\| id->subvendor == dev->subsystem_vendor) &&
	170	(id->subdevice == PCI_ANY_ID \|\| id->subdevice == dev->subsystem_device) &&
	171	!((id->class ^ dev->class) & id->class_mask))
	172	return id;
	173	return NULL;
	174	}
	175
994a65e2	176	struct pci_dev pci_find_upstream_pcie_bridge(struct pci_dev pdev);
f46753c5 AC	177
	178	/* PCI slot sysfs helper code */
	179	#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
	180
	181	extern struct kset *pci_slots_kset;
	182
	183	struct pci_slot_attribute {
	184	struct attribute attr;
	185	ssize_t (show)(struct pci_slot , char *);
	186	ssize_t (store)(struct pci_slot , const char *, size_t);
	187	};
	188	#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
	189
0b400c7e YZ	190	enum pci_bar_type {
	191	pci_bar_unknown, /* Standard PCI BAR probe */
	192	pci_bar_io, /* An io port BAR */
	193	pci_bar_mem32, /* A 32-bit memory BAR */
	194	pci_bar_mem64, /* A 64-bit memory BAR */
	195	};
	196
480b93b7	197	extern int pci_setup_device(struct pci_dev *dev);
0b400c7e YZ	198	extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
0b400c7e YZ	199	struct resource *res, unsigned int reg);
613e7ed6 YZ	200	extern int pci_resource_bar(struct pci_dev *dev, int resno,
613e7ed6 YZ	201	enum pci_bar_type *type);
876e501a	202	extern int pci_bus_add_child(struct pci_bus *bus);
58c3a727 YZ	203	extern void pci_enable_ari(struct pci_dev *dev);
	204	/**
	205	* pci_ari_enabled - query ARI forwarding status
6a49d812	206	* @bus: the PCI bus
58c3a727 YZ	207	*
	208	* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
	209	*/
6a49d812	210	static inline int pci_ari_enabled(struct pci_bus *bus)
58c3a727	211	{
6a49d812	212	return bus->self && bus->self->ari_enabled;
58c3a727 YZ	213	}
58c3a727 YZ	214
32a9a682 YS	215	#ifdef CONFIG_PCI_QUIRKS
	216	extern int pci_is_reassigndev(struct pci_dev *dev);
	217	resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
	218	extern void pci_disable_bridge_window(struct pci_dev *dev);
	219	#endif
	220
d1b054da YZ	221	/* Single Root I/O Virtualization */
	222	struct pci_sriov {
	223	int pos; /* capability position */
	224	int nres; /* number of resources */
	225	u32 cap; /* SR-IOV Capabilities */
	226	u16 ctrl; /* SR-IOV Control */
	227	u16 total; /* total VFs associated with the PF */
dd7cc44d YZ	228	u16 initial; /* initial VFs associated with the PF */
dd7cc44d YZ	229	u16 nr_virtfn; /* number of VFs available */
d1b054da YZ	230	u16 offset; /* first VF Routing ID offset */
	231	u16 stride; /* following VF stride */
	232	u32 pgsz; /* page size for BAR alignment */
	233	u8 link; /* Function Dependency Link */
	234	struct pci_dev dev; / lowest numbered PF */
	235	struct pci_dev self; / this PF */
	236	struct mutex lock; /* lock for VF bus */
74bb1bcc YZ	237	struct work_struct mtask; /* VF Migration task */
74bb1bcc YZ	238	u8 __iomem mstate; / VF Migration State Array */
d1b054da YZ	239	};
d1b054da YZ	240
302b4215 YZ	241	/* Address Translation Service */
	242	struct pci_ats {
	243	int pos; /* capability position */
	244	int stu; /* Smallest Translation Unit */
	245	int qdep; /* Invalidate Queue Depth */
e277d2fc YZ	246	int ref_cnt; /* Physical Function reference count */
e277d2fc YZ	247	int is_enabled:1; /* Enable bit is set */
302b4215 YZ	248	};
302b4215 YZ	249
d1b054da YZ	250	#ifdef CONFIG_PCI_IOV
	251	extern int pci_iov_init(struct pci_dev *dev);
	252	extern void pci_iov_release(struct pci_dev *dev);
	253	extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	254	enum pci_bar_type *type);
6faf17f6	255	extern int pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
8c5cdb6a	256	extern void pci_restore_iov_state(struct pci_dev *dev);
a28724b0	257	extern int pci_iov_bus_range(struct pci_bus *bus);
302b4215 YZ	258
	259	extern int pci_enable_ats(struct pci_dev *dev, int ps);
	260	extern void pci_disable_ats(struct pci_dev *dev);
	261	extern int pci_ats_queue_depth(struct pci_dev *dev);
	262	/**
	263	* pci_ats_enabled - query the ATS status
	264	* @dev: the PCI device
	265	*
	266	* Returns 1 if ATS capability is enabled, or 0 if not.
	267	*/
	268	static inline int pci_ats_enabled(struct pci_dev *dev)
	269	{
e277d2fc	270	return dev->ats && dev->ats->is_enabled;
302b4215	271	}
d1b054da YZ	272	#else
	273	static inline int pci_iov_init(struct pci_dev *dev)
	274	{
	275	return -ENODEV;
	276	}
	277	static inline void pci_iov_release(struct pci_dev *dev)
	278
	279	{
	280	}
	281	static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	282	enum pci_bar_type *type)
	283	{
	284	return 0;
	285	}
8c5cdb6a YZ	286	static inline void pci_restore_iov_state(struct pci_dev *dev)
	287	{
	288	}
a28724b0 YZ	289	static inline int pci_iov_bus_range(struct pci_bus *bus)
	290	{
	291	return 0;
	292	}
302b4215 YZ	293
	294	static inline int pci_enable_ats(struct pci_dev *dev, int ps)
	295	{
	296	return -ENODEV;
	297	}
	298	static inline void pci_disable_ats(struct pci_dev *dev)
	299	{
	300	}
	301	static inline int pci_ats_queue_depth(struct pci_dev *dev)
	302	{
	303	return -ENODEV;
	304	}
	305	static inline int pci_ats_enabled(struct pci_dev *dev)
	306	{
	307	return 0;
	308	}
d1b054da YZ	309	#endif /* CONFIG_PCI_IOV */
d1b054da YZ	310
6faf17f6 CW	311	static inline int pci_resource_alignment(struct pci_dev *dev,
	312	struct resource *res)
	313	{
	314	#ifdef CONFIG_PCI_IOV
	315	int resno = res - dev->resource;
	316
	317	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	318	return pci_sriov_resource_alignment(dev, resno);
	319	#endif
	320	return resource_alignment(res);
	321	}
	322
ae21ee65 AK	323	extern void pci_enable_acs(struct pci_dev *dev);
ae21ee65 AK	324
b9c3b266 DC	325	struct pci_dev_reset_methods {
	326	u16 vendor;
	327	u16 device;
	328	int (reset)(struct pci_dev dev, int probe);
	329	};
	330
93177a74	331	#ifdef CONFIG_PCI_QUIRKS
5b889bf2	332	extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
93177a74 RW	333	#else
	334	static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
	335	{
	336	return -ENOTTY;
	337	}
	338	#endif
b9c3b266	339
557848c3	340	#endif /* DRIVERS_PCI_H */