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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/spinlock.h> | |
4e57b681 | 17 | #include <linux/string.h> |
229f5afd | 18 | #include <linux/log2.h> |
7d715a6c | 19 | #include <linux/pci-aspm.h> |
c300bd2f | 20 | #include <linux/pm_wakeup.h> |
8dd7f803 | 21 | #include <linux/interrupt.h> |
32a9a682 YS |
22 | #include <linux/device.h> |
23 | #include <asm/setup.h> | |
bc56b9e0 | 24 | #include "pci.h" |
1da177e4 | 25 | |
00240c38 AS |
26 | const char *pci_power_names[] = { |
27 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
28 | }; | |
29 | EXPORT_SYMBOL_GPL(pci_power_names); | |
30 | ||
93177a74 RW |
31 | int isa_dma_bridge_buggy; |
32 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
33 | ||
34 | int pci_pci_problems; | |
35 | EXPORT_SYMBOL(pci_pci_problems); | |
36 | ||
1ae861e6 RW |
37 | unsigned int pci_pm_d3_delay; |
38 | ||
39 | static void pci_dev_d3_sleep(struct pci_dev *dev) | |
40 | { | |
41 | unsigned int delay = dev->d3_delay; | |
42 | ||
43 | if (delay < pci_pm_d3_delay) | |
44 | delay = pci_pm_d3_delay; | |
45 | ||
46 | msleep(delay); | |
47 | } | |
1da177e4 | 48 | |
32a2eea7 JG |
49 | #ifdef CONFIG_PCI_DOMAINS |
50 | int pci_domains_supported = 1; | |
51 | #endif | |
52 | ||
4516a618 AN |
53 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
54 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
55 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
56 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
57 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
58 | ||
28760489 EB |
59 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
60 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
61 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
62 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
63 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
64 | ||
ac1aa47b JB |
65 | /* |
66 | * The default CLS is used if arch didn't set CLS explicitly and not | |
67 | * all pci devices agree on the same value. Arch can override either | |
68 | * the dfl or actual value as it sees fit. Don't forget this is | |
69 | * measured in 32-bit words, not bytes. | |
70 | */ | |
98e724c7 | 71 | u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
72 | u8 pci_cache_line_size; |
73 | ||
1da177e4 LT |
74 | /** |
75 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
76 | * @bus: pointer to PCI bus structure to search | |
77 | * | |
78 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
79 | * including the given PCI bus and its list of child PCI buses. | |
80 | */ | |
96bde06a | 81 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
82 | { |
83 | struct list_head *tmp; | |
84 | unsigned char max, n; | |
85 | ||
b82db5ce | 86 | max = bus->subordinate; |
1da177e4 LT |
87 | list_for_each(tmp, &bus->children) { |
88 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
89 | if(n > max) | |
90 | max = n; | |
91 | } | |
92 | return max; | |
93 | } | |
b82db5ce | 94 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 95 | |
1684f5dd AM |
96 | #ifdef CONFIG_HAS_IOMEM |
97 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
98 | { | |
99 | /* | |
100 | * Make sure the BAR is actually a memory resource, not an IO resource | |
101 | */ | |
102 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
103 | WARN_ON(1); | |
104 | return NULL; | |
105 | } | |
106 | return ioremap_nocache(pci_resource_start(pdev, bar), | |
107 | pci_resource_len(pdev, bar)); | |
108 | } | |
109 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
110 | #endif | |
111 | ||
b82db5ce | 112 | #if 0 |
1da177e4 LT |
113 | /** |
114 | * pci_max_busnr - returns maximum PCI bus number | |
115 | * | |
116 | * Returns the highest PCI bus number present in the system global list of | |
117 | * PCI buses. | |
118 | */ | |
119 | unsigned char __devinit | |
120 | pci_max_busnr(void) | |
121 | { | |
122 | struct pci_bus *bus = NULL; | |
123 | unsigned char max, n; | |
124 | ||
125 | max = 0; | |
126 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
127 | n = pci_bus_max_busnr(bus); | |
128 | if(n > max) | |
129 | max = n; | |
130 | } | |
131 | return max; | |
132 | } | |
133 | ||
54c762fe AB |
134 | #endif /* 0 */ |
135 | ||
687d5fe3 ME |
136 | #define PCI_FIND_CAP_TTL 48 |
137 | ||
138 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
139 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
140 | { |
141 | u8 id; | |
24a4e377 | 142 | |
687d5fe3 | 143 | while ((*ttl)--) { |
24a4e377 RD |
144 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
145 | if (pos < 0x40) | |
146 | break; | |
147 | pos &= ~3; | |
148 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
149 | &id); | |
150 | if (id == 0xff) | |
151 | break; | |
152 | if (id == cap) | |
153 | return pos; | |
154 | pos += PCI_CAP_LIST_NEXT; | |
155 | } | |
156 | return 0; | |
157 | } | |
158 | ||
687d5fe3 ME |
159 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
160 | u8 pos, int cap) | |
161 | { | |
162 | int ttl = PCI_FIND_CAP_TTL; | |
163 | ||
164 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
165 | } | |
166 | ||
24a4e377 RD |
167 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
168 | { | |
169 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
170 | pos + PCI_CAP_LIST_NEXT, cap); | |
171 | } | |
172 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
173 | ||
d3bac118 ME |
174 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
175 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
176 | { |
177 | u16 status; | |
1da177e4 LT |
178 | |
179 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
180 | if (!(status & PCI_STATUS_CAP_LIST)) | |
181 | return 0; | |
182 | ||
183 | switch (hdr_type) { | |
184 | case PCI_HEADER_TYPE_NORMAL: | |
185 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 186 | return PCI_CAPABILITY_LIST; |
1da177e4 | 187 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 188 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
189 | default: |
190 | return 0; | |
191 | } | |
d3bac118 ME |
192 | |
193 | return 0; | |
1da177e4 LT |
194 | } |
195 | ||
196 | /** | |
197 | * pci_find_capability - query for devices' capabilities | |
198 | * @dev: PCI device to query | |
199 | * @cap: capability code | |
200 | * | |
201 | * Tell if a device supports a given PCI capability. | |
202 | * Returns the address of the requested capability structure within the | |
203 | * device's PCI configuration space or 0 in case the device does not | |
204 | * support it. Possible values for @cap: | |
205 | * | |
206 | * %PCI_CAP_ID_PM Power Management | |
207 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
208 | * %PCI_CAP_ID_VPD Vital Product Data | |
209 | * %PCI_CAP_ID_SLOTID Slot Identification | |
210 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
211 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
212 | * %PCI_CAP_ID_PCIX PCI-X | |
213 | * %PCI_CAP_ID_EXP PCI Express | |
214 | */ | |
215 | int pci_find_capability(struct pci_dev *dev, int cap) | |
216 | { | |
d3bac118 ME |
217 | int pos; |
218 | ||
219 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
220 | if (pos) | |
221 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
222 | ||
223 | return pos; | |
1da177e4 LT |
224 | } |
225 | ||
226 | /** | |
227 | * pci_bus_find_capability - query for devices' capabilities | |
228 | * @bus: the PCI bus to query | |
229 | * @devfn: PCI device to query | |
230 | * @cap: capability code | |
231 | * | |
232 | * Like pci_find_capability() but works for pci devices that do not have a | |
233 | * pci_dev structure set up yet. | |
234 | * | |
235 | * Returns the address of the requested capability structure within the | |
236 | * device's PCI configuration space or 0 in case the device does not | |
237 | * support it. | |
238 | */ | |
239 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
240 | { | |
d3bac118 | 241 | int pos; |
1da177e4 LT |
242 | u8 hdr_type; |
243 | ||
244 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
245 | ||
d3bac118 ME |
246 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
247 | if (pos) | |
248 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
249 | ||
250 | return pos; | |
1da177e4 LT |
251 | } |
252 | ||
253 | /** | |
254 | * pci_find_ext_capability - Find an extended capability | |
255 | * @dev: PCI device to query | |
256 | * @cap: capability code | |
257 | * | |
258 | * Returns the address of the requested extended capability structure | |
259 | * within the device's PCI configuration space or 0 if the device does | |
260 | * not support it. Possible values for @cap: | |
261 | * | |
262 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
263 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
264 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
265 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
266 | */ | |
267 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
268 | { | |
269 | u32 header; | |
557848c3 ZY |
270 | int ttl; |
271 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 272 | |
557848c3 ZY |
273 | /* minimum 8 bytes per capability */ |
274 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
275 | ||
276 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
277 | return 0; |
278 | ||
279 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
280 | return 0; | |
281 | ||
282 | /* | |
283 | * If we have no capabilities, this is indicated by cap ID, | |
284 | * cap version and next pointer all being 0. | |
285 | */ | |
286 | if (header == 0) | |
287 | return 0; | |
288 | ||
289 | while (ttl-- > 0) { | |
290 | if (PCI_EXT_CAP_ID(header) == cap) | |
291 | return pos; | |
292 | ||
293 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 294 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
295 | break; |
296 | ||
297 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
298 | break; | |
299 | } | |
300 | ||
301 | return 0; | |
302 | } | |
3a720d72 | 303 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 304 | |
687d5fe3 ME |
305 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
306 | { | |
307 | int rc, ttl = PCI_FIND_CAP_TTL; | |
308 | u8 cap, mask; | |
309 | ||
310 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
311 | mask = HT_3BIT_CAP_MASK; | |
312 | else | |
313 | mask = HT_5BIT_CAP_MASK; | |
314 | ||
315 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
316 | PCI_CAP_ID_HT, &ttl); | |
317 | while (pos) { | |
318 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
319 | if (rc != PCIBIOS_SUCCESSFUL) | |
320 | return 0; | |
321 | ||
322 | if ((cap & mask) == ht_cap) | |
323 | return pos; | |
324 | ||
47a4d5be BG |
325 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
326 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
327 | PCI_CAP_ID_HT, &ttl); |
328 | } | |
329 | ||
330 | return 0; | |
331 | } | |
332 | /** | |
333 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
334 | * @dev: PCI device to query | |
335 | * @pos: Position from which to continue searching | |
336 | * @ht_cap: Hypertransport capability code | |
337 | * | |
338 | * To be used in conjunction with pci_find_ht_capability() to search for | |
339 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
340 | * from pci_find_ht_capability(). | |
341 | * | |
342 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
343 | * steps to avoid an infinite loop. | |
344 | */ | |
345 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
346 | { | |
347 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
348 | } | |
349 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
350 | ||
351 | /** | |
352 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
353 | * @dev: PCI device to query | |
354 | * @ht_cap: Hypertransport capability code | |
355 | * | |
356 | * Tell if a device supports a given Hypertransport capability. | |
357 | * Returns an address within the device's PCI configuration space | |
358 | * or 0 in case the device does not support the request capability. | |
359 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
360 | * which has a Hypertransport capability matching @ht_cap. | |
361 | */ | |
362 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
363 | { | |
364 | int pos; | |
365 | ||
366 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
367 | if (pos) | |
368 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
369 | ||
370 | return pos; | |
371 | } | |
372 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
373 | ||
1da177e4 LT |
374 | /** |
375 | * pci_find_parent_resource - return resource region of parent bus of given region | |
376 | * @dev: PCI device structure contains resources to be searched | |
377 | * @res: child resource record for which parent is sought | |
378 | * | |
379 | * For given resource region of given device, return the resource | |
380 | * region of parent bus the given region is contained in or where | |
381 | * it should be allocated from. | |
382 | */ | |
383 | struct resource * | |
384 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
385 | { | |
386 | const struct pci_bus *bus = dev->bus; | |
387 | int i; | |
388 | struct resource *best = NULL; | |
389 | ||
390 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
391 | struct resource *r = bus->resource[i]; | |
392 | if (!r) | |
393 | continue; | |
394 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
395 | continue; /* Not contained */ | |
396 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
397 | continue; /* Wrong type */ | |
398 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
399 | return r; /* Exact match */ | |
8c8def26 LT |
400 | /* We can't insert a non-prefetch resource inside a prefetchable parent .. */ |
401 | if (r->flags & IORESOURCE_PREFETCH) | |
402 | continue; | |
403 | /* .. but we can put a prefetchable resource inside a non-prefetchable one */ | |
404 | if (!best) | |
405 | best = r; | |
1da177e4 LT |
406 | } |
407 | return best; | |
408 | } | |
409 | ||
064b53db JL |
410 | /** |
411 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
412 | * @dev: PCI device to have its BARs restored | |
413 | * | |
414 | * Restore the BAR values for a given device, so as to make it | |
415 | * accessible by its driver. | |
416 | */ | |
ad668599 | 417 | static void |
064b53db JL |
418 | pci_restore_bars(struct pci_dev *dev) |
419 | { | |
bc5f5a82 | 420 | int i; |
064b53db | 421 | |
bc5f5a82 | 422 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 423 | pci_update_resource(dev, i); |
064b53db JL |
424 | } |
425 | ||
961d9120 RW |
426 | static struct pci_platform_pm_ops *pci_platform_pm; |
427 | ||
428 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
429 | { | |
eb9d0fe4 RW |
430 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
431 | || !ops->sleep_wake || !ops->can_wakeup) | |
961d9120 RW |
432 | return -EINVAL; |
433 | pci_platform_pm = ops; | |
434 | return 0; | |
435 | } | |
436 | ||
437 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
438 | { | |
439 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
440 | } | |
441 | ||
442 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
443 | pci_power_t t) | |
444 | { | |
445 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
446 | } | |
447 | ||
448 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
449 | { | |
450 | return pci_platform_pm ? | |
451 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
452 | } | |
8f7020d3 | 453 | |
eb9d0fe4 RW |
454 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
455 | { | |
456 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; | |
457 | } | |
458 | ||
459 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) | |
460 | { | |
461 | return pci_platform_pm ? | |
462 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
463 | } | |
464 | ||
1da177e4 | 465 | /** |
44e4e66e RW |
466 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
467 | * given PCI device | |
468 | * @dev: PCI device to handle. | |
44e4e66e | 469 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 470 | * |
44e4e66e RW |
471 | * RETURN VALUE: |
472 | * -EINVAL if the requested state is invalid. | |
473 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
474 | * wrong version, or device doesn't support the requested state. | |
475 | * 0 if device already is in the requested state. | |
476 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 477 | */ |
f00a20ef | 478 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 479 | { |
337001b6 | 480 | u16 pmcsr; |
44e4e66e | 481 | bool need_restore = false; |
1da177e4 | 482 | |
4a865905 RW |
483 | /* Check if we're already there */ |
484 | if (dev->current_state == state) | |
485 | return 0; | |
486 | ||
337001b6 | 487 | if (!dev->pm_cap) |
cca03dec AL |
488 | return -EIO; |
489 | ||
44e4e66e RW |
490 | if (state < PCI_D0 || state > PCI_D3hot) |
491 | return -EINVAL; | |
492 | ||
1da177e4 LT |
493 | /* Validate current state: |
494 | * Can enter D0 from any state, but if we can only go deeper | |
495 | * to sleep if we're already in a low power state | |
496 | */ | |
4a865905 | 497 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 498 | && dev->current_state > state) { |
80ccba11 BH |
499 | dev_err(&dev->dev, "invalid power transition " |
500 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 501 | return -EINVAL; |
44e4e66e | 502 | } |
1da177e4 | 503 | |
1da177e4 | 504 | /* check if this device supports the desired state */ |
337001b6 RW |
505 | if ((state == PCI_D1 && !dev->d1_support) |
506 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 507 | return -EIO; |
1da177e4 | 508 | |
337001b6 | 509 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 510 | |
32a36585 | 511 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
512 | * This doesn't affect PME_Status, disables PME_En, and |
513 | * sets PowerState to 0. | |
514 | */ | |
32a36585 | 515 | switch (dev->current_state) { |
d3535fbb JL |
516 | case PCI_D0: |
517 | case PCI_D1: | |
518 | case PCI_D2: | |
519 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
520 | pmcsr |= state; | |
521 | break; | |
f62795f1 RW |
522 | case PCI_D3hot: |
523 | case PCI_D3cold: | |
32a36585 JL |
524 | case PCI_UNKNOWN: /* Boot-up */ |
525 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 526 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 527 | need_restore = true; |
32a36585 | 528 | /* Fall-through: force to D0 */ |
32a36585 | 529 | default: |
d3535fbb | 530 | pmcsr = 0; |
32a36585 | 531 | break; |
1da177e4 LT |
532 | } |
533 | ||
534 | /* enter specified state */ | |
337001b6 | 535 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
536 | |
537 | /* Mandatory power management transition delays */ | |
538 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
539 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 540 | pci_dev_d3_sleep(dev); |
1da177e4 | 541 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 542 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 543 | |
e13cdbd7 RW |
544 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
545 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
546 | if (dev->current_state != state && printk_ratelimit()) | |
547 | dev_info(&dev->dev, "Refused to change power state, " | |
548 | "currently in D%d\n", dev->current_state); | |
064b53db JL |
549 | |
550 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
551 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
552 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
553 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
554 | * For example, at least some versions of the 3c905B and the | |
555 | * 3c556B exhibit this behaviour. | |
556 | * | |
557 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
558 | * devices in a D3hot state at boot. Consequently, we need to | |
559 | * restore at least the BARs so that the device will be | |
560 | * accessible to its driver. | |
561 | */ | |
562 | if (need_restore) | |
563 | pci_restore_bars(dev); | |
564 | ||
f00a20ef | 565 | if (dev->bus->self) |
7d715a6c SL |
566 | pcie_aspm_pm_state_change(dev->bus->self); |
567 | ||
1da177e4 LT |
568 | return 0; |
569 | } | |
570 | ||
44e4e66e RW |
571 | /** |
572 | * pci_update_current_state - Read PCI power state of given device from its | |
573 | * PCI PM registers and cache it | |
574 | * @dev: PCI device to handle. | |
f06fc0b6 | 575 | * @state: State to cache in case the device doesn't have the PM capability |
44e4e66e | 576 | */ |
73410429 | 577 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 578 | { |
337001b6 | 579 | if (dev->pm_cap) { |
44e4e66e RW |
580 | u16 pmcsr; |
581 | ||
337001b6 | 582 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 583 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
584 | } else { |
585 | dev->current_state = state; | |
44e4e66e RW |
586 | } |
587 | } | |
588 | ||
0e5dd46b RW |
589 | /** |
590 | * pci_platform_power_transition - Use platform to change device power state | |
591 | * @dev: PCI device to handle. | |
592 | * @state: State to put the device into. | |
593 | */ | |
594 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
595 | { | |
596 | int error; | |
597 | ||
598 | if (platform_pci_power_manageable(dev)) { | |
599 | error = platform_pci_set_power_state(dev, state); | |
600 | if (!error) | |
601 | pci_update_current_state(dev, state); | |
602 | } else { | |
603 | error = -ENODEV; | |
604 | /* Fall back to PCI_D0 if native PM is not supported */ | |
b3bad72e RW |
605 | if (!dev->pm_cap) |
606 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
607 | } |
608 | ||
609 | return error; | |
610 | } | |
611 | ||
612 | /** | |
613 | * __pci_start_power_transition - Start power transition of a PCI device | |
614 | * @dev: PCI device to handle. | |
615 | * @state: State to put the device into. | |
616 | */ | |
617 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
618 | { | |
619 | if (state == PCI_D0) | |
620 | pci_platform_power_transition(dev, PCI_D0); | |
621 | } | |
622 | ||
623 | /** | |
624 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
625 | * @dev: PCI device to handle. | |
626 | * @state: State to put the device into. | |
627 | * | |
628 | * This function should not be called directly by device drivers. | |
629 | */ | |
630 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
631 | { | |
632 | return state > PCI_D0 ? | |
633 | pci_platform_power_transition(dev, state) : -EINVAL; | |
634 | } | |
635 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
636 | ||
44e4e66e RW |
637 | /** |
638 | * pci_set_power_state - Set the power state of a PCI device | |
639 | * @dev: PCI device to handle. | |
640 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
641 | * | |
877d0310 | 642 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
643 | * the device's PCI PM registers. |
644 | * | |
645 | * RETURN VALUE: | |
646 | * -EINVAL if the requested state is invalid. | |
647 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
648 | * wrong version, or device doesn't support the requested state. | |
649 | * 0 if device already is in the requested state. | |
650 | * 0 if device's power state has been successfully changed. | |
651 | */ | |
652 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
653 | { | |
337001b6 | 654 | int error; |
44e4e66e RW |
655 | |
656 | /* bound the state we're entering */ | |
657 | if (state > PCI_D3hot) | |
658 | state = PCI_D3hot; | |
659 | else if (state < PCI_D0) | |
660 | state = PCI_D0; | |
661 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
662 | /* | |
663 | * If the device or the parent bridge do not support PCI PM, | |
664 | * ignore the request if we're doing anything other than putting | |
665 | * it into D0 (which would only happen on boot). | |
666 | */ | |
667 | return 0; | |
668 | ||
4a865905 RW |
669 | /* Check if we're already there */ |
670 | if (dev->current_state == state) | |
671 | return 0; | |
672 | ||
0e5dd46b RW |
673 | __pci_start_power_transition(dev, state); |
674 | ||
979b1791 AC |
675 | /* This device is quirked not to be put into D3, so |
676 | don't put it in D3 */ | |
677 | if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) | |
678 | return 0; | |
44e4e66e | 679 | |
f00a20ef | 680 | error = pci_raw_set_power_state(dev, state); |
44e4e66e | 681 | |
0e5dd46b RW |
682 | if (!__pci_complete_power_transition(dev, state)) |
683 | error = 0; | |
44e4e66e RW |
684 | |
685 | return error; | |
686 | } | |
687 | ||
1da177e4 LT |
688 | /** |
689 | * pci_choose_state - Choose the power state of a PCI device | |
690 | * @dev: PCI device to be suspended | |
691 | * @state: target sleep state for the whole system. This is the value | |
692 | * that is passed to suspend() function. | |
693 | * | |
694 | * Returns PCI power state suitable for given device and given system | |
695 | * message. | |
696 | */ | |
697 | ||
698 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
699 | { | |
ab826ca4 | 700 | pci_power_t ret; |
0f64474b | 701 | |
1da177e4 LT |
702 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
703 | return PCI_D0; | |
704 | ||
961d9120 RW |
705 | ret = platform_pci_choose_state(dev); |
706 | if (ret != PCI_POWER_ERROR) | |
707 | return ret; | |
ca078bae PM |
708 | |
709 | switch (state.event) { | |
710 | case PM_EVENT_ON: | |
711 | return PCI_D0; | |
712 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
713 | case PM_EVENT_PRETHAW: |
714 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 715 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 716 | case PM_EVENT_HIBERNATE: |
ca078bae | 717 | return PCI_D3hot; |
1da177e4 | 718 | default: |
80ccba11 BH |
719 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
720 | state.event); | |
1da177e4 LT |
721 | BUG(); |
722 | } | |
723 | return PCI_D0; | |
724 | } | |
725 | ||
726 | EXPORT_SYMBOL(pci_choose_state); | |
727 | ||
89858517 YZ |
728 | #define PCI_EXP_SAVE_REGS 7 |
729 | ||
1b6b8ce2 YZ |
730 | #define pcie_cap_has_devctl(type, flags) 1 |
731 | #define pcie_cap_has_lnkctl(type, flags) \ | |
732 | ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ | |
733 | (type == PCI_EXP_TYPE_ROOT_PORT || \ | |
734 | type == PCI_EXP_TYPE_ENDPOINT || \ | |
735 | type == PCI_EXP_TYPE_LEG_END)) | |
736 | #define pcie_cap_has_sltctl(type, flags) \ | |
737 | ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ | |
738 | ((type == PCI_EXP_TYPE_ROOT_PORT) || \ | |
739 | (type == PCI_EXP_TYPE_DOWNSTREAM && \ | |
740 | (flags & PCI_EXP_FLAGS_SLOT)))) | |
741 | #define pcie_cap_has_rtctl(type, flags) \ | |
742 | ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ | |
743 | (type == PCI_EXP_TYPE_ROOT_PORT || \ | |
744 | type == PCI_EXP_TYPE_RC_EC)) | |
745 | #define pcie_cap_has_devctl2(type, flags) \ | |
746 | ((flags & PCI_EXP_FLAGS_VERS) > 1) | |
747 | #define pcie_cap_has_lnkctl2(type, flags) \ | |
748 | ((flags & PCI_EXP_FLAGS_VERS) > 1) | |
749 | #define pcie_cap_has_sltctl2(type, flags) \ | |
750 | ((flags & PCI_EXP_FLAGS_VERS) > 1) | |
751 | ||
b56a5a23 MT |
752 | static int pci_save_pcie_state(struct pci_dev *dev) |
753 | { | |
754 | int pos, i = 0; | |
755 | struct pci_cap_saved_state *save_state; | |
756 | u16 *cap; | |
1b6b8ce2 | 757 | u16 flags; |
b56a5a23 | 758 | |
06a1cbaf KK |
759 | pos = pci_pcie_cap(dev); |
760 | if (!pos) | |
b56a5a23 MT |
761 | return 0; |
762 | ||
9f35575d | 763 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 764 | if (!save_state) { |
e496b617 | 765 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
766 | return -ENOMEM; |
767 | } | |
768 | cap = (u16 *)&save_state->data[0]; | |
769 | ||
1b6b8ce2 YZ |
770 | pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); |
771 | ||
772 | if (pcie_cap_has_devctl(dev->pcie_type, flags)) | |
773 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
774 | if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) | |
775 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
776 | if (pcie_cap_has_sltctl(dev->pcie_type, flags)) | |
777 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
778 | if (pcie_cap_has_rtctl(dev->pcie_type, flags)) | |
779 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
780 | if (pcie_cap_has_devctl2(dev->pcie_type, flags)) | |
781 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]); | |
782 | if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) | |
783 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]); | |
784 | if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) | |
785 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]); | |
63f4898a | 786 | |
b56a5a23 MT |
787 | return 0; |
788 | } | |
789 | ||
790 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
791 | { | |
792 | int i = 0, pos; | |
793 | struct pci_cap_saved_state *save_state; | |
794 | u16 *cap; | |
1b6b8ce2 | 795 | u16 flags; |
b56a5a23 MT |
796 | |
797 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
798 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
799 | if (!save_state || pos <= 0) | |
800 | return; | |
801 | cap = (u16 *)&save_state->data[0]; | |
802 | ||
1b6b8ce2 YZ |
803 | pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); |
804 | ||
805 | if (pcie_cap_has_devctl(dev->pcie_type, flags)) | |
806 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
807 | if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) | |
808 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
809 | if (pcie_cap_has_sltctl(dev->pcie_type, flags)) | |
810 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
811 | if (pcie_cap_has_rtctl(dev->pcie_type, flags)) | |
812 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
813 | if (pcie_cap_has_devctl2(dev->pcie_type, flags)) | |
814 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); | |
815 | if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) | |
816 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); | |
817 | if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) | |
818 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
819 | } |
820 | ||
cc692a5f SH |
821 | |
822 | static int pci_save_pcix_state(struct pci_dev *dev) | |
823 | { | |
63f4898a | 824 | int pos; |
cc692a5f | 825 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
826 | |
827 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
828 | if (pos <= 0) | |
829 | return 0; | |
830 | ||
f34303de | 831 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 832 | if (!save_state) { |
e496b617 | 833 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
834 | return -ENOMEM; |
835 | } | |
cc692a5f | 836 | |
63f4898a RW |
837 | pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data); |
838 | ||
cc692a5f SH |
839 | return 0; |
840 | } | |
841 | ||
842 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
843 | { | |
844 | int i = 0, pos; | |
845 | struct pci_cap_saved_state *save_state; | |
846 | u16 *cap; | |
847 | ||
848 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
849 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
850 | if (!save_state || pos <= 0) | |
851 | return; | |
852 | cap = (u16 *)&save_state->data[0]; | |
853 | ||
854 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
855 | } |
856 | ||
857 | ||
1da177e4 LT |
858 | /** |
859 | * pci_save_state - save the PCI configuration space of a device before suspending | |
860 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
861 | */ |
862 | int | |
863 | pci_save_state(struct pci_dev *dev) | |
864 | { | |
865 | int i; | |
866 | /* XXX: 100% dword access ok here? */ | |
867 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 868 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 869 | dev->state_saved = true; |
b56a5a23 MT |
870 | if ((i = pci_save_pcie_state(dev)) != 0) |
871 | return i; | |
cc692a5f SH |
872 | if ((i = pci_save_pcix_state(dev)) != 0) |
873 | return i; | |
1da177e4 LT |
874 | return 0; |
875 | } | |
876 | ||
877 | /** | |
878 | * pci_restore_state - Restore the saved state of a PCI device | |
879 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
880 | */ |
881 | int | |
882 | pci_restore_state(struct pci_dev *dev) | |
883 | { | |
884 | int i; | |
b4482a4b | 885 | u32 val; |
1da177e4 | 886 | |
c82f63e4 AD |
887 | if (!dev->state_saved) |
888 | return 0; | |
4b77b0a2 | 889 | |
b56a5a23 MT |
890 | /* PCI Express register must be restored first */ |
891 | pci_restore_pcie_state(dev); | |
892 | ||
8b8c8d28 YL |
893 | /* |
894 | * The Base Address register should be programmed before the command | |
895 | * register(s) | |
896 | */ | |
897 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
898 | pci_read_config_dword(dev, i * 4, &val); |
899 | if (val != dev->saved_config_space[i]) { | |
80ccba11 BH |
900 | dev_printk(KERN_DEBUG, &dev->dev, "restoring config " |
901 | "space at offset %#x (was %#x, writing %#x)\n", | |
902 | i, val, (int)dev->saved_config_space[i]); | |
04d9c1a1 DJ |
903 | pci_write_config_dword(dev,i * 4, |
904 | dev->saved_config_space[i]); | |
905 | } | |
906 | } | |
cc692a5f | 907 | pci_restore_pcix_state(dev); |
41017f0c | 908 | pci_restore_msi_state(dev); |
8c5cdb6a | 909 | pci_restore_iov_state(dev); |
8fed4b65 | 910 | |
4b77b0a2 RW |
911 | dev->state_saved = false; |
912 | ||
1da177e4 LT |
913 | return 0; |
914 | } | |
915 | ||
38cc1302 HS |
916 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
917 | { | |
918 | int err; | |
919 | ||
920 | err = pci_set_power_state(dev, PCI_D0); | |
921 | if (err < 0 && err != -EIO) | |
922 | return err; | |
923 | err = pcibios_enable_device(dev, bars); | |
924 | if (err < 0) | |
925 | return err; | |
926 | pci_fixup_device(pci_fixup_enable, dev); | |
927 | ||
928 | return 0; | |
929 | } | |
930 | ||
931 | /** | |
0b62e13b | 932 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
933 | * @dev: PCI device to be resumed |
934 | * | |
935 | * Note this function is a backend of pci_default_resume and is not supposed | |
936 | * to be called by normal code, write proper resume handler and use it instead. | |
937 | */ | |
0b62e13b | 938 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 939 | { |
296ccb08 | 940 | if (pci_is_enabled(dev)) |
38cc1302 HS |
941 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
942 | return 0; | |
943 | } | |
944 | ||
b718989d BH |
945 | static int __pci_enable_device_flags(struct pci_dev *dev, |
946 | resource_size_t flags) | |
1da177e4 LT |
947 | { |
948 | int err; | |
b718989d | 949 | int i, bars = 0; |
1da177e4 | 950 | |
9fb625c3 HS |
951 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
952 | return 0; /* already enabled */ | |
953 | ||
b718989d BH |
954 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
955 | if (dev->resource[i].flags & flags) | |
956 | bars |= (1 << i); | |
957 | ||
38cc1302 | 958 | err = do_pci_enable_device(dev, bars); |
95a62965 | 959 | if (err < 0) |
38cc1302 | 960 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 961 | return err; |
1da177e4 LT |
962 | } |
963 | ||
b718989d BH |
964 | /** |
965 | * pci_enable_device_io - Initialize a device for use with IO space | |
966 | * @dev: PCI device to be initialized | |
967 | * | |
968 | * Initialize device before it's used by a driver. Ask low-level code | |
969 | * to enable I/O resources. Wake up the device if it was suspended. | |
970 | * Beware, this function can fail. | |
971 | */ | |
972 | int pci_enable_device_io(struct pci_dev *dev) | |
973 | { | |
974 | return __pci_enable_device_flags(dev, IORESOURCE_IO); | |
975 | } | |
976 | ||
977 | /** | |
978 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
979 | * @dev: PCI device to be initialized | |
980 | * | |
981 | * Initialize device before it's used by a driver. Ask low-level code | |
982 | * to enable Memory resources. Wake up the device if it was suspended. | |
983 | * Beware, this function can fail. | |
984 | */ | |
985 | int pci_enable_device_mem(struct pci_dev *dev) | |
986 | { | |
987 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); | |
988 | } | |
989 | ||
bae94d02 IPG |
990 | /** |
991 | * pci_enable_device - Initialize device before it's used by a driver. | |
992 | * @dev: PCI device to be initialized | |
993 | * | |
994 | * Initialize device before it's used by a driver. Ask low-level code | |
995 | * to enable I/O and memory. Wake up the device if it was suspended. | |
996 | * Beware, this function can fail. | |
997 | * | |
998 | * Note we don't actually enable the device many times if we call | |
999 | * this function repeatedly (we just increment the count). | |
1000 | */ | |
1001 | int pci_enable_device(struct pci_dev *dev) | |
1002 | { | |
b718989d | 1003 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
1004 | } |
1005 | ||
9ac7849e TH |
1006 | /* |
1007 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1008 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1009 | * there's no need to track it separately. pci_devres is initialized | |
1010 | * when a device is enabled using managed PCI device enable interface. | |
1011 | */ | |
1012 | struct pci_devres { | |
7f375f32 TH |
1013 | unsigned int enabled:1; |
1014 | unsigned int pinned:1; | |
9ac7849e TH |
1015 | unsigned int orig_intx:1; |
1016 | unsigned int restore_intx:1; | |
1017 | u32 region_mask; | |
1018 | }; | |
1019 | ||
1020 | static void pcim_release(struct device *gendev, void *res) | |
1021 | { | |
1022 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
1023 | struct pci_devres *this = res; | |
1024 | int i; | |
1025 | ||
1026 | if (dev->msi_enabled) | |
1027 | pci_disable_msi(dev); | |
1028 | if (dev->msix_enabled) | |
1029 | pci_disable_msix(dev); | |
1030 | ||
1031 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1032 | if (this->region_mask & (1 << i)) | |
1033 | pci_release_region(dev, i); | |
1034 | ||
1035 | if (this->restore_intx) | |
1036 | pci_intx(dev, this->orig_intx); | |
1037 | ||
7f375f32 | 1038 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1039 | pci_disable_device(dev); |
1040 | } | |
1041 | ||
1042 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
1043 | { | |
1044 | struct pci_devres *dr, *new_dr; | |
1045 | ||
1046 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1047 | if (dr) | |
1048 | return dr; | |
1049 | ||
1050 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1051 | if (!new_dr) | |
1052 | return NULL; | |
1053 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1054 | } | |
1055 | ||
1056 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
1057 | { | |
1058 | if (pci_is_managed(pdev)) | |
1059 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1060 | return NULL; | |
1061 | } | |
1062 | ||
1063 | /** | |
1064 | * pcim_enable_device - Managed pci_enable_device() | |
1065 | * @pdev: PCI device to be initialized | |
1066 | * | |
1067 | * Managed pci_enable_device(). | |
1068 | */ | |
1069 | int pcim_enable_device(struct pci_dev *pdev) | |
1070 | { | |
1071 | struct pci_devres *dr; | |
1072 | int rc; | |
1073 | ||
1074 | dr = get_pci_dr(pdev); | |
1075 | if (unlikely(!dr)) | |
1076 | return -ENOMEM; | |
b95d58ea TH |
1077 | if (dr->enabled) |
1078 | return 0; | |
9ac7849e TH |
1079 | |
1080 | rc = pci_enable_device(pdev); | |
1081 | if (!rc) { | |
1082 | pdev->is_managed = 1; | |
7f375f32 | 1083 | dr->enabled = 1; |
9ac7849e TH |
1084 | } |
1085 | return rc; | |
1086 | } | |
1087 | ||
1088 | /** | |
1089 | * pcim_pin_device - Pin managed PCI device | |
1090 | * @pdev: PCI device to pin | |
1091 | * | |
1092 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1093 | * driver detach. @pdev must have been enabled with | |
1094 | * pcim_enable_device(). | |
1095 | */ | |
1096 | void pcim_pin_device(struct pci_dev *pdev) | |
1097 | { | |
1098 | struct pci_devres *dr; | |
1099 | ||
1100 | dr = find_pci_dr(pdev); | |
7f375f32 | 1101 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1102 | if (dr) |
7f375f32 | 1103 | dr->pinned = 1; |
9ac7849e TH |
1104 | } |
1105 | ||
1da177e4 LT |
1106 | /** |
1107 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1108 | * @dev: the PCI device to disable | |
1109 | * | |
1110 | * Disables architecture specific PCI resources for the device. This | |
1111 | * is the default implementation. Architecture implementations can | |
1112 | * override this. | |
1113 | */ | |
1114 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
1115 | ||
fa58d305 RW |
1116 | static void do_pci_disable_device(struct pci_dev *dev) |
1117 | { | |
1118 | u16 pci_command; | |
1119 | ||
1120 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1121 | if (pci_command & PCI_COMMAND_MASTER) { | |
1122 | pci_command &= ~PCI_COMMAND_MASTER; | |
1123 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1124 | } | |
1125 | ||
1126 | pcibios_disable_device(dev); | |
1127 | } | |
1128 | ||
1129 | /** | |
1130 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1131 | * @dev: PCI device to disable | |
1132 | * | |
1133 | * NOTE: This function is a backend of PCI power management routines and is | |
1134 | * not supposed to be called drivers. | |
1135 | */ | |
1136 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1137 | { | |
296ccb08 | 1138 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1139 | do_pci_disable_device(dev); |
1140 | } | |
1141 | ||
1da177e4 LT |
1142 | /** |
1143 | * pci_disable_device - Disable PCI device after use | |
1144 | * @dev: PCI device to be disabled | |
1145 | * | |
1146 | * Signal to the system that the PCI device is not in use by the system | |
1147 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1148 | * |
1149 | * Note we don't actually disable the device until all callers of | |
1150 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
1151 | */ |
1152 | void | |
1153 | pci_disable_device(struct pci_dev *dev) | |
1154 | { | |
9ac7849e | 1155 | struct pci_devres *dr; |
99dc804d | 1156 | |
9ac7849e TH |
1157 | dr = find_pci_dr(dev); |
1158 | if (dr) | |
7f375f32 | 1159 | dr->enabled = 0; |
9ac7849e | 1160 | |
bae94d02 IPG |
1161 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
1162 | return; | |
1163 | ||
fa58d305 | 1164 | do_pci_disable_device(dev); |
1da177e4 | 1165 | |
fa58d305 | 1166 | dev->is_busmaster = 0; |
1da177e4 LT |
1167 | } |
1168 | ||
f7bdd12d BK |
1169 | /** |
1170 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1171 | * @dev: the PCIe device reset |
f7bdd12d BK |
1172 | * @state: Reset state to enter into |
1173 | * | |
1174 | * | |
45e829ea | 1175 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1176 | * implementation. Architecture implementations can override this. |
1177 | */ | |
1178 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1179 | enum pcie_reset_state state) | |
1180 | { | |
1181 | return -EINVAL; | |
1182 | } | |
1183 | ||
1184 | /** | |
1185 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1186 | * @dev: the PCIe device reset |
f7bdd12d BK |
1187 | * @state: Reset state to enter into |
1188 | * | |
1189 | * | |
1190 | * Sets the PCI reset state for the device. | |
1191 | */ | |
1192 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1193 | { | |
1194 | return pcibios_set_pcie_reset_state(dev, state); | |
1195 | } | |
1196 | ||
58ff4633 RW |
1197 | /** |
1198 | * pci_check_pme_status - Check if given device has generated PME. | |
1199 | * @dev: Device to check. | |
1200 | * | |
1201 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1202 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1203 | * 'false' otherwise. | |
1204 | */ | |
1205 | bool pci_check_pme_status(struct pci_dev *dev) | |
1206 | { | |
1207 | int pmcsr_pos; | |
1208 | u16 pmcsr; | |
1209 | bool ret = false; | |
1210 | ||
1211 | if (!dev->pm_cap) | |
1212 | return false; | |
1213 | ||
1214 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1215 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1216 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1217 | return false; | |
1218 | ||
1219 | /* Clear PME status. */ | |
1220 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1221 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1222 | /* Disable PME to avoid interrupt flood. */ | |
1223 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1224 | ret = true; | |
1225 | } | |
1226 | ||
1227 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1228 | ||
1229 | return ret; | |
1230 | } | |
1231 | ||
eb9d0fe4 RW |
1232 | /** |
1233 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1234 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1235 | * @state: PCI state from which device will issue PME#. |
1236 | */ | |
e5899e1b | 1237 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1238 | { |
337001b6 | 1239 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1240 | return false; |
1241 | ||
337001b6 | 1242 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 RW |
1243 | } |
1244 | ||
1245 | /** | |
1246 | * pci_pme_active - enable or disable PCI device's PME# function | |
1247 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1248 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1249 | * | |
1250 | * The caller must verify that the device is capable of generating PME# before | |
1251 | * calling this function with @enable equal to 'true'. | |
1252 | */ | |
5a6c9b60 | 1253 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1254 | { |
1255 | u16 pmcsr; | |
1256 | ||
337001b6 | 1257 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1258 | return; |
1259 | ||
337001b6 | 1260 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1261 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1262 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1263 | if (!enable) | |
1264 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1265 | ||
337001b6 | 1266 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 | 1267 | |
10c3d71d | 1268 | dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n", |
eb9d0fe4 RW |
1269 | enable ? "enabled" : "disabled"); |
1270 | } | |
1271 | ||
1da177e4 | 1272 | /** |
075c1771 DB |
1273 | * pci_enable_wake - enable PCI device as wakeup event source |
1274 | * @dev: PCI device affected | |
1275 | * @state: PCI state from which device will issue wakeup events | |
1276 | * @enable: True to enable event generation; false to disable | |
1277 | * | |
1278 | * This enables the device as a wakeup event source, or disables it. | |
1279 | * When such events involves platform-specific hooks, those hooks are | |
1280 | * called automatically by this routine. | |
1281 | * | |
1282 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1283 | * always require such platform hooks. |
075c1771 | 1284 | * |
eb9d0fe4 RW |
1285 | * RETURN VALUE: |
1286 | * 0 is returned on success | |
1287 | * -EINVAL is returned if device is not supposed to wake up the system | |
1288 | * Error code depending on the platform is returned if both the platform and | |
1289 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 1290 | */ |
7d9a73f6 | 1291 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) |
1da177e4 | 1292 | { |
5bcc2fb4 | 1293 | int ret = 0; |
075c1771 | 1294 | |
bebd590c | 1295 | if (enable && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1296 | return -EINVAL; |
1da177e4 | 1297 | |
e80bb09d RW |
1298 | /* Don't do the same thing twice in a row for one device. */ |
1299 | if (!!enable == !!dev->wakeup_prepared) | |
1300 | return 0; | |
1301 | ||
eb9d0fe4 RW |
1302 | /* |
1303 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1304 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1305 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1306 | */ |
1da177e4 | 1307 | |
5bcc2fb4 RW |
1308 | if (enable) { |
1309 | int error; | |
1da177e4 | 1310 | |
5bcc2fb4 RW |
1311 | if (pci_pme_capable(dev, state)) |
1312 | pci_pme_active(dev, true); | |
1313 | else | |
1314 | ret = 1; | |
eb9d0fe4 | 1315 | error = platform_pci_sleep_wake(dev, true); |
5bcc2fb4 RW |
1316 | if (ret) |
1317 | ret = error; | |
e80bb09d RW |
1318 | if (!ret) |
1319 | dev->wakeup_prepared = true; | |
5bcc2fb4 RW |
1320 | } else { |
1321 | platform_pci_sleep_wake(dev, false); | |
1322 | pci_pme_active(dev, false); | |
e80bb09d | 1323 | dev->wakeup_prepared = false; |
5bcc2fb4 | 1324 | } |
1da177e4 | 1325 | |
5bcc2fb4 | 1326 | return ret; |
eb9d0fe4 | 1327 | } |
1da177e4 | 1328 | |
0235c4fc RW |
1329 | /** |
1330 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1331 | * @dev: PCI device to prepare | |
1332 | * @enable: True to enable wake-up event generation; false to disable | |
1333 | * | |
1334 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1335 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1336 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1337 | * ordering constraints. | |
1338 | * | |
1339 | * This function only returns error code if the device is not capable of | |
1340 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1341 | * enable wake-up power for it. | |
1342 | */ | |
1343 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1344 | { | |
1345 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1346 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1347 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1348 | } | |
1349 | ||
404cc2d8 | 1350 | /** |
37139074 JB |
1351 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1352 | * @dev: PCI device | |
1353 | * | |
1354 | * Use underlying platform code to find a supported low power state for @dev. | |
1355 | * If the platform can't manage @dev, return the deepest state from which it | |
1356 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1357 | */ |
e5899e1b | 1358 | pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1359 | { |
1360 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1361 | |
1362 | if (platform_pci_power_manageable(dev)) { | |
1363 | /* | |
1364 | * Call the platform to choose the target state of the device | |
1365 | * and enable wake-up from this state if supported. | |
1366 | */ | |
1367 | pci_power_t state = platform_pci_choose_state(dev); | |
1368 | ||
1369 | switch (state) { | |
1370 | case PCI_POWER_ERROR: | |
1371 | case PCI_UNKNOWN: | |
1372 | break; | |
1373 | case PCI_D1: | |
1374 | case PCI_D2: | |
1375 | if (pci_no_d1d2(dev)) | |
1376 | break; | |
1377 | default: | |
1378 | target_state = state; | |
404cc2d8 | 1379 | } |
d2abdf62 RW |
1380 | } else if (!dev->pm_cap) { |
1381 | target_state = PCI_D0; | |
404cc2d8 RW |
1382 | } else if (device_may_wakeup(&dev->dev)) { |
1383 | /* | |
1384 | * Find the deepest state from which the device can generate | |
1385 | * wake-up events, make it the target state and enable device | |
1386 | * to generate PME#. | |
1387 | */ | |
337001b6 RW |
1388 | if (dev->pme_support) { |
1389 | while (target_state | |
1390 | && !(dev->pme_support & (1 << target_state))) | |
1391 | target_state--; | |
404cc2d8 RW |
1392 | } |
1393 | } | |
1394 | ||
e5899e1b RW |
1395 | return target_state; |
1396 | } | |
1397 | ||
1398 | /** | |
1399 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1400 | * @dev: Device to handle. | |
1401 | * | |
1402 | * Choose the power state appropriate for the device depending on whether | |
1403 | * it can wake up the system and/or is power manageable by the platform | |
1404 | * (PCI_D3hot is the default) and put the device into that state. | |
1405 | */ | |
1406 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1407 | { | |
1408 | pci_power_t target_state = pci_target_state(dev); | |
1409 | int error; | |
1410 | ||
1411 | if (target_state == PCI_POWER_ERROR) | |
1412 | return -EIO; | |
1413 | ||
8efb8c76 | 1414 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
c157dfa3 | 1415 | |
404cc2d8 RW |
1416 | error = pci_set_power_state(dev, target_state); |
1417 | ||
1418 | if (error) | |
1419 | pci_enable_wake(dev, target_state, false); | |
1420 | ||
1421 | return error; | |
1422 | } | |
1423 | ||
1424 | /** | |
443bd1c4 | 1425 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1426 | * @dev: Device to handle. |
1427 | * | |
1428 | * Disable device's sytem wake-up capability and put it into D0. | |
1429 | */ | |
1430 | int pci_back_from_sleep(struct pci_dev *dev) | |
1431 | { | |
1432 | pci_enable_wake(dev, PCI_D0, false); | |
1433 | return pci_set_power_state(dev, PCI_D0); | |
1434 | } | |
1435 | ||
eb9d0fe4 RW |
1436 | /** |
1437 | * pci_pm_init - Initialize PM functions of given PCI device | |
1438 | * @dev: PCI device to handle. | |
1439 | */ | |
1440 | void pci_pm_init(struct pci_dev *dev) | |
1441 | { | |
1442 | int pm; | |
1443 | u16 pmc; | |
1da177e4 | 1444 | |
e80bb09d | 1445 | dev->wakeup_prepared = false; |
337001b6 RW |
1446 | dev->pm_cap = 0; |
1447 | ||
eb9d0fe4 RW |
1448 | /* find PCI PM capability in list */ |
1449 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1450 | if (!pm) | |
50246dd4 | 1451 | return; |
eb9d0fe4 RW |
1452 | /* Check device's ability to generate PME# */ |
1453 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 1454 | |
eb9d0fe4 RW |
1455 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1456 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
1457 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 1458 | return; |
eb9d0fe4 RW |
1459 | } |
1460 | ||
337001b6 | 1461 | dev->pm_cap = pm; |
1ae861e6 | 1462 | dev->d3_delay = PCI_PM_D3_WAIT; |
337001b6 RW |
1463 | |
1464 | dev->d1_support = false; | |
1465 | dev->d2_support = false; | |
1466 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 1467 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 1468 | dev->d1_support = true; |
c9ed77ee | 1469 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 1470 | dev->d2_support = true; |
c9ed77ee BH |
1471 | |
1472 | if (dev->d1_support || dev->d2_support) | |
1473 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
1474 | dev->d1_support ? " D1" : "", |
1475 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
1476 | } |
1477 | ||
1478 | pmc &= PCI_PM_CAP_PME_MASK; | |
1479 | if (pmc) { | |
10c3d71d BH |
1480 | dev_printk(KERN_DEBUG, &dev->dev, |
1481 | "PME# supported from%s%s%s%s%s\n", | |
c9ed77ee BH |
1482 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
1483 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
1484 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
1485 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
1486 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 1487 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
eb9d0fe4 RW |
1488 | /* |
1489 | * Make device's PM flags reflect the wake-up capability, but | |
1490 | * let the user space enable it to wake up the system as needed. | |
1491 | */ | |
1492 | device_set_wakeup_capable(&dev->dev, true); | |
1493 | device_set_wakeup_enable(&dev->dev, false); | |
1494 | /* Disable the PME# generation functionality */ | |
337001b6 RW |
1495 | pci_pme_active(dev, false); |
1496 | } else { | |
1497 | dev->pme_support = 0; | |
eb9d0fe4 | 1498 | } |
1da177e4 LT |
1499 | } |
1500 | ||
eb9c39d0 JB |
1501 | /** |
1502 | * platform_pci_wakeup_init - init platform wakeup if present | |
1503 | * @dev: PCI device | |
1504 | * | |
1505 | * Some devices don't have PCI PM caps but can still generate wakeup | |
1506 | * events through platform methods (like ACPI events). If @dev supports | |
1507 | * platform wakeup events, set the device flag to indicate as much. This | |
1508 | * may be redundant if the device also supports PCI PM caps, but double | |
1509 | * initialization should be safe in that case. | |
1510 | */ | |
1511 | void platform_pci_wakeup_init(struct pci_dev *dev) | |
1512 | { | |
1513 | if (!platform_pci_can_wakeup(dev)) | |
1514 | return; | |
1515 | ||
1516 | device_set_wakeup_capable(&dev->dev, true); | |
1517 | device_set_wakeup_enable(&dev->dev, false); | |
1518 | platform_pci_sleep_wake(dev, false); | |
1519 | } | |
1520 | ||
63f4898a RW |
1521 | /** |
1522 | * pci_add_save_buffer - allocate buffer for saving given capability registers | |
1523 | * @dev: the PCI device | |
1524 | * @cap: the capability to allocate the buffer for | |
1525 | * @size: requested size of the buffer | |
1526 | */ | |
1527 | static int pci_add_cap_save_buffer( | |
1528 | struct pci_dev *dev, char cap, unsigned int size) | |
1529 | { | |
1530 | int pos; | |
1531 | struct pci_cap_saved_state *save_state; | |
1532 | ||
1533 | pos = pci_find_capability(dev, cap); | |
1534 | if (pos <= 0) | |
1535 | return 0; | |
1536 | ||
1537 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
1538 | if (!save_state) | |
1539 | return -ENOMEM; | |
1540 | ||
1541 | save_state->cap_nr = cap; | |
1542 | pci_add_saved_cap(dev, save_state); | |
1543 | ||
1544 | return 0; | |
1545 | } | |
1546 | ||
1547 | /** | |
1548 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
1549 | * @dev: the PCI device | |
1550 | */ | |
1551 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
1552 | { | |
1553 | int error; | |
1554 | ||
89858517 YZ |
1555 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
1556 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a RW |
1557 | if (error) |
1558 | dev_err(&dev->dev, | |
1559 | "unable to preallocate PCI Express save buffer\n"); | |
1560 | ||
1561 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
1562 | if (error) | |
1563 | dev_err(&dev->dev, | |
1564 | "unable to preallocate PCI-X save buffer\n"); | |
1565 | } | |
1566 | ||
58c3a727 YZ |
1567 | /** |
1568 | * pci_enable_ari - enable ARI forwarding if hardware support it | |
1569 | * @dev: the PCI device | |
1570 | */ | |
1571 | void pci_enable_ari(struct pci_dev *dev) | |
1572 | { | |
1573 | int pos; | |
1574 | u32 cap; | |
1575 | u16 ctrl; | |
8113587c | 1576 | struct pci_dev *bridge; |
58c3a727 | 1577 | |
5f4d91a1 | 1578 | if (!pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
1579 | return; |
1580 | ||
8113587c ZY |
1581 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); |
1582 | if (!pos) | |
58c3a727 YZ |
1583 | return; |
1584 | ||
8113587c | 1585 | bridge = dev->bus->self; |
5f4d91a1 | 1586 | if (!bridge || !pci_is_pcie(bridge)) |
8113587c ZY |
1587 | return; |
1588 | ||
06a1cbaf | 1589 | pos = pci_pcie_cap(bridge); |
58c3a727 YZ |
1590 | if (!pos) |
1591 | return; | |
1592 | ||
8113587c | 1593 | pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
1594 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
1595 | return; | |
1596 | ||
8113587c | 1597 | pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); |
58c3a727 | 1598 | ctrl |= PCI_EXP_DEVCTL2_ARI; |
8113587c | 1599 | pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl); |
58c3a727 | 1600 | |
8113587c | 1601 | bridge->ari_enabled = 1; |
58c3a727 YZ |
1602 | } |
1603 | ||
5d990b62 CW |
1604 | static int pci_acs_enable; |
1605 | ||
1606 | /** | |
1607 | * pci_request_acs - ask for ACS to be enabled if supported | |
1608 | */ | |
1609 | void pci_request_acs(void) | |
1610 | { | |
1611 | pci_acs_enable = 1; | |
1612 | } | |
1613 | ||
ae21ee65 AK |
1614 | /** |
1615 | * pci_enable_acs - enable ACS if hardware support it | |
1616 | * @dev: the PCI device | |
1617 | */ | |
1618 | void pci_enable_acs(struct pci_dev *dev) | |
1619 | { | |
1620 | int pos; | |
1621 | u16 cap; | |
1622 | u16 ctrl; | |
1623 | ||
5d990b62 CW |
1624 | if (!pci_acs_enable) |
1625 | return; | |
1626 | ||
5f4d91a1 | 1627 | if (!pci_is_pcie(dev)) |
ae21ee65 AK |
1628 | return; |
1629 | ||
1630 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); | |
1631 | if (!pos) | |
1632 | return; | |
1633 | ||
1634 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
1635 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
1636 | ||
1637 | /* Source Validation */ | |
1638 | ctrl |= (cap & PCI_ACS_SV); | |
1639 | ||
1640 | /* P2P Request Redirect */ | |
1641 | ctrl |= (cap & PCI_ACS_RR); | |
1642 | ||
1643 | /* P2P Completion Redirect */ | |
1644 | ctrl |= (cap & PCI_ACS_CR); | |
1645 | ||
1646 | /* Upstream Forwarding */ | |
1647 | ctrl |= (cap & PCI_ACS_UF); | |
1648 | ||
1649 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
1650 | } | |
1651 | ||
57c2cf71 BH |
1652 | /** |
1653 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
1654 | * @dev: the PCI device | |
1655 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
1656 | * | |
1657 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
1658 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
1659 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
1660 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
1661 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 BH |
1662 | */ |
1663 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin) | |
1664 | { | |
46b952a3 MW |
1665 | int slot; |
1666 | ||
1667 | if (pci_ari_enabled(dev->bus)) | |
1668 | slot = 0; | |
1669 | else | |
1670 | slot = PCI_SLOT(dev->devfn); | |
1671 | ||
1672 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
1673 | } |
1674 | ||
1da177e4 LT |
1675 | int |
1676 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1677 | { | |
1678 | u8 pin; | |
1679 | ||
514d207d | 1680 | pin = dev->pin; |
1da177e4 LT |
1681 | if (!pin) |
1682 | return -1; | |
878f2e50 | 1683 | |
8784fd4d | 1684 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 1685 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
1686 | dev = dev->bus->self; |
1687 | } | |
1688 | *bridge = dev; | |
1689 | return pin; | |
1690 | } | |
1691 | ||
68feac87 BH |
1692 | /** |
1693 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
1694 | * @dev: the PCI device | |
1695 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
1696 | * | |
1697 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
1698 | * bridges all the way up to a PCI root bus. | |
1699 | */ | |
1700 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
1701 | { | |
1702 | u8 pin = *pinp; | |
1703 | ||
1eb39487 | 1704 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
1705 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1706 | dev = dev->bus->self; | |
1707 | } | |
1708 | *pinp = pin; | |
1709 | return PCI_SLOT(dev->devfn); | |
1710 | } | |
1711 | ||
1da177e4 LT |
1712 | /** |
1713 | * pci_release_region - Release a PCI bar | |
1714 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1715 | * @bar: BAR to release | |
1716 | * | |
1717 | * Releases the PCI I/O and memory resources previously reserved by a | |
1718 | * successful call to pci_request_region. Call this function only | |
1719 | * after all use of the PCI regions has ceased. | |
1720 | */ | |
1721 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1722 | { | |
9ac7849e TH |
1723 | struct pci_devres *dr; |
1724 | ||
1da177e4 LT |
1725 | if (pci_resource_len(pdev, bar) == 0) |
1726 | return; | |
1727 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1728 | release_region(pci_resource_start(pdev, bar), | |
1729 | pci_resource_len(pdev, bar)); | |
1730 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1731 | release_mem_region(pci_resource_start(pdev, bar), | |
1732 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1733 | |
1734 | dr = find_pci_dr(pdev); | |
1735 | if (dr) | |
1736 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1737 | } |
1738 | ||
1739 | /** | |
f5ddcac4 | 1740 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
1741 | * @pdev: PCI device whose resources are to be reserved |
1742 | * @bar: BAR to be reserved | |
1743 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 1744 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
1745 | * |
1746 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1747 | * being reserved by owner @res_name. Do not access any | |
1748 | * address inside the PCI regions unless this call returns | |
1749 | * successfully. | |
1750 | * | |
f5ddcac4 RD |
1751 | * If @exclusive is set, then the region is marked so that userspace |
1752 | * is explicitly not allowed to map the resource via /dev/mem or | |
1753 | * sysfs MMIO access. | |
1754 | * | |
1da177e4 LT |
1755 | * Returns 0 on success, or %EBUSY on error. A warning |
1756 | * message is also printed on failure. | |
1757 | */ | |
e8de1481 AV |
1758 | static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, |
1759 | int exclusive) | |
1da177e4 | 1760 | { |
9ac7849e TH |
1761 | struct pci_devres *dr; |
1762 | ||
1da177e4 LT |
1763 | if (pci_resource_len(pdev, bar) == 0) |
1764 | return 0; | |
1765 | ||
1766 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1767 | if (!request_region(pci_resource_start(pdev, bar), | |
1768 | pci_resource_len(pdev, bar), res_name)) | |
1769 | goto err_out; | |
1770 | } | |
1771 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
e8de1481 AV |
1772 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
1773 | pci_resource_len(pdev, bar), res_name, | |
1774 | exclusive)) | |
1da177e4 LT |
1775 | goto err_out; |
1776 | } | |
9ac7849e TH |
1777 | |
1778 | dr = find_pci_dr(pdev); | |
1779 | if (dr) | |
1780 | dr->region_mask |= 1 << bar; | |
1781 | ||
1da177e4 LT |
1782 | return 0; |
1783 | ||
1784 | err_out: | |
c7dabef8 | 1785 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 1786 | &pdev->resource[bar]); |
1da177e4 LT |
1787 | return -EBUSY; |
1788 | } | |
1789 | ||
e8de1481 | 1790 | /** |
f5ddcac4 | 1791 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
1792 | * @pdev: PCI device whose resources are to be reserved |
1793 | * @bar: BAR to be reserved | |
f5ddcac4 | 1794 | * @res_name: Name to be associated with resource |
e8de1481 | 1795 | * |
f5ddcac4 | 1796 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
1797 | * being reserved by owner @res_name. Do not access any |
1798 | * address inside the PCI regions unless this call returns | |
1799 | * successfully. | |
1800 | * | |
1801 | * Returns 0 on success, or %EBUSY on error. A warning | |
1802 | * message is also printed on failure. | |
1803 | */ | |
1804 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
1805 | { | |
1806 | return __pci_request_region(pdev, bar, res_name, 0); | |
1807 | } | |
1808 | ||
1809 | /** | |
1810 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
1811 | * @pdev: PCI device whose resources are to be reserved | |
1812 | * @bar: BAR to be reserved | |
1813 | * @res_name: Name to be associated with resource. | |
1814 | * | |
1815 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1816 | * being reserved by owner @res_name. Do not access any | |
1817 | * address inside the PCI regions unless this call returns | |
1818 | * successfully. | |
1819 | * | |
1820 | * Returns 0 on success, or %EBUSY on error. A warning | |
1821 | * message is also printed on failure. | |
1822 | * | |
1823 | * The key difference that _exclusive makes it that userspace is | |
1824 | * explicitly not allowed to map the resource via /dev/mem or | |
1825 | * sysfs. | |
1826 | */ | |
1827 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) | |
1828 | { | |
1829 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
1830 | } | |
c87deff7 HS |
1831 | /** |
1832 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1833 | * @pdev: PCI device whose resources were previously reserved | |
1834 | * @bars: Bitmask of BARs to be released | |
1835 | * | |
1836 | * Release selected PCI I/O and memory resources previously reserved. | |
1837 | * Call this function only after all use of the PCI regions has ceased. | |
1838 | */ | |
1839 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1840 | { | |
1841 | int i; | |
1842 | ||
1843 | for (i = 0; i < 6; i++) | |
1844 | if (bars & (1 << i)) | |
1845 | pci_release_region(pdev, i); | |
1846 | } | |
1847 | ||
e8de1481 AV |
1848 | int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
1849 | const char *res_name, int excl) | |
c87deff7 HS |
1850 | { |
1851 | int i; | |
1852 | ||
1853 | for (i = 0; i < 6; i++) | |
1854 | if (bars & (1 << i)) | |
e8de1481 | 1855 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
1856 | goto err_out; |
1857 | return 0; | |
1858 | ||
1859 | err_out: | |
1860 | while(--i >= 0) | |
1861 | if (bars & (1 << i)) | |
1862 | pci_release_region(pdev, i); | |
1863 | ||
1864 | return -EBUSY; | |
1865 | } | |
1da177e4 | 1866 | |
e8de1481 AV |
1867 | |
1868 | /** | |
1869 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1870 | * @pdev: PCI device whose resources are to be reserved | |
1871 | * @bars: Bitmask of BARs to be requested | |
1872 | * @res_name: Name to be associated with resource | |
1873 | */ | |
1874 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1875 | const char *res_name) | |
1876 | { | |
1877 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
1878 | } | |
1879 | ||
1880 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, | |
1881 | int bars, const char *res_name) | |
1882 | { | |
1883 | return __pci_request_selected_regions(pdev, bars, res_name, | |
1884 | IORESOURCE_EXCLUSIVE); | |
1885 | } | |
1886 | ||
1da177e4 LT |
1887 | /** |
1888 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1889 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1890 | * | |
1891 | * Releases all PCI I/O and memory resources previously reserved by a | |
1892 | * successful call to pci_request_regions. Call this function only | |
1893 | * after all use of the PCI regions has ceased. | |
1894 | */ | |
1895 | ||
1896 | void pci_release_regions(struct pci_dev *pdev) | |
1897 | { | |
c87deff7 | 1898 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1899 | } |
1900 | ||
1901 | /** | |
1902 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1903 | * @pdev: PCI device whose resources are to be reserved | |
1904 | * @res_name: Name to be associated with resource. | |
1905 | * | |
1906 | * Mark all PCI regions associated with PCI device @pdev as | |
1907 | * being reserved by owner @res_name. Do not access any | |
1908 | * address inside the PCI regions unless this call returns | |
1909 | * successfully. | |
1910 | * | |
1911 | * Returns 0 on success, or %EBUSY on error. A warning | |
1912 | * message is also printed on failure. | |
1913 | */ | |
3c990e92 | 1914 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1915 | { |
c87deff7 | 1916 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1917 | } |
1918 | ||
e8de1481 AV |
1919 | /** |
1920 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
1921 | * @pdev: PCI device whose resources are to be reserved | |
1922 | * @res_name: Name to be associated with resource. | |
1923 | * | |
1924 | * Mark all PCI regions associated with PCI device @pdev as | |
1925 | * being reserved by owner @res_name. Do not access any | |
1926 | * address inside the PCI regions unless this call returns | |
1927 | * successfully. | |
1928 | * | |
1929 | * pci_request_regions_exclusive() will mark the region so that | |
1930 | * /dev/mem and the sysfs MMIO access will not be allowed. | |
1931 | * | |
1932 | * Returns 0 on success, or %EBUSY on error. A warning | |
1933 | * message is also printed on failure. | |
1934 | */ | |
1935 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
1936 | { | |
1937 | return pci_request_selected_regions_exclusive(pdev, | |
1938 | ((1 << 6) - 1), res_name); | |
1939 | } | |
1940 | ||
6a479079 BH |
1941 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
1942 | { | |
1943 | u16 old_cmd, cmd; | |
1944 | ||
1945 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
1946 | if (enable) | |
1947 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
1948 | else | |
1949 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
1950 | if (cmd != old_cmd) { | |
1951 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
1952 | enable ? "enabling" : "disabling"); | |
1953 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1954 | } | |
1955 | dev->is_busmaster = enable; | |
1956 | } | |
e8de1481 | 1957 | |
1da177e4 LT |
1958 | /** |
1959 | * pci_set_master - enables bus-mastering for device dev | |
1960 | * @dev: the PCI device to enable | |
1961 | * | |
1962 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1963 | * to do the needed arch specific settings. | |
1964 | */ | |
6a479079 | 1965 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 1966 | { |
6a479079 | 1967 | __pci_set_master(dev, true); |
1da177e4 LT |
1968 | pcibios_set_master(dev); |
1969 | } | |
1970 | ||
6a479079 BH |
1971 | /** |
1972 | * pci_clear_master - disables bus-mastering for device dev | |
1973 | * @dev: the PCI device to disable | |
1974 | */ | |
1975 | void pci_clear_master(struct pci_dev *dev) | |
1976 | { | |
1977 | __pci_set_master(dev, false); | |
1978 | } | |
1979 | ||
1da177e4 | 1980 | /** |
edb2d97e MW |
1981 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1982 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1983 | * |
edb2d97e MW |
1984 | * Helper function for pci_set_mwi. |
1985 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1986 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1987 | * | |
1988 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1989 | */ | |
15ea76d4 | 1990 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1991 | { |
1992 | u8 cacheline_size; | |
1993 | ||
1994 | if (!pci_cache_line_size) | |
15ea76d4 | 1995 | return -EINVAL; |
1da177e4 LT |
1996 | |
1997 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1998 | equal to or multiple of the right value. */ | |
1999 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2000 | if (cacheline_size >= pci_cache_line_size && | |
2001 | (cacheline_size % pci_cache_line_size) == 0) | |
2002 | return 0; | |
2003 | ||
2004 | /* Write the correct value. */ | |
2005 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
2006 | /* Read it back. */ | |
2007 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2008 | if (cacheline_size == pci_cache_line_size) | |
2009 | return 0; | |
2010 | ||
80ccba11 BH |
2011 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
2012 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
2013 | |
2014 | return -EINVAL; | |
2015 | } | |
15ea76d4 TH |
2016 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
2017 | ||
2018 | #ifdef PCI_DISABLE_MWI | |
2019 | int pci_set_mwi(struct pci_dev *dev) | |
2020 | { | |
2021 | return 0; | |
2022 | } | |
2023 | ||
2024 | int pci_try_set_mwi(struct pci_dev *dev) | |
2025 | { | |
2026 | return 0; | |
2027 | } | |
2028 | ||
2029 | void pci_clear_mwi(struct pci_dev *dev) | |
2030 | { | |
2031 | } | |
2032 | ||
2033 | #else | |
1da177e4 LT |
2034 | |
2035 | /** | |
2036 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
2037 | * @dev: the PCI device for which MWI is enabled | |
2038 | * | |
694625c0 | 2039 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
2040 | * |
2041 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2042 | */ | |
2043 | int | |
2044 | pci_set_mwi(struct pci_dev *dev) | |
2045 | { | |
2046 | int rc; | |
2047 | u16 cmd; | |
2048 | ||
edb2d97e | 2049 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
2050 | if (rc) |
2051 | return rc; | |
2052 | ||
2053 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2054 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 2055 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
2056 | cmd |= PCI_COMMAND_INVALIDATE; |
2057 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2058 | } | |
2059 | ||
2060 | return 0; | |
2061 | } | |
2062 | ||
694625c0 RD |
2063 | /** |
2064 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
2065 | * @dev: the PCI device for which MWI is enabled | |
2066 | * | |
2067 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
2068 | * Callers are not required to check the return value. | |
2069 | * | |
2070 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2071 | */ | |
2072 | int pci_try_set_mwi(struct pci_dev *dev) | |
2073 | { | |
2074 | int rc = pci_set_mwi(dev); | |
2075 | return rc; | |
2076 | } | |
2077 | ||
1da177e4 LT |
2078 | /** |
2079 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
2080 | * @dev: the PCI device to disable | |
2081 | * | |
2082 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
2083 | */ | |
2084 | void | |
2085 | pci_clear_mwi(struct pci_dev *dev) | |
2086 | { | |
2087 | u16 cmd; | |
2088 | ||
2089 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2090 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
2091 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
2092 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2093 | } | |
2094 | } | |
edb2d97e | 2095 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 2096 | |
a04ce0ff BR |
2097 | /** |
2098 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
2099 | * @pdev: the PCI device to operate on |
2100 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
2101 | * |
2102 | * Enables/disables PCI INTx for device dev | |
2103 | */ | |
2104 | void | |
2105 | pci_intx(struct pci_dev *pdev, int enable) | |
2106 | { | |
2107 | u16 pci_command, new; | |
2108 | ||
2109 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
2110 | ||
2111 | if (enable) { | |
2112 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
2113 | } else { | |
2114 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
2115 | } | |
2116 | ||
2117 | if (new != pci_command) { | |
9ac7849e TH |
2118 | struct pci_devres *dr; |
2119 | ||
2fd9d74b | 2120 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
2121 | |
2122 | dr = find_pci_dr(pdev); | |
2123 | if (dr && !dr->restore_intx) { | |
2124 | dr->restore_intx = 1; | |
2125 | dr->orig_intx = !enable; | |
2126 | } | |
a04ce0ff BR |
2127 | } |
2128 | } | |
2129 | ||
f5f2b131 EB |
2130 | /** |
2131 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 2132 | * @dev: the PCI device to operate on |
f5f2b131 EB |
2133 | * |
2134 | * If you want to use msi see pci_enable_msi and friends. | |
2135 | * This is a lower level primitive that allows us to disable | |
2136 | * msi operation at the device level. | |
2137 | */ | |
2138 | void pci_msi_off(struct pci_dev *dev) | |
2139 | { | |
2140 | int pos; | |
2141 | u16 control; | |
2142 | ||
2143 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
2144 | if (pos) { | |
2145 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
2146 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
2147 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
2148 | } | |
2149 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
2150 | if (pos) { | |
2151 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
2152 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
2153 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
2154 | } | |
2155 | } | |
2156 | ||
1da177e4 LT |
2157 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
2158 | /* | |
2159 | * These can be overridden by arch-specific implementations | |
2160 | */ | |
2161 | int | |
2162 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
2163 | { | |
2164 | if (!pci_dma_supported(dev, mask)) | |
2165 | return -EIO; | |
2166 | ||
2167 | dev->dma_mask = mask; | |
c6a41576 | 2168 | dev_dbg(&dev->dev, "using %dbit DMA mask\n", fls64(mask)); |
1da177e4 LT |
2169 | |
2170 | return 0; | |
2171 | } | |
2172 | ||
1da177e4 LT |
2173 | int |
2174 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
2175 | { | |
2176 | if (!pci_dma_supported(dev, mask)) | |
2177 | return -EIO; | |
2178 | ||
2179 | dev->dev.coherent_dma_mask = mask; | |
c6a41576 | 2180 | dev_dbg(&dev->dev, "using %dbit consistent DMA mask\n", fls64(mask)); |
1da177e4 LT |
2181 | |
2182 | return 0; | |
2183 | } | |
2184 | #endif | |
c87deff7 | 2185 | |
4d57cdfa FT |
2186 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
2187 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) | |
2188 | { | |
2189 | return dma_set_max_seg_size(&dev->dev, size); | |
2190 | } | |
2191 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
2192 | #endif | |
2193 | ||
59fc67de FT |
2194 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
2195 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) | |
2196 | { | |
2197 | return dma_set_seg_boundary(&dev->dev, mask); | |
2198 | } | |
2199 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
2200 | #endif | |
2201 | ||
8c1c699f | 2202 | static int pcie_flr(struct pci_dev *dev, int probe) |
8dd7f803 | 2203 | { |
8c1c699f YZ |
2204 | int i; |
2205 | int pos; | |
8dd7f803 | 2206 | u32 cap; |
04b55c47 | 2207 | u16 status, control; |
8dd7f803 | 2208 | |
06a1cbaf | 2209 | pos = pci_pcie_cap(dev); |
8c1c699f | 2210 | if (!pos) |
8dd7f803 | 2211 | return -ENOTTY; |
8c1c699f YZ |
2212 | |
2213 | pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); | |
8dd7f803 SY |
2214 | if (!(cap & PCI_EXP_DEVCAP_FLR)) |
2215 | return -ENOTTY; | |
2216 | ||
d91cdc74 SY |
2217 | if (probe) |
2218 | return 0; | |
2219 | ||
8dd7f803 | 2220 | /* Wait for Transaction Pending bit clean */ |
8c1c699f YZ |
2221 | for (i = 0; i < 4; i++) { |
2222 | if (i) | |
2223 | msleep((1 << (i - 1)) * 100); | |
5fe5db05 | 2224 | |
8c1c699f YZ |
2225 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); |
2226 | if (!(status & PCI_EXP_DEVSTA_TRPND)) | |
2227 | goto clear; | |
2228 | } | |
2229 | ||
2230 | dev_err(&dev->dev, "transaction is not cleared; " | |
2231 | "proceeding with reset anyway\n"); | |
2232 | ||
2233 | clear: | |
04b55c47 SR |
2234 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control); |
2235 | control |= PCI_EXP_DEVCTL_BCR_FLR; | |
2236 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control); | |
2237 | ||
8c1c699f | 2238 | msleep(100); |
8dd7f803 | 2239 | |
8dd7f803 SY |
2240 | return 0; |
2241 | } | |
d91cdc74 | 2242 | |
8c1c699f | 2243 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 2244 | { |
8c1c699f YZ |
2245 | int i; |
2246 | int pos; | |
1ca88797 | 2247 | u8 cap; |
8c1c699f | 2248 | u8 status; |
1ca88797 | 2249 | |
8c1c699f YZ |
2250 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
2251 | if (!pos) | |
1ca88797 | 2252 | return -ENOTTY; |
8c1c699f YZ |
2253 | |
2254 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); | |
1ca88797 SY |
2255 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
2256 | return -ENOTTY; | |
2257 | ||
2258 | if (probe) | |
2259 | return 0; | |
2260 | ||
1ca88797 | 2261 | /* Wait for Transaction Pending bit clean */ |
8c1c699f YZ |
2262 | for (i = 0; i < 4; i++) { |
2263 | if (i) | |
2264 | msleep((1 << (i - 1)) * 100); | |
2265 | ||
2266 | pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status); | |
2267 | if (!(status & PCI_AF_STATUS_TP)) | |
2268 | goto clear; | |
2269 | } | |
5fe5db05 | 2270 | |
8c1c699f YZ |
2271 | dev_err(&dev->dev, "transaction is not cleared; " |
2272 | "proceeding with reset anyway\n"); | |
5fe5db05 | 2273 | |
8c1c699f YZ |
2274 | clear: |
2275 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); | |
1ca88797 | 2276 | msleep(100); |
8c1c699f | 2277 | |
1ca88797 SY |
2278 | return 0; |
2279 | } | |
2280 | ||
f85876ba | 2281 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 2282 | { |
f85876ba YZ |
2283 | u16 csr; |
2284 | ||
2285 | if (!dev->pm_cap) | |
2286 | return -ENOTTY; | |
d91cdc74 | 2287 | |
f85876ba YZ |
2288 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
2289 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
2290 | return -ENOTTY; | |
d91cdc74 | 2291 | |
f85876ba YZ |
2292 | if (probe) |
2293 | return 0; | |
1ca88797 | 2294 | |
f85876ba YZ |
2295 | if (dev->current_state != PCI_D0) |
2296 | return -EINVAL; | |
2297 | ||
2298 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
2299 | csr |= PCI_D3hot; | |
2300 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 2301 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
2302 | |
2303 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
2304 | csr |= PCI_D0; | |
2305 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 2306 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
2307 | |
2308 | return 0; | |
2309 | } | |
2310 | ||
c12ff1df YZ |
2311 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) |
2312 | { | |
2313 | u16 ctrl; | |
2314 | struct pci_dev *pdev; | |
2315 | ||
654b75e0 | 2316 | if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) |
c12ff1df YZ |
2317 | return -ENOTTY; |
2318 | ||
2319 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
2320 | if (pdev != dev) | |
2321 | return -ENOTTY; | |
2322 | ||
2323 | if (probe) | |
2324 | return 0; | |
2325 | ||
2326 | pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl); | |
2327 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
2328 | pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); | |
2329 | msleep(100); | |
2330 | ||
2331 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
2332 | pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); | |
2333 | msleep(100); | |
2334 | ||
2335 | return 0; | |
2336 | } | |
2337 | ||
8c1c699f | 2338 | static int pci_dev_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 2339 | { |
8c1c699f YZ |
2340 | int rc; |
2341 | ||
2342 | might_sleep(); | |
2343 | ||
2344 | if (!probe) { | |
2345 | pci_block_user_cfg_access(dev); | |
2346 | /* block PM suspend, driver probe, etc. */ | |
2347 | down(&dev->dev.sem); | |
2348 | } | |
d91cdc74 | 2349 | |
b9c3b266 DC |
2350 | rc = pci_dev_specific_reset(dev, probe); |
2351 | if (rc != -ENOTTY) | |
2352 | goto done; | |
2353 | ||
8c1c699f YZ |
2354 | rc = pcie_flr(dev, probe); |
2355 | if (rc != -ENOTTY) | |
2356 | goto done; | |
d91cdc74 | 2357 | |
8c1c699f | 2358 | rc = pci_af_flr(dev, probe); |
f85876ba YZ |
2359 | if (rc != -ENOTTY) |
2360 | goto done; | |
2361 | ||
2362 | rc = pci_pm_reset(dev, probe); | |
c12ff1df YZ |
2363 | if (rc != -ENOTTY) |
2364 | goto done; | |
2365 | ||
2366 | rc = pci_parent_bus_reset(dev, probe); | |
8c1c699f YZ |
2367 | done: |
2368 | if (!probe) { | |
2369 | up(&dev->dev.sem); | |
2370 | pci_unblock_user_cfg_access(dev); | |
2371 | } | |
1ca88797 | 2372 | |
8c1c699f | 2373 | return rc; |
d91cdc74 SY |
2374 | } |
2375 | ||
2376 | /** | |
8c1c699f YZ |
2377 | * __pci_reset_function - reset a PCI device function |
2378 | * @dev: PCI device to reset | |
d91cdc74 SY |
2379 | * |
2380 | * Some devices allow an individual function to be reset without affecting | |
2381 | * other functions in the same device. The PCI device must be responsive | |
2382 | * to PCI config space in order to use this function. | |
2383 | * | |
2384 | * The device function is presumed to be unused when this function is called. | |
2385 | * Resetting the device will make the contents of PCI configuration space | |
2386 | * random, so any caller of this must be prepared to reinitialise the | |
2387 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
2388 | * etc. | |
2389 | * | |
8c1c699f | 2390 | * Returns 0 if the device function was successfully reset or negative if the |
d91cdc74 SY |
2391 | * device doesn't support resetting a single function. |
2392 | */ | |
8c1c699f | 2393 | int __pci_reset_function(struct pci_dev *dev) |
d91cdc74 | 2394 | { |
8c1c699f | 2395 | return pci_dev_reset(dev, 0); |
d91cdc74 | 2396 | } |
8c1c699f | 2397 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
8dd7f803 | 2398 | |
711d5779 MT |
2399 | /** |
2400 | * pci_probe_reset_function - check whether the device can be safely reset | |
2401 | * @dev: PCI device to reset | |
2402 | * | |
2403 | * Some devices allow an individual function to be reset without affecting | |
2404 | * other functions in the same device. The PCI device must be responsive | |
2405 | * to PCI config space in order to use this function. | |
2406 | * | |
2407 | * Returns 0 if the device function can be reset or negative if the | |
2408 | * device doesn't support resetting a single function. | |
2409 | */ | |
2410 | int pci_probe_reset_function(struct pci_dev *dev) | |
2411 | { | |
2412 | return pci_dev_reset(dev, 1); | |
2413 | } | |
2414 | ||
8dd7f803 | 2415 | /** |
8c1c699f YZ |
2416 | * pci_reset_function - quiesce and reset a PCI device function |
2417 | * @dev: PCI device to reset | |
8dd7f803 SY |
2418 | * |
2419 | * Some devices allow an individual function to be reset without affecting | |
2420 | * other functions in the same device. The PCI device must be responsive | |
2421 | * to PCI config space in order to use this function. | |
2422 | * | |
2423 | * This function does not just reset the PCI portion of a device, but | |
2424 | * clears all the state associated with the device. This function differs | |
8c1c699f | 2425 | * from __pci_reset_function in that it saves and restores device state |
8dd7f803 SY |
2426 | * over the reset. |
2427 | * | |
8c1c699f | 2428 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
2429 | * device doesn't support resetting a single function. |
2430 | */ | |
2431 | int pci_reset_function(struct pci_dev *dev) | |
2432 | { | |
8c1c699f | 2433 | int rc; |
8dd7f803 | 2434 | |
8c1c699f YZ |
2435 | rc = pci_dev_reset(dev, 1); |
2436 | if (rc) | |
2437 | return rc; | |
8dd7f803 | 2438 | |
8dd7f803 SY |
2439 | pci_save_state(dev); |
2440 | ||
8c1c699f YZ |
2441 | /* |
2442 | * both INTx and MSI are disabled after the Interrupt Disable bit | |
2443 | * is set and the Bus Master bit is cleared. | |
2444 | */ | |
8dd7f803 SY |
2445 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); |
2446 | ||
8c1c699f | 2447 | rc = pci_dev_reset(dev, 0); |
8dd7f803 SY |
2448 | |
2449 | pci_restore_state(dev); | |
8dd7f803 | 2450 | |
8c1c699f | 2451 | return rc; |
8dd7f803 SY |
2452 | } |
2453 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
2454 | ||
d556ad4b PO |
2455 | /** |
2456 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
2457 | * @dev: PCI device to query | |
2458 | * | |
2459 | * Returns mmrbc: maximum designed memory read count in bytes | |
2460 | * or appropriate error value. | |
2461 | */ | |
2462 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
2463 | { | |
b7b095c1 | 2464 | int err, cap; |
d556ad4b PO |
2465 | u32 stat; |
2466 | ||
2467 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2468 | if (!cap) | |
2469 | return -EINVAL; | |
2470 | ||
2471 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
2472 | if (err) | |
2473 | return -EINVAL; | |
2474 | ||
b7b095c1 | 2475 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
d556ad4b PO |
2476 | } |
2477 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
2478 | ||
2479 | /** | |
2480 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
2481 | * @dev: PCI device to query | |
2482 | * | |
2483 | * Returns mmrbc: maximum memory read count in bytes | |
2484 | * or appropriate error value. | |
2485 | */ | |
2486 | int pcix_get_mmrbc(struct pci_dev *dev) | |
2487 | { | |
2488 | int ret, cap; | |
2489 | u32 cmd; | |
2490 | ||
2491 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2492 | if (!cap) | |
2493 | return -EINVAL; | |
2494 | ||
2495 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
2496 | if (!ret) | |
2497 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); | |
2498 | ||
2499 | return ret; | |
2500 | } | |
2501 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
2502 | ||
2503 | /** | |
2504 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
2505 | * @dev: PCI device to query | |
2506 | * @mmrbc: maximum memory read count in bytes | |
2507 | * valid values are 512, 1024, 2048, 4096 | |
2508 | * | |
2509 | * If possible sets maximum memory read byte count, some bridges have erratas | |
2510 | * that prevent this. | |
2511 | */ | |
2512 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
2513 | { | |
2514 | int cap, err = -EINVAL; | |
2515 | u32 stat, cmd, v, o; | |
2516 | ||
229f5afd | 2517 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
d556ad4b PO |
2518 | goto out; |
2519 | ||
2520 | v = ffs(mmrbc) - 10; | |
2521 | ||
2522 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2523 | if (!cap) | |
2524 | goto out; | |
2525 | ||
2526 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
2527 | if (err) | |
2528 | goto out; | |
2529 | ||
2530 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
2531 | return -E2BIG; | |
2532 | ||
2533 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
2534 | if (err) | |
2535 | goto out; | |
2536 | ||
2537 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
2538 | if (o != v) { | |
2539 | if (v > o && dev->bus && | |
2540 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
2541 | return -EIO; | |
2542 | ||
2543 | cmd &= ~PCI_X_CMD_MAX_READ; | |
2544 | cmd |= v << 2; | |
2545 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); | |
2546 | } | |
2547 | out: | |
2548 | return err; | |
2549 | } | |
2550 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
2551 | ||
2552 | /** | |
2553 | * pcie_get_readrq - get PCI Express read request size | |
2554 | * @dev: PCI device to query | |
2555 | * | |
2556 | * Returns maximum memory read request in bytes | |
2557 | * or appropriate error value. | |
2558 | */ | |
2559 | int pcie_get_readrq(struct pci_dev *dev) | |
2560 | { | |
2561 | int ret, cap; | |
2562 | u16 ctl; | |
2563 | ||
06a1cbaf | 2564 | cap = pci_pcie_cap(dev); |
d556ad4b PO |
2565 | if (!cap) |
2566 | return -EINVAL; | |
2567 | ||
2568 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
2569 | if (!ret) | |
2570 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
2571 | ||
2572 | return ret; | |
2573 | } | |
2574 | EXPORT_SYMBOL(pcie_get_readrq); | |
2575 | ||
2576 | /** | |
2577 | * pcie_set_readrq - set PCI Express maximum memory read request | |
2578 | * @dev: PCI device to query | |
42e61f4a | 2579 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
2580 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
2581 | * | |
2582 | * If possible sets maximum read byte count | |
2583 | */ | |
2584 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
2585 | { | |
2586 | int cap, err = -EINVAL; | |
2587 | u16 ctl, v; | |
2588 | ||
229f5afd | 2589 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
2590 | goto out; |
2591 | ||
2592 | v = (ffs(rq) - 8) << 12; | |
2593 | ||
06a1cbaf | 2594 | cap = pci_pcie_cap(dev); |
d556ad4b PO |
2595 | if (!cap) |
2596 | goto out; | |
2597 | ||
2598 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
2599 | if (err) | |
2600 | goto out; | |
2601 | ||
2602 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
2603 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
2604 | ctl |= v; | |
2605 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
2606 | } | |
2607 | ||
2608 | out: | |
2609 | return err; | |
2610 | } | |
2611 | EXPORT_SYMBOL(pcie_set_readrq); | |
2612 | ||
c87deff7 HS |
2613 | /** |
2614 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 2615 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
2616 | * @flags: resource type mask to be selected |
2617 | * | |
2618 | * This helper routine makes bar mask from the type of resource. | |
2619 | */ | |
2620 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
2621 | { | |
2622 | int i, bars = 0; | |
2623 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
2624 | if (pci_resource_flags(dev, i) & flags) | |
2625 | bars |= (1 << i); | |
2626 | return bars; | |
2627 | } | |
2628 | ||
613e7ed6 YZ |
2629 | /** |
2630 | * pci_resource_bar - get position of the BAR associated with a resource | |
2631 | * @dev: the PCI device | |
2632 | * @resno: the resource number | |
2633 | * @type: the BAR type to be filled in | |
2634 | * | |
2635 | * Returns BAR position in config space, or 0 if the BAR is invalid. | |
2636 | */ | |
2637 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) | |
2638 | { | |
d1b054da YZ |
2639 | int reg; |
2640 | ||
613e7ed6 YZ |
2641 | if (resno < PCI_ROM_RESOURCE) { |
2642 | *type = pci_bar_unknown; | |
2643 | return PCI_BASE_ADDRESS_0 + 4 * resno; | |
2644 | } else if (resno == PCI_ROM_RESOURCE) { | |
2645 | *type = pci_bar_mem32; | |
2646 | return dev->rom_base_reg; | |
d1b054da YZ |
2647 | } else if (resno < PCI_BRIDGE_RESOURCES) { |
2648 | /* device specific resource */ | |
2649 | reg = pci_iov_resource_bar(dev, resno, type); | |
2650 | if (reg) | |
2651 | return reg; | |
613e7ed6 YZ |
2652 | } |
2653 | ||
865df576 | 2654 | dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); |
613e7ed6 YZ |
2655 | return 0; |
2656 | } | |
2657 | ||
deb2d2ec BH |
2658 | /** |
2659 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
2660 | * @dev: the PCI device |
2661 | * @decode: true = enable decoding, false = disable decoding | |
2662 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
2663 | * @change_bridge: traverse ancestors and change bridges | |
deb2d2ec BH |
2664 | */ |
2665 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
2666 | unsigned int command_bits, bool change_bridge) | |
2667 | { | |
2668 | struct pci_bus *bus; | |
2669 | struct pci_dev *bridge; | |
2670 | u16 cmd; | |
2671 | ||
2672 | WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)); | |
2673 | ||
2674 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2675 | if (decode == true) | |
2676 | cmd |= command_bits; | |
2677 | else | |
2678 | cmd &= ~command_bits; | |
2679 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2680 | ||
2681 | if (change_bridge == false) | |
2682 | return 0; | |
2683 | ||
2684 | bus = dev->bus; | |
2685 | while (bus) { | |
2686 | bridge = bus->self; | |
2687 | if (bridge) { | |
2688 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
2689 | &cmd); | |
2690 | if (decode == true) | |
2691 | cmd |= PCI_BRIDGE_CTL_VGA; | |
2692 | else | |
2693 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
2694 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
2695 | cmd); | |
2696 | } | |
2697 | bus = bus->parent; | |
2698 | } | |
2699 | return 0; | |
2700 | } | |
2701 | ||
32a9a682 YS |
2702 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
2703 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 2704 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
2705 | |
2706 | /** | |
2707 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
2708 | * @dev: the PCI device to get | |
2709 | * | |
2710 | * RETURNS: Resource alignment if it is specified. | |
2711 | * Zero if it is not specified. | |
2712 | */ | |
2713 | resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) | |
2714 | { | |
2715 | int seg, bus, slot, func, align_order, count; | |
2716 | resource_size_t align = 0; | |
2717 | char *p; | |
2718 | ||
2719 | spin_lock(&resource_alignment_lock); | |
2720 | p = resource_alignment_param; | |
2721 | while (*p) { | |
2722 | count = 0; | |
2723 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
2724 | p[count] == '@') { | |
2725 | p += count + 1; | |
2726 | } else { | |
2727 | align_order = -1; | |
2728 | } | |
2729 | if (sscanf(p, "%x:%x:%x.%x%n", | |
2730 | &seg, &bus, &slot, &func, &count) != 4) { | |
2731 | seg = 0; | |
2732 | if (sscanf(p, "%x:%x.%x%n", | |
2733 | &bus, &slot, &func, &count) != 3) { | |
2734 | /* Invalid format */ | |
2735 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", | |
2736 | p); | |
2737 | break; | |
2738 | } | |
2739 | } | |
2740 | p += count; | |
2741 | if (seg == pci_domain_nr(dev->bus) && | |
2742 | bus == dev->bus->number && | |
2743 | slot == PCI_SLOT(dev->devfn) && | |
2744 | func == PCI_FUNC(dev->devfn)) { | |
2745 | if (align_order == -1) { | |
2746 | align = PAGE_SIZE; | |
2747 | } else { | |
2748 | align = 1 << align_order; | |
2749 | } | |
2750 | /* Found */ | |
2751 | break; | |
2752 | } | |
2753 | if (*p != ';' && *p != ',') { | |
2754 | /* End of param or invalid format */ | |
2755 | break; | |
2756 | } | |
2757 | p++; | |
2758 | } | |
2759 | spin_unlock(&resource_alignment_lock); | |
2760 | return align; | |
2761 | } | |
2762 | ||
2763 | /** | |
2764 | * pci_is_reassigndev - check if specified PCI is target device to reassign | |
2765 | * @dev: the PCI device to check | |
2766 | * | |
2767 | * RETURNS: non-zero for PCI device is a target device to reassign, | |
2768 | * or zero is not. | |
2769 | */ | |
2770 | int pci_is_reassigndev(struct pci_dev *dev) | |
2771 | { | |
2772 | return (pci_specified_resource_alignment(dev) != 0); | |
2773 | } | |
2774 | ||
2775 | ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) | |
2776 | { | |
2777 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
2778 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
2779 | spin_lock(&resource_alignment_lock); | |
2780 | strncpy(resource_alignment_param, buf, count); | |
2781 | resource_alignment_param[count] = '\0'; | |
2782 | spin_unlock(&resource_alignment_lock); | |
2783 | return count; | |
2784 | } | |
2785 | ||
2786 | ssize_t pci_get_resource_alignment_param(char *buf, size_t size) | |
2787 | { | |
2788 | size_t count; | |
2789 | spin_lock(&resource_alignment_lock); | |
2790 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
2791 | spin_unlock(&resource_alignment_lock); | |
2792 | return count; | |
2793 | } | |
2794 | ||
2795 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) | |
2796 | { | |
2797 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
2798 | } | |
2799 | ||
2800 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, | |
2801 | const char *buf, size_t count) | |
2802 | { | |
2803 | return pci_set_resource_alignment_param(buf, count); | |
2804 | } | |
2805 | ||
2806 | BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, | |
2807 | pci_resource_alignment_store); | |
2808 | ||
2809 | static int __init pci_resource_alignment_sysfs_init(void) | |
2810 | { | |
2811 | return bus_create_file(&pci_bus_type, | |
2812 | &bus_attr_resource_alignment); | |
2813 | } | |
2814 | ||
2815 | late_initcall(pci_resource_alignment_sysfs_init); | |
2816 | ||
32a2eea7 JG |
2817 | static void __devinit pci_no_domains(void) |
2818 | { | |
2819 | #ifdef CONFIG_PCI_DOMAINS | |
2820 | pci_domains_supported = 0; | |
2821 | #endif | |
2822 | } | |
2823 | ||
0ef5f8f6 AP |
2824 | /** |
2825 | * pci_ext_cfg_enabled - can we access extended PCI config space? | |
2826 | * @dev: The PCI device of the root bridge. | |
2827 | * | |
2828 | * Returns 1 if we can access PCI extended config space (offsets | |
2829 | * greater than 0xff). This is the default implementation. Architecture | |
2830 | * implementations can override this. | |
2831 | */ | |
2832 | int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) | |
2833 | { | |
2834 | return 1; | |
2835 | } | |
2836 | ||
2d1c8618 BH |
2837 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
2838 | { | |
2839 | } | |
2840 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
2841 | ||
ad04d31e | 2842 | static int __init pci_setup(char *str) |
1da177e4 LT |
2843 | { |
2844 | while (str) { | |
2845 | char *k = strchr(str, ','); | |
2846 | if (k) | |
2847 | *k++ = 0; | |
2848 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
2849 | if (!strcmp(str, "nomsi")) { |
2850 | pci_no_msi(); | |
7f785763 RD |
2851 | } else if (!strcmp(str, "noaer")) { |
2852 | pci_no_aer(); | |
32a2eea7 JG |
2853 | } else if (!strcmp(str, "nodomains")) { |
2854 | pci_no_domains(); | |
4516a618 AN |
2855 | } else if (!strncmp(str, "cbiosize=", 9)) { |
2856 | pci_cardbus_io_size = memparse(str + 9, &str); | |
2857 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
2858 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
2859 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
2860 | pci_set_resource_alignment_param(str + 19, | |
2861 | strlen(str + 19)); | |
43c16408 AP |
2862 | } else if (!strncmp(str, "ecrc=", 5)) { |
2863 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
2864 | } else if (!strncmp(str, "hpiosize=", 9)) { |
2865 | pci_hotplug_io_size = memparse(str + 9, &str); | |
2866 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
2867 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
309e57df MW |
2868 | } else { |
2869 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
2870 | str); | |
2871 | } | |
1da177e4 LT |
2872 | } |
2873 | str = k; | |
2874 | } | |
0637a70a | 2875 | return 0; |
1da177e4 | 2876 | } |
0637a70a | 2877 | early_param("pci", pci_setup); |
1da177e4 | 2878 | |
0b62e13b | 2879 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
2880 | EXPORT_SYMBOL(pci_enable_device_io); |
2881 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 2882 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
2883 | EXPORT_SYMBOL(pcim_enable_device); |
2884 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 2885 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
2886 | EXPORT_SYMBOL(pci_find_capability); |
2887 | EXPORT_SYMBOL(pci_bus_find_capability); | |
2888 | EXPORT_SYMBOL(pci_release_regions); | |
2889 | EXPORT_SYMBOL(pci_request_regions); | |
e8de1481 | 2890 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
1da177e4 LT |
2891 | EXPORT_SYMBOL(pci_release_region); |
2892 | EXPORT_SYMBOL(pci_request_region); | |
e8de1481 | 2893 | EXPORT_SYMBOL(pci_request_region_exclusive); |
c87deff7 HS |
2894 | EXPORT_SYMBOL(pci_release_selected_regions); |
2895 | EXPORT_SYMBOL(pci_request_selected_regions); | |
e8de1481 | 2896 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
1da177e4 | 2897 | EXPORT_SYMBOL(pci_set_master); |
6a479079 | 2898 | EXPORT_SYMBOL(pci_clear_master); |
1da177e4 | 2899 | EXPORT_SYMBOL(pci_set_mwi); |
694625c0 | 2900 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 2901 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 2902 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 2903 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
2904 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
2905 | EXPORT_SYMBOL(pci_assign_resource); | |
2906 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 2907 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
2908 | |
2909 | EXPORT_SYMBOL(pci_set_power_state); | |
2910 | EXPORT_SYMBOL(pci_save_state); | |
2911 | EXPORT_SYMBOL(pci_restore_state); | |
e5899e1b | 2912 | EXPORT_SYMBOL(pci_pme_capable); |
5a6c9b60 | 2913 | EXPORT_SYMBOL(pci_pme_active); |
1da177e4 | 2914 | EXPORT_SYMBOL(pci_enable_wake); |
0235c4fc | 2915 | EXPORT_SYMBOL(pci_wake_from_d3); |
e5899e1b | 2916 | EXPORT_SYMBOL(pci_target_state); |
404cc2d8 RW |
2917 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
2918 | EXPORT_SYMBOL(pci_back_from_sleep); | |
f7bdd12d | 2919 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
1da177e4 | 2920 |