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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
11df1f05 ME |
30 | #ifndef arch_msi_check_device |
31 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
32 | { |
33 | return 0; | |
34 | } | |
11df1f05 | 35 | #endif |
6a9e7f20 | 36 | |
11df1f05 | 37 | #ifndef arch_setup_msi_irqs |
1525bf0d TG |
38 | # define arch_setup_msi_irqs default_setup_msi_irqs |
39 | # define HAVE_DEFAULT_MSI_SETUP_IRQS | |
40 | #endif | |
41 | ||
42 | #ifdef HAVE_DEFAULT_MSI_SETUP_IRQS | |
43 | int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
44 | { |
45 | struct msi_desc *entry; | |
46 | int ret; | |
47 | ||
1c8d7b0a MW |
48 | /* |
49 | * If an architecture wants to support multiple MSI, it needs to | |
50 | * override arch_setup_msi_irqs() | |
51 | */ | |
52 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
53 | return 1; | |
54 | ||
6a9e7f20 AB |
55 | list_for_each_entry(entry, &dev->msi_list, list) { |
56 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 57 | if (ret < 0) |
6a9e7f20 | 58 | return ret; |
b5fbf533 ME |
59 | if (ret > 0) |
60 | return -ENOSPC; | |
6a9e7f20 AB |
61 | } |
62 | ||
63 | return 0; | |
64 | } | |
11df1f05 | 65 | #endif |
6a9e7f20 | 66 | |
11df1f05 | 67 | #ifndef arch_teardown_msi_irqs |
1525bf0d TG |
68 | # define arch_teardown_msi_irqs default_teardown_msi_irqs |
69 | # define HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
70 | #endif | |
71 | ||
72 | #ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
73 | void default_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
74 | { |
75 | struct msi_desc *entry; | |
76 | ||
77 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
78 | int i, nvec; |
79 | if (entry->irq == 0) | |
80 | continue; | |
81 | nvec = 1 << entry->msi_attrib.multiple; | |
82 | for (i = 0; i < nvec; i++) | |
83 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
84 | } |
85 | } | |
11df1f05 | 86 | #endif |
6a9e7f20 | 87 | |
110828c9 | 88 | static void msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 89 | { |
b1cbf4e4 EB |
90 | u16 control; |
91 | ||
110828c9 | 92 | BUG_ON(!pos); |
b1cbf4e4 | 93 | |
110828c9 MW |
94 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
95 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
96 | if (enable) | |
97 | control |= PCI_MSI_FLAGS_ENABLE; | |
98 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
5ca5c02f HS |
99 | } |
100 | ||
b1cbf4e4 EB |
101 | static void msix_set_enable(struct pci_dev *dev, int enable) |
102 | { | |
103 | int pos; | |
104 | u16 control; | |
105 | ||
106 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
107 | if (pos) { | |
108 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
109 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
110 | if (enable) | |
111 | control |= PCI_MSIX_FLAGS_ENABLE; | |
112 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
113 | } | |
114 | } | |
115 | ||
bffac3c5 MW |
116 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
117 | { | |
0b49ec37 MW |
118 | /* Don't shift by >= width of type */ |
119 | if (x >= 5) | |
120 | return 0xffffffff; | |
121 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
122 | } |
123 | ||
f2440d9a | 124 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 125 | { |
f2440d9a MW |
126 | return msi_mask((control >> 1) & 7); |
127 | } | |
988cbb15 | 128 | |
f2440d9a MW |
129 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
130 | { | |
131 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
132 | } |
133 | ||
ce6fce42 MW |
134 | /* |
135 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
136 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
137 | * reliably as devices without an INTx disable bit will then generate a | |
138 | * level IRQ which will never be cleared. | |
ce6fce42 | 139 | */ |
12abb8ba | 140 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 141 | { |
f2440d9a | 142 | u32 mask_bits = desc->masked; |
1da177e4 | 143 | |
f2440d9a | 144 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 145 | return 0; |
f2440d9a MW |
146 | |
147 | mask_bits &= ~mask; | |
148 | mask_bits |= flag; | |
149 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
150 | |
151 | return mask_bits; | |
152 | } | |
153 | ||
154 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
155 | { | |
156 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
157 | } |
158 | ||
159 | /* | |
160 | * This internal function does not flush PCI writes to the device. | |
161 | * All users must ensure that they read from the device before either | |
162 | * assuming that the device state is up to date, or returning out of this | |
163 | * file. This saves a few milliseconds when initialising devices with lots | |
164 | * of MSI-X interrupts. | |
165 | */ | |
12abb8ba | 166 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
167 | { |
168 | u32 mask_bits = desc->masked; | |
169 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 170 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
f2440d9a MW |
171 | mask_bits &= ~1; |
172 | mask_bits |= flag; | |
173 | writel(mask_bits, desc->mask_base + offset); | |
12abb8ba HS |
174 | |
175 | return mask_bits; | |
176 | } | |
177 | ||
178 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
179 | { | |
180 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 181 | } |
24d27553 | 182 | |
1c9db525 | 183 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 184 | { |
1c9db525 | 185 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 186 | |
f2440d9a MW |
187 | if (desc->msi_attrib.is_msix) { |
188 | msix_mask_irq(desc, flag); | |
189 | readl(desc->mask_base); /* Flush write to device */ | |
190 | } else { | |
1c9db525 | 191 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 192 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 193 | } |
f2440d9a MW |
194 | } |
195 | ||
1c9db525 | 196 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 197 | { |
1c9db525 | 198 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
199 | } |
200 | ||
1c9db525 | 201 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 202 | { |
1c9db525 | 203 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
204 | } |
205 | ||
39431acb | 206 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 207 | { |
30da5524 BH |
208 | BUG_ON(entry->dev->current_state != PCI_D0); |
209 | ||
210 | if (entry->msi_attrib.is_msix) { | |
211 | void __iomem *base = entry->mask_base + | |
212 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
213 | ||
214 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
215 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
216 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
217 | } else { | |
218 | struct pci_dev *dev = entry->dev; | |
219 | int pos = entry->msi_attrib.pos; | |
220 | u16 data; | |
221 | ||
222 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
223 | &msg->address_lo); | |
224 | if (entry->msi_attrib.is_64) { | |
225 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
226 | &msg->address_hi); | |
227 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
228 | } else { | |
229 | msg->address_hi = 0; | |
230 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); | |
231 | } | |
232 | msg->data = data; | |
233 | } | |
234 | } | |
235 | ||
236 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
237 | { | |
39431acb | 238 | struct msi_desc *entry = get_irq_msi(irq); |
30da5524 | 239 | |
39431acb | 240 | __read_msi_msg(entry, msg); |
30da5524 BH |
241 | } |
242 | ||
39431acb | 243 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 244 | { |
30da5524 | 245 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
246 | * valid messages are not all-zeroes. */ |
247 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
248 | entry->msg.data)); | |
0366f8f7 | 249 | |
fcd097f3 | 250 | *msg = entry->msg; |
0366f8f7 | 251 | } |
1da177e4 | 252 | |
30da5524 | 253 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 254 | { |
39431acb | 255 | struct msi_desc *entry = get_irq_msi(irq); |
3145e941 | 256 | |
39431acb | 257 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
258 | } |
259 | ||
39431acb | 260 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 261 | { |
fcd097f3 BH |
262 | if (entry->dev->current_state != PCI_D0) { |
263 | /* Don't touch the hardware now */ | |
264 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
265 | void __iomem *base; |
266 | base = entry->mask_base + | |
267 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
268 | ||
2c21fd4b HS |
269 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
270 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
271 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 272 | } else { |
0366f8f7 EB |
273 | struct pci_dev *dev = entry->dev; |
274 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
275 | u16 msgctl; |
276 | ||
277 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
278 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
279 | msgctl |= entry->msi_attrib.multiple << 4; | |
280 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
281 | |
282 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
283 | msg->address_lo); | |
284 | if (entry->msi_attrib.is_64) { | |
285 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
286 | msg->address_hi); | |
287 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
288 | msg->data); | |
289 | } else { | |
290 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
291 | msg->data); | |
292 | } | |
1da177e4 | 293 | } |
392ee1e6 | 294 | entry->msg = *msg; |
1da177e4 | 295 | } |
0366f8f7 | 296 | |
3145e941 YL |
297 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
298 | { | |
39431acb | 299 | struct msi_desc *entry = get_irq_msi(irq); |
3145e941 | 300 | |
39431acb | 301 | __write_msi_msg(entry, msg); |
3145e941 YL |
302 | } |
303 | ||
f56e4481 HS |
304 | static void free_msi_irqs(struct pci_dev *dev) |
305 | { | |
306 | struct msi_desc *entry, *tmp; | |
307 | ||
308 | list_for_each_entry(entry, &dev->msi_list, list) { | |
309 | int i, nvec; | |
310 | if (!entry->irq) | |
311 | continue; | |
312 | nvec = 1 << entry->msi_attrib.multiple; | |
313 | for (i = 0; i < nvec; i++) | |
314 | BUG_ON(irq_has_action(entry->irq + i)); | |
315 | } | |
316 | ||
317 | arch_teardown_msi_irqs(dev); | |
318 | ||
319 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
320 | if (entry->msi_attrib.is_msix) { | |
321 | if (list_is_last(&entry->list, &dev->msi_list)) | |
322 | iounmap(entry->mask_base); | |
323 | } | |
324 | list_del(&entry->list); | |
325 | kfree(entry); | |
326 | } | |
327 | } | |
c54c1879 | 328 | |
379f5327 | 329 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 330 | { |
379f5327 MW |
331 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
332 | if (!desc) | |
1da177e4 LT |
333 | return NULL; |
334 | ||
379f5327 MW |
335 | INIT_LIST_HEAD(&desc->list); |
336 | desc->dev = dev; | |
1da177e4 | 337 | |
379f5327 | 338 | return desc; |
1da177e4 LT |
339 | } |
340 | ||
ba698ad4 DM |
341 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
342 | { | |
343 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
344 | pci_intx(dev, enable); | |
345 | } | |
346 | ||
8fed4b65 | 347 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 348 | { |
392ee1e6 | 349 | int pos; |
41017f0c | 350 | u16 control; |
392ee1e6 | 351 | struct msi_desc *entry; |
41017f0c | 352 | |
b1cbf4e4 EB |
353 | if (!dev->msi_enabled) |
354 | return; | |
355 | ||
392ee1e6 EB |
356 | entry = get_irq_msi(dev->irq); |
357 | pos = entry->msi_attrib.pos; | |
41017f0c | 358 | |
ba698ad4 | 359 | pci_intx_for_msi(dev, 0); |
110828c9 | 360 | msi_set_enable(dev, pos, 0); |
392ee1e6 | 361 | write_msi_msg(dev->irq, &entry->msg); |
392ee1e6 EB |
362 | |
363 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 364 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 365 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 366 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 367 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
368 | } |
369 | ||
370 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 371 | { |
41017f0c | 372 | int pos; |
41017f0c | 373 | struct msi_desc *entry; |
392ee1e6 | 374 | u16 control; |
41017f0c | 375 | |
ded86d8d EB |
376 | if (!dev->msix_enabled) |
377 | return; | |
f598282f | 378 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 379 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f598282f MW |
380 | pos = entry->msi_attrib.pos; |
381 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
ded86d8d | 382 | |
41017f0c | 383 | /* route the table */ |
ba698ad4 | 384 | pci_intx_for_msi(dev, 0); |
f598282f MW |
385 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
386 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 387 | |
4aa9bc95 ME |
388 | list_for_each_entry(entry, &dev->msi_list, list) { |
389 | write_msi_msg(entry->irq, &entry->msg); | |
f2440d9a | 390 | msix_mask_irq(entry, entry->masked); |
41017f0c | 391 | } |
41017f0c | 392 | |
392ee1e6 | 393 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
392ee1e6 | 394 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
41017f0c | 395 | } |
8fed4b65 ME |
396 | |
397 | void pci_restore_msi_state(struct pci_dev *dev) | |
398 | { | |
399 | __pci_restore_msi_state(dev); | |
400 | __pci_restore_msix_state(dev); | |
401 | } | |
94688cf2 | 402 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 403 | |
1da177e4 LT |
404 | /** |
405 | * msi_capability_init - configure device's MSI capability structure | |
406 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 407 | * @nvec: number of interrupts to allocate |
1da177e4 | 408 | * |
1c8d7b0a MW |
409 | * Setup the MSI capability structure of the device with the requested |
410 | * number of interrupts. A return value of zero indicates the successful | |
411 | * setup of an entry with the new MSI irq. A negative return value indicates | |
412 | * an error, and a positive return value indicates the number of interrupts | |
413 | * which could have been allocated. | |
414 | */ | |
415 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
416 | { |
417 | struct msi_desc *entry; | |
7fe3730d | 418 | int pos, ret; |
1da177e4 | 419 | u16 control; |
f2440d9a | 420 | unsigned mask; |
1da177e4 | 421 | |
500559a9 | 422 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
110828c9 MW |
423 | msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ |
424 | ||
1da177e4 LT |
425 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
426 | /* MSI Entry Initialization */ | |
379f5327 | 427 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
428 | if (!entry) |
429 | return -ENOMEM; | |
1ce03373 | 430 | |
500559a9 HS |
431 | entry->msi_attrib.is_msix = 0; |
432 | entry->msi_attrib.is_64 = is_64bit_address(control); | |
433 | entry->msi_attrib.entry_nr = 0; | |
434 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
435 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
436 | entry->msi_attrib.pos = pos; | |
f2440d9a | 437 | |
67b5db65 | 438 | entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); |
f2440d9a MW |
439 | /* All MSIs are unmasked by default, Mask them all */ |
440 | if (entry->msi_attrib.maskbit) | |
441 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
442 | mask = msi_capable_mask(control); | |
443 | msi_mask_irq(entry, mask, mask); | |
444 | ||
0dd11f9b | 445 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 446 | |
1da177e4 | 447 | /* Configure MSI capability structure */ |
1c8d7b0a | 448 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 449 | if (ret) { |
7ba1930d | 450 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 451 | free_msi_irqs(dev); |
7fe3730d | 452 | return ret; |
fd58e55f | 453 | } |
f7feaca7 | 454 | |
1da177e4 | 455 | /* Set MSI enabled bits */ |
ba698ad4 | 456 | pci_intx_for_msi(dev, 0); |
110828c9 | 457 | msi_set_enable(dev, pos, 1); |
b1cbf4e4 | 458 | dev->msi_enabled = 1; |
1da177e4 | 459 | |
7fe3730d | 460 | dev->irq = entry->irq; |
1da177e4 LT |
461 | return 0; |
462 | } | |
463 | ||
5a05a9d8 HS |
464 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos, |
465 | unsigned nr_entries) | |
466 | { | |
4302e0fb | 467 | resource_size_t phys_addr; |
5a05a9d8 HS |
468 | u32 table_offset; |
469 | u8 bir; | |
470 | ||
471 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
472 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
473 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; | |
474 | phys_addr = pci_resource_start(dev, bir) + table_offset; | |
475 | ||
476 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
477 | } | |
478 | ||
d9d7070e HS |
479 | static int msix_setup_entries(struct pci_dev *dev, unsigned pos, |
480 | void __iomem *base, struct msix_entry *entries, | |
481 | int nvec) | |
482 | { | |
483 | struct msi_desc *entry; | |
484 | int i; | |
485 | ||
486 | for (i = 0; i < nvec; i++) { | |
487 | entry = alloc_msi_entry(dev); | |
488 | if (!entry) { | |
489 | if (!i) | |
490 | iounmap(base); | |
491 | else | |
492 | free_msi_irqs(dev); | |
493 | /* No enough memory. Don't try again */ | |
494 | return -ENOMEM; | |
495 | } | |
496 | ||
497 | entry->msi_attrib.is_msix = 1; | |
498 | entry->msi_attrib.is_64 = 1; | |
499 | entry->msi_attrib.entry_nr = entries[i].entry; | |
500 | entry->msi_attrib.default_irq = dev->irq; | |
501 | entry->msi_attrib.pos = pos; | |
502 | entry->mask_base = base; | |
503 | ||
504 | list_add_tail(&entry->list, &dev->msi_list); | |
505 | } | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
75cb3426 HS |
510 | static void msix_program_entries(struct pci_dev *dev, |
511 | struct msix_entry *entries) | |
512 | { | |
513 | struct msi_desc *entry; | |
514 | int i = 0; | |
515 | ||
516 | list_for_each_entry(entry, &dev->msi_list, list) { | |
517 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
518 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
519 | ||
520 | entries[i].vector = entry->irq; | |
521 | set_irq_msi(entry->irq, entry); | |
522 | entry->masked = readl(entry->mask_base + offset); | |
523 | msix_mask_irq(entry, 1); | |
524 | i++; | |
525 | } | |
526 | } | |
527 | ||
1da177e4 LT |
528 | /** |
529 | * msix_capability_init - configure device's MSI-X capability | |
530 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
531 | * @entries: pointer to an array of struct msix_entry entries |
532 | * @nvec: number of @entries | |
1da177e4 | 533 | * |
eaae4b3a | 534 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
535 | * single MSI-X irq. A return of zero indicates the successful setup of |
536 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
537 | **/ |
538 | static int msix_capability_init(struct pci_dev *dev, | |
539 | struct msix_entry *entries, int nvec) | |
540 | { | |
d9d7070e | 541 | int pos, ret; |
5a05a9d8 | 542 | u16 control; |
1da177e4 LT |
543 | void __iomem *base; |
544 | ||
500559a9 | 545 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
f598282f MW |
546 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
547 | ||
548 | /* Ensure MSI-X is disabled while it is set up */ | |
549 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
550 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
551 | ||
1da177e4 | 552 | /* Request & Map MSI-X table region */ |
5a05a9d8 HS |
553 | base = msix_map_region(dev, pos, multi_msix_capable(control)); |
554 | if (!base) | |
1da177e4 LT |
555 | return -ENOMEM; |
556 | ||
d9d7070e HS |
557 | ret = msix_setup_entries(dev, pos, base, entries, nvec); |
558 | if (ret) | |
559 | return ret; | |
9c831334 ME |
560 | |
561 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
562 | if (ret) |
563 | goto error; | |
9c831334 | 564 | |
f598282f MW |
565 | /* |
566 | * Some devices require MSI-X to be enabled before we can touch the | |
567 | * MSI-X registers. We need to mask all the vectors to prevent | |
568 | * interrupts coming in before they're fully set up. | |
569 | */ | |
570 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
571 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
572 | ||
75cb3426 | 573 | msix_program_entries(dev, entries); |
f598282f MW |
574 | |
575 | /* Set MSI-X enabled bits and unmask the function */ | |
ba698ad4 | 576 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 577 | dev->msix_enabled = 1; |
1da177e4 | 578 | |
f598282f MW |
579 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
580 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
8d181018 | 581 | |
1da177e4 | 582 | return 0; |
583871d4 HS |
583 | |
584 | error: | |
585 | if (ret < 0) { | |
586 | /* | |
587 | * If we had some success, report the number of irqs | |
588 | * we succeeded in setting up. | |
589 | */ | |
d9d7070e | 590 | struct msi_desc *entry; |
583871d4 HS |
591 | int avail = 0; |
592 | ||
593 | list_for_each_entry(entry, &dev->msi_list, list) { | |
594 | if (entry->irq != 0) | |
595 | avail++; | |
596 | } | |
597 | if (avail != 0) | |
598 | ret = avail; | |
599 | } | |
600 | ||
601 | free_msi_irqs(dev); | |
602 | ||
603 | return ret; | |
1da177e4 LT |
604 | } |
605 | ||
24334a12 | 606 | /** |
17bbc12a | 607 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 608 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 609 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 610 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 611 | * |
0306ebfa | 612 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
613 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
614 | * supported return 0, else return an error code. | |
24334a12 | 615 | **/ |
500559a9 | 616 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
617 | { |
618 | struct pci_bus *bus; | |
c9953a73 | 619 | int ret; |
24334a12 | 620 | |
0306ebfa | 621 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
622 | if (!pci_msi_enable || !dev || dev->no_msi) |
623 | return -EINVAL; | |
624 | ||
314e77b3 ME |
625 | /* |
626 | * You can't ask to have 0 or less MSIs configured. | |
627 | * a) it's stupid .. | |
628 | * b) the list manipulation code assumes nvec >= 1. | |
629 | */ | |
630 | if (nvec < 1) | |
631 | return -ERANGE; | |
632 | ||
500559a9 HS |
633 | /* |
634 | * Any bridge which does NOT route MSI transactions from its | |
635 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
636 | * the secondary pci_bus. |
637 | * We expect only arch-specific PCI host bus controller driver | |
638 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
639 | */ | |
24334a12 BG |
640 | for (bus = dev->bus; bus; bus = bus->parent) |
641 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
642 | return -EINVAL; | |
643 | ||
c9953a73 ME |
644 | ret = arch_msi_check_device(dev, nvec, type); |
645 | if (ret) | |
646 | return ret; | |
647 | ||
b1e2303d ME |
648 | if (!pci_find_capability(dev, type)) |
649 | return -EINVAL; | |
650 | ||
24334a12 BG |
651 | return 0; |
652 | } | |
653 | ||
1da177e4 | 654 | /** |
1c8d7b0a MW |
655 | * pci_enable_msi_block - configure device's MSI capability structure |
656 | * @dev: device to configure | |
657 | * @nvec: number of interrupts to configure | |
1da177e4 | 658 | * |
1c8d7b0a MW |
659 | * Allocate IRQs for a device with the MSI capability. |
660 | * This function returns a negative errno if an error occurs. If it | |
661 | * is unable to allocate the number of interrupts requested, it returns | |
662 | * the number of interrupts it might be able to allocate. If it successfully | |
663 | * allocates at least the number of interrupts requested, it returns 0 and | |
664 | * updates the @dev's irq member to the lowest new interrupt number; the | |
665 | * other interrupt numbers allocated to this device are consecutive. | |
666 | */ | |
667 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 668 | { |
1c8d7b0a MW |
669 | int status, pos, maxvec; |
670 | u16 msgctl; | |
671 | ||
672 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
673 | if (!pos) | |
674 | return -EINVAL; | |
675 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
676 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
677 | if (nvec > maxvec) | |
678 | return maxvec; | |
1da177e4 | 679 | |
1c8d7b0a | 680 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
681 | if (status) |
682 | return status; | |
1da177e4 | 683 | |
ded86d8d | 684 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 685 | |
1c8d7b0a | 686 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 687 | if (dev->msix_enabled) { |
80ccba11 BH |
688 | dev_info(&dev->dev, "can't enable MSI " |
689 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 690 | return -EINVAL; |
1da177e4 | 691 | } |
1c8d7b0a MW |
692 | |
693 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
694 | return status; |
695 | } | |
1c8d7b0a | 696 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 697 | |
f2440d9a | 698 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 699 | { |
f2440d9a MW |
700 | struct msi_desc *desc; |
701 | u32 mask; | |
702 | u16 ctrl; | |
110828c9 | 703 | unsigned pos; |
1da177e4 | 704 | |
128bc5fc | 705 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
706 | return; |
707 | ||
110828c9 MW |
708 | BUG_ON(list_empty(&dev->msi_list)); |
709 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
710 | pos = desc->msi_attrib.pos; | |
711 | ||
712 | msi_set_enable(dev, pos, 0); | |
ba698ad4 | 713 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 714 | dev->msi_enabled = 0; |
7bd007e4 | 715 | |
12abb8ba | 716 | /* Return the device with MSI unmasked as initial states */ |
110828c9 | 717 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 718 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
719 | /* Keep cached state to be restored */ |
720 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
721 | |
722 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 723 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 724 | } |
24d27553 | 725 | |
500559a9 | 726 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 727 | { |
d52877c7 YL |
728 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
729 | return; | |
730 | ||
731 | pci_msi_shutdown(dev); | |
f56e4481 | 732 | free_msi_irqs(dev); |
1da177e4 | 733 | } |
4cc086fa | 734 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 735 | |
a52e2e35 RW |
736 | /** |
737 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
738 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
739 | */ | |
740 | int pci_msix_table_size(struct pci_dev *dev) | |
741 | { | |
742 | int pos; | |
743 | u16 control; | |
744 | ||
745 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
746 | if (!pos) | |
747 | return 0; | |
748 | ||
749 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
750 | return multi_msix_capable(control); | |
751 | } | |
752 | ||
1da177e4 LT |
753 | /** |
754 | * pci_enable_msix - configure device's MSI-X capability structure | |
755 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 756 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 757 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
758 | * |
759 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 760 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
761 | * MSI-X mode enabled on its hardware device function. A return of zero |
762 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 763 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 764 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
765 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
766 | * re-send its request. | |
1da177e4 | 767 | **/ |
500559a9 | 768 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 769 | { |
a52e2e35 | 770 | int status, nr_entries; |
ded86d8d | 771 | int i, j; |
1da177e4 | 772 | |
c9953a73 | 773 | if (!entries) |
500559a9 | 774 | return -EINVAL; |
1da177e4 | 775 | |
c9953a73 ME |
776 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
777 | if (status) | |
778 | return status; | |
779 | ||
a52e2e35 | 780 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 781 | if (nvec > nr_entries) |
57fbf52c | 782 | return nr_entries; |
1da177e4 LT |
783 | |
784 | /* Check for any invalid entries */ | |
785 | for (i = 0; i < nvec; i++) { | |
786 | if (entries[i].entry >= nr_entries) | |
787 | return -EINVAL; /* invalid entry */ | |
788 | for (j = i + 1; j < nvec; j++) { | |
789 | if (entries[i].entry == entries[j].entry) | |
790 | return -EINVAL; /* duplicate entry */ | |
791 | } | |
792 | } | |
ded86d8d | 793 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 794 | |
1ce03373 | 795 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 796 | if (dev->msi_enabled) { |
80ccba11 BH |
797 | dev_info(&dev->dev, "can't enable MSI-X " |
798 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
799 | return -EINVAL; |
800 | } | |
1da177e4 | 801 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
802 | return status; |
803 | } | |
4cc086fa | 804 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 805 | |
500559a9 | 806 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 807 | { |
12abb8ba HS |
808 | struct msi_desc *entry; |
809 | ||
128bc5fc | 810 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
811 | return; |
812 | ||
12abb8ba HS |
813 | /* Return the device with MSI-X masked as initial states */ |
814 | list_for_each_entry(entry, &dev->msi_list, list) { | |
815 | /* Keep cached states to be restored */ | |
816 | __msix_mask_irq(entry, 1); | |
817 | } | |
818 | ||
b1cbf4e4 | 819 | msix_set_enable(dev, 0); |
ba698ad4 | 820 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 821 | dev->msix_enabled = 0; |
d52877c7 | 822 | } |
c901851f | 823 | |
500559a9 | 824 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
825 | { |
826 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
827 | return; | |
828 | ||
829 | pci_msix_shutdown(dev); | |
f56e4481 | 830 | free_msi_irqs(dev); |
1da177e4 | 831 | } |
4cc086fa | 832 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
833 | |
834 | /** | |
1ce03373 | 835 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
836 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
837 | * | |
eaae4b3a | 838 | * Being called during hotplug remove, from which the device function |
1ce03373 | 839 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
840 | * allocated for this device function, are reclaimed to unused state, |
841 | * which may be used later on. | |
842 | **/ | |
500559a9 | 843 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 844 | { |
1da177e4 | 845 | if (!pci_msi_enable || !dev) |
500559a9 | 846 | return; |
1da177e4 | 847 | |
f56e4481 HS |
848 | if (dev->msi_enabled || dev->msix_enabled) |
849 | free_msi_irqs(dev); | |
1da177e4 LT |
850 | } |
851 | ||
309e57df MW |
852 | void pci_no_msi(void) |
853 | { | |
854 | pci_msi_enable = 0; | |
855 | } | |
c9953a73 | 856 | |
07ae95f9 AP |
857 | /** |
858 | * pci_msi_enabled - is MSI enabled? | |
859 | * | |
860 | * Returns true if MSI has not been disabled by the command-line option | |
861 | * pci=nomsi. | |
862 | **/ | |
863 | int pci_msi_enabled(void) | |
d389fec6 | 864 | { |
07ae95f9 | 865 | return pci_msi_enable; |
d389fec6 | 866 | } |
07ae95f9 | 867 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 868 | |
07ae95f9 | 869 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 870 | { |
07ae95f9 | 871 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 872 | } |