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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
[net-next-2.6.git] / drivers / parisc / ccio-dma.c
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1da177e4
LT		 1/*
2** ccio-dma.c:
3** DMA management routines for first generation cache-coherent machines.
4** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
5**
6** (c) Copyright 2000 Grant Grundler
7** (c) Copyright 2000 Ryan Bradetich
8** (c) Copyright 2000 Hewlett-Packard Company
9**
10** This program is free software; you can redistribute it and/or modify
11** it under the terms of the GNU General Public License as published by
12** the Free Software Foundation; either version 2 of the License, or
13** (at your option) any later version.
14**
15**
16** "Real Mode" operation refers to U2/Uturn chip operation.
17** U2/Uturn were designed to perform coherency checks w/o using
18** the I/O MMU - basically what x86 does.
19**
20** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
21** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
22** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
23**
24** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
25**
26** Drawbacks of using Real Mode are:
27** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
28** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
29** o Ability to do scatter/gather in HW is lost.
30** o Doesn't work under PCX-U/U+ machines since they didn't follow
31** the coherency design originally worked out. Only PCX-W does.
32*/
33
34#include <linux/config.h>
35#include <linux/types.h>
36#include <linux/init.h>
37#include <linux/mm.h>
38#include <linux/spinlock.h>
39#include <linux/slab.h>
40#include <linux/string.h>
41#include <linux/pci.h>
42#include <linux/reboot.h>
43
44#include <asm/byteorder.h>
45#include <asm/cache.h> /* for L1_CACHE_BYTES */
46#include <asm/uaccess.h>
47#include <asm/page.h>
48#include <asm/dma.h>
49#include <asm/io.h>
50#include <asm/hardware.h> /* for register_module() */
51#include <asm/parisc-device.h>
52
53/*
54** Choose "ccio" since that's what HP-UX calls it.
55** Make it easier for folks to migrate from one to the other :^)
56*/
57#define MODULE_NAME "ccio"
58
59#undef DEBUG_CCIO_RES
60#undef DEBUG_CCIO_RUN
61#undef DEBUG_CCIO_INIT
62#undef DEBUG_CCIO_RUN_SG
63
64#ifdef CONFIG_PROC_FS
65/*
66 * CCIO_SEARCH_TIME can help measure how fast the bitmap search is.
67 * impacts performance though - ditch it if you don't use it.
68 */
69#define CCIO_SEARCH_TIME
70#undef CCIO_MAP_STATS
71#else
72#undef CCIO_SEARCH_TIME
73#undef CCIO_MAP_STATS
74#endif
75
76#include <linux/proc_fs.h>
77#include <asm/runway.h> /* for proc_runway_root */
78
79#ifdef DEBUG_CCIO_INIT
80#define DBG_INIT(x...) printk(x)
81#else
82#define DBG_INIT(x...)
83#endif
84
85#ifdef DEBUG_CCIO_RUN
86#define DBG_RUN(x...) printk(x)
87#else
88#define DBG_RUN(x...)
89#endif
90
91#ifdef DEBUG_CCIO_RES
92#define DBG_RES(x...) printk(x)
93#else
94#define DBG_RES(x...)
95#endif
96
97#ifdef DEBUG_CCIO_RUN_SG
98#define DBG_RUN_SG(x...) printk(x)
99#else
100#define DBG_RUN_SG(x...)
101#endif
102
86a61ee9
GG		 103#define CCIO_INLINE inline
104#define WRITE_U32(value, addr) __raw_writel(value, addr)
105#define READ_U32(addr) __raw_readl(addr)
1da177e4
LT		 106
107#define U2_IOA_RUNWAY 0x580
108#define U2_BC_GSC 0x501
109#define UTURN_IOA_RUNWAY 0x581
110#define UTURN_BC_GSC 0x502
111
112#define IOA_NORMAL_MODE 0x00020080 /* IO_CONTROL to turn on CCIO */
113#define CMD_TLB_DIRECT_WRITE 35 /* IO_COMMAND for I/O TLB Writes */
114#define CMD_TLB_PURGE 33 /* IO_COMMAND to Purge I/O TLB entry */
115
116struct ioa_registers {
117 /* Runway Supervisory Set */
86a61ee9
GG		 118 int32_t unused1[12];
119 uint32_t io_command; /* Offset 12 */
120 uint32_t io_status; /* Offset 13 */
121 uint32_t io_control; /* Offset 14 */
122 int32_t unused2[1];
1da177e4
LT		 123
124 /* Runway Auxiliary Register Set */
86a61ee9
GG		 125 uint32_t io_err_resp; /* Offset 0 */
126 uint32_t io_err_info; /* Offset 1 */
127 uint32_t io_err_req; /* Offset 2 */
128 uint32_t io_err_resp_hi; /* Offset 3 */
129 uint32_t io_tlb_entry_m; /* Offset 4 */
130 uint32_t io_tlb_entry_l; /* Offset 5 */
131 uint32_t unused3[1];
132 uint32_t io_pdir_base; /* Offset 7 */
133 uint32_t io_io_low_hv; /* Offset 8 */
134 uint32_t io_io_high_hv; /* Offset 9 */
135 uint32_t unused4[1];
136 uint32_t io_chain_id_mask; /* Offset 11 */
137 uint32_t unused5[2];
138 uint32_t io_io_low; /* Offset 14 */
139 uint32_t io_io_high; /* Offset 15 */
1da177e4
LT		 140};
141
142/*
143** IOA Registers
144** -------------
145**
146** Runway IO_CONTROL Register (+0x38)
147**
148** The Runway IO_CONTROL register controls the forwarding of transactions.
149**
150** | 0 ... 13 | 14 15 | 16 ... 21 | 22 | 23 24 | 25 ... 31 |
151** | HV | TLB | reserved | HV | mode | reserved |
152**
153** o mode field indicates the address translation of transactions
154** forwarded from Runway to GSC+:
155** Mode Name Value Definition
156** Off (default) 0 Opaque to matching addresses.
157** Include 1 Transparent for matching addresses.
158** Peek 3 Map matching addresses.
159**
160** + "Off" mode: Runway transactions which match the I/O range
161** specified by the IO_IO_LOW/IO_IO_HIGH registers will be ignored.
162** + "Include" mode: all addresses within the I/O range specified
163** by the IO_IO_LOW and IO_IO_HIGH registers are transparently
164** forwarded. This is the I/O Adapter's normal operating mode.
165** + "Peek" mode: used during system configuration to initialize the
166** GSC+ bus. Runway Write_Shorts in the address range specified by
167** IO_IO_LOW and IO_IO_HIGH are forwarded through the I/O Adapter
168** *AND* the GSC+ address is remapped to the Broadcast Physical
169** Address space by setting the 14 high order address bits of the
170** 32 bit GSC+ address to ones.
171**
172** o TLB field affects transactions which are forwarded from GSC+ to Runway.
173** "Real" mode is the poweron default.
174**
175** TLB Mode Value Description
176** Real 0 No TLB translation. Address is directly mapped and the
177** virtual address is composed of selected physical bits.
178** Error 1 Software fills the TLB manually.
179** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory).
180**
181**
182** IO_IO_LOW_HV +0x60 (HV dependent)
183** IO_IO_HIGH_HV +0x64 (HV dependent)
184** IO_IO_LOW +0x78 (Architected register)
185** IO_IO_HIGH +0x7c (Architected register)
186**
187** IO_IO_LOW and IO_IO_HIGH set the lower and upper bounds of the
188** I/O Adapter address space, respectively.
189**
190** 0 ... 7 | 8 ... 15 | 16 ... 31 |
191** 11111111 | 11111111 | address |
192**
193** Each LOW/HIGH pair describes a disjoint address space region.
194** (2 per GSC+ port). Each incoming Runway transaction address is compared
195** with both sets of LOW/HIGH registers. If the address is in the range
196** greater than or equal to IO_IO_LOW and less than IO_IO_HIGH the transaction
197** for forwarded to the respective GSC+ bus.
198** Specify IO_IO_LOW equal to or greater than IO_IO_HIGH to avoid specifying
199** an address space region.
200**
201** In order for a Runway address to reside within GSC+ extended address space:
202** Runway Address [0:7] must identically compare to 8'b11111111
203** Runway Address [8:11] must be equal to IO_IO_LOW(_HV)[16:19]
204** Runway Address [12:23] must be greater than or equal to
205** IO_IO_LOW(_HV)[20:31] and less than IO_IO_HIGH(_HV)[20:31].
206** Runway Address [24:39] is not used in the comparison.
207**
208** When the Runway transaction is forwarded to GSC+, the GSC+ address is
209** as follows:
210** GSC+ Address[0:3] 4'b1111
211** GSC+ Address[4:29] Runway Address[12:37]
212** GSC+ Address[30:31] 2'b00
213**
214** All 4 Low/High registers must be initialized (by PDC) once the lower bus
215** is interrogated and address space is defined. The operating system will
216** modify the architectural IO_IO_LOW and IO_IO_HIGH registers following
217** the PDC initialization. However, the hardware version dependent IO_IO_LOW
218** and IO_IO_HIGH registers should not be subsequently altered by the OS.
219**
220** Writes to both sets of registers will take effect immediately, bypassing
221** the queues, which ensures that subsequent Runway transactions are checked
222** against the updated bounds values. However reads are queued, introducing
223** the possibility of a read being bypassed by a subsequent write to the same
224** register. This sequence can be avoided by having software wait for read
225** returns before issuing subsequent writes.
226*/
227
228struct ioc {
86a61ee9 229 struct ioa_registers __iomem *ioc_regs; /* I/O MMU base address */
1da177e4
LT		 230 u8 *res_map; /* resource map, bit == pdir entry */
231 u64 *pdir_base; /* physical base address */
232 u32 pdir_size; /* bytes, function of IOV Space size */
233 u32 res_hint; /* next available IOVP -
234 circular search */
235 u32 res_size; /* size of resource map in bytes */
236 spinlock_t res_lock;
237
238#ifdef CCIO_SEARCH_TIME
239#define CCIO_SEARCH_SAMPLE 0x100
240 unsigned long avg_search[CCIO_SEARCH_SAMPLE];
241 unsigned long avg_idx; /* current index into avg_search */
242#endif
243#ifdef CCIO_MAP_STATS
244 unsigned long used_pages;
245 unsigned long msingle_calls;
246 unsigned long msingle_pages;
247 unsigned long msg_calls;
248 unsigned long msg_pages;
249 unsigned long usingle_calls;
250 unsigned long usingle_pages;
251 unsigned long usg_calls;
252 unsigned long usg_pages;
253#endif
254 unsigned short cujo20_bug;
255
256 /* STUFF We don't need in performance path */
257 u32 chainid_shift; /* specify bit location of chain_id */
258 struct ioc *next; /* Linked list of discovered iocs */
259 const char *name; /* device name from firmware */
260 unsigned int hw_path; /* the hardware path this ioc is associatd with */
261 struct pci_dev *fake_pci_dev; /* the fake pci_dev for non-pci devs */
262 struct resource mmio_region[2]; /* The "routed" MMIO regions */
263};
264
265static struct ioc *ioc_list;
266static int ioc_count;
267
268/**************************************************************
269*
270* I/O Pdir Resource Management
271*
272* Bits set in the resource map are in use.
273* Each bit can represent a number of pages.
274* LSbs represent lower addresses (IOVA's).
275*
276* This was was copied from sba_iommu.c. Don't try to unify
277* the two resource managers unless a way to have different
278* allocation policies is also adjusted. We'd like to avoid
279* I/O TLB thrashing by having resource allocation policy
280* match the I/O TLB replacement policy.
281*
282***************************************************************/
283#define IOVP_SIZE PAGE_SIZE
284#define IOVP_SHIFT PAGE_SHIFT
285#define IOVP_MASK PAGE_MASK
286
287/* Convert from IOVP to IOVA and vice versa. */
288#define CCIO_IOVA(iovp,offset) ((iovp) | (offset))
289#define CCIO_IOVP(iova) ((iova) & IOVP_MASK)
290
291#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
292#define MKIOVP(pdir_idx) ((long)(pdir_idx) << IOVP_SHIFT)
293#define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset)
294#define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
295
296/*
297** Don't worry about the 150% average search length on a miss.
298** If the search wraps around, and passes the res_hint, it will
299** cause the kernel to panic anyhow.
300*/
301#define CCIO_SEARCH_LOOP(ioc, res_idx, mask, size) \
302 for(; res_ptr < res_end; ++res_ptr) { \
303 if(0 == (*res_ptr & mask)) { \
304 *res_ptr |= mask; \
305 res_idx = (unsigned int)((unsigned long)res_ptr - (unsigned long)ioc->res_map); \
306 ioc->res_hint = res_idx + (size >> 3); \
307 goto resource_found; \
308 } \
309 }
310
311#define CCIO_FIND_FREE_MAPPING(ioa, res_idx, mask, size) \
312 u##size *res_ptr = (u##size *)&((ioc)->res_map[ioa->res_hint & ~((size >> 3) - 1)]); \
313 u##size *res_end = (u##size *)&(ioc)->res_map[ioa->res_size]; \
314 CCIO_SEARCH_LOOP(ioc, res_idx, mask, size); \
315 res_ptr = (u##size *)&(ioc)->res_map[0]; \
316 CCIO_SEARCH_LOOP(ioa, res_idx, mask, size);
317
318/*
319** Find available bit in this ioa's resource map.
320** Use a "circular" search:
321** o Most IOVA's are "temporary" - avg search time should be small.
322** o keep a history of what happened for debugging
323** o KISS.
324**
325** Perf optimizations:
326** o search for log2(size) bits at a time.
327** o search for available resource bits using byte/word/whatever.
328** o use different search for "large" (eg > 4 pages) or "very large"
329** (eg > 16 pages) mappings.
330*/
331
332/**
333 * ccio_alloc_range - Allocate pages in the ioc's resource map.
334 * @ioc: The I/O Controller.
335 * @pages_needed: The requested number of pages to be mapped into the
336 * I/O Pdir...
337 *
338 * This function searches the resource map of the ioc to locate a range
339 * of available pages for the requested size.
340 */
341static int
342ccio_alloc_range(struct ioc *ioc, size_t size)
343{
344 unsigned int pages_needed = size >> IOVP_SHIFT;
345 unsigned int res_idx;
346#ifdef CCIO_SEARCH_TIME
347 unsigned long cr_start = mfctl(16);
348#endif
349
350 BUG_ON(pages_needed == 0);
351 BUG_ON((pages_needed * IOVP_SIZE) > DMA_CHUNK_SIZE);
352
353 DBG_RES("%s() size: %d pages_needed %d\n",
354 __FUNCTION__, size, pages_needed);
355
356 /*
357 ** "seek and ye shall find"...praying never hurts either...
358 ** ggg sacrifices another 710 to the computer gods.
359 */
360
361 if (pages_needed <= 8) {
362 /*
363 * LAN traffic will not thrash the TLB IFF the same NIC
364 * uses 8 adjacent pages to map seperate payload data.
365 * ie the same byte in the resource bit map.
366 */
367#if 0
368 /* FIXME: bit search should shift it's way through
369 * an unsigned long - not byte at a time. As it is now,
370 * we effectively allocate this byte to this mapping.
371 */
372 unsigned long mask = ~(~0UL >> pages_needed);
373 CCIO_FIND_FREE_MAPPING(ioc, res_idx, mask, 8);
374#else
375 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xff, 8);
376#endif
377 } else if (pages_needed <= 16) {
378 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xffff, 16);
379 } else if (pages_needed <= 32) {
380 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~(unsigned int)0, 32);
381#ifdef __LP64__
382 } else if (pages_needed <= 64) {
383 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~0UL, 64);
384#endif
385 } else {
386 panic("%s: %s() Too many pages to map. pages_needed: %u\n",
387 __FILE__, __FUNCTION__, pages_needed);
388 }
389
390 panic("%s: %s() I/O MMU is out of mapping resources.\n", __FILE__,
391 __FUNCTION__);
392
393resource_found:
394
395 DBG_RES("%s() res_idx %d res_hint: %d\n",
396 __FUNCTION__, res_idx, ioc->res_hint);
397
398#ifdef CCIO_SEARCH_TIME
399 {
400 unsigned long cr_end = mfctl(16);
401 unsigned long tmp = cr_end - cr_start;
402 /* check for roll over */
403 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
404 }
405 ioc->avg_search[ioc->avg_idx++] = cr_start;
406 ioc->avg_idx &= CCIO_SEARCH_SAMPLE - 1;
407#endif
408#ifdef CCIO_MAP_STATS
409 ioc->used_pages += pages_needed;
410#endif
411 /*
412 ** return the bit address.
413 */
414 return res_idx << 3;
415}
416
417#define CCIO_FREE_MAPPINGS(ioc, res_idx, mask, size) \
418 u##size *res_ptr = (u##size *)&((ioc)->res_map[res_idx]); \
419 BUG_ON((*res_ptr & mask) != mask); \
420 *res_ptr &= ~(mask);
421
422/**
423 * ccio_free_range - Free pages from the ioc's resource map.
424 * @ioc: The I/O Controller.
425 * @iova: The I/O Virtual Address.
426 * @pages_mapped: The requested number of pages to be freed from the
427 * I/O Pdir.
428 *
429 * This function frees the resouces allocated for the iova.
430 */
431static void
432ccio_free_range(struct ioc *ioc, dma_addr_t iova, unsigned long pages_mapped)
433{
434 unsigned long iovp = CCIO_IOVP(iova);
435 unsigned int res_idx = PDIR_INDEX(iovp) >> 3;
436
437 BUG_ON(pages_mapped == 0);
438 BUG_ON((pages_mapped * IOVP_SIZE) > DMA_CHUNK_SIZE);
439 BUG_ON(pages_mapped > BITS_PER_LONG);
440
441 DBG_RES("%s(): res_idx: %d pages_mapped %d\n",
442 __FUNCTION__, res_idx, pages_mapped);
443
444#ifdef CCIO_MAP_STATS
445 ioc->used_pages -= pages_mapped;
446#endif
447
448 if(pages_mapped <= 8) {
449#if 0
450 /* see matching comments in alloc_range */
451 unsigned long mask = ~(~0UL >> pages_mapped);
452 CCIO_FREE_MAPPINGS(ioc, res_idx, mask, 8);
453#else
454 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xff, 8);
455#endif
456 } else if(pages_mapped <= 16) {
457 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffff, 16);
458 } else if(pages_mapped <= 32) {
459 CCIO_FREE_MAPPINGS(ioc, res_idx, ~(unsigned int)0, 32);
460#ifdef __LP64__
461 } else if(pages_mapped <= 64) {
462 CCIO_FREE_MAPPINGS(ioc, res_idx, ~0UL, 64);
463#endif
464 } else {
465 panic("%s:%s() Too many pages to unmap.\n", __FILE__,
466 __FUNCTION__);
467 }
468}
469
470/****************************************************************
471**
472** CCIO dma_ops support routines
473**
474*****************************************************************/
475
476typedef unsigned long space_t;
477#define KERNEL_SPACE 0
478
479/*
480** DMA "Page Type" and Hints
481** o if SAFE_DMA isn't set, mapping is for FAST_DMA. SAFE_DMA should be
482** set for subcacheline DMA transfers since we don't want to damage the
483** other part of a cacheline.
484** o SAFE_DMA must be set for "memory" allocated via pci_alloc_consistent().
485** This bit tells U2 to do R/M/W for partial cachelines. "Streaming"
486** data can avoid this if the mapping covers full cache lines.
487** o STOP_MOST is needed for atomicity across cachelines.
488** Apperently only "some EISA devices" need this.
489** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs
490** to use this hint iff the EISA devices needs this feature.
491** According to the U2 ERS, STOP_MOST enabled pages hurt performance.
492** o PREFETCH should *not* be set for cases like Multiple PCI devices
493** behind GSCtoPCI (dino) bus converter. Only one cacheline per GSC
494** device can be fetched and multiply DMA streams will thrash the
495** prefetch buffer and burn memory bandwidth. See 6.7.3 "Prefetch Rules
496** and Invalidation of Prefetch Entries".
497**
498** FIXME: the default hints need to be per GSC device - not global.
499**
500** HP-UX dorks: linux device driver programming model is totally different
501** than HP-UX's. HP-UX always sets HINT_PREFETCH since it's drivers
502** do special things to work on non-coherent platforms...linux has to
503** be much more careful with this.
504*/
505#define IOPDIR_VALID 0x01UL
506#define HINT_SAFE_DMA 0x02UL /* used for pci_alloc_consistent() pages */
507#ifdef CONFIG_EISA
508#define HINT_STOP_MOST 0x04UL /* LSL support */
509#else
510#define HINT_STOP_MOST 0x00UL /* only needed for "some EISA devices" */
511#endif
512#define HINT_UDPATE_ENB 0x08UL /* not used/supported by U2 */
513#define HINT_PREFETCH 0x10UL /* for outbound pages which are not SAFE */
514
515
516/*
517** Use direction (ie PCI_DMA_TODEVICE) to pick hint.
518** ccio_alloc_consistent() depends on this to get SAFE_DMA
519** when it passes in BIDIRECTIONAL flag.
520*/
521static u32 hint_lookup[] = {
522 [PCI_DMA_BIDIRECTIONAL] = HINT_STOP_MOST | HINT_SAFE_DMA | IOPDIR_VALID,
523 [PCI_DMA_TODEVICE] = HINT_STOP_MOST | HINT_PREFETCH | IOPDIR_VALID,
524 [PCI_DMA_FROMDEVICE] = HINT_STOP_MOST | IOPDIR_VALID,
525};
526
527/**
528 * ccio_io_pdir_entry - Initialize an I/O Pdir.
529 * @pdir_ptr: A pointer into I/O Pdir.
530 * @sid: The Space Identifier.
531 * @vba: The virtual address.
532 * @hints: The DMA Hint.
533 *
534 * Given a virtual address (vba, arg2) and space id, (sid, arg1),
535 * load the I/O PDIR entry pointed to by pdir_ptr (arg0). Each IO Pdir
536 * entry consists of 8 bytes as shown below (MSB == bit 0):
537 *
538 *
539 * WORD 0:
540 * +------+----------------+-----------------------------------------------+
541 * | Phys | Virtual Index | Phys |
542 * | 0:3 | 0:11 | 4:19 |
543 * |4 bits| 12 bits | 16 bits |
544 * +------+----------------+-----------------------------------------------+
545 * WORD 1:
546 * +-----------------------+-----------------------------------------------+
547 * | Phys | Rsvd | Prefetch |Update |Rsvd |Lock |Safe |Valid |
548 * | 20:39 | | Enable |Enable | |Enable|DMA | |
549 * | 20 bits | 5 bits | 1 bit |1 bit |2 bits|1 bit |1 bit |1 bit |
550 * +-----------------------+-----------------------------------------------+
551 *
552 * The virtual index field is filled with the results of the LCI
553 * (Load Coherence Index) instruction. The 8 bits used for the virtual
554 * index are bits 12:19 of the value returned by LCI.
555 */
556void CCIO_INLINE
557ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
558 unsigned long hints)
559{
560 register unsigned long pa;
561 register unsigned long ci; /* coherent index */
562
563 /* We currently only support kernel addresses */
564 BUG_ON(sid != KERNEL_SPACE);
565
566 mtsp(sid,1);
567
568 /*
569 ** WORD 1 - low order word
570 ** "hints" parm includes the VALID bit!
571 ** "dep" clobbers the physical address offset bits as well.
572 */
573 pa = virt_to_phys(vba);
574 asm volatile("depw %1,31,12,%0" : "+r" (pa) : "r" (hints));
575 ((u32 *)pdir_ptr)[1] = (u32) pa;
576
577 /*
578 ** WORD 0 - high order word
579 */
580
581#ifdef __LP64__
582 /*
583 ** get bits 12:15 of physical address
584 ** shift bits 16:31 of physical address
585 ** and deposit them
586 */
587 asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa));
588 asm volatile ("extrd,u %1,31,16,%0" : "+r" (pa) : "r" (pa));
589 asm volatile ("depd %1,35,4,%0" : "+r" (pa) : "r" (ci));
590#else
591 pa = 0;
592#endif
593 /*
594 ** get CPU coherency index bits
595 ** Grab virtual index [0:11]
596 ** Deposit virt_idx bits into I/O PDIR word
597 */
86a61ee9 598 asm volatile ("lci %%r0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
1da177e4
LT		 599 asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci));
600 asm volatile ("depw %1,15,12,%0" : "+r" (pa) : "r" (ci));
601
602 ((u32 *)pdir_ptr)[0] = (u32) pa;
603
604
605 /* FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360)
606 ** PCX-U/U+ do. (eg C200/C240)
607 ** PCX-T'? Don't know. (eg C110 or similar K-class)
608 **
609 ** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit".
610 ** Hopefully we can patch (NOP) these out at boot time somehow.
611 **
612 ** "Since PCX-U employs an offset hash that is incompatible with
613 ** the real mode coherence index generation of U2, the PDIR entry
614 ** must be flushed to memory to retain coherence."
615 */
86a61ee9 616 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
1da177e4
LT		 617 asm volatile("sync");
618}
619
620/**
621 * ccio_clear_io_tlb - Remove stale entries from the I/O TLB.
622 * @ioc: The I/O Controller.
623 * @iovp: The I/O Virtual Page.
624 * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir.
625 *
626 * Purge invalid I/O PDIR entries from the I/O TLB.
627 *
628 * FIXME: Can we change the byte_cnt to pages_mapped?
629 */
630static CCIO_INLINE void
631ccio_clear_io_tlb(struct ioc *ioc, dma_addr_t iovp, size_t byte_cnt)
632{
633 u32 chain_size = 1 << ioc->chainid_shift;
634
635 iovp &= IOVP_MASK; /* clear offset bits, just want pagenum */
636 byte_cnt += chain_size;
637
638 while(byte_cnt > chain_size) {
86a61ee9 639 WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command);
1da177e4
LT		 640 iovp += chain_size;
641 byte_cnt -= chain_size;
642 }
643}
644
645/**
646 * ccio_mark_invalid - Mark the I/O Pdir entries invalid.
647 * @ioc: The I/O Controller.
648 * @iova: The I/O Virtual Address.
649 * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir.
650 *
651 * Mark the I/O Pdir entries invalid and blow away the corresponding I/O
652 * TLB entries.
653 *
654 * FIXME: at some threshhold it might be "cheaper" to just blow
655 * away the entire I/O TLB instead of individual entries.
656 *
657 * FIXME: Uturn has 256 TLB entries. We don't need to purge every
658 * PDIR entry - just once for each possible TLB entry.
659 * (We do need to maker I/O PDIR entries invalid regardless).
660 *
661 * FIXME: Can we change byte_cnt to pages_mapped?
662 */
663static CCIO_INLINE void
664ccio_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
665{
666 u32 iovp = (u32)CCIO_IOVP(iova);
667 size_t saved_byte_cnt;
668
669 /* round up to nearest page size */
670 saved_byte_cnt = byte_cnt = ROUNDUP(byte_cnt, IOVP_SIZE);
671
672 while(byte_cnt > 0) {
673 /* invalidate one page at a time */
674 unsigned int idx = PDIR_INDEX(iovp);
675 char *pdir_ptr = (char *) &(ioc->pdir_base[idx]);
676
677 BUG_ON(idx >= (ioc->pdir_size / sizeof(u64)));
678 pdir_ptr[7] = 0; /* clear only VALID bit */
679 /*
680 ** FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360)
681 ** PCX-U/U+ do. (eg C200/C240)
682 ** See PDC_MODEL/option 0/SW_CAP for "Non-coherent IO-PDIR bit".
683 **
684 ** Hopefully someone figures out how to patch (NOP) the
685 ** FDC/SYNC out at boot time.
686 */
86a61ee9 687 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr[7]));
1da177e4
LT		 688
689 iovp += IOVP_SIZE;
690 byte_cnt -= IOVP_SIZE;
691 }
692
693 asm volatile("sync");
694 ccio_clear_io_tlb(ioc, CCIO_IOVP(iova), saved_byte_cnt);
695}
696
697/****************************************************************
698**
699** CCIO dma_ops
700**
701*****************************************************************/
702
703/**
704 * ccio_dma_supported - Verify the IOMMU supports the DMA address range.
705 * @dev: The PCI device.
706 * @mask: A bit mask describing the DMA address range of the device.
707 *
708 * This function implements the pci_dma_supported function.
709 */
710static int
711ccio_dma_supported(struct device *dev, u64 mask)
712{
713 if(dev == NULL) {
714 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
715 BUG();
716 return 0;
717 }
718
719 /* only support 32-bit devices (ie PCI/GSC) */
720 return (int)(mask == 0xffffffffUL);
721}
722
723/**
724 * ccio_map_single - Map an address range into the IOMMU.
725 * @dev: The PCI device.
726 * @addr: The start address of the DMA region.
727 * @size: The length of the DMA region.
728 * @direction: The direction of the DMA transaction (to/from device).
729 *
730 * This function implements the pci_map_single function.
731 */
732static dma_addr_t
733ccio_map_single(struct device *dev, void *addr, size_t size,
734 enum dma_data_direction direction)
735{
736 int idx;
737 struct ioc *ioc;
738 unsigned long flags;
739 dma_addr_t iovp;
740 dma_addr_t offset;
741 u64 *pdir_start;
742 unsigned long hint = hint_lookup[(int)direction];
743
744 BUG_ON(!dev);
745 ioc = GET_IOC(dev);
746
747 BUG_ON(size <= 0);
748
749 /* save offset bits */
750 offset = ((unsigned long) addr) & ~IOVP_MASK;
751
752 /* round up to nearest IOVP_SIZE */
753 size = ROUNDUP(size + offset, IOVP_SIZE);
754 spin_lock_irqsave(&ioc->res_lock, flags);
755
756#ifdef CCIO_MAP_STATS
757 ioc->msingle_calls++;
758 ioc->msingle_pages += size >> IOVP_SHIFT;
759#endif
760
761 idx = ccio_alloc_range(ioc, size);
762 iovp = (dma_addr_t)MKIOVP(idx);
763
764 pdir_start = &(ioc->pdir_base[idx]);
765
766 DBG_RUN("%s() 0x%p -> 0x%lx size: %0x%x\n",
767 __FUNCTION__, addr, (long)iovp | offset, size);
768
769 /* If not cacheline aligned, force SAFE_DMA on the whole mess */
770 if((size % L1_CACHE_BYTES) || ((unsigned long)addr % L1_CACHE_BYTES))
771 hint |= HINT_SAFE_DMA;
772
773 while(size > 0) {
774 ccio_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long)addr, hint);
775
776 DBG_RUN(" pdir %p %08x%08x\n",
777 pdir_start,
778 (u32) (((u32 *) pdir_start)[0]),
779 (u32) (((u32 *) pdir_start)[1]));
780 ++pdir_start;
781 addr += IOVP_SIZE;
782 size -= IOVP_SIZE;
783 }
784
785 spin_unlock_irqrestore(&ioc->res_lock, flags);
786
787 /* form complete address */
788 return CCIO_IOVA(iovp, offset);
789}
790
791/**
792 * ccio_unmap_single - Unmap an address range from the IOMMU.
793 * @dev: The PCI device.
794 * @addr: The start address of the DMA region.
795 * @size: The length of the DMA region.
796 * @direction: The direction of the DMA transaction (to/from device).
797 *
798 * This function implements the pci_unmap_single function.
799 */
800static void
801ccio_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
802 enum dma_data_direction direction)
803{
804 struct ioc *ioc;
805 unsigned long flags;
806 dma_addr_t offset = iova & ~IOVP_MASK;
807
808 BUG_ON(!dev);
809 ioc = GET_IOC(dev);
810
811 DBG_RUN("%s() iovp 0x%lx/%x\n",
812 __FUNCTION__, (long)iova, size);
813
814 iova ^= offset; /* clear offset bits */
815 size += offset;
816 size = ROUNDUP(size, IOVP_SIZE);
817
818 spin_lock_irqsave(&ioc->res_lock, flags);
819
820#ifdef CCIO_MAP_STATS
821 ioc->usingle_calls++;
822 ioc->usingle_pages += size >> IOVP_SHIFT;
823#endif
824
825 ccio_mark_invalid(ioc, iova, size);
826 ccio_free_range(ioc, iova, (size >> IOVP_SHIFT));
827 spin_unlock_irqrestore(&ioc->res_lock, flags);
828}
829
830/**
831 * ccio_alloc_consistent - Allocate a consistent DMA mapping.
832 * @dev: The PCI device.
833 * @size: The length of the DMA region.
834 * @dma_handle: The DMA address handed back to the device (not the cpu).
835 *
836 * This function implements the pci_alloc_consistent function.
837 */
838static void *
5c1fb41f 839ccio_alloc_consistent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag)
1da177e4
LT		 840{
841 void *ret;
842#if 0
843/* GRANT Need to establish hierarchy for non-PCI devs as well
844** and then provide matching gsc_map_xxx() functions for them as well.
845*/
846 if(!hwdev) {
847 /* only support PCI */
848 *dma_handle = 0;
849 return 0;
850 }
851#endif
852 ret = (void *) __get_free_pages(flag, get_order(size));
853
854 if (ret) {
855 memset(ret, 0, size);
856 *dma_handle = ccio_map_single(dev, ret, size, PCI_DMA_BIDIRECTIONAL);
857 }
858
859 return ret;
860}
861
862/**
863 * ccio_free_consistent - Free a consistent DMA mapping.
864 * @dev: The PCI device.
865 * @size: The length of the DMA region.
866 * @cpu_addr: The cpu address returned from the ccio_alloc_consistent.
867 * @dma_handle: The device address returned from the ccio_alloc_consistent.
868 *
869 * This function implements the pci_free_consistent function.
870 */
871static void
872ccio_free_consistent(struct device *dev, size_t size, void *cpu_addr,
873 dma_addr_t dma_handle)
874{
875 ccio_unmap_single(dev, dma_handle, size, 0);
876 free_pages((unsigned long)cpu_addr, get_order(size));
877}
878
879/*
880** Since 0 is a valid pdir_base index value, can't use that
881** to determine if a value is valid or not. Use a flag to indicate
882** the SG list entry contains a valid pdir index.
883*/
884#define PIDE_FLAG 0x80000000UL
885
886#ifdef CCIO_MAP_STATS
887#define IOMMU_MAP_STATS
888#endif
889#include "iommu-helpers.h"
890
891/**
892 * ccio_map_sg - Map the scatter/gather list into the IOMMU.
893 * @dev: The PCI device.
894 * @sglist: The scatter/gather list to be mapped in the IOMMU.
895 * @nents: The number of entries in the scatter/gather list.
896 * @direction: The direction of the DMA transaction (to/from device).
897 *
898 * This function implements the pci_map_sg function.
899 */
900static int
901ccio_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
902 enum dma_data_direction direction)
903{
904 struct ioc *ioc;
905 int coalesced, filled = 0;
906 unsigned long flags;
907 unsigned long hint = hint_lookup[(int)direction];
908 unsigned long prev_len = 0, current_len = 0;
909 int i;
910
911 BUG_ON(!dev);
912 ioc = GET_IOC(dev);
913
914 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
915
916 /* Fast path single entry scatterlists. */
917 if (nents == 1) {
918 sg_dma_address(sglist) = ccio_map_single(dev,
919 (void *)sg_virt_addr(sglist), sglist->length,
920 direction);
921 sg_dma_len(sglist) = sglist->length;
922 return 1;
923 }
924
925 for(i = 0; i < nents; i++)
926 prev_len += sglist[i].length;
927
928 spin_lock_irqsave(&ioc->res_lock, flags);
929
930#ifdef CCIO_MAP_STATS
931 ioc->msg_calls++;
932#endif
933
934 /*
935 ** First coalesce the chunks and allocate I/O pdir space
936 **
937 ** If this is one DMA stream, we can properly map using the
938 ** correct virtual address associated with each DMA page.
939 ** w/o this association, we wouldn't have coherent DMA!
940 ** Access to the virtual address is what forces a two pass algorithm.
941 */
942 coalesced = iommu_coalesce_chunks(ioc, sglist, nents, ccio_alloc_range);
943
944 /*
945 ** Program the I/O Pdir
946 **
947 ** map the virtual addresses to the I/O Pdir
948 ** o dma_address will contain the pdir index
949 ** o dma_len will contain the number of bytes to map
950 ** o page/offset contain the virtual address.
951 */
952 filled = iommu_fill_pdir(ioc, sglist, nents, hint, ccio_io_pdir_entry);
953
954 spin_unlock_irqrestore(&ioc->res_lock, flags);
955
956 BUG_ON(coalesced != filled);
957
958 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
959
960 for (i = 0; i < filled; i++)
961 current_len += sg_dma_len(sglist + i);
962
963 BUG_ON(current_len != prev_len);
964
965 return filled;
966}
967
968/**
969 * ccio_unmap_sg - Unmap the scatter/gather list from the IOMMU.
970 * @dev: The PCI device.
971 * @sglist: The scatter/gather list to be unmapped from the IOMMU.
972 * @nents: The number of entries in the scatter/gather list.
973 * @direction: The direction of the DMA transaction (to/from device).
974 *
975 * This function implements the pci_unmap_sg function.
976 */
977static void
978ccio_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
979 enum dma_data_direction direction)
980{
981 struct ioc *ioc;
982
983 BUG_ON(!dev);
984 ioc = GET_IOC(dev);
985
986 DBG_RUN_SG("%s() START %d entries, %08lx,%x\n",
987 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
988
989#ifdef CCIO_MAP_STATS
990 ioc->usg_calls++;
991#endif
992
993 while(sg_dma_len(sglist) && nents--) {
994
995#ifdef CCIO_MAP_STATS
996 ioc->usg_pages += sg_dma_len(sglist) >> PAGE_SHIFT;
997#endif
998 ccio_unmap_single(dev, sg_dma_address(sglist),
999 sg_dma_len(sglist), direction);
1000 ++sglist;
1001 }
1002
1003 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1004}
1005
1006static struct hppa_dma_ops ccio_ops = {
1007 .dma_supported = ccio_dma_supported,
1008 .alloc_consistent = ccio_alloc_consistent,
1009 .alloc_noncoherent = ccio_alloc_consistent,
1010 .free_consistent = ccio_free_consistent,
1011 .map_single = ccio_map_single,
1012 .unmap_single = ccio_unmap_single,
1013 .map_sg = ccio_map_sg,
1014 .unmap_sg = ccio_unmap_sg,
1015 .dma_sync_single_for_cpu = NULL, /* NOP for U2/Uturn */
1016 .dma_sync_single_for_device = NULL, /* NOP for U2/Uturn */
1017 .dma_sync_sg_for_cpu = NULL, /* ditto */
1018 .dma_sync_sg_for_device = NULL, /* ditto */
1019};
1020
1021#ifdef CONFIG_PROC_FS
1022static int proc_append(char *src, int len, char **dst, off_t *offset, int *max)
1023{
1024 if (len < *offset) {
1025 *offset -= len;
1026 return 0;
1027 }
1028 if (*offset > 0) {
1029 src += *offset;
1030 len -= *offset;
1031 *offset = 0;
1032 }
1033 if (len > *max) {
1034 len = *max;
1035 }
1036 memcpy(*dst, src, len);
1037 *dst += len;
1038 *max -= len;
1039 return (*max == 0);
1040}
1041
1042static int ccio_proc_info(char *buf, char **start, off_t offset, int count,
1043 int *eof, void *data)
1044{
1045 int max = count;
1046 char tmp[80]; /* width of an ANSI-standard terminal */
1047 struct ioc *ioc = ioc_list;
1048
1049 while (ioc != NULL) {
1050 unsigned int total_pages = ioc->res_size << 3;
1051 unsigned long avg = 0, min, max;
1052 int j, len;
1053
1054 len = sprintf(tmp, "%s\n", ioc->name);
1055 if (proc_append(tmp, len, &buf, &offset, &count))
1056 break;
1057
1058 len = sprintf(tmp, "Cujo 2.0 bug : %s\n",
1059 (ioc->cujo20_bug ? "yes" : "no"));
1060 if (proc_append(tmp, len, &buf, &offset, &count))
1061 break;
1062
1063 len = sprintf(tmp, "IO PDIR size : %d bytes (%d entries)\n",
1064 total_pages * 8, total_pages);
1065 if (proc_append(tmp, len, &buf, &offset, &count))
1066 break;
1067#ifdef CCIO_MAP_STATS
1068 len = sprintf(tmp, "IO PDIR entries : %ld free %ld used (%d%%)\n",
1069 total_pages - ioc->used_pages, ioc->used_pages,
1070 (int)(ioc->used_pages * 100 / total_pages));
1071 if (proc_append(tmp, len, &buf, &offset, &count))
1072 break;
1073#endif
1074 len = sprintf(tmp, "Resource bitmap : %d bytes (%d pages)\n",
1075 ioc->res_size, total_pages);
1076 if (proc_append(tmp, len, &buf, &offset, &count))
1077 break;
1078#ifdef CCIO_SEARCH_TIME
1079 min = max = ioc->avg_search[0];
1080 for(j = 0; j < CCIO_SEARCH_SAMPLE; ++j) {
1081 avg += ioc->avg_search[j];
1082 if(ioc->avg_search[j] > max)
1083 max = ioc->avg_search[j];
1084 if(ioc->avg_search[j] < min)
1085 min = ioc->avg_search[j];
1086 }
1087 avg /= CCIO_SEARCH_SAMPLE;
1088 len = sprintf(tmp, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1089 min, avg, max);
1090 if (proc_append(tmp, len, &buf, &offset, &count))
1091 break;
1092#endif
1093#ifdef CCIO_MAP_STATS
1094 len = sprintf(tmp, "pci_map_single(): %8ld calls %8ld pages (avg %d/1000)\n",
1095 ioc->msingle_calls, ioc->msingle_pages,
1096 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1097 if (proc_append(tmp, len, &buf, &offset, &count))
1098 break;
1099
1100
1101 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1102 min = ioc->usingle_calls - ioc->usg_calls;
1103 max = ioc->usingle_pages - ioc->usg_pages;
1104 len = sprintf(tmp, "pci_unmap_single: %8ld calls %8ld pages (avg %d/1000)\n",
1105 min, max, (int)((max * 1000)/min));
1106 if (proc_append(tmp, len, &buf, &offset, &count))
1107 break;
1108
1109 len = sprintf(tmp, "pci_map_sg() : %8ld calls %8ld pages (avg %d/1000)\n",
1110 ioc->msg_calls, ioc->msg_pages,
1111 (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
1112 if (proc_append(tmp, len, &buf, &offset, &count))
1113 break;
1114 len = sprintf(tmp, "pci_unmap_sg() : %8ld calls %8ld pages (avg %d/1000)\n\n\n",
1115 ioc->usg_calls, ioc->usg_pages,
1116 (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
1117 if (proc_append(tmp, len, &buf, &offset, &count))
1118 break;
1119#endif /* CCIO_MAP_STATS */
1120 ioc = ioc->next;
1121 }
1122
1123 if (count == 0) {
1124 *eof = 1;
1125 }
1126 return (max - count);
1127}
1128
1129static int ccio_resource_map(char *buf, char **start, off_t offset, int len,
1130 int *eof, void *data)
1131{
1132 struct ioc *ioc = ioc_list;
1133
1134 buf[0] = '\0';
1135 while (ioc != NULL) {
1136 u32 *res_ptr = (u32 *)ioc->res_map;
1137 int j;
1138
1139 for (j = 0; j < (ioc->res_size / sizeof(u32)); j++) {
1140 if ((j & 7) == 0)
1141 strcat(buf,"\n ");
1142 sprintf(buf, "%s %08x", buf, *res_ptr);
1143 res_ptr++;
1144 }
1145 strcat(buf, "\n\n");
1146 ioc = ioc->next;
1147 break; /* XXX - remove me */
1148 }
1149
1150 return strlen(buf);
1151}
1152#endif
1153
1154/**
1155 * ccio_find_ioc - Find the ioc in the ioc_list
1156 * @hw_path: The hardware path of the ioc.
1157 *
1158 * This function searches the ioc_list for an ioc that matches
1159 * the provide hardware path.
1160 */
1161static struct ioc * ccio_find_ioc(int hw_path)
1162{
1163 int i;
1164 struct ioc *ioc;
1165
1166 ioc = ioc_list;
1167 for (i = 0; i < ioc_count; i++) {
1168 if (ioc->hw_path == hw_path)
1169 return ioc;
1170
1171 ioc = ioc->next;
1172 }
1173
1174 return NULL;
1175}
1176
1177/**
1178 * ccio_get_iommu - Find the iommu which controls this device
1179 * @dev: The parisc device.
1180 *
1181 * This function searches through the registered IOMMU's and returns
1182 * the appropriate IOMMU for the device based on its hardware path.
1183 */
1184void * ccio_get_iommu(const struct parisc_device *dev)
1185{
1186 dev = find_pa_parent_type(dev, HPHW_IOA);
1187 if (!dev)
1188 return NULL;
1189
1190 return ccio_find_ioc(dev->hw_path);
1191}
1192
1193#define CUJO_20_STEP 0x10000000 /* inc upper nibble */
1194
1195/* Cujo 2.0 has a bug which will silently corrupt data being transferred
1196 * to/from certain pages. To avoid this happening, we mark these pages
1197 * as `used', and ensure that nothing will try to allocate from them.
1198 */
1199void ccio_cujo20_fixup(struct parisc_device *cujo, u32 iovp)
1200{
1201 unsigned int idx;
1202 struct parisc_device *dev = parisc_parent(cujo);
1203 struct ioc *ioc = ccio_get_iommu(dev);
1204 u8 *res_ptr;
1205
1206 ioc->cujo20_bug = 1;
1207 res_ptr = ioc->res_map;
1208 idx = PDIR_INDEX(iovp) >> 3;
1209
1210 while (idx < ioc->res_size) {
1211 res_ptr[idx] |= 0xff;
1212 idx += PDIR_INDEX(CUJO_20_STEP) >> 3;
1213 }
1214}
1215
1216#if 0
1217/* GRANT - is this needed for U2 or not? */
1218
1219/*
1220** Get the size of the I/O TLB for this I/O MMU.
1221**
1222** If spa_shift is non-zero (ie probably U2),
1223** then calculate the I/O TLB size using spa_shift.
1224**
1225** Otherwise we are supposed to get the IODC entry point ENTRY TLB
1226** and execute it. However, both U2 and Uturn firmware supplies spa_shift.
1227** I think only Java (K/D/R-class too?) systems don't do this.
1228*/
1229static int
1230ccio_get_iotlb_size(struct parisc_device *dev)
1231{
1232 if (dev->spa_shift == 0) {
1233 panic("%s() : Can't determine I/O TLB size.\n", __FUNCTION__);
1234 }
1235 return (1 << dev->spa_shift);
1236}
1237#else
1238
1239/* Uturn supports 256 TLB entries */
1240#define CCIO_CHAINID_SHIFT 8
1241#define CCIO_CHAINID_MASK 0xff
1242#endif /* 0 */
1243
1244/* We *can't* support JAVA (T600). Venture there at your own risk. */
1245static struct parisc_device_id ccio_tbl[] = {
1246 { HPHW_IOA, HVERSION_REV_ANY_ID, U2_IOA_RUNWAY, 0xb }, /* U2 */
1247 { HPHW_IOA, HVERSION_REV_ANY_ID, UTURN_IOA_RUNWAY, 0xb }, /* UTurn */
1248 { 0, }
1249};
1250
1251static int ccio_probe(struct parisc_device *dev);
1252
1253static struct parisc_driver ccio_driver = {
bdad1f83 1254 .name = "ccio",
1da177e4
LT		 1255 .id_table = ccio_tbl,
1256 .probe = ccio_probe,
1257};
1258
1259/**
1260 * ccio_ioc_init - Initalize the I/O Controller
1261 * @ioc: The I/O Controller.
1262 *
1263 * Initalize the I/O Controller which includes setting up the
1264 * I/O Page Directory, the resource map, and initalizing the
1265 * U2/Uturn chip into virtual mode.
1266 */
1267static void
1268ccio_ioc_init(struct ioc *ioc)
1269{
1270 int i;
1271 unsigned int iov_order;
1272 u32 iova_space_size;
1273
1274 /*
1275 ** Determine IOVA Space size from memory size.
1276 **
1277 ** Ideally, PCI drivers would register the maximum number
1278 ** of DMA they can have outstanding for each device they
1279 ** own. Next best thing would be to guess how much DMA
1280 ** can be outstanding based on PCI Class/sub-class. Both
1281 ** methods still require some "extra" to support PCI
1282 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1283 */
1284
1285 iova_space_size = (u32) (num_physpages / count_parisc_driver(&ccio_driver));
1286
1287 /* limit IOVA space size to 1MB-1GB */
1288
1289 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1290 iova_space_size = 1 << (20 - PAGE_SHIFT);
1291#ifdef __LP64__
1292 } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1293 iova_space_size = 1 << (30 - PAGE_SHIFT);
1294#endif
1295 }
1296
1297 /*
1298 ** iova space must be log2() in size.
1299 ** thus, pdir/res_map will also be log2().
1300 */
1301
1302 /* We could use larger page sizes in order to *decrease* the number
1303 ** of mappings needed. (ie 8k pages means 1/2 the mappings).
1304 **
1305 ** Note: Grant Grunder says "Using 8k I/O pages isn't trivial either
1306 ** since the pages must also be physically contiguous - typically
1307 ** this is the case under linux."
1308 */
1309
1310 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1311
1312 /* iova_space_size is now bytes, not pages */
1313 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1314
1315 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1316
86a61ee9 1317 BUG_ON(ioc->pdir_size > 8 * 1024 * 1024); /* max pdir size <= 8MB */
1da177e4
LT		 1318
1319 /* Verify it's a power of two */
1320 BUG_ON((1 << get_order(ioc->pdir_size)) != (ioc->pdir_size >> PAGE_SHIFT));
1321
86a61ee9
GG		 1322 DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n",
1323 __FUNCTION__, ioc->ioc_regs,
1da177e4
LT		 1324 (unsigned long) num_physpages >> (20 - PAGE_SHIFT),
1325 iova_space_size>>20,
1326 iov_order + PAGE_SHIFT);
1327
1328 ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL,
1329 get_order(ioc->pdir_size));
1330 if(NULL == ioc->pdir_base) {
86a61ee9 1331 panic("%s() could not allocate I/O Page Table\n", __FUNCTION__);
1da177e4
LT		 1332 }
1333 memset(ioc->pdir_base, 0, ioc->pdir_size);
1334
1335 BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned long)ioc->pdir_base);
86a61ee9 1336 DBG_INIT(" base %p\n", ioc->pdir_base);
1da177e4
LT		 1337
1338 /* resource map size dictated by pdir_size */
1339 ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3;
1340 DBG_INIT("%s() res_size 0x%x\n", __FUNCTION__, ioc->res_size);
1341
1342 ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL,
1343 get_order(ioc->res_size));
1344 if(NULL == ioc->res_map) {
86a61ee9 1345 panic("%s() could not allocate resource map\n", __FUNCTION__);
1da177e4
LT		 1346 }
1347 memset(ioc->res_map, 0, ioc->res_size);
1348
1349 /* Initialize the res_hint to 16 */
1350 ioc->res_hint = 16;
1351
1352 /* Initialize the spinlock */
1353 spin_lock_init(&ioc->res_lock);
1354
1355 /*
1356 ** Chainid is the upper most bits of an IOVP used to determine
1357 ** which TLB entry an IOVP will use.
1358 */
1359 ioc->chainid_shift = get_order(iova_space_size) + PAGE_SHIFT - CCIO_CHAINID_SHIFT;
1360 DBG_INIT(" chainid_shift 0x%x\n", ioc->chainid_shift);
1361
1362 /*
1363 ** Initialize IOA hardware
1364 */
1365 WRITE_U32(CCIO_CHAINID_MASK << ioc->chainid_shift,
86a61ee9 1366 &ioc->ioc_regs->io_chain_id_mask);
1da177e4
LT		 1367
1368 WRITE_U32(virt_to_phys(ioc->pdir_base),
86a61ee9 1369 &ioc->ioc_regs->io_pdir_base);
1da177e4
LT		 1370
1371 /*
1372 ** Go to "Virtual Mode"
1373 */
86a61ee9 1374 WRITE_U32(IOA_NORMAL_MODE, &ioc->ioc_regs->io_control);
1da177e4
LT		 1375
1376 /*
1377 ** Initialize all I/O TLB entries to 0 (Valid bit off).
1378 */
86a61ee9
GG		 1379 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m);
1380 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l);
1da177e4
LT		 1381
1382 for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) {
1383 WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)),
86a61ee9 1384 &ioc->ioc_regs->io_command);
1da177e4
LT		 1385 }
1386}
1387
1388static void
86a61ee9 1389ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr)
1da177e4
LT		 1390{
1391 int result;
1392
1393 res->parent = NULL;
1394 res->flags = IORESOURCE_MEM;
86a61ee9
GG		 1395 /*
1396 * bracing ((signed) ...) are required for 64bit kernel because
1397 * we only want to sign extend the lower 16 bits of the register.
1398 * The upper 16-bits of range registers are hardcoded to 0xffff.
1399 */
1400 res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16);
1401 res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16) - 1);
1da177e4 1402 res->name = name;
86a61ee9
GG		 1403 /*
1404 * Check if this MMIO range is disable
1405 */
1da177e4
LT		 1406 if (res->end + 1 == res->start)
1407 return;
86a61ee9
GG		 1408
1409 /* On some platforms (e.g. K-Class), we have already registered
1410 * resources for devices reported by firmware. Some are children
1411 * of ccio.
1412 * "insert" ccio ranges in the mmio hierarchy (/proc/iomem).
1413 */
1414 result = insert_resource(&iomem_resource, res);
1da177e4 1415 if (result < 0) {
86a61ee9
GG		 1416 printk(KERN_ERR "%s() failed to claim CCIO bus address space (%08lx,%08lx)\n",
1417 __FUNCTION__, res->start, res->end);
1da177e4
LT		 1418 }
1419}
1420
1421static void __init ccio_init_resources(struct ioc *ioc)
1422{
1423 struct resource *res = ioc->mmio_region;
1424 char *name = kmalloc(14, GFP_KERNEL);
1425
cb6fc18e 1426 snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path);
1da177e4 1427
86a61ee9
GG		 1428 ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low);
1429 ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv);
1da177e4
LT		 1430}
1431
1432static int new_ioc_area(struct resource *res, unsigned long size,
1433 unsigned long min, unsigned long max, unsigned long align)
1434{
1435 if (max <= min)
1436 return -EBUSY;
1437
1438 res->start = (max - size + 1) &~ (align - 1);
1439 res->end = res->start + size;
86a61ee9
GG		 1440
1441 /* We might be trying to expand the MMIO range to include
1442 * a child device that has already registered it's MMIO space.
1443 * Use "insert" instead of request_resource().
1444 */
1445 if (!insert_resource(&iomem_resource, res))
1da177e4
LT		 1446 return 0;
1447
1448 return new_ioc_area(res, size, min, max - size, align);
1449}
1450
1451static int expand_ioc_area(struct resource *res, unsigned long size,
1452 unsigned long min, unsigned long max, unsigned long align)
1453{
1454 unsigned long start, len;
1455
1456 if (!res->parent)
1457 return new_ioc_area(res, size, min, max, align);
1458
1459 start = (res->start - size) &~ (align - 1);
1460 len = res->end - start + 1;
1461 if (start >= min) {
1462 if (!adjust_resource(res, start, len))
1463 return 0;
1464 }
1465
1466 start = res->start;
1467 len = ((size + res->end + align) &~ (align - 1)) - start;
1468 if (start + len <= max) {
1469 if (!adjust_resource(res, start, len))
1470 return 0;
1471 }
1472
1473 return -EBUSY;
1474}
1475
1476/*
1477 * Dino calls this function. Beware that we may get called on systems
1478 * which have no IOC (725, B180, C160L, etc) but do have a Dino.
1479 * So it's legal to find no parent IOC.
1480 *
1481 * Some other issues: one of the resources in the ioc may be unassigned.
1482 */
1483int ccio_allocate_resource(const struct parisc_device *dev,
1484 struct resource *res, unsigned long size,
1485 unsigned long min, unsigned long max, unsigned long align)
1486{
1487 struct resource *parent = &iomem_resource;
1488 struct ioc *ioc = ccio_get_iommu(dev);
1489 if (!ioc)
1490 goto out;
1491
1492 parent = ioc->mmio_region;
1493 if (parent->parent &&
1494 !allocate_resource(parent, res, size, min, max, align, NULL, NULL))
1495 return 0;
1496
1497 if ((parent + 1)->parent &&
1498 !allocate_resource(parent + 1, res, size, min, max, align,
1499 NULL, NULL))
1500 return 0;
1501
1502 if (!expand_ioc_area(parent, size, min, max, align)) {
1503 __raw_writel(((parent->start)>>16) | 0xffff0000,
86a61ee9 1504 &ioc->ioc_regs->io_io_low);
1da177e4 1505 __raw_writel(((parent->end)>>16) | 0xffff0000,
86a61ee9 1506 &ioc->ioc_regs->io_io_high);
1da177e4
LT		 1507 } else if (!expand_ioc_area(parent + 1, size, min, max, align)) {
1508 parent++;
1509 __raw_writel(((parent->start)>>16) | 0xffff0000,
86a61ee9 1510 &ioc->ioc_regs->io_io_low_hv);
1da177e4 1511 __raw_writel(((parent->end)>>16) | 0xffff0000,
86a61ee9 1512 &ioc->ioc_regs->io_io_high_hv);
1da177e4
LT		 1513 } else {
1514 return -EBUSY;
1515 }
1516
1517 out:
1518 return allocate_resource(parent, res, size, min, max, align, NULL,NULL);
1519}
1520
1521int ccio_request_resource(const struct parisc_device *dev,
1522 struct resource *res)
1523{
1524 struct resource *parent;
1525 struct ioc *ioc = ccio_get_iommu(dev);
1526
1527 if (!ioc) {
1528 parent = &iomem_resource;
1529 } else if ((ioc->mmio_region->start <= res->start) &&
1530 (res->end <= ioc->mmio_region->end)) {
1531 parent = ioc->mmio_region;
1532 } else if (((ioc->mmio_region + 1)->start <= res->start) &&
1533 (res->end <= (ioc->mmio_region + 1)->end)) {
1534 parent = ioc->mmio_region + 1;
1535 } else {
1536 return -EBUSY;
1537 }
1538
86a61ee9
GG		 1539 /* "transparent" bus bridges need to register MMIO resources
1540 * firmware assigned them. e.g. children of hppb.c (e.g. K-class)
1541 * registered their resources in the PDC "bus walk" (See
1542 * arch/parisc/kernel/inventory.c).
1543 */
1544 return insert_resource(parent, res);
1da177e4
LT		 1545}
1546
1547/**
1548 * ccio_probe - Determine if ccio should claim this device.
1549 * @dev: The device which has been found
1550 *
1551 * Determine if ccio should claim this chip (return 0) or not (return 1).
1552 * If so, initialize the chip and tell other partners in crime they
1553 * have work to do.
1554 */
1555static int ccio_probe(struct parisc_device *dev)
1556{
1557 int i;
1558 struct ioc *ioc, **ioc_p = &ioc_list;
1559
cb6fc18e 1560 ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL);
1da177e4
LT		 1561 if (ioc == NULL) {
1562 printk(KERN_ERR MODULE_NAME ": memory allocation failure\n");
1563 return 1;
1564 }
1da177e4
LT		 1565
1566 ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn";
1567
53f01bba 1568 printk(KERN_INFO "Found %s at 0x%lx\n", ioc->name, dev->hpa.start);
1da177e4
LT		 1569
1570 for (i = 0; i < ioc_count; i++) {
1571 ioc_p = &(*ioc_p)->next;
1572 }
1573 *ioc_p = ioc;
1574
1575 ioc->hw_path = dev->hw_path;
53f01bba 1576 ioc->ioc_regs = ioremap(dev->hpa.start, 4096);
1da177e4
LT		 1577 ccio_ioc_init(ioc);
1578 ccio_init_resources(ioc);
1579 hppa_dma_ops = &ccio_ops;
cb6fc18e 1580 dev->dev.platform_data = kzalloc(sizeof(struct pci_hba_data), GFP_KERNEL);
1da177e4
LT		 1581
1582 /* if this fails, no I/O cards will work, so may as well bug */
1583 BUG_ON(dev->dev.platform_data == NULL);
1584 HBA_DATA(dev->dev.platform_data)->iommu = ioc;
1585
1586
1587 if (ioc_count == 0) {
1588 /* FIXME: Create separate entries for each ioc */
1589 create_proc_read_entry(MODULE_NAME, S_IRWXU, proc_runway_root,
1590 ccio_proc_info, NULL);
1591 create_proc_read_entry(MODULE_NAME"-bitmap", S_IRWXU,
1592 proc_runway_root, ccio_resource_map, NULL);
1593 }
1594
1595 ioc_count++;
1596
1597 parisc_vmerge_boundary = IOVP_SIZE;
1598 parisc_vmerge_max_size = BITS_PER_LONG * IOVP_SIZE;
1599 parisc_has_iommu();
1600 return 0;
1601}
1602
1603/**
1604 * ccio_init - ccio initalization procedure.
1605 *
1606 * Register this driver.
1607 */
1608void __init ccio_init(void)
1609{
1610 register_parisc_driver(&ccio_driver);
1611}
1612
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