[net-next-2.6.git] / drivers / net / wireless / wl12xx / wl1271.h

/*
 * This file is part of wl1271
 *
 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
 * Copyright (C) 2008-2009 Nokia Corporation
 *
 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#ifndef __WL1271_H__
#define __WL1271_H__

#include <linux/mutex.h>
#include <linux/completion.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/bitops.h>
#include <net/mac80211.h>

#include "wl1271_conf.h"
#include "wl1271_ini.h"

#define DRIVER_NAME "wl1271"
#define DRIVER_PREFIX DRIVER_NAME ": "

enum {
	DEBUG_NONE	= 0,
	DEBUG_IRQ	= BIT(0),
	DEBUG_SPI	= BIT(1),
	DEBUG_BOOT	= BIT(2),
	DEBUG_MAILBOX	= BIT(3),
	DEBUG_TESTMODE	= BIT(4),
	DEBUG_EVENT	= BIT(5),
	DEBUG_TX	= BIT(6),
	DEBUG_RX	= BIT(7),
	DEBUG_SCAN	= BIT(8),
	DEBUG_CRYPT	= BIT(9),
	DEBUG_PSM	= BIT(10),
	DEBUG_MAC80211	= BIT(11),
	DEBUG_CMD	= BIT(12),
	DEBUG_ACX	= BIT(13),
	DEBUG_SDIO	= BIT(14),
	DEBUG_FILTERS   = BIT(15),
	DEBUG_ADHOC     = BIT(16),
	DEBUG_ALL	= ~0,
};

#define DEBUG_LEVEL (DEBUG_NONE)

#define DEBUG_DUMP_LIMIT 1024

#define wl1271_error(fmt, arg...) \
	printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg)

#define wl1271_warning(fmt, arg...) \
	printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg)

#define wl1271_notice(fmt, arg...) \
	printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg)

#define wl1271_info(fmt, arg...) \
	printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg)

#define wl1271_debug(level, fmt, arg...) \
	do { \
		if (level & DEBUG_LEVEL) \
			printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \
	} while (0)

#define wl1271_dump(level, prefix, buf, len)	\
	do { \
		if (level & DEBUG_LEVEL) \
			print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
				       DUMP_PREFIX_OFFSET, 16, 1,	\
				       buf,				\
				       min_t(size_t, len, DEBUG_DUMP_LIMIT), \
				       0);				\
	} while (0)

#define wl1271_dump_ascii(level, prefix, buf, len)	\
	do { \
		if (level & DEBUG_LEVEL) \
			print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
				       DUMP_PREFIX_OFFSET, 16, 1,	\
				       buf,				\
				       min_t(size_t, len, DEBUG_DUMP_LIMIT), \
				       true);				\
	} while (0)

#define WL1271_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN |	\
				  CFG_BSSID_FILTER_EN | \
				  CFG_MC_FILTER_EN)

#define WL1271_DEFAULT_RX_FILTER (CFG_RX_RCTS_ACK | CFG_RX_PRSP_EN |  \
				  CFG_RX_MGMT_EN | CFG_RX_DATA_EN |   \
				  CFG_RX_CTL_EN | CFG_RX_BCN_EN |     \
				  CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)

#define WL1271_FW_NAME "wl1271-fw.bin"
#define WL1271_NVS_NAME "wl1271-nvs.bin"

#define WL1271_TX_SECURITY_LO16(s) ((u16)((s) & 0xffff))
#define WL1271_TX_SECURITY_HI32(s) ((u32)(((s) >> 16) & 0xffffffff))

#define WL1271_CIPHER_SUITE_GEM 0x00147201

#define WL1271_BUSY_WORD_CNT 1
#define WL1271_BUSY_WORD_LEN (WL1271_BUSY_WORD_CNT * sizeof(u32))

#define WL1271_ELP_HW_STATE_ASLEEP 0
#define WL1271_ELP_HW_STATE_IRQ    1

#define WL1271_DEFAULT_BEACON_INT  100
#define WL1271_DEFAULT_DTIM_PERIOD 1

#define ACX_TX_DESCRIPTORS         32

#define WL1271_AGGR_BUFFER_SIZE (4 * PAGE_SIZE)

enum wl1271_state {
	WL1271_STATE_OFF,
	WL1271_STATE_ON,
	WL1271_STATE_PLT,
};

enum wl1271_partition_type {
	PART_DOWN,
	PART_WORK,
	PART_DRPW,

	PART_TABLE_LEN
};

struct wl1271_partition {
	u32 size;
	u32 start;
};

struct wl1271_partition_set {
	struct wl1271_partition mem;
	struct wl1271_partition reg;
	struct wl1271_partition mem2;
	struct wl1271_partition mem3;
};

struct wl1271;

/* FIXME: I'm not sure about this structure name */
struct wl1271_chip {
	u32 id;
	char fw_ver[21];
};

struct wl1271_stats {
	struct acx_statistics *fw_stats;
	unsigned long fw_stats_update;

	unsigned int retry_count;
	unsigned int excessive_retries;
};

struct wl1271_debugfs {
	struct dentry *rootdir;
	struct dentry *fw_statistics;

	struct dentry *tx_internal_desc_overflow;

	struct dentry *rx_out_of_mem;
	struct dentry *rx_hdr_overflow;
	struct dentry *rx_hw_stuck;
	struct dentry *rx_dropped;
	struct dentry *rx_fcs_err;
	struct dentry *rx_xfr_hint_trig;
	struct dentry *rx_path_reset;
	struct dentry *rx_reset_counter;

	struct dentry *dma_rx_requested;
	struct dentry *dma_rx_errors;
	struct dentry *dma_tx_requested;
	struct dentry *dma_tx_errors;

	struct dentry *isr_cmd_cmplt;
	struct dentry *isr_fiqs;
	struct dentry *isr_rx_headers;
	struct dentry *isr_rx_mem_overflow;
	struct dentry *isr_rx_rdys;
	struct dentry *isr_irqs;
	struct dentry *isr_tx_procs;
	struct dentry *isr_decrypt_done;
	struct dentry *isr_dma0_done;
	struct dentry *isr_dma1_done;
	struct dentry *isr_tx_exch_complete;
	struct dentry *isr_commands;
	struct dentry *isr_rx_procs;
	struct dentry *isr_hw_pm_mode_changes;
	struct dentry *isr_host_acknowledges;
	struct dentry *isr_pci_pm;
	struct dentry *isr_wakeups;
	struct dentry *isr_low_rssi;

	struct dentry *wep_addr_key_count;
	struct dentry *wep_default_key_count;
	/* skipping wep.reserved */
	struct dentry *wep_key_not_found;
	struct dentry *wep_decrypt_fail;
	struct dentry *wep_packets;
	struct dentry *wep_interrupt;

	struct dentry *pwr_ps_enter;
	struct dentry *pwr_elp_enter;
	struct dentry *pwr_missing_bcns;
	struct dentry *pwr_wake_on_host;
	struct dentry *pwr_wake_on_timer_exp;
	struct dentry *pwr_tx_with_ps;
	struct dentry *pwr_tx_without_ps;
	struct dentry *pwr_rcvd_beacons;
	struct dentry *pwr_power_save_off;
	struct dentry *pwr_enable_ps;
	struct dentry *pwr_disable_ps;
	struct dentry *pwr_fix_tsf_ps;
	/* skipping cont_miss_bcns_spread for now */
	struct dentry *pwr_rcvd_awake_beacons;

	struct dentry *mic_rx_pkts;
	struct dentry *mic_calc_failure;

	struct dentry *aes_encrypt_fail;
	struct dentry *aes_decrypt_fail;
	struct dentry *aes_encrypt_packets;
	struct dentry *aes_decrypt_packets;
	struct dentry *aes_encrypt_interrupt;
	struct dentry *aes_decrypt_interrupt;

	struct dentry *event_heart_beat;
	struct dentry *event_calibration;
	struct dentry *event_rx_mismatch;
	struct dentry *event_rx_mem_empty;
	struct dentry *event_rx_pool;
	struct dentry *event_oom_late;
	struct dentry *event_phy_transmit_error;
	struct dentry *event_tx_stuck;

	struct dentry *ps_pspoll_timeouts;
	struct dentry *ps_upsd_timeouts;
	struct dentry *ps_upsd_max_sptime;
	struct dentry *ps_upsd_max_apturn;
	struct dentry *ps_pspoll_max_apturn;
	struct dentry *ps_pspoll_utilization;
	struct dentry *ps_upsd_utilization;

	struct dentry *rxpipe_rx_prep_beacon_drop;
	struct dentry *rxpipe_descr_host_int_trig_rx_data;
	struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data;
	struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data;
	struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data;

	struct dentry *tx_queue_len;

	struct dentry *retry_count;
	struct dentry *excessive_retries;
	struct dentry *gpio_power;
};

#define NUM_TX_QUEUES              4
#define NUM_RX_PKT_DESC            8

/* FW status registers */
struct wl1271_fw_status {
	__le32 intr;
	u8  fw_rx_counter;
	u8  drv_rx_counter;
	u8  reserved;
	u8  tx_results_counter;
	__le32 rx_pkt_descs[NUM_RX_PKT_DESC];
	__le32 tx_released_blks[NUM_TX_QUEUES];
	__le32 fw_localtime;
	__le32 padding[2];
} __packed;

struct wl1271_rx_mem_pool_addr {
	u32 addr;
	u32 addr_extra;
};

struct wl1271_scan {
	struct cfg80211_scan_request *req;
	bool *scanned_ch;
	bool failed;
	u8 state;
	u8 ssid[IW_ESSID_MAX_SIZE+1];
	size_t ssid_len;
};

struct wl1271_if_operations {
	void (*read)(struct wl1271 *wl, int addr, void *buf, size_t len,
		     bool fixed);
	void (*write)(struct wl1271 *wl, int addr, void *buf, size_t len,
		     bool fixed);
	void (*reset)(struct wl1271 *wl);
	void (*init)(struct wl1271 *wl);
	int (*power)(struct wl1271 *wl, bool enable);
	struct device* (*dev)(struct wl1271 *wl);
	void (*enable_irq)(struct wl1271 *wl);
	void (*disable_irq)(struct wl1271 *wl);
};

struct wl1271 {
	struct platform_device *plat_dev;
	struct ieee80211_hw *hw;
	bool mac80211_registered;

	void *if_priv;

	struct wl1271_if_operations *if_ops;

	void (*set_power)(bool enable);
	int irq;
	int ref_clock;

	spinlock_t wl_lock;

	enum wl1271_state state;
	struct mutex mutex;

#define WL1271_FLAG_STA_RATES_CHANGED  (0)
#define WL1271_FLAG_STA_ASSOCIATED     (1)
#define WL1271_FLAG_JOINED             (2)
#define WL1271_FLAG_GPIO_POWER         (3)
#define WL1271_FLAG_TX_QUEUE_STOPPED   (4)
#define WL1271_FLAG_IN_ELP             (5)
#define WL1271_FLAG_PSM                (6)
#define WL1271_FLAG_PSM_REQUESTED      (7)
#define WL1271_FLAG_IRQ_PENDING        (8)
#define WL1271_FLAG_IRQ_RUNNING        (9)
#define WL1271_FLAG_IDLE              (10)
#define WL1271_FLAG_IDLE_REQUESTED    (11)
#define WL1271_FLAG_PSPOLL_FAILURE    (12)
#define WL1271_FLAG_STA_STATE_SENT    (13)
#define WL1271_FLAG_FW_TX_BUSY        (14)
	unsigned long flags;

	struct wl1271_partition_set part;

	struct wl1271_chip chip;

	int cmd_box_addr;
	int event_box_addr;

	u8 *fw;
	size_t fw_len;
	struct wl1271_nvs_file *nvs;
	size_t nvs_len;

	s8 hw_pg_ver;

	u8 bssid[ETH_ALEN];
	u8 mac_addr[ETH_ALEN];
	u8 bss_type;
	u8 set_bss_type;
	u8 ssid[IW_ESSID_MAX_SIZE + 1];
	u8 ssid_len;
	int channel;

	struct wl1271_acx_mem_map *target_mem_map;

	/* Accounting for allocated / available TX blocks on HW */
	u32 tx_blocks_freed[NUM_TX_QUEUES];
	u32 tx_blocks_available;
	u32 tx_results_count;

	/* Transmitted TX packets counter for chipset interface */
	u32 tx_packets_count;

	/* Time-offset between host and chipset clocks */
	s64 time_offset;

	/* Session counter for the chipset */
	int session_counter;

	/* Frames scheduled for transmission, not handled yet */
	struct sk_buff_head tx_queue;

	struct work_struct tx_work;

	/* Pending TX frames */
	unsigned long tx_frames_map[BITS_TO_LONGS(ACX_TX_DESCRIPTORS)];
	struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS];
	int tx_frames_cnt;

	/* Security sequence number counters */
	u8 tx_security_last_seq;
	s64 tx_security_seq;

	/* FW Rx counter */
	u32 rx_counter;

	/* Rx memory pool address */
	struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;

	/* Intermediate buffer, used for packet aggregation */
	u8 *aggr_buf;

	/* The target interrupt mask */
	struct work_struct irq_work;

	/* Hardware recovery work */
	struct work_struct recovery_work;

	/* The mbox event mask */
	u32 event_mask;

	/* Mailbox pointers */
	u32 mbox_ptr[2];

	/* Are we currently scanning */
	struct wl1271_scan scan;
	struct delayed_work scan_complete_work;

	/* Our association ID */
	u16 aid;

	/* currently configured rate set */
	u32 sta_rate_set;
	u32 basic_rate_set;
	u32 basic_rate;
	u32 rate_set;

	/* The current band */
	enum ieee80211_band band;

	/* Beaconing interval (needed for ad-hoc) */
	u32 beacon_int;

	/* Default key (for WEP) */
	u32 default_key;

	unsigned int filters;
	unsigned int rx_config;
	unsigned int rx_filter;

	struct completion *elp_compl;
	struct delayed_work elp_work;
	struct delayed_work pspoll_work;

	/* counter for ps-poll delivery failures */
	int ps_poll_failures;

	/* retry counter for PSM entries */
	u8 psm_entry_retry;

	/* in dBm */
	int power_level;

	int rssi_thold;
	int last_rssi_event;

	struct wl1271_stats stats;
	struct wl1271_debugfs debugfs;

	__le32 buffer_32;
	u32 buffer_cmd;
	u32 buffer_busyword[WL1271_BUSY_WORD_CNT];

	struct wl1271_fw_status *fw_status;
	struct wl1271_tx_hw_res_if *tx_res_if;

	struct ieee80211_vif *vif;

	/* Current chipset configuration */
	struct conf_drv_settings conf;

	bool sg_enabled;

	bool enable_11a;

	struct list_head list;

	/* Most recently reported noise in dBm */
	s8 noise;
};

int wl1271_plt_start(struct wl1271 *wl);
int wl1271_plt_stop(struct wl1271 *wl);

#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */

#define SESSION_COUNTER_MAX 7 /* maximum value for the session counter */

#define WL1271_DEFAULT_POWER_LEVEL 0

#define WL1271_TX_QUEUE_LOW_WATERMARK  10
#define WL1271_TX_QUEUE_HIGH_WATERMARK 25

/* WL1271 needs a 200ms sleep after power on, and a 20ms sleep before power
   on in case is has been shut down shortly before */
#define WL1271_PRE_POWER_ON_SLEEP 20 /* in miliseconds */
#define WL1271_POWER_ON_SLEEP 200 /* in miliseconds */

#endif
Commit	Line	Data
f5fc0f86 LC	1	/*
	2	* This file is part of wl1271
	3	*
	4	* Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
	5	* Copyright (C) 2008-2009 Nokia Corporation
	6	*
	7	* Contact: Luciano Coelho <luciano.coelho@nokia.com>
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	16	* General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	21	* 02110-1301 USA
	22	*
	23	*/
	24
	25	#ifndef __WL1271_H__
	26	#define __WL1271_H__
	27
	28	#include <linux/mutex.h>
	29	#include <linux/completion.h>
	30	#include <linux/spinlock.h>
	31	#include <linux/list.h>
	32	#include <linux/bitops.h>
	33	#include <net/mac80211.h>
	34
2b60100b	35	#include "wl1271_conf.h"
eb70eb72	36	#include "wl1271_ini.h"
2b60100b	37
f5fc0f86 LC	38	#define DRIVER_NAME "wl1271"
	39	#define DRIVER_PREFIX DRIVER_NAME ": "
	40
	41	enum {
	42	DEBUG_NONE = 0,
	43	DEBUG_IRQ = BIT(0),
	44	DEBUG_SPI = BIT(1),
	45	DEBUG_BOOT = BIT(2),
	46	DEBUG_MAILBOX = BIT(3),
c8c90873	47	DEBUG_TESTMODE = BIT(4),
f5fc0f86 LC	48	DEBUG_EVENT = BIT(5),
	49	DEBUG_TX = BIT(6),
	50	DEBUG_RX = BIT(7),
	51	DEBUG_SCAN = BIT(8),
	52	DEBUG_CRYPT = BIT(9),
	53	DEBUG_PSM = BIT(10),
	54	DEBUG_MAC80211 = BIT(11),
	55	DEBUG_CMD = BIT(12),
	56	DEBUG_ACX = BIT(13),
a3b8ea75	57	DEBUG_SDIO = BIT(14),
14b228a0	58	DEBUG_FILTERS = BIT(15),
5da11dcd	59	DEBUG_ADHOC = BIT(16),
f5fc0f86 LC	60	DEBUG_ALL = ~0,
	61	};
	62
	63	#define DEBUG_LEVEL (DEBUG_NONE)
	64
	65	#define DEBUG_DUMP_LIMIT 1024
	66
	67	#define wl1271_error(fmt, arg...) \
	68	printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg)
	69
	70	#define wl1271_warning(fmt, arg...) \
	71	printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg)
	72
	73	#define wl1271_notice(fmt, arg...) \
	74	printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg)
	75
	76	#define wl1271_info(fmt, arg...) \
	77	printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg)
	78
	79	#define wl1271_debug(level, fmt, arg...) \
	80	do { \
	81	if (level & DEBUG_LEVEL) \
	82	printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \
	83	} while (0)
	84
	85	#define wl1271_dump(level, prefix, buf, len) \
	86	do { \
	87	if (level & DEBUG_LEVEL) \
	88	print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
	89	DUMP_PREFIX_OFFSET, 16, 1, \
	90	buf, \
	91	min_t(size_t, len, DEBUG_DUMP_LIMIT), \
	92	0); \
	93	} while (0)
	94
	95	#define wl1271_dump_ascii(level, prefix, buf, len) \
	96	do { \
	97	if (level & DEBUG_LEVEL) \
	98	print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
	99	DUMP_PREFIX_OFFSET, 16, 1, \
	100	buf, \
	101	min_t(size_t, len, DEBUG_DUMP_LIMIT), \
	102	true); \
	103	} while (0)
	104
	105	#define WL1271_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN \| \
c87dec9f JO	106	CFG_BSSID_FILTER_EN \| \
c87dec9f JO	107	CFG_MC_FILTER_EN)
f5fc0f86 LC	108
	109	#define WL1271_DEFAULT_RX_FILTER (CFG_RX_RCTS_ACK \| CFG_RX_PRSP_EN \| \
	110	CFG_RX_MGMT_EN \| CFG_RX_DATA_EN \| \
	111	CFG_RX_CTL_EN \| CFG_RX_BCN_EN \| \
	112	CFG_RX_AUTH_EN \| CFG_RX_ASSOC_EN)
	113
	114	#define WL1271_FW_NAME "wl1271-fw.bin"
	115	#define WL1271_NVS_NAME "wl1271-nvs.bin"
152ee6e0	116
04e36fc5 JO	117	#define WL1271_TX_SECURITY_LO16(s) ((u16)((s) & 0xffff))
	118	#define WL1271_TX_SECURITY_HI32(s) ((u32)(((s) >> 16) & 0xffffffff))
	119
7a55724e JO	120	#define WL1271_CIPHER_SUITE_GEM 0x00147201
7a55724e JO	121
259da430	122	#define WL1271_BUSY_WORD_CNT 1
545f1da8	123	#define WL1271_BUSY_WORD_LEN (WL1271_BUSY_WORD_CNT * sizeof(u32))
f5fc0f86 LC	124
	125	#define WL1271_ELP_HW_STATE_ASLEEP 0
	126	#define WL1271_ELP_HW_STATE_IRQ 1
	127
d94cd297 JO	128	#define WL1271_DEFAULT_BEACON_INT 100
	129	#define WL1271_DEFAULT_DTIM_PERIOD 1
	130
c87dec9f	131	#define ACX_TX_DESCRIPTORS 32
be7078c2	132
1f37cbc9 IY	133	#define WL1271_AGGR_BUFFER_SIZE (4 * PAGE_SIZE)
1f37cbc9 IY	134
f5fc0f86 LC	135	enum wl1271_state {
	136	WL1271_STATE_OFF,
	137	WL1271_STATE_ON,
	138	WL1271_STATE_PLT,
	139	};
	140
	141	enum wl1271_partition_type {
	142	PART_DOWN,
	143	PART_WORK,
	144	PART_DRPW,
	145
	146	PART_TABLE_LEN
	147	};
	148
	149	struct wl1271_partition {
	150	u32 size;
	151	u32 start;
	152	};
	153
	154	struct wl1271_partition_set {
	155	struct wl1271_partition mem;
	156	struct wl1271_partition reg;
451de97a JO	157	struct wl1271_partition mem2;
451de97a JO	158	struct wl1271_partition mem3;
f5fc0f86 LC	159	};
	160
	161	struct wl1271;
	162
	163	/* FIXME: I'm not sure about this structure name */
	164	struct wl1271_chip {
	165	u32 id;
	166	char fw_ver[21];
	167	};
	168
	169	struct wl1271_stats {
	170	struct acx_statistics *fw_stats;
	171	unsigned long fw_stats_update;
	172
	173	unsigned int retry_count;
	174	unsigned int excessive_retries;
	175	};
	176
	177	struct wl1271_debugfs {
	178	struct dentry *rootdir;
	179	struct dentry *fw_statistics;
	180
	181	struct dentry *tx_internal_desc_overflow;
	182
	183	struct dentry *rx_out_of_mem;
	184	struct dentry *rx_hdr_overflow;
	185	struct dentry *rx_hw_stuck;
	186	struct dentry *rx_dropped;
	187	struct dentry *rx_fcs_err;
	188	struct dentry *rx_xfr_hint_trig;
	189	struct dentry *rx_path_reset;
	190	struct dentry *rx_reset_counter;
	191
	192	struct dentry *dma_rx_requested;
	193	struct dentry *dma_rx_errors;
	194	struct dentry *dma_tx_requested;
	195	struct dentry *dma_tx_errors;
	196
	197	struct dentry *isr_cmd_cmplt;
	198	struct dentry *isr_fiqs;
	199	struct dentry *isr_rx_headers;
	200	struct dentry *isr_rx_mem_overflow;
	201	struct dentry *isr_rx_rdys;
	202	struct dentry *isr_irqs;
	203	struct dentry *isr_tx_procs;
	204	struct dentry *isr_decrypt_done;
	205	struct dentry *isr_dma0_done;
	206	struct dentry *isr_dma1_done;
	207	struct dentry *isr_tx_exch_complete;
	208	struct dentry *isr_commands;
	209	struct dentry *isr_rx_procs;
	210	struct dentry *isr_hw_pm_mode_changes;
	211	struct dentry *isr_host_acknowledges;
	212	struct dentry *isr_pci_pm;
	213	struct dentry *isr_wakeups;
	214	struct dentry *isr_low_rssi;
	215
	216	struct dentry *wep_addr_key_count;
	217	struct dentry *wep_default_key_count;
	218	/* skipping wep.reserved */
	219	struct dentry *wep_key_not_found;
	220	struct dentry *wep_decrypt_fail;
	221	struct dentry *wep_packets;
	222	struct dentry *wep_interrupt;
223
224	struct dentry *pwr_ps_enter;
225	struct dentry *pwr_elp_enter;
226	struct dentry *pwr_missing_bcns;
227	struct dentry *pwr_wake_on_host;
228	struct dentry *pwr_wake_on_timer_exp;
229	struct dentry *pwr_tx_with_ps;
230	struct dentry *pwr_tx_without_ps;
231	struct dentry *pwr_rcvd_beacons;
232	struct dentry *pwr_power_save_off;
233	struct dentry *pwr_enable_ps;
234	struct dentry *pwr_disable_ps;
235	struct dentry *pwr_fix_tsf_ps;
236	/* skipping cont_miss_bcns_spread for now */
237	struct dentry *pwr_rcvd_awake_beacons;
238
239	struct dentry *mic_rx_pkts;
240	struct dentry *mic_calc_failure;
241
242	struct dentry *aes_encrypt_fail;
243	struct dentry *aes_decrypt_fail;
244	struct dentry *aes_encrypt_packets;
245	struct dentry *aes_decrypt_packets;
246	struct dentry *aes_encrypt_interrupt;
247	struct dentry *aes_decrypt_interrupt;
248
249	struct dentry *event_heart_beat;
250	struct dentry *event_calibration;
251	struct dentry *event_rx_mismatch;
252	struct dentry *event_rx_mem_empty;
253	struct dentry *event_rx_pool;
254	struct dentry *event_oom_late;
255	struct dentry *event_phy_transmit_error;
256	struct dentry *event_tx_stuck;
257
258	struct dentry *ps_pspoll_timeouts;
259	struct dentry *ps_upsd_timeouts;
260	struct dentry *ps_upsd_max_sptime;
261	struct dentry *ps_upsd_max_apturn;
262	struct dentry *ps_pspoll_max_apturn;
263	struct dentry *ps_pspoll_utilization;
264	struct dentry *ps_upsd_utilization;
265
266	struct dentry *rxpipe_rx_prep_beacon_drop;
267	struct dentry *rxpipe_descr_host_int_trig_rx_data;
268	struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data;
269	struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data;
270	struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data;
271
272	struct dentry *tx_queue_len;
273
274	struct dentry *retry_count;
275	struct dentry *excessive_retries;
98b2a684	276	struct dentry *gpio_power;
f5fc0f86 LC	277	};
	278
	279	#define NUM_TX_QUEUES 4
	280	#define NUM_RX_PKT_DESC 8
	281
	282	/* FW status registers */
	283	struct wl1271_fw_status {
d0f63b20	284	__le32 intr;
f5fc0f86 LC	285	u8 fw_rx_counter;
	286	u8 drv_rx_counter;
	287	u8 reserved;
	288	u8 tx_results_counter;
d0f63b20 LC	289	__le32 rx_pkt_descs[NUM_RX_PKT_DESC];
	290	__le32 tx_released_blks[NUM_TX_QUEUES];
	291	__le32 fw_localtime;
	292	__le32 padding[2];
ba2d3587	293	} __packed;
f5fc0f86 LC	294
	295	struct wl1271_rx_mem_pool_addr {
	296	u32 addr;
	297	u32 addr_extra;
	298	};
	299
abb0b3bf	300	struct wl1271_scan {
4fb26fa9	301	struct cfg80211_scan_request *req;
08688d6b	302	bool *scanned_ch;
78abd320	303	bool failed;
abb0b3bf TP	304	u8 state;
	305	u8 ssid[IW_ESSID_MAX_SIZE+1];
	306	size_t ssid_len;
abb0b3bf TP	307	};
abb0b3bf TP	308
8197b711 TP	309	struct wl1271_if_operations {
	310	void (read)(struct wl1271 wl, int addr, void *buf, size_t len,
	311	bool fixed);
	312	void (write)(struct wl1271 wl, int addr, void *buf, size_t len,
	313	bool fixed);
	314	void (reset)(struct wl1271 wl);
	315	void (init)(struct wl1271 wl);
2cc78ff7	316	int (power)(struct wl1271 wl, bool enable);
8197b711 TP	317	struct device* (dev)(struct wl1271 wl);
	318	void (enable_irq)(struct wl1271 wl);
	319	void (disable_irq)(struct wl1271 wl);
	320	};
	321
f5fc0f86	322	struct wl1271 {
3b56dd6a	323	struct platform_device *plat_dev;
f5fc0f86 LC	324	struct ieee80211_hw *hw;
	325	bool mac80211_registered;
	326
8197b711 TP	327	void *if_priv;
	328
	329	struct wl1271_if_operations *if_ops;
f5fc0f86 LC	330
	331	void (*set_power)(bool enable);
	332	int irq;
15cea993	333	int ref_clock;
f5fc0f86 LC	334
	335	spinlock_t wl_lock;
	336
	337	enum wl1271_state state;
	338	struct mutex mutex;
	339
830fb67b JO	340	#define WL1271_FLAG_STA_RATES_CHANGED (0)
830fb67b JO	341	#define WL1271_FLAG_STA_ASSOCIATED (1)
71449f8d JO	342	#define WL1271_FLAG_JOINED (2)
	343	#define WL1271_FLAG_GPIO_POWER (3)
	344	#define WL1271_FLAG_TX_QUEUE_STOPPED (4)
08688d6b LC	345	#define WL1271_FLAG_IN_ELP (5)
	346	#define WL1271_FLAG_PSM (6)
	347	#define WL1271_FLAG_PSM_REQUESTED (7)
	348	#define WL1271_FLAG_IRQ_PENDING (8)
	349	#define WL1271_FLAG_IRQ_RUNNING (9)
	350	#define WL1271_FLAG_IDLE (10)
	351	#define WL1271_FLAG_IDLE_REQUESTED (11)
	352	#define WL1271_FLAG_PSPOLL_FAILURE (12)
c2c192ac	353	#define WL1271_FLAG_STA_STATE_SENT (13)
a522550a	354	#define WL1271_FLAG_FW_TX_BUSY (14)
830fb67b JO	355	unsigned long flags;
830fb67b JO	356
451de97a	357	struct wl1271_partition_set part;
f5fc0f86 LC	358
	359	struct wl1271_chip chip;
	360
	361	int cmd_box_addr;
	362	int event_box_addr;
	363
	364	u8 *fw;
	365	size_t fw_len;
152ee6e0	366	struct wl1271_nvs_file *nvs;
02fabb0e	367	size_t nvs_len;
f5fc0f86	368
d717fd61 JO	369	s8 hw_pg_ver;
d717fd61 JO	370
f5fc0f86 LC	371	u8 bssid[ETH_ALEN];
	372	u8 mac_addr[ETH_ALEN];
	373	u8 bss_type;
5da11dcd	374	u8 set_bss_type;
f5fc0f86 LC	375	u8 ssid[IW_ESSID_MAX_SIZE + 1];
f5fc0f86 LC	376	u8 ssid_len;
f5fc0f86 LC	377	int channel;
	378
	379	struct wl1271_acx_mem_map *target_mem_map;
	380
	381	/* Accounting for allocated / available TX blocks on HW */
	382	u32 tx_blocks_freed[NUM_TX_QUEUES];
	383	u32 tx_blocks_available;
ffb591cd	384	u32 tx_results_count;
f5fc0f86 LC	385
f5fc0f86 LC	386	/* Transmitted TX packets counter for chipset interface */
ffb591cd	387	u32 tx_packets_count;
f5fc0f86 LC	388
f5fc0f86 LC	389	/* Time-offset between host and chipset clocks */
ac5e1e39	390	s64 time_offset;
f5fc0f86 LC	391
	392	/* Session counter for the chipset */
	393	int session_counter;
	394
	395	/* Frames scheduled for transmission, not handled yet */
	396	struct sk_buff_head tx_queue;
f5fc0f86 LC	397
f5fc0f86 LC	398	struct work_struct tx_work;
c87dec9f	399
f5fc0f86	400	/* Pending TX frames */
25eeb9e3	401	unsigned long tx_frames_map[BITS_TO_LONGS(ACX_TX_DESCRIPTORS)];
be7078c2	402	struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS];
781608c4	403	int tx_frames_cnt;
f5fc0f86	404
ac4e4ce5 JO	405	/* Security sequence number counters */
ac4e4ce5 JO	406	u8 tx_security_last_seq;
04e36fc5	407	s64 tx_security_seq;
ac4e4ce5	408
f5fc0f86 LC	409	/* FW Rx counter */
	410	u32 rx_counter;
	411
	412	/* Rx memory pool address */
	413	struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
	414
1f37cbc9 IY	415	/* Intermediate buffer, used for packet aggregation */
	416	u8 *aggr_buf;
	417
f5fc0f86 LC	418	/* The target interrupt mask */
	419	struct work_struct irq_work;
	420
52b0e7a6 JO	421	/* Hardware recovery work */
	422	struct work_struct recovery_work;
	423
f5fc0f86 LC	424	/* The mbox event mask */
	425	u32 event_mask;
	426
	427	/* Mailbox pointers */
	428	u32 mbox_ptr[2];
	429
	430	/* Are we currently scanning */
abb0b3bf	431	struct wl1271_scan scan;
78abd320	432	struct delayed_work scan_complete_work;
f5fc0f86 LC	433
	434	/* Our association ID */
	435	u16 aid;
	436
d94cd297	437	/* currently configured rate set */
830fb67b	438	u32 sta_rate_set;
d94cd297	439	u32 basic_rate_set;
ebba60c6	440	u32 basic_rate;
830fb67b	441	u32 rate_set;
d94cd297	442
8a5a37a6 JO	443	/* The current band */
	444	enum ieee80211_band band;
	445
60e84c2e JO	446	/* Beaconing interval (needed for ad-hoc) */
	447	u32 beacon_int;
	448
f5fc0f86 LC	449	/* Default key (for WEP) */
	450	u32 default_key;
	451
14b228a0	452	unsigned int filters;
f5fc0f86 LC	453	unsigned int rx_config;
	454	unsigned int rx_filter;
	455
f5fc0f86	456	struct completion *elp_compl;
37b70a81	457	struct delayed_work elp_work;
90494a90 JO	458	struct delayed_work pspoll_work;
	459
	460	/* counter for ps-poll delivery failures */
	461	int ps_poll_failures;
f5fc0f86	462
19ad0715 JO	463	/* retry counter for PSM entries */
	464	u8 psm_entry_retry;
	465
f5fc0f86 LC	466	/* in dBm */
	467	int power_level;
	468
00236aed JO	469	int rssi_thold;
	470	int last_rssi_event;
	471
f5fc0f86 LC	472	struct wl1271_stats stats;
	473	struct wl1271_debugfs debugfs;
	474
554d7209	475	__le32 buffer_32;
f5fc0f86	476	u32 buffer_cmd;
545f1da8	477	u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
f5fc0f86 LC	478
	479	struct wl1271_fw_status *fw_status;
	480	struct wl1271_tx_hw_res_if *tx_res_if;
b771eee5 JO	481
b771eee5 JO	482	struct ieee80211_vif *vif;
d6e19d13	483
2b60100b JO	484	/* Current chipset configuration */
2b60100b JO	485	struct conf_drv_settings conf;
01c09162	486
7fc3a864 JO	487	bool sg_enabled;
7fc3a864 JO	488
02fabb0e JO	489	bool enable_11a;
02fabb0e JO	490
01c09162	491	struct list_head list;
ece550d0 JL	492
	493	/* Most recently reported noise in dBm */
	494	s8 noise;
f5fc0f86 LC	495	};
	496
	497	int wl1271_plt_start(struct wl1271 *wl);
	498	int wl1271_plt_stop(struct wl1271 *wl);
	499
	500	#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */
	501
	502	#define SESSION_COUNTER_MAX 7 /* maximum value for the session counter */
	503
	504	#define WL1271_DEFAULT_POWER_LEVEL 0
	505
06f7bc7d JO	506	#define WL1271_TX_QUEUE_LOW_WATERMARK 10
06f7bc7d JO	507	#define WL1271_TX_QUEUE_HIGH_WATERMARK 25
f5fc0f86	508
01ac17ec JO	509	/* WL1271 needs a 200ms sleep after power on, and a 20ms sleep before power
	510	on in case is has been shut down shortly before */
	511	#define WL1271_PRE_POWER_ON_SLEEP 20 /* in miliseconds */
f5fc0f86 LC	512	#define WL1271_POWER_ON_SLEEP 200 /* in miliseconds */
	513
	514	#endif