[net-next-2.6.git] / drivers / net / wireless / wl12xx / wl1251_tx.h

/*
 * This file is part of wl1251
 *
 * Copyright (c) 1998-2007 Texas Instruments Incorporated
 * Copyright (C) 2008 Nokia Corporation
 *
 * Contact: Kalle Valo <kalle.valo@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#ifndef __WL1251_TX_H__
#define __WL1251_TX_H__

#include <linux/bitops.h>
#include "wl1251_acx.h"

/*
 *
 * TX PATH
 *
 * The Tx path uses a double buffer and a tx_control structure, each located
 * at a fixed address in the device's memory. On startup, the host retrieves
 * the pointers to these addresses. A double buffer allows for continuous data
 * flow towards the device. The host keeps track of which buffer is available
 * and alternates between these two buffers on a per packet basis.
 *
 * The size of each of the two buffers is large enough to hold the longest
 * 802.3 packet - maximum size Ethernet packet + header + descriptor.
 * TX complete indication will be received a-synchronously in a TX done cyclic
 * buffer which is composed of 16 tx_result descriptors structures and is used
 * in a cyclic manner.
 *
 * The TX (HOST) procedure is as follows:
 * 1. Read the Tx path status, that will give the data_out_count.
 * 2. goto 1, if not possible.
 *    i.e. if data_in_count - data_out_count >= HwBuffer size (2 for double
 *    buffer).
 * 3. Copy the packet (preceded by double_buffer_desc), if possible.
 *    i.e. if data_in_count - data_out_count < HwBuffer size (2 for double
 *    buffer).
 * 4. increment data_in_count.
 * 5. Inform the firmware by generating a firmware internal interrupt.
 * 6. FW will increment data_out_count after it reads the buffer.
 *
 * The TX Complete procedure:
 * 1. To get a TX complete indication the host enables the tx_complete flag in
 *    the TX descriptor Structure.
 * 2. For each packet with a Tx Complete field set, the firmware adds the
 *    transmit results to the cyclic buffer (txDoneRing) and sets both done_1
 *    and done_2 to 1 to indicate driver ownership.
 * 3. The firmware sends a Tx Complete interrupt to the host to trigger the
 *    host to process the new data. Note: interrupt will be send per packet if
 *    TX complete indication was requested in tx_control or per crossing
 *    aggregation threshold.
 * 4. After receiving the Tx Complete interrupt, the host reads the
 *    TxDescriptorDone information in a cyclic manner and clears both done_1
 *    and done_2 fields.
 *
 */

#define TX_COMPLETE_REQUIRED_BIT	0x80
#define TX_STATUS_DATA_OUT_COUNT_MASK   0xf

#define WL1251_TX_ALIGN_TO 4
#define WL1251_TX_ALIGN(len) (((len) + WL1251_TX_ALIGN_TO - 1) & \
			     ~(WL1251_TX_ALIGN_TO - 1))
#define WL1251_TKIP_IV_SPACE 4

struct tx_control {
	/* Rate Policy (class) index */
	unsigned rate_policy:3;

	/* When set, no ack policy is expected */
	unsigned ack_policy:1;

	/*
	 * Packet type:
	 * 0 -> 802.11
	 * 1 -> 802.3
	 * 2 -> IP
	 * 3 -> raw codec
	 */
	unsigned packet_type:2;

	/* If set, this is a QoS-Null or QoS-Data frame */
	unsigned qos:1;

	/*
	 * If set, the target triggers the tx complete INT
	 * upon frame sending completion.
	 */
	unsigned tx_complete:1;

	/* 2 bytes padding before packet header */
	unsigned xfer_pad:1;

	unsigned reserved:7;
} __attribute__ ((packed));


struct tx_double_buffer_desc {
	/* Length of payload, including headers. */
	u16 length;

	/*
	 * A bit mask that specifies the initial rate to be used
	 * Possible values are:
	 * 0x0001 - 1Mbits
	 * 0x0002 - 2Mbits
	 * 0x0004 - 5.5Mbits
	 * 0x0008 - 6Mbits
	 * 0x0010 - 9Mbits
	 * 0x0020 - 11Mbits
	 * 0x0040 - 12Mbits
	 * 0x0080 - 18Mbits
	 * 0x0100 - 22Mbits
	 * 0x0200 - 24Mbits
	 * 0x0400 - 36Mbits
	 * 0x0800 - 48Mbits
	 * 0x1000 - 54Mbits
	 */
	u16 rate;

	/* Time in us that a packet can spend in the target */
	u32 expiry_time;

	/* index of the TX queue used for this packet */
	u8 xmit_queue;

	/* Used to identify a packet */
	u8 id;

	struct tx_control control;

	/*
	 * The FW should cut the packet into fragments
	 * of this size.
	 */
	u16 frag_threshold;

	/* Numbers of HW queue blocks to be allocated */
	u8 num_mem_blocks;

	u8 reserved;
} __attribute__ ((packed));

enum {
	TX_SUCCESS              = 0,
	TX_DMA_ERROR            = BIT(7),
	TX_DISABLED             = BIT(6),
	TX_RETRY_EXCEEDED       = BIT(5),
	TX_TIMEOUT              = BIT(4),
	TX_KEY_NOT_FOUND        = BIT(3),
	TX_ENCRYPT_FAIL         = BIT(2),
	TX_UNAVAILABLE_PRIORITY = BIT(1),
};

struct tx_result {
	/*
	 * Ownership synchronization between the host and
	 * the firmware. If done_1 and done_2 are cleared,
	 * owned by the FW (no info ready).
	 */
	u8 done_1;

	/* same as double_buffer_desc->id */
	u8 id;

	/*
	 * Total air access duration consumed by this
	 * packet, including all retries and overheads.
	 */
	u16 medium_usage;

	/* Total media delay (from 1st EDCA AIFS counter until TX Complete). */
	u32 medium_delay;

	/* Time between host xfer and tx complete */
	u32 fw_hnadling_time;

	/* The LS-byte of the last TKIP sequence number. */
	u8 lsb_seq_num;

	/* Retry count */
	u8 ack_failures;

	/* At which rate we got a ACK */
	u16 rate;

	u16 reserved;

	/* TX_* */
	u8 status;

	/* See done_1 */
	u8 done_2;
} __attribute__ ((packed));

static inline int wl1251_tx_get_queue(int queue)
{
	switch (queue) {
	case 0:
		return QOS_AC_VO;
	case 1:
		return QOS_AC_VI;
	case 2:
		return QOS_AC_BE;
	case 3:
		return QOS_AC_BK;
	default:
		return QOS_AC_BE;
	}
}

void wl1251_tx_work(struct work_struct *work);
void wl1251_tx_complete(struct wl1251 *wl);
void wl1251_tx_flush(struct wl1251 *wl);

#endif
Commit	Line	Data
2f01a1f5	1	/*
80301cdc	2	* This file is part of wl1251
2f01a1f5 KV	3	*
	4	* Copyright (c) 1998-2007 Texas Instruments Incorporated
	5	* Copyright (C) 2008 Nokia Corporation
	6	*
	7	* Contact: Kalle Valo <kalle.valo@nokia.com>
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	16	* General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	21	* 02110-1301 USA
	22	*
	23	*/
	24
9f2ad4fb JO	25	#ifndef __WL1251_TX_H__
9f2ad4fb JO	26	#define __WL1251_TX_H__
2f01a1f5 KV	27
2f01a1f5 KV	28	#include <linux/bitops.h>
86dff7a7	29	#include "wl1251_acx.h"
2f01a1f5 KV	30
	31	/*
	32	*
	33	* TX PATH
	34	*
	35	* The Tx path uses a double buffer and a tx_control structure, each located
	36	* at a fixed address in the device's memory. On startup, the host retrieves
	37	* the pointers to these addresses. A double buffer allows for continuous data
	38	* flow towards the device. The host keeps track of which buffer is available
	39	* and alternates between these two buffers on a per packet basis.
	40	*
	41	* The size of each of the two buffers is large enough to hold the longest
	42	* 802.3 packet - maximum size Ethernet packet + header + descriptor.
	43	* TX complete indication will be received a-synchronously in a TX done cyclic
	44	* buffer which is composed of 16 tx_result descriptors structures and is used
	45	* in a cyclic manner.
	46	*
	47	* The TX (HOST) procedure is as follows:
	48	* 1. Read the Tx path status, that will give the data_out_count.
	49	* 2. goto 1, if not possible.
	50	* i.e. if data_in_count - data_out_count >= HwBuffer size (2 for double
	51	* buffer).
	52	* 3. Copy the packet (preceded by double_buffer_desc), if possible.
	53	* i.e. if data_in_count - data_out_count < HwBuffer size (2 for double
	54	* buffer).
	55	* 4. increment data_in_count.
	56	* 5. Inform the firmware by generating a firmware internal interrupt.
	57	* 6. FW will increment data_out_count after it reads the buffer.
	58	*
	59	* The TX Complete procedure:
	60	* 1. To get a TX complete indication the host enables the tx_complete flag in
	61	* the TX descriptor Structure.
	62	* 2. For each packet with a Tx Complete field set, the firmware adds the
	63	* transmit results to the cyclic buffer (txDoneRing) and sets both done_1
	64	* and done_2 to 1 to indicate driver ownership.
	65	* 3. The firmware sends a Tx Complete interrupt to the host to trigger the
	66	* host to process the new data. Note: interrupt will be send per packet if
	67	* TX complete indication was requested in tx_control or per crossing
	68	* aggregation threshold.
	69	* 4. After receiving the Tx Complete interrupt, the host reads the
	70	* TxDescriptorDone information in a cyclic manner and clears both done_1
	71	* and done_2 fields.
	72	*
	73	*/
	74
	75	#define TX_COMPLETE_REQUIRED_BIT 0x80
	76	#define TX_STATUS_DATA_OUT_COUNT_MASK 0xf
9f2ad4fb JO	77
	78	#define WL1251_TX_ALIGN_TO 4
	79	#define WL1251_TX_ALIGN(len) (((len) + WL1251_TX_ALIGN_TO - 1) & \
	80	~(WL1251_TX_ALIGN_TO - 1))
	81	#define WL1251_TKIP_IV_SPACE 4
2f01a1f5 KV	82
	83	struct tx_control {
	84	/* Rate Policy (class) index */
	85	unsigned rate_policy:3;
	86
	87	/* When set, no ack policy is expected */
	88	unsigned ack_policy:1;
	89
	90	/*
	91	* Packet type:
	92	* 0 -> 802.11
	93	* 1 -> 802.3
	94	* 2 -> IP
	95	* 3 -> raw codec
	96	*/
	97	unsigned packet_type:2;
	98
	99	/* If set, this is a QoS-Null or QoS-Data frame */
	100	unsigned qos:1;
	101
	102	/*
	103	* If set, the target triggers the tx complete INT
	104	* upon frame sending completion.
	105	*/
	106	unsigned tx_complete:1;
	107
	108	/* 2 bytes padding before packet header */
	109	unsigned xfer_pad:1;
	110
	111	unsigned reserved:7;
	112	} __attribute__ ((packed));
	113
	114
	115	struct tx_double_buffer_desc {
	116	/* Length of payload, including headers. */
	117	u16 length;
	118
	119	/*
	120	* A bit mask that specifies the initial rate to be used
	121	* Possible values are:
	122	* 0x0001 - 1Mbits
	123	* 0x0002 - 2Mbits
	124	* 0x0004 - 5.5Mbits
	125	* 0x0008 - 6Mbits
	126	* 0x0010 - 9Mbits
	127	* 0x0020 - 11Mbits
	128	* 0x0040 - 12Mbits
	129	* 0x0080 - 18Mbits
	130	* 0x0100 - 22Mbits
	131	* 0x0200 - 24Mbits
	132	* 0x0400 - 36Mbits
	133	* 0x0800 - 48Mbits
	134	* 0x1000 - 54Mbits
	135	*/
	136	u16 rate;
	137
	138	/* Time in us that a packet can spend in the target */
	139	u32 expiry_time;
	140
	141	/* index of the TX queue used for this packet */
	142	u8 xmit_queue;
	143
	144	/* Used to identify a packet */
	145	u8 id;
146
147	struct tx_control control;
148
149	/*
150	* The FW should cut the packet into fragments
151	* of this size.
152	*/
153	u16 frag_threshold;
154
155	/* Numbers of HW queue blocks to be allocated */
156	u8 num_mem_blocks;
157
158	u8 reserved;
159	} __attribute__ ((packed));
160
161	enum {
162	TX_SUCCESS = 0,
163	TX_DMA_ERROR = BIT(7),
164	TX_DISABLED = BIT(6),
165	TX_RETRY_EXCEEDED = BIT(5),
166	TX_TIMEOUT = BIT(4),
167	TX_KEY_NOT_FOUND = BIT(3),
168	TX_ENCRYPT_FAIL = BIT(2),
169	TX_UNAVAILABLE_PRIORITY = BIT(1),
170	};
171
172	struct tx_result {
173	/*
174	* Ownership synchronization between the host and
175	* the firmware. If done_1 and done_2 are cleared,
176	* owned by the FW (no info ready).
177	*/
178	u8 done_1;
179
180	/* same as double_buffer_desc->id */
181	u8 id;
182
183	/*
184	* Total air access duration consumed by this
185	* packet, including all retries and overheads.
186	*/
187	u16 medium_usage;
188
189	/* Total media delay (from 1st EDCA AIFS counter until TX Complete). */
190	u32 medium_delay;
191
192	/* Time between host xfer and tx complete */
193	u32 fw_hnadling_time;
194
195	/* The LS-byte of the last TKIP sequence number. */
196	u8 lsb_seq_num;
197
198	/* Retry count */
199	u8 ack_failures;
200
201	/* At which rate we got a ACK */
202	u16 rate;
203
204	u16 reserved;
205
206	/* TX_* */
207	u8 status;
208
209	/* See done_1 */
210	u8 done_2;
211	} __attribute__ ((packed));
212
86dff7a7 KV	213	static inline int wl1251_tx_get_queue(int queue)
86dff7a7 KV	214	{
86dff7a7 KV	215	switch (queue) {
	216	case 0:
	217	return QOS_AC_VO;
	218	case 1:
	219	return QOS_AC_VI;
	220	case 2:
	221	return QOS_AC_BE;
	222	case 3:
	223	return QOS_AC_BK;
	224	default:
	225	return QOS_AC_BE;
	226	}
	227	}
	228
9f2ad4fb	229	void wl1251_tx_work(struct work_struct *work);
80301cdc KV	230	void wl1251_tx_complete(struct wl1251 *wl);
80301cdc KV	231	void wl1251_tx_flush(struct wl1251 *wl);
2f01a1f5 KV	232
2f01a1f5 KV	233	#endif