[net-next-2.6.git] / drivers / net / wireless / rtl818x.h

/*
 * Definitions for RTL818x hardware
 *
 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
 *
 * Based on the r8187 driver, which is:
 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef RTL818X_H
#define RTL818X_H

struct rtl818x_csr {
	u8	MAC[6];
	u8	reserved_0[2];
	__le32	MAR[2];
	u8	RX_FIFO_COUNT;
	u8	reserved_1;
	u8	TX_FIFO_COUNT;
	u8	BQREQ;
	u8	reserved_2[4];
	__le32	TSFT[2];
	__le32	TLPDA;
	__le32	TNPDA;
	__le32	THPDA;
	__le16	BRSR;
	u8	BSSID[6];
	u8	RESP_RATE;
	u8	EIFS;
	u8	reserved_3[1];
	u8	CMD;
#define RTL818X_CMD_TX_ENABLE		(1 << 2)
#define RTL818X_CMD_RX_ENABLE		(1 << 3)
#define RTL818X_CMD_RESET		(1 << 4)
	u8	reserved_4[4];
	__le16	INT_MASK;
	__le16	INT_STATUS;
#define RTL818X_INT_RX_OK		(1 <<  0)
#define RTL818X_INT_RX_ERR		(1 <<  1)
#define RTL818X_INT_TXL_OK		(1 <<  2)
#define RTL818X_INT_TXL_ERR		(1 <<  3)
#define RTL818X_INT_RX_DU		(1 <<  4)
#define RTL818X_INT_RX_FO		(1 <<  5)
#define RTL818X_INT_TXN_OK		(1 <<  6)
#define RTL818X_INT_TXN_ERR		(1 <<  7)
#define RTL818X_INT_TXH_OK		(1 <<  8)
#define RTL818X_INT_TXH_ERR		(1 <<  9)
#define RTL818X_INT_TXB_OK		(1 << 10)
#define RTL818X_INT_TXB_ERR		(1 << 11)
#define RTL818X_INT_ATIM		(1 << 12)
#define RTL818X_INT_BEACON		(1 << 13)
#define RTL818X_INT_TIME_OUT		(1 << 14)
#define RTL818X_INT_TX_FO		(1 << 15)
	__le32	TX_CONF;
#define RTL818X_TX_CONF_LOOPBACK_MAC	(1 << 17)
#define RTL818X_TX_CONF_LOOPBACK_CONT	(3 << 17)
#define RTL818X_TX_CONF_NO_ICV		(1 << 19)
#define RTL818X_TX_CONF_DISCW		(1 << 20)
#define RTL818X_TX_CONF_SAT_HWPLCP	(1 << 24)
#define RTL818X_TX_CONF_R8180_ABCD	(2 << 25)
#define RTL818X_TX_CONF_R8180_F		(3 << 25)
#define RTL818X_TX_CONF_R8185_ABC	(4 << 25)
#define RTL818X_TX_CONF_R8185_D		(5 << 25)
#define RTL818X_TX_CONF_R8187vD		(5 << 25)
#define RTL818X_TX_CONF_R8187vD_B	(6 << 25)
#define RTL818X_TX_CONF_HWVER_MASK	(7 << 25)
#define RTL818X_TX_CONF_DISREQQSIZE	(1 << 28)
#define RTL818X_TX_CONF_PROBE_DTS	(1 << 29)
#define RTL818X_TX_CONF_HW_SEQNUM	(1 << 30)
#define RTL818X_TX_CONF_CW_MIN		(1 << 31)
	__le32	RX_CONF;
#define RTL818X_RX_CONF_MONITOR		(1 <<  0)
#define RTL818X_RX_CONF_NICMAC		(1 <<  1)
#define RTL818X_RX_CONF_MULTICAST	(1 <<  2)
#define RTL818X_RX_CONF_BROADCAST	(1 <<  3)
#define RTL818X_RX_CONF_FCS		(1 <<  5)
#define RTL818X_RX_CONF_DATA		(1 << 18)
#define RTL818X_RX_CONF_CTRL		(1 << 19)
#define RTL818X_RX_CONF_MGMT		(1 << 20)
#define RTL818X_RX_CONF_ADDR3		(1 << 21)
#define RTL818X_RX_CONF_PM		(1 << 22)
#define RTL818X_RX_CONF_BSSID		(1 << 23)
#define RTL818X_RX_CONF_RX_AUTORESETPHY	(1 << 28)
#define RTL818X_RX_CONF_CSDM1		(1 << 29)
#define RTL818X_RX_CONF_CSDM2		(1 << 30)
#define RTL818X_RX_CONF_ONLYERLPKT	(1 << 31)
	__le32	INT_TIMEOUT;
	__le32	TBDA;
	u8	EEPROM_CMD;
#define RTL818X_EEPROM_CMD_READ		(1 << 0)
#define RTL818X_EEPROM_CMD_WRITE	(1 << 1)
#define RTL818X_EEPROM_CMD_CK		(1 << 2)
#define RTL818X_EEPROM_CMD_CS		(1 << 3)
#define RTL818X_EEPROM_CMD_NORMAL	(0 << 6)
#define RTL818X_EEPROM_CMD_LOAD		(1 << 6)
#define RTL818X_EEPROM_CMD_PROGRAM	(2 << 6)
#define RTL818X_EEPROM_CMD_CONFIG	(3 << 6)
	u8	CONFIG0;
	u8	CONFIG1;
	u8	CONFIG2;
#define RTL818X_CONFIG2_ANTENNA_DIV	(1 << 6)
	__le32	ANAPARAM;
	u8	MSR;
#define RTL818X_MSR_NO_LINK		(0 << 2)
#define RTL818X_MSR_ADHOC		(1 << 2)
#define RTL818X_MSR_INFRA		(2 << 2)
#define RTL818X_MSR_MASTER		(3 << 2)
#define RTL818X_MSR_ENEDCA		(4 << 2)
	u8	CONFIG3;
#define RTL818X_CONFIG3_ANAPARAM_WRITE	(1 << 6)
#define RTL818X_CONFIG3_GNT_SELECT	(1 << 7)
	u8	CONFIG4;
#define RTL818X_CONFIG4_POWEROFF	(1 << 6)
#define RTL818X_CONFIG4_VCOOFF		(1 << 7)
	u8	TESTR;
	u8	reserved_9[2];
	u8	PGSELECT;
	u8	SECURITY;
	__le32	ANAPARAM2;
	u8	reserved_10[12];
	__le16	BEACON_INTERVAL;
	__le16	ATIM_WND;
	__le16	BEACON_INTERVAL_TIME;
	__le16	ATIMTR_INTERVAL;
	u8	PHY_DELAY;
	u8	CARRIER_SENSE_COUNTER;
	u8	reserved_11[2];
	u8	PHY[4];
	__le16	RFPinsOutput;
	__le16	RFPinsEnable;
	__le16	RFPinsSelect;
	__le16	RFPinsInput;
	__le32	RF_PARA;
	__le32	RF_TIMING;
	u8	GP_ENABLE;
	u8	GPIO;
	u8	reserved_12[2];
	__le32	HSSI_PARA;
	u8	reserved_13[4];
	u8	TX_AGC_CTL;
#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT		(1 << 0)
#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT	(1 << 1)
#define RTL818X_TX_AGC_CTL_FEEDBACK_ANT			(1 << 2)
	u8	TX_GAIN_CCK;
	u8	TX_GAIN_OFDM;
	u8	TX_ANTENNA;
	u8	reserved_14[16];
	u8	WPA_CONF;
	u8	reserved_15[3];
	u8	SIFS;
	u8	DIFS;
	u8	SLOT;
	u8	reserved_16[5];
	u8	CW_CONF;
#define RTL818X_CW_CONF_PERPACKET_CW_SHIFT	(1 << 0)
#define RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT	(1 << 1)
	u8	CW_VAL;
	u8	RATE_FALLBACK;
#define RTL818X_RATE_FALLBACK_ENABLE	(1 << 7)
	u8	ACM_CONTROL;
	u8	reserved_17[24];
	u8	CONFIG5;
	u8	TX_DMA_POLLING;
	u8	reserved_18[2];
	__le16	CWR;
	u8	RETRY_CTR;
	u8	reserved_19[3];
	__le16	INT_MIG;
/* RTL818X_R8187B_*: magic numbers from ioregisters */
#define RTL818X_R8187B_B	0
#define RTL818X_R8187B_D	1
#define RTL818X_R8187B_E	2
	__le32	RDSAR;
	__le16	TID_AC_MAP;
	u8	reserved_20[4];
	u8	ANAPARAM3;
	u8	reserved_21[5];
	__le16	FEMR;
	u8	reserved_22[4];
	__le16	TALLY_CNT;
	u8	TALLY_SEL;
} __attribute__((packed));

struct rtl818x_rf_ops {
	char *name;
	void (*init)(struct ieee80211_hw *);
	void (*stop)(struct ieee80211_hw *);
	void (*set_chan)(struct ieee80211_hw *, struct ieee80211_conf *);
};

/* Tx/Rx flags are common between RTL818X chips */

enum rtl818x_tx_desc_flags {
	RTL818X_TX_DESC_FLAG_NO_ENC	= (1 << 15),
	RTL818X_TX_DESC_FLAG_TX_OK	= (1 << 15),
	RTL818X_TX_DESC_FLAG_SPLCP	= (1 << 16),
	RTL818X_TX_DESC_FLAG_RX_UNDER	= (1 << 16),
	RTL818X_TX_DESC_FLAG_MOREFRAG	= (1 << 17),
	RTL818X_TX_DESC_FLAG_CTS	= (1 << 18),
	RTL818X_TX_DESC_FLAG_RTS	= (1 << 23),
	RTL818X_TX_DESC_FLAG_LS		= (1 << 28),
	RTL818X_TX_DESC_FLAG_FS		= (1 << 29),
	RTL818X_TX_DESC_FLAG_DMA	= (1 << 30),
	RTL818X_TX_DESC_FLAG_OWN	= (1 << 31)
};

enum rtl818x_rx_desc_flags {
	RTL818X_RX_DESC_FLAG_ICV_ERR	= (1 << 12),
	RTL818X_RX_DESC_FLAG_CRC32_ERR	= (1 << 13),
	RTL818X_RX_DESC_FLAG_PM		= (1 << 14),
	RTL818X_RX_DESC_FLAG_RX_ERR	= (1 << 15),
	RTL818X_RX_DESC_FLAG_BCAST	= (1 << 16),
	RTL818X_RX_DESC_FLAG_PAM	= (1 << 17),
	RTL818X_RX_DESC_FLAG_MCAST	= (1 << 18),
	RTL818X_RX_DESC_FLAG_QOS	= (1 << 19), /* RTL8187(B) only */
	RTL818X_RX_DESC_FLAG_TRSW	= (1 << 24), /* RTL8187(B) only */
	RTL818X_RX_DESC_FLAG_SPLCP	= (1 << 25),
	RTL818X_RX_DESC_FLAG_FOF	= (1 << 26),
	RTL818X_RX_DESC_FLAG_DMA_FAIL	= (1 << 27),
	RTL818X_RX_DESC_FLAG_LS		= (1 << 28),
	RTL818X_RX_DESC_FLAG_FS		= (1 << 29),
	RTL818X_RX_DESC_FLAG_EOR	= (1 << 30),
	RTL818X_RX_DESC_FLAG_OWN	= (1 << 31)
};

#endif /* RTL818X_H */
Commit	Line	Data
0aec00ae JL	1	/*
	2	* Definitions for RTL818x hardware
	3	*
	4	* Copyright 2007 Michael Wu <flamingice@sourmilk.net>
	5	* Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
	6	*
	7	* Based on the r8187 driver, which is:
	8	* Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
605bebe2 MW	15	#ifndef RTL818X_H
	16	#define RTL818X_H
	17
	18	struct rtl818x_csr {
	19	u8 MAC[6];
	20	u8 reserved_0[2];
	21	__le32 MAR[2];
	22	u8 RX_FIFO_COUNT;
	23	u8 reserved_1;
	24	u8 TX_FIFO_COUNT;
	25	u8 BQREQ;
	26	u8 reserved_2[4];
	27	__le32 TSFT[2];
	28	__le32 TLPDA;
	29	__le32 TNPDA;
	30	__le32 THPDA;
	31	__le16 BRSR;
	32	u8 BSSID[6];
	33	u8 RESP_RATE;
	34	u8 EIFS;
	35	u8 reserved_3[1];
	36	u8 CMD;
	37	#define RTL818X_CMD_TX_ENABLE (1 << 2)
	38	#define RTL818X_CMD_RX_ENABLE (1 << 3)
	39	#define RTL818X_CMD_RESET (1 << 4)
	40	u8 reserved_4[4];
	41	__le16 INT_MASK;
	42	__le16 INT_STATUS;
	43	#define RTL818X_INT_RX_OK (1 << 0)
	44	#define RTL818X_INT_RX_ERR (1 << 1)
	45	#define RTL818X_INT_TXL_OK (1 << 2)
	46	#define RTL818X_INT_TXL_ERR (1 << 3)
	47	#define RTL818X_INT_RX_DU (1 << 4)
	48	#define RTL818X_INT_RX_FO (1 << 5)
	49	#define RTL818X_INT_TXN_OK (1 << 6)
	50	#define RTL818X_INT_TXN_ERR (1 << 7)
	51	#define RTL818X_INT_TXH_OK (1 << 8)
	52	#define RTL818X_INT_TXH_ERR (1 << 9)
	53	#define RTL818X_INT_TXB_OK (1 << 10)
	54	#define RTL818X_INT_TXB_ERR (1 << 11)
	55	#define RTL818X_INT_ATIM (1 << 12)
	56	#define RTL818X_INT_BEACON (1 << 13)
	57	#define RTL818X_INT_TIME_OUT (1 << 14)
	58	#define RTL818X_INT_TX_FO (1 << 15)
	59	__le32 TX_CONF;
	60	#define RTL818X_TX_CONF_LOOPBACK_MAC (1 << 17)
f6532111	61	#define RTL818X_TX_CONF_LOOPBACK_CONT (3 << 17)
605bebe2 MW	62	#define RTL818X_TX_CONF_NO_ICV (1 << 19)
605bebe2 MW	63	#define RTL818X_TX_CONF_DISCW (1 << 20)
f6532111	64	#define RTL818X_TX_CONF_SAT_HWPLCP (1 << 24)
605bebe2 MW	65	#define RTL818X_TX_CONF_R8180_ABCD (2 << 25)
	66	#define RTL818X_TX_CONF_R8180_F (3 << 25)
	67	#define RTL818X_TX_CONF_R8185_ABC (4 << 25)
	68	#define RTL818X_TX_CONF_R8185_D (5 << 25)
0e25b4ef LF	69	#define RTL818X_TX_CONF_R8187vD (5 << 25)
0e25b4ef LF	70	#define RTL818X_TX_CONF_R8187vD_B (6 << 25)
605bebe2	71	#define RTL818X_TX_CONF_HWVER_MASK (7 << 25)
d1e11af5	72	#define RTL818X_TX_CONF_DISREQQSIZE (1 << 28)
f6532111 MW	73	#define RTL818X_TX_CONF_PROBE_DTS (1 << 29)
f6532111 MW	74	#define RTL818X_TX_CONF_HW_SEQNUM (1 << 30)
605bebe2 MW	75	#define RTL818X_TX_CONF_CW_MIN (1 << 31)
	76	__le32 RX_CONF;
	77	#define RTL818X_RX_CONF_MONITOR (1 << 0)
	78	#define RTL818X_RX_CONF_NICMAC (1 << 1)
	79	#define RTL818X_RX_CONF_MULTICAST (1 << 2)
	80	#define RTL818X_RX_CONF_BROADCAST (1 << 3)
4150c572	81	#define RTL818X_RX_CONF_FCS (1 << 5)
605bebe2 MW	82	#define RTL818X_RX_CONF_DATA (1 << 18)
	83	#define RTL818X_RX_CONF_CTRL (1 << 19)
	84	#define RTL818X_RX_CONF_MGMT (1 << 20)
f6532111 MW	85	#define RTL818X_RX_CONF_ADDR3 (1 << 21)
f6532111 MW	86	#define RTL818X_RX_CONF_PM (1 << 22)
605bebe2 MW	87	#define RTL818X_RX_CONF_BSSID (1 << 23)
605bebe2 MW	88	#define RTL818X_RX_CONF_RX_AUTORESETPHY (1 << 28)
f6532111 MW	89	#define RTL818X_RX_CONF_CSDM1 (1 << 29)
f6532111 MW	90	#define RTL818X_RX_CONF_CSDM2 (1 << 30)
605bebe2 MW	91	#define RTL818X_RX_CONF_ONLYERLPKT (1 << 31)
	92	__le32 INT_TIMEOUT;
	93	__le32 TBDA;
	94	u8 EEPROM_CMD;
	95	#define RTL818X_EEPROM_CMD_READ (1 << 0)
	96	#define RTL818X_EEPROM_CMD_WRITE (1 << 1)
	97	#define RTL818X_EEPROM_CMD_CK (1 << 2)
	98	#define RTL818X_EEPROM_CMD_CS (1 << 3)
	99	#define RTL818X_EEPROM_CMD_NORMAL (0 << 6)
	100	#define RTL818X_EEPROM_CMD_LOAD (1 << 6)
	101	#define RTL818X_EEPROM_CMD_PROGRAM (2 << 6)
	102	#define RTL818X_EEPROM_CMD_CONFIG (3 << 6)
	103	u8 CONFIG0;
	104	u8 CONFIG1;
	105	u8 CONFIG2;
f6532111	106	#define RTL818X_CONFIG2_ANTENNA_DIV (1 << 6)
605bebe2 MW	107	__le32 ANAPARAM;
	108	u8 MSR;
	109	#define RTL818X_MSR_NO_LINK (0 << 2)
	110	#define RTL818X_MSR_ADHOC (1 << 2)
	111	#define RTL818X_MSR_INFRA (2 << 2)
d1e11af5 HTL	112	#define RTL818X_MSR_MASTER (3 << 2)
d1e11af5 HTL	113	#define RTL818X_MSR_ENEDCA (4 << 2)
605bebe2 MW	114	u8 CONFIG3;
605bebe2 MW	115	#define RTL818X_CONFIG3_ANAPARAM_WRITE (1 << 6)
d1e11af5	116	#define RTL818X_CONFIG3_GNT_SELECT (1 << 7)
605bebe2 MW	117	u8 CONFIG4;
	118	#define RTL818X_CONFIG4_POWEROFF (1 << 6)
	119	#define RTL818X_CONFIG4_VCOOFF (1 << 7)
	120	u8 TESTR;
	121	u8 reserved_9[2];
f6532111 MW	122	u8 PGSELECT;
f6532111 MW	123	u8 SECURITY;
605bebe2 MW	124	__le32 ANAPARAM2;
	125	u8 reserved_10[12];
	126	__le16 BEACON_INTERVAL;
	127	__le16 ATIM_WND;
	128	__le16 BEACON_INTERVAL_TIME;
	129	__le16 ATIMTR_INTERVAL;
f6532111 MW	130	u8 PHY_DELAY;
	131	u8 CARRIER_SENSE_COUNTER;
	132	u8 reserved_11[2];
605bebe2 MW	133	u8 PHY[4];
	134	__le16 RFPinsOutput;
	135	__le16 RFPinsEnable;
	136	__le16 RFPinsSelect;
	137	__le16 RFPinsInput;
	138	__le32 RF_PARA;
	139	__le32 RF_TIMING;
	140	u8 GP_ENABLE;
	141	u8 GPIO;
d1e11af5 HTL	142	u8 reserved_12[2];
	143	__le32 HSSI_PARA;
	144	u8 reserved_13[4];
605bebe2 MW	145	u8 TX_AGC_CTL;
	146	#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT (1 << 0)
	147	#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT (1 << 1)
	148	#define RTL818X_TX_AGC_CTL_FEEDBACK_ANT (1 << 2)
	149	u8 TX_GAIN_CCK;
	150	u8 TX_GAIN_OFDM;
	151	u8 TX_ANTENNA;
d1e11af5	152	u8 reserved_14[16];
605bebe2	153	u8 WPA_CONF;
d1e11af5	154	u8 reserved_15[3];
605bebe2 MW	155	u8 SIFS;
	156	u8 DIFS;
	157	u8 SLOT;
d1e11af5	158	u8 reserved_16[5];
605bebe2 MW	159	u8 CW_CONF;
	160	#define RTL818X_CW_CONF_PERPACKET_CW_SHIFT (1 << 0)
	161	#define RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT (1 << 1)
	162	u8 CW_VAL;
	163	u8 RATE_FALLBACK;
d1e11af5 HTL	164	#define RTL818X_RATE_FALLBACK_ENABLE (1 << 7)
	165	u8 ACM_CONTROL;
	166	u8 reserved_17[24];
605bebe2 MW	167	u8 CONFIG5;
605bebe2 MW	168	u8 TX_DMA_POLLING;
d1e11af5	169	u8 reserved_18[2];
605bebe2 MW	170	__le16 CWR;
605bebe2 MW	171	u8 RETRY_CTR;
d1e11af5 HTL	172	u8 reserved_19[3];
	173	__le16 INT_MIG;
	174	/* RTL818X_R8187B_: magic numbers from ioregisters /
	175	#define RTL818X_R8187B_B 0
	176	#define RTL818X_R8187B_D 1
	177	#define RTL818X_R8187B_E 2
605bebe2	178	__le32 RDSAR;
d1e11af5	179	__le16 TID_AC_MAP;
f6532111	180	u8 reserved_20[4];
d1e11af5 HTL	181	u8 ANAPARAM3;
	182	u8 reserved_21[5];
	183	__le16 FEMR;
	184	u8 reserved_22[4];
f6532111	185	__le16 TALLY_CNT;
605bebe2 MW	186	u8 TALLY_SEL;
	187	} __attribute__((packed));
	188
f6532111 MW	189	struct rtl818x_rf_ops {
	190	char *name;
	191	void (init)(struct ieee80211_hw );
	192	void (stop)(struct ieee80211_hw );
	193	void (set_chan)(struct ieee80211_hw , struct ieee80211_conf *);
	194	};
	195
38e3b0d8 HRK	196	/* Tx/Rx flags are common between RTL818X chips */
	197
	198	enum rtl818x_tx_desc_flags {
	199	RTL818X_TX_DESC_FLAG_NO_ENC = (1 << 15),
	200	RTL818X_TX_DESC_FLAG_TX_OK = (1 << 15),
	201	RTL818X_TX_DESC_FLAG_SPLCP = (1 << 16),
	202	RTL818X_TX_DESC_FLAG_RX_UNDER = (1 << 16),
	203	RTL818X_TX_DESC_FLAG_MOREFRAG = (1 << 17),
	204	RTL818X_TX_DESC_FLAG_CTS = (1 << 18),
	205	RTL818X_TX_DESC_FLAG_RTS = (1 << 23),
	206	RTL818X_TX_DESC_FLAG_LS = (1 << 28),
	207	RTL818X_TX_DESC_FLAG_FS = (1 << 29),
	208	RTL818X_TX_DESC_FLAG_DMA = (1 << 30),
	209	RTL818X_TX_DESC_FLAG_OWN = (1 << 31)
	210	};
	211
	212	enum rtl818x_rx_desc_flags {
	213	RTL818X_RX_DESC_FLAG_ICV_ERR = (1 << 12),
	214	RTL818X_RX_DESC_FLAG_CRC32_ERR = (1 << 13),
	215	RTL818X_RX_DESC_FLAG_PM = (1 << 14),
	216	RTL818X_RX_DESC_FLAG_RX_ERR = (1 << 15),
	217	RTL818X_RX_DESC_FLAG_BCAST = (1 << 16),
	218	RTL818X_RX_DESC_FLAG_PAM = (1 << 17),
	219	RTL818X_RX_DESC_FLAG_MCAST = (1 << 18),
	220	RTL818X_RX_DESC_FLAG_QOS = (1 << 19), /* RTL8187(B) only */
	221	RTL818X_RX_DESC_FLAG_TRSW = (1 << 24), /* RTL8187(B) only */
	222	RTL818X_RX_DESC_FLAG_SPLCP = (1 << 25),
	223	RTL818X_RX_DESC_FLAG_FOF = (1 << 26),
	224	RTL818X_RX_DESC_FLAG_DMA_FAIL = (1 << 27),
	225	RTL818X_RX_DESC_FLAG_LS = (1 << 28),
	226	RTL818X_RX_DESC_FLAG_FS = (1 << 29),
	227	RTL818X_RX_DESC_FLAG_EOR = (1 << 30),
	228	RTL818X_RX_DESC_FLAG_OWN = (1 << 31)
	229	};
	230
605bebe2	231	#endif /* RTL818X_H */