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rtl8187: Add termination packet to prevent stall
[net-next-2.6.git] / drivers / net / wireless / rtl818x / rtl8187_dev.c
CommitLineData
605bebe2
MW		 1/*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
3461fc12
LF		 10 * The driver was extended to the RTL8187B in 2008 by:
11 * Herton Ronaldo Krzesinski <herton@mandriva.com.br>
12 * Hin-Tak Leung <htl10@users.sourceforge.net>
13 * Larry Finger <Larry.Finger@lwfinger.net>
14 *
0aec00ae
JL		 15 * Magic delays and register offsets below are taken from the original
16 * r8187 driver sources. Thanks to Realtek for their support!
605bebe2
MW		 17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/init.h>
24#include <linux/usb.h>
25#include <linux/delay.h>
26#include <linux/etherdevice.h>
27#include <linux/eeprom_93cx6.h>
28#include <net/mac80211.h>
29
30#include "rtl8187.h"
31#include "rtl8187_rtl8225.h"
32
33MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
3461fc12
LF		 35MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
36MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
37MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
f8a08c34 38MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
605bebe2
MW		 39MODULE_LICENSE("GPL");
40
41static struct usb_device_id rtl8187_table[] __devinitdata = {
7c7e6af3
AM		 42 /* Asus */
43 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
eaca90da
FF		 44 /* Belkin */
45 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
605bebe2 46 /* Realtek */
f8a08c34
HTL		 47 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
48 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
49 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
746db510 50 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
605bebe2 51 /* Netgear */
f8a08c34
HTL		 52 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
53 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
fcd7cc14 54 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
c3cf60a9 55 /* HP */
f8a08c34 56 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
9934550d 57 /* Sitecom */
f8a08c34 58 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
f3c76918 59 {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
8f7c41d4
IK		 60 /* Abocom */
61 {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
605bebe2
MW		 62 {}
63};
64
65MODULE_DEVICE_TABLE(usb, rtl8187_table);
66
8318d78a
JB		 67static const struct ieee80211_rate rtl818x_rates[] = {
68 { .bitrate = 10, .hw_value = 0, },
69 { .bitrate = 20, .hw_value = 1, },
70 { .bitrate = 55, .hw_value = 2, },
71 { .bitrate = 110, .hw_value = 3, },
72 { .bitrate = 60, .hw_value = 4, },
73 { .bitrate = 90, .hw_value = 5, },
74 { .bitrate = 120, .hw_value = 6, },
75 { .bitrate = 180, .hw_value = 7, },
76 { .bitrate = 240, .hw_value = 8, },
77 { .bitrate = 360, .hw_value = 9, },
78 { .bitrate = 480, .hw_value = 10, },
79 { .bitrate = 540, .hw_value = 11, },
80};
81
82static const struct ieee80211_channel rtl818x_channels[] = {
83 { .center_freq = 2412 },
84 { .center_freq = 2417 },
85 { .center_freq = 2422 },
86 { .center_freq = 2427 },
87 { .center_freq = 2432 },
88 { .center_freq = 2437 },
89 { .center_freq = 2442 },
90 { .center_freq = 2447 },
91 { .center_freq = 2452 },
92 { .center_freq = 2457 },
93 { .center_freq = 2462 },
94 { .center_freq = 2467 },
95 { .center_freq = 2472 },
96 { .center_freq = 2484 },
97};
98
4150c572
JB		 99static void rtl8187_iowrite_async_cb(struct urb *urb)
100{
101 kfree(urb->context);
4150c572
JB		 102}
103
104static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
105 void *data, u16 len)
106{
107 struct usb_ctrlrequest *dr;
108 struct urb *urb;
109 struct rtl8187_async_write_data {
110 u8 data[4];
111 struct usb_ctrlrequest dr;
112 } *buf;
ea8ee240 113 int rc;
4150c572
JB		 114
115 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
116 if (!buf)
117 return;
118
119 urb = usb_alloc_urb(0, GFP_ATOMIC);
120 if (!urb) {
121 kfree(buf);
122 return;
123 }
124
125 dr = &buf->dr;
126
127 dr->bRequestType = RTL8187_REQT_WRITE;
128 dr->bRequest = RTL8187_REQ_SET_REG;
129 dr->wValue = addr;
130 dr->wIndex = 0;
131 dr->wLength = cpu_to_le16(len);
132
133 memcpy(buf, data, len);
134
135 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
136 (unsigned char *)dr, buf, len,
137 rtl8187_iowrite_async_cb, buf);
c1db52b9 138 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 139 rc = usb_submit_urb(urb, GFP_ATOMIC);
140 if (rc < 0) {
141 kfree(buf);
c1db52b9 142 usb_unanchor_urb(urb);
ea8ee240 143 }
c1db52b9 144 usb_free_urb(urb);
4150c572
JB		 145}
146
147static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
148 __le32 *addr, u32 val)
149{
150 __le32 buf = cpu_to_le32(val);
151
152 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
153 &buf, sizeof(buf));
154}
155
605bebe2
MW		 156void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
157{
158 struct rtl8187_priv *priv = dev->priv;
159
160 data <<= 8;
161 data |= addr | 0x80;
162
163 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
164 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
165 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
166 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
605bebe2
MW		 167}
168
169static void rtl8187_tx_cb(struct urb *urb)
170{
605bebe2 171 struct sk_buff *skb = (struct sk_buff *)urb->context;
e039fa4a 172 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e6a9854b 173 struct ieee80211_hw *hw = info->rate_driver_data[0];
6f7853f3 174 struct rtl8187_priv *priv = hw->priv;
605bebe2 175
6f7853f3
HTL		 176 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
177 sizeof(struct rtl8187_tx_hdr));
e6a9854b 178 ieee80211_tx_info_clear_status(info);
3517afde
HRK		 179
180 if (!urb->status &&
181 !(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
182 priv->is_rtl8187b) {
183 skb_queue_tail(&priv->b_tx_status.queue, skb);
184
185 /* queue is "full", discard last items */
186 while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
187 struct sk_buff *old_skb;
188
189 dev_dbg(&priv->udev->dev,
190 "transmit status queue full\n");
191
192 old_skb = skb_dequeue(&priv->b_tx_status.queue);
193 ieee80211_tx_status_irqsafe(hw, old_skb);
194 }
195 } else {
196 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) && !urb->status)
197 info->flags |= IEEE80211_TX_STAT_ACK;
198 ieee80211_tx_status_irqsafe(hw, skb);
199 }
605bebe2
MW		 200}
201
e039fa4a 202static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
605bebe2
MW		 203{
204 struct rtl8187_priv *priv = dev->priv;
e039fa4a 205 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
6f7853f3
HTL		 206 unsigned int ep;
207 void *buf;
605bebe2 208 struct urb *urb;
98798f48
MW		 209 __le16 rts_dur = 0;
210 u32 flags;
ea8ee240 211 int rc;
605bebe2
MW		 212
213 urb = usb_alloc_urb(0, GFP_ATOMIC);
214 if (!urb) {
215 kfree_skb(skb);
d6e2be98 216 return NETDEV_TX_OK;
605bebe2
MW		 217 }
218
98798f48 219 flags = skb->len;
38e3b0d8 220 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
aa68cbfb 221
e039fa4a 222 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
8b7b1e05 223 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
38e3b0d8 224 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
e6a9854b 225 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
38e3b0d8 226 flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 227 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
32bfd35d 228 rts_dur = ieee80211_rts_duration(dev, priv->vif,
e039fa4a 229 skb->len, info);
e6a9854b 230 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
38e3b0d8 231 flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 232 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 233 }
98798f48 234
6f7853f3
HTL		 235 if (!priv->is_rtl8187b) {
236 struct rtl8187_tx_hdr *hdr =
237 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
238 hdr->flags = cpu_to_le32(flags);
239 hdr->len = 0;
240 hdr->rts_duration = rts_dur;
d9a1f486 241 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 242 buf = hdr;
243
244 ep = 2;
245 } else {
246 /* fc needs to be calculated before skb_push() */
247 unsigned int epmap[4] = { 6, 7, 5, 4 };
248 struct ieee80211_hdr *tx_hdr =
249 (struct ieee80211_hdr *)(skb->data);
250 u16 fc = le16_to_cpu(tx_hdr->frame_control);
251
252 struct rtl8187b_tx_hdr *hdr =
253 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
254 struct ieee80211_rate *txrate =
255 ieee80211_get_tx_rate(dev, info);
256 memset(hdr, 0, sizeof(*hdr));
257 hdr->flags = cpu_to_le32(flags);
258 hdr->rts_duration = rts_dur;
d9a1f486 259 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 260 hdr->tx_duration =
261 ieee80211_generic_frame_duration(dev, priv->vif,
262 skb->len, txrate);
263 buf = hdr;
264
265 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
266 ep = 12;
267 else
268 ep = epmap[skb_get_queue_mapping(skb)];
269 }
605bebe2 270
e6a9854b
JB		 271 info->rate_driver_data[0] = dev;
272 info->rate_driver_data[1] = urb;
6f7853f3
HTL		 273
274 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
275 buf, skb->len, rtl8187_tx_cb, skb);
2fcbab04 276 urb->transfer_flags |= URB_ZERO_PACKET;
c1db52b9 277 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 278 rc = usb_submit_urb(urb, GFP_ATOMIC);
279 if (rc < 0) {
c1db52b9 280 usb_unanchor_urb(urb);
ea8ee240
ON		 281 kfree_skb(skb);
282 }
c1db52b9 283 usb_free_urb(urb);
605bebe2 284
d6e2be98 285 return NETDEV_TX_OK;
605bebe2
MW		 286}
287
288static void rtl8187_rx_cb(struct urb *urb)
289{
290 struct sk_buff *skb = (struct sk_buff *)urb->context;
291 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
292 struct ieee80211_hw *dev = info->dev;
293 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 294 struct ieee80211_rx_status rx_status = { 0 };
295 int rate, signal;
4150c572 296 u32 flags;
0ccd58fc 297 u32 quality;
d8588227 298 unsigned long f;
605bebe2 299
d8588227 300 spin_lock_irqsave(&priv->rx_queue.lock, f);
605bebe2
MW		 301 if (skb->next)
302 __skb_unlink(skb, &priv->rx_queue);
303 else {
d8588227 304 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
605bebe2
MW		 305 return;
306 }
d8588227 307 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
c1db52b9 308 skb_put(skb, urb->actual_length);
605bebe2
MW		 309
310 if (unlikely(urb->status)) {
605bebe2
MW		 311 dev_kfree_skb_irq(skb);
312 return;
313 }
314
6f7853f3
HTL		 315 if (!priv->is_rtl8187b) {
316 struct rtl8187_rx_hdr *hdr =
317 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
318 flags = le32_to_cpu(hdr->flags);
a7db74f4
LF		 319 /* As with the RTL8187B below, the AGC is used to calculate
320 * signal strength and quality. In this case, the scaling
321 * constants are derived from the output of p54usb.
322 */
323 quality = 130 - ((41 * hdr->agc) >> 6);
324 signal = -4 - ((27 * hdr->agc) >> 6);
6f7853f3 325 rx_status.antenna = (hdr->signal >> 7) & 1;
6f7853f3 326 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3
HTL		 327 } else {
328 struct rtl8187b_rx_hdr *hdr =
329 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
0ccd58fc
LF		 330 /* The Realtek datasheet for the RTL8187B shows that the RX
331 * header contains the following quantities: signal quality,
332 * RSSI, AGC, the received power in dB, and the measured SNR.
333 * In testing, none of these quantities show qualitative
334 * agreement with AP signal strength, except for the AGC,
335 * which is inversely proportional to the strength of the
336 * signal. In the following, the quality and signal strength
337 * are derived from the AGC. The arbitrary scaling constants
338 * are chosen to make the results close to the values obtained
339 * for a BCM4312 using b43 as the driver. The noise is ignored
340 * for now.
341 */
6f7853f3 342 flags = le32_to_cpu(hdr->flags);
0ccd58fc 343 quality = 170 - hdr->agc;
0ccd58fc 344 signal = 14 - hdr->agc / 2;
0ccd58fc 345 rx_status.antenna = (hdr->rssi >> 7) & 1;
6f7853f3 346 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3 347 }
605bebe2 348
a7db74f4
LF		 349 if (quality > 100)
350 quality = 100;
351 rx_status.qual = quality;
352 priv->quality = quality;
353 rx_status.signal = signal;
354 priv->signal = signal;
355 rate = (flags >> 20) & 0xF;
6f7853f3 356 skb_trim(skb, flags & 0x0FFF);
8318d78a
JB		 357 rx_status.rate_idx = rate;
358 rx_status.freq = dev->conf.channel->center_freq;
359 rx_status.band = dev->conf.channel->band;
03bffc13 360 rx_status.flag |= RX_FLAG_TSFT;
38e3b0d8 361 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
4150c572 362 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
605bebe2
MW		 363 ieee80211_rx_irqsafe(dev, skb, &rx_status);
364
365 skb = dev_alloc_skb(RTL8187_MAX_RX);
366 if (unlikely(!skb)) {
605bebe2
MW		 367 /* TODO check rx queue length and refill *somewhere* */
368 return;
369 }
370
371 info = (struct rtl8187_rx_info *)skb->cb;
372 info->urb = urb;
373 info->dev = dev;
374 urb->transfer_buffer = skb_tail_pointer(skb);
375 urb->context = skb;
376 skb_queue_tail(&priv->rx_queue, skb);
377
c1db52b9
LF		 378 usb_anchor_urb(urb, &priv->anchored);
379 if (usb_submit_urb(urb, GFP_ATOMIC)) {
380 usb_unanchor_urb(urb);
381 skb_unlink(skb, &priv->rx_queue);
382 dev_kfree_skb_irq(skb);
383 }
605bebe2
MW		 384}
385
386static int rtl8187_init_urbs(struct ieee80211_hw *dev)
387{
388 struct rtl8187_priv *priv = dev->priv;
c1db52b9 389 struct urb *entry = NULL;
605bebe2
MW		 390 struct sk_buff *skb;
391 struct rtl8187_rx_info *info;
c1db52b9 392 int ret = 0;
605bebe2
MW		 393
394 while (skb_queue_len(&priv->rx_queue) < 8) {
395 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
c1db52b9
LF		 396 if (!skb) {
397 ret = -ENOMEM;
398 goto err;
399 }
605bebe2
MW		 400 entry = usb_alloc_urb(0, GFP_KERNEL);
401 if (!entry) {
c1db52b9
LF		 402 ret = -ENOMEM;
403 goto err;
605bebe2
MW		 404 }
405 usb_fill_bulk_urb(entry, priv->udev,
6f7853f3
HTL		 406 usb_rcvbulkpipe(priv->udev,
407 priv->is_rtl8187b ? 3 : 1),
605bebe2
MW		 408 skb_tail_pointer(skb),
409 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
410 info = (struct rtl8187_rx_info *)skb->cb;
411 info->urb = entry;
412 info->dev = dev;
413 skb_queue_tail(&priv->rx_queue, skb);
c1db52b9
LF		 414 usb_anchor_urb(entry, &priv->anchored);
415 ret = usb_submit_urb(entry, GFP_KERNEL);
416 if (ret) {
417 skb_unlink(skb, &priv->rx_queue);
418 usb_unanchor_urb(entry);
419 goto err;
420 }
421 usb_free_urb(entry);
605bebe2 422 }
c1db52b9 423 return ret;
605bebe2 424
c1db52b9
LF		 425err:
426 usb_free_urb(entry);
427 kfree_skb(skb);
428 usb_kill_anchored_urbs(&priv->anchored);
429 return ret;
605bebe2
MW		 430}
431
3517afde
HRK		 432static void rtl8187b_status_cb(struct urb *urb)
433{
434 struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
435 struct rtl8187_priv *priv = hw->priv;
436 u64 val;
437 unsigned int cmd_type;
438
c1db52b9 439 if (unlikely(urb->status))
3517afde 440 return;
3517afde
HRK		 441
442 /*
443 * Read from status buffer:
444 *
445 * bits [30:31] = cmd type:
446 * - 0 indicates tx beacon interrupt
447 * - 1 indicates tx close descriptor
448 *
449 * In the case of tx beacon interrupt:
450 * [0:9] = Last Beacon CW
451 * [10:29] = reserved
452 * [30:31] = 00b
453 * [32:63] = Last Beacon TSF
454 *
455 * If it's tx close descriptor:
456 * [0:7] = Packet Retry Count
457 * [8:14] = RTS Retry Count
458 * [15] = TOK
459 * [16:27] = Sequence No
460 * [28] = LS
461 * [29] = FS
462 * [30:31] = 01b
463 * [32:47] = unused (reserved?)
464 * [48:63] = MAC Used Time
465 */
466 val = le64_to_cpu(priv->b_tx_status.buf);
467
468 cmd_type = (val >> 30) & 0x3;
469 if (cmd_type == 1) {
470 unsigned int pkt_rc, seq_no;
471 bool tok;
472 struct sk_buff *skb;
473 struct ieee80211_hdr *ieee80211hdr;
474 unsigned long flags;
475
476 pkt_rc = val & 0xFF;
477 tok = val & (1 << 15);
478 seq_no = (val >> 16) & 0xFFF;
479
480 spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
481 skb_queue_reverse_walk(&priv->b_tx_status.queue, skb) {
482 ieee80211hdr = (struct ieee80211_hdr *)skb->data;
483
484 /*
485 * While testing, it was discovered that the seq_no
486 * doesn't actually contains the sequence number.
487 * Instead of returning just the 12 bits of sequence
488 * number, hardware is returning entire sequence control
489 * (fragment number plus sequence number) in a 12 bit
490 * only field overflowing after some time. As a
491 * workaround, just consider the lower bits, and expect
492 * it's unlikely we wrongly ack some sent data
493 */
494 if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
495 & 0xFFF) == seq_no)
496 break;
497 }
498 if (skb != (struct sk_buff *) &priv->b_tx_status.queue) {
499 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
500
501 __skb_unlink(skb, &priv->b_tx_status.queue);
502 if (tok)
503 info->flags |= IEEE80211_TX_STAT_ACK;
1548c86a 504 info->status.rates[0].count = pkt_rc + 1;
3517afde
HRK		 505
506 ieee80211_tx_status_irqsafe(hw, skb);
507 }
508 spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
509 }
510
c1db52b9
LF		 511 usb_anchor_urb(urb, &priv->anchored);
512 if (usb_submit_urb(urb, GFP_ATOMIC))
513 usb_unanchor_urb(urb);
3517afde
HRK		 514}
515
516static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
517{
518 struct rtl8187_priv *priv = dev->priv;
519 struct urb *entry;
c1db52b9 520 int ret = 0;
3517afde
HRK		 521
522 entry = usb_alloc_urb(0, GFP_KERNEL);
523 if (!entry)
524 return -ENOMEM;
3517afde
HRK		 525
526 usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
527 &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
528 rtl8187b_status_cb, dev);
529
c1db52b9
LF		 530 usb_anchor_urb(entry, &priv->anchored);
531 ret = usb_submit_urb(entry, GFP_KERNEL);
532 if (ret)
533 usb_unanchor_urb(entry);
534 usb_free_urb(entry);
3517afde 535
c1db52b9 536 return ret;
3517afde
HRK		 537}
538
f8a08c34 539static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
605bebe2
MW		 540{
541 struct rtl8187_priv *priv = dev->priv;
542 u8 reg;
543 int i;
544
605bebe2
MW		 545 reg = rtl818x_ioread8(priv, &priv->map->CMD);
546 reg &= (1 << 1);
547 reg |= RTL818X_CMD_RESET;
548 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
549
550 i = 10;
551 do {
552 msleep(2);
553 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
554 RTL818X_CMD_RESET))
555 break;
556 } while (--i);
557
558 if (!i) {
559 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
560 return -ETIMEDOUT;
561 }
562
563 /* reload registers from eeprom */
564 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
565
566 i = 10;
567 do {
568 msleep(4);
569 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
570 RTL818X_EEPROM_CMD_CONFIG))
571 break;
572 } while (--i);
573
574 if (!i) {
575 printk(KERN_ERR "%s: eeprom reset timeout!\n",
576 wiphy_name(dev->wiphy));
577 return -ETIMEDOUT;
578 }
579
f8a08c34
HTL		 580 return 0;
581}
582
583static int rtl8187_init_hw(struct ieee80211_hw *dev)
584{
585 struct rtl8187_priv *priv = dev->priv;
586 u8 reg;
587 int res;
588
589 /* reset */
590 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
591 RTL818X_EEPROM_CMD_CONFIG);
592 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
593 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
594 RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 595 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
596 RTL8187_RTL8225_ANAPARAM_ON);
597 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
598 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 599 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
600 ~RTL818X_CONFIG3_ANAPARAM_WRITE);
601 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
602 RTL818X_EEPROM_CMD_NORMAL);
603
604 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
605
606 msleep(200);
607 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
608 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
609 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
610 msleep(200);
611
612 res = rtl8187_cmd_reset(dev);
613 if (res)
614 return res;
615
605bebe2
MW		 616 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
617 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
f8a08c34
HTL		 618 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
619 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 620 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
621 RTL8187_RTL8225_ANAPARAM_ON);
622 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
623 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 624 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
625 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
605bebe2
MW		 626 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
627
628 /* setup card */
629 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
630 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
631
632 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
633 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
634 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
635
636 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
605bebe2
MW		 637
638 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
639 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
640 reg &= 0x3F;
641 reg |= 0x80;
642 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
643
644 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
645
646 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
647 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
648 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
649
650 // TODO: set RESP_RATE and BRSR properly
651 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
652 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
653
654 /* host_usb_init */
655 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
656 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
657 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
658 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
659 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
660 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
661 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
662 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
663 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
664 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
665 msleep(100);
666
667 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
668 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
669 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
f8a08c34
HTL		 670 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
671 RTL818X_EEPROM_CMD_CONFIG);
605bebe2 672 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
f8a08c34
HTL		 673 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
674 RTL818X_EEPROM_CMD_NORMAL);
605bebe2
MW		 675 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
676 msleep(100);
677
f6532111 678 priv->rf->init(dev);
605bebe2
MW		 679
680 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
f6532111
MW		 681 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
682 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 683 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
684 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
685 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
f6532111 686 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 687
688 return 0;
689}
690
f8a08c34
HTL		 691static const u8 rtl8187b_reg_table[][3] = {
692 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
693 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
694 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
695 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
696
697 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
698 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
699 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
700 {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
701 {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
702 {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
703
704 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
705 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
706 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
707 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
708 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
709 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
710 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
711 {0x73, 0x9A, 2},
712
713 {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
714 {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
715 {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
716 {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
717 {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x91, 0x03, 0},
718
719 {0x4C, 0x00, 2}, {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0},
720 {0x8E, 0x08, 0}, {0x8F, 0x00, 0}
721};
722
723static int rtl8187b_init_hw(struct ieee80211_hw *dev)
724{
725 struct rtl8187_priv *priv = dev->priv;
726 int res, i;
727 u8 reg;
728
729 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
730 RTL818X_EEPROM_CMD_CONFIG);
731
732 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
733 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
734 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
4ece16a1
HRK		 735 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
736 RTL8187B_RTL8225_ANAPARAM2_ON);
737 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
738 RTL8187B_RTL8225_ANAPARAM_ON);
739 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
740 RTL8187B_RTL8225_ANAPARAM3_ON);
f8a08c34
HTL		 741
742 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
743 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
744 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
745 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
746
747 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
748 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
749 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
750
751 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
752 RTL818X_EEPROM_CMD_NORMAL);
753
754 res = rtl8187_cmd_reset(dev);
755 if (res)
756 return res;
757
758 rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
759 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
760 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
761 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
762 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
763 reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
764 RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
765 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
766
767 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
768 reg = rtl818x_ioread8(priv, &priv->map->RATE_FALLBACK);
769 reg |= RTL818X_RATE_FALLBACK_ENABLE;
770 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, reg);
771
772 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
773 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
774 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
775
776 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
777 RTL818X_EEPROM_CMD_CONFIG);
778 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
779 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
780 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
781 RTL818X_EEPROM_CMD_NORMAL);
782
783 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
784 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
785 rtl818x_iowrite8_idx(priv,
786 (u8 *)(uintptr_t)
787 (rtl8187b_reg_table[i][0] | 0xFF00),
788 rtl8187b_reg_table[i][1],
789 rtl8187b_reg_table[i][2]);
790 }
791
792 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
793 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
794
795 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
796 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
797 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
798
799 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
800
801 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
802
803 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
804 RTL818X_EEPROM_CMD_CONFIG);
805 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
806 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
807 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
808 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
809 RTL818X_EEPROM_CMD_NORMAL);
810
811 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
812 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
813 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
2f20596b 814 msleep(100);
f8a08c34
HTL		 815
816 priv->rf->init(dev);
817
818 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
819 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
820 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
821
822 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
823 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
824 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
825 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
826 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
827 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
828 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
829
830 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
831 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
832 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
833 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
834 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
835 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
836 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
837 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
838 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
839 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
840 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
841 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
842 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
843
844 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
845
846 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
847
b4572a92
HRK		 848 priv->slot_time = 0x9;
849 priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
850 priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
851 priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
852 priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
853 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
854
f8a08c34
HTL		 855 return 0;
856}
857
4150c572 858static int rtl8187_start(struct ieee80211_hw *dev)
605bebe2
MW		 859{
860 struct rtl8187_priv *priv = dev->priv;
861 u32 reg;
862 int ret;
863
f8a08c34
HTL		 864 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
865 rtl8187b_init_hw(dev);
605bebe2
MW		 866 if (ret)
867 return ret;
868
7dcdd073 869 mutex_lock(&priv->conf_mutex);
c1db52b9
LF		 870
871 init_usb_anchor(&priv->anchored);
872
f8a08c34
HTL		 873 if (priv->is_rtl8187b) {
874 reg = RTL818X_RX_CONF_MGMT |
875 RTL818X_RX_CONF_DATA |
876 RTL818X_RX_CONF_BROADCAST |
877 RTL818X_RX_CONF_NICMAC |
878 RTL818X_RX_CONF_BSSID |
879 (7 << 13 /* RX FIFO threshold NONE */) |
880 (7 << 10 /* MAX RX DMA */) |
881 RTL818X_RX_CONF_RX_AUTORESETPHY |
882 RTL818X_RX_CONF_ONLYERLPKT |
883 RTL818X_RX_CONF_MULTICAST;
884 priv->rx_conf = reg;
885 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
886
887 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
888 RTL818X_TX_CONF_HW_SEQNUM |
889 RTL818X_TX_CONF_DISREQQSIZE |
890 (7 << 8 /* short retry limit */) |
891 (7 << 0 /* long retry limit */) |
892 (7 << 21 /* MAX TX DMA */));
893 rtl8187_init_urbs(dev);
3517afde 894 rtl8187b_init_status_urb(dev);
7dcdd073 895 mutex_unlock(&priv->conf_mutex);
f8a08c34
HTL		 896 return 0;
897 }
898
605bebe2
MW		 899 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
900
2fe14263
MW		 901 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
902 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
903
605bebe2
MW		 904 rtl8187_init_urbs(dev);
905
906 reg = RTL818X_RX_CONF_ONLYERLPKT |
907 RTL818X_RX_CONF_RX_AUTORESETPHY |
908 RTL818X_RX_CONF_BSSID |
909 RTL818X_RX_CONF_MGMT |
605bebe2
MW		 910 RTL818X_RX_CONF_DATA |
911 (7 << 13 /* RX FIFO threshold NONE */) |
912 (7 << 10 /* MAX RX DMA */) |
913 RTL818X_RX_CONF_BROADCAST |
605bebe2 914 RTL818X_RX_CONF_NICMAC;
605bebe2 915
4150c572 916 priv->rx_conf = reg;
605bebe2
MW		 917 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
918
919 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
920 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
921 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
922 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
923
924 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
925 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
926 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
927 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
928 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
929
930 reg = RTL818X_TX_CONF_CW_MIN |
931 (7 << 21 /* MAX TX DMA */) |
932 RTL818X_TX_CONF_NO_ICV;
933 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
934
935 reg = rtl818x_ioread8(priv, &priv->map->CMD);
936 reg |= RTL818X_CMD_TX_ENABLE;
937 reg |= RTL818X_CMD_RX_ENABLE;
938 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
7dcdd073 939 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 940
941 return 0;
942}
943
4150c572 944static void rtl8187_stop(struct ieee80211_hw *dev)
605bebe2
MW		 945{
946 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 947 struct sk_buff *skb;
948 u32 reg;
949
7dcdd073 950 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 951 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
952
953 reg = rtl818x_ioread8(priv, &priv->map->CMD);
954 reg &= ~RTL818X_CMD_TX_ENABLE;
955 reg &= ~RTL818X_CMD_RX_ENABLE;
956 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
957
f6532111 958 priv->rf->stop(dev);
605bebe2
MW		 959
960 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
961 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
962 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
963 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
964
3517afde
HRK		 965 while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
966 dev_kfree_skb_any(skb);
c1db52b9
LF		 967
968 usb_kill_anchored_urbs(&priv->anchored);
7dcdd073 969 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 970}
971
972static int rtl8187_add_interface(struct ieee80211_hw *dev,
973 struct ieee80211_if_init_conf *conf)
974{
975 struct rtl8187_priv *priv = dev->priv;
4150c572 976 int i;
605bebe2 977
05c914fe 978 if (priv->mode != NL80211_IFTYPE_MONITOR)
4150c572 979 return -EOPNOTSUPP;
605bebe2
MW		 980
981 switch (conf->type) {
05c914fe 982 case NL80211_IFTYPE_STATION:
605bebe2
MW		 983 priv->mode = conf->type;
984 break;
985 default:
986 return -EOPNOTSUPP;
987 }
988
7dcdd073 989 mutex_lock(&priv->conf_mutex);
aa979a6a
HRK		 990 priv->vif = conf->vif;
991
4150c572
JB		 992 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
993 for (i = 0; i < ETH_ALEN; i++)
994 rtl818x_iowrite8(priv, &priv->map->MAC[i],
995 ((u8 *)conf->mac_addr)[i]);
996 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
605bebe2 997
7dcdd073 998 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 999 return 0;
1000}
1001
1002static void rtl8187_remove_interface(struct ieee80211_hw *dev,
1003 struct ieee80211_if_init_conf *conf)
1004{
1005 struct rtl8187_priv *priv = dev->priv;
7dcdd073 1006 mutex_lock(&priv->conf_mutex);
05c914fe 1007 priv->mode = NL80211_IFTYPE_MONITOR;
aa979a6a 1008 priv->vif = NULL;
7dcdd073 1009 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1010}
1011
e8975581 1012static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
605bebe2
MW		 1013{
1014 struct rtl8187_priv *priv = dev->priv;
e8975581 1015 struct ieee80211_conf *conf = &dev->conf;
f6532111
MW		 1016 u32 reg;
1017
7dcdd073 1018 mutex_lock(&priv->conf_mutex);
f6532111
MW		 1019 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1020 /* Enable TX loopback on MAC level to avoid TX during channel
1021 * changes, as this has be seen to causes problems and the
1022 * card will stop work until next reset
1023 */
1024 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
1025 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
f6532111
MW		 1026 priv->rf->set_chan(dev, conf);
1027 msleep(10);
1028 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
605bebe2 1029
605bebe2
MW		 1030 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
1031 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
1032 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
1033 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
7dcdd073 1034 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1035 return 0;
1036}
1037
32bfd35d
JB		 1038static int rtl8187_config_interface(struct ieee80211_hw *dev,
1039 struct ieee80211_vif *vif,
605bebe2
MW		 1040 struct ieee80211_if_conf *conf)
1041{
1042 struct rtl8187_priv *priv = dev->priv;
1043 int i;
6f7853f3 1044 u8 reg;
605bebe2 1045
7dcdd073 1046 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 1047 for (i = 0; i < ETH_ALEN; i++)
1048 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
1049
6f7853f3
HTL		 1050 if (is_valid_ether_addr(conf->bssid)) {
1051 reg = RTL818X_MSR_INFRA;
1052 if (priv->is_rtl8187b)
1053 reg |= RTL818X_MSR_ENEDCA;
1054 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1055 } else {
1056 reg = RTL818X_MSR_NO_LINK;
1057 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1058 }
605bebe2 1059
7dcdd073 1060 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1061 return 0;
1062}
1063
b4572a92
HRK		 1064/*
1065 * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
1066 * example. Thus we have to use raw values for AC_*_PARAM register addresses.
1067 */
1068static __le32 *rtl8187b_ac_addr[4] = {
1069 (__le32 *) 0xFFF0, /* AC_VO */
1070 (__le32 *) 0xFFF4, /* AC_VI */
1071 (__le32 *) 0xFFFC, /* AC_BK */
1072 (__le32 *) 0xFFF8, /* AC_BE */
1073};
1074
1075#define SIFS_TIME 0xa
1076
f8288317
HRK		 1077static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
1078 bool use_short_preamble)
64761077 1079{
f8288317 1080 if (priv->is_rtl8187b) {
b4572a92 1081 u8 difs, eifs;
f8288317 1082 u16 ack_timeout;
b4572a92 1083 int queue;
f8288317
HRK		 1084
1085 if (use_short_slot) {
b4572a92 1086 priv->slot_time = 0x9;
f8288317
HRK		 1087 difs = 0x1c;
1088 eifs = 0x53;
1089 } else {
b4572a92 1090 priv->slot_time = 0x14;
f8288317
HRK		 1091 difs = 0x32;
1092 eifs = 0x5b;
1093 }
54ac218a 1094 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
b4572a92 1095 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
f8288317
HRK		 1096 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1097
1098 /*
1099 * BRSR+1 on 8187B is in fact EIFS register
1100 * Value in units of 4 us
1101 */
1102 rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
1103
1104 /*
1105 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
1106 * register. In units of 4 us like eifs register
1107 * ack_timeout = ack duration + plcp + difs + preamble
1108 */
1109 ack_timeout = 112 + 48 + difs;
1110 if (use_short_preamble)
1111 ack_timeout += 72;
1112 else
1113 ack_timeout += 144;
1114 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
1115 DIV_ROUND_UP(ack_timeout, 4));
b4572a92
HRK		 1116
1117 for (queue = 0; queue < 4; queue++)
1118 rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
1119 priv->aifsn[queue] * priv->slot_time +
1120 SIFS_TIME);
f8288317 1121 } else {
64761077
HRK		 1122 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1123 if (use_short_slot) {
1124 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
1125 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
1126 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
64761077
HRK		 1127 } else {
1128 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
1129 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
1130 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
64761077
HRK		 1131 }
1132 }
1133}
1134
1135static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
1136 struct ieee80211_vif *vif,
1137 struct ieee80211_bss_conf *info,
1138 u32 changed)
1139{
1140 struct rtl8187_priv *priv = dev->priv;
1141
f8288317
HRK		 1142 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
1143 rtl8187_conf_erp(priv, info->use_short_slot,
1144 info->use_short_preamble);
64761077
HRK		 1145}
1146
4150c572
JB		 1147static void rtl8187_configure_filter(struct ieee80211_hw *dev,
1148 unsigned int changed_flags,
1149 unsigned int *total_flags,
2fe14263 1150 int mc_count, struct dev_addr_list *mclist)
4150c572
JB		 1151{
1152 struct rtl8187_priv *priv = dev->priv;
1153
4150c572
JB		 1154 if (changed_flags & FIF_FCSFAIL)
1155 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1156 if (changed_flags & FIF_CONTROL)
1157 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1158 if (changed_flags & FIF_OTHER_BSS)
1159 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
2fe14263 1160 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
4150c572 1161 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
2fe14263
MW		 1162 else
1163 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1164
1165 *total_flags = 0;
4150c572 1166
4150c572
JB		 1167 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1168 *total_flags |= FIF_FCSFAIL;
1169 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1170 *total_flags |= FIF_CONTROL;
1171 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1172 *total_flags |= FIF_OTHER_BSS;
2fe14263
MW		 1173 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1174 *total_flags |= FIF_ALLMULTI;
4150c572
JB		 1175
1176 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1177}
1178
b4572a92
HRK		 1179static int rtl8187_conf_tx(struct ieee80211_hw *dev, u16 queue,
1180 const struct ieee80211_tx_queue_params *params)
1181{
1182 struct rtl8187_priv *priv = dev->priv;
1183 u8 cw_min, cw_max;
1184
1185 if (queue > 3)
1186 return -EINVAL;
1187
1188 cw_min = fls(params->cw_min);
1189 cw_max = fls(params->cw_max);
1190
1191 if (priv->is_rtl8187b) {
1192 priv->aifsn[queue] = params->aifs;
1193
1194 /*
1195 * This is the structure of AC_*_PARAM registers in 8187B:
1196 * - TXOP limit field, bit offset = 16
1197 * - ECWmax, bit offset = 12
1198 * - ECWmin, bit offset = 8
1199 * - AIFS, bit offset = 0
1200 */
1201 rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
1202 (params->txop << 16) | (cw_max << 12) |
1203 (cw_min << 8) | (params->aifs *
1204 priv->slot_time + SIFS_TIME));
1205 } else {
1206 if (queue != 0)
1207 return -EINVAL;
1208
1209 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1210 cw_min | (cw_max << 4));
1211 }
1212 return 0;
1213}
1214
605bebe2
MW		 1215static const struct ieee80211_ops rtl8187_ops = {
1216 .tx = rtl8187_tx,
4150c572 1217 .start = rtl8187_start,
605bebe2
MW		 1218 .stop = rtl8187_stop,
1219 .add_interface = rtl8187_add_interface,
1220 .remove_interface = rtl8187_remove_interface,
1221 .config = rtl8187_config,
1222 .config_interface = rtl8187_config_interface,
64761077 1223 .bss_info_changed = rtl8187_bss_info_changed,
4150c572 1224 .configure_filter = rtl8187_configure_filter,
b4572a92 1225 .conf_tx = rtl8187_conf_tx
605bebe2
MW		 1226};
1227
1228static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1229{
1230 struct ieee80211_hw *dev = eeprom->data;
1231 struct rtl8187_priv *priv = dev->priv;
1232 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1233
1234 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1235 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1236 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1237 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1238}
1239
1240static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1241{
1242 struct ieee80211_hw *dev = eeprom->data;
1243 struct rtl8187_priv *priv = dev->priv;
1244 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1245
1246 if (eeprom->reg_data_in)
1247 reg |= RTL818X_EEPROM_CMD_WRITE;
1248 if (eeprom->reg_data_out)
1249 reg |= RTL818X_EEPROM_CMD_READ;
1250 if (eeprom->reg_data_clock)
1251 reg |= RTL818X_EEPROM_CMD_CK;
1252 if (eeprom->reg_chip_select)
1253 reg |= RTL818X_EEPROM_CMD_CS;
1254
1255 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1256 udelay(10);
1257}
1258
1259static int __devinit rtl8187_probe(struct usb_interface *intf,
1260 const struct usb_device_id *id)
1261{
1262 struct usb_device *udev = interface_to_usbdev(intf);
1263 struct ieee80211_hw *dev;
1264 struct rtl8187_priv *priv;
1265 struct eeprom_93cx6 eeprom;
1266 struct ieee80211_channel *channel;
6f7853f3 1267 const char *chip_name;
605bebe2
MW		 1268 u16 txpwr, reg;
1269 int err, i;
1270
1271 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1272 if (!dev) {
1273 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1274 return -ENOMEM;
1275 }
1276
1277 priv = dev->priv;
0e25b4ef 1278 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
605bebe2
MW		 1279
1280 SET_IEEE80211_DEV(dev, &intf->dev);
1281 usb_set_intfdata(intf, dev);
1282 priv->udev = udev;
1283
1284 usb_get_dev(udev);
1285
1286 skb_queue_head_init(&priv->rx_queue);
8318d78a
JB		 1287
1288 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1289 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1290
605bebe2
MW		 1291 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1292 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1293 priv->map = (struct rtl818x_csr *)0xFF00;
8318d78a
JB		 1294
1295 priv->band.band = IEEE80211_BAND_2GHZ;
1296 priv->band.channels = priv->channels;
1297 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1298 priv->band.bitrates = priv->rates;
1299 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1300 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1301
1302
05c914fe 1303 priv->mode = NL80211_IFTYPE_MONITOR;
605bebe2 1304 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
a7db74f4 1305 IEEE80211_HW_SIGNAL_DBM |
0ccd58fc 1306 IEEE80211_HW_RX_INCLUDES_FCS;
605bebe2 1307
605bebe2
MW		 1308 eeprom.data = dev;
1309 eeprom.register_read = rtl8187_eeprom_register_read;
1310 eeprom.register_write = rtl8187_eeprom_register_write;
1311 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1312 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1313 else
1314 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1315
1316 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1317 udelay(10);
1318
1319 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1320 (__le16 __force *)dev->wiphy->perm_addr, 3);
1321 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
1322 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1323 "generated MAC address\n");
1324 random_ether_addr(dev->wiphy->perm_addr);
1325 }
1326
1327 channel = priv->channels;
1328 for (i = 0; i < 3; i++) {
1329 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1330 &txpwr);
8318d78a
JB		 1331 (*channel++).hw_value = txpwr & 0xFF;
1332 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 1333 }
1334 for (i = 0; i < 2; i++) {
1335 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1336 &txpwr);
8318d78a
JB		 1337 (*channel++).hw_value = txpwr & 0xFF;
1338 (*channel++).hw_value = txpwr >> 8;
605bebe2 1339 }
605bebe2
MW		 1340
1341 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1342 &priv->txpwr_base);
1343
f6532111
MW		 1344 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1345 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 1346 /* 0 means asic B-cut, we should use SW 3 wire
1347 * bit-by-bit banging for radio. 1 means we can use
1348 * USB specific request to write radio registers */
1349 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
f6532111 1350 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 1351 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1352
6f7853f3
HTL		 1353 if (!priv->is_rtl8187b) {
1354 u32 reg32;
1355 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1356 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1357 switch (reg32) {
0e25b4ef
LF		 1358 case RTL818X_TX_CONF_R8187vD_B:
1359 /* Some RTL8187B devices have a USB ID of 0x8187
1360 * detect them here */
1361 chip_name = "RTL8187BvB(early)";
1362 priv->is_rtl8187b = 1;
1363 priv->hw_rev = RTL8187BvB;
1364 break;
1365 case RTL818X_TX_CONF_R8187vD:
6f7853f3
HTL		 1366 chip_name = "RTL8187vD";
1367 break;
1368 default:
1369 chip_name = "RTL8187vB (default)";
1370 }
1371 } else {
6f7853f3
HTL		 1372 /*
1373 * Force USB request to write radio registers for 8187B, Realtek
1374 * only uses it in their sources
1375 */
1376 /*if (priv->asic_rev == 0) {
1377 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1378 "requests to write to radio registers\n");
1379 priv->asic_rev = 1;
1380 }*/
1381 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1382 case RTL818X_R8187B_B:
1383 chip_name = "RTL8187BvB";
1384 priv->hw_rev = RTL8187BvB;
1385 break;
1386 case RTL818X_R8187B_D:
1387 chip_name = "RTL8187BvD";
1388 priv->hw_rev = RTL8187BvD;
1389 break;
1390 case RTL818X_R8187B_E:
1391 chip_name = "RTL8187BvE";
1392 priv->hw_rev = RTL8187BvE;
1393 break;
1394 default:
1395 chip_name = "RTL8187BvB (default)";
1396 priv->hw_rev = RTL8187BvB;
1397 }
1398 }
1399
0e25b4ef
LF		 1400 if (!priv->is_rtl8187b) {
1401 for (i = 0; i < 2; i++) {
1402 eeprom_93cx6_read(&eeprom,
1403 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1404 &txpwr);
1405 (*channel++).hw_value = txpwr & 0xFF;
1406 (*channel++).hw_value = txpwr >> 8;
1407 }
1408 } else {
1409 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1410 &txpwr);
1411 (*channel++).hw_value = txpwr & 0xFF;
1412
1413 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1414 (*channel++).hw_value = txpwr & 0xFF;
1415
1416 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1417 (*channel++).hw_value = txpwr & 0xFF;
1418 (*channel++).hw_value = txpwr >> 8;
1419 }
1420
a7db74f4 1421 if (priv->is_rtl8187b)
c8f96974 1422 printk(KERN_WARNING "rtl8187: 8187B chip detected.\n");
0ccd58fc 1423
94778280
JB		 1424 /*
1425 * XXX: Once this driver supports anything that requires
1426 * beacons it must implement IEEE80211_TX_CTL_ASSIGN_SEQ.
1427 */
f59ac048
LR		 1428 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1429
0e25b4ef
LF		 1430 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1431 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1432 " info!\n");
1433
f6532111 1434 priv->rf = rtl8187_detect_rf(dev);
0e25b4ef
LF		 1435 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1436 sizeof(struct rtl8187_tx_hdr) :
1437 sizeof(struct rtl8187b_tx_hdr);
1438 if (!priv->is_rtl8187b)
1439 dev->queues = 1;
1440 else
1441 dev->queues = 4;
605bebe2
MW		 1442
1443 err = ieee80211_register_hw(dev);
1444 if (err) {
1445 printk(KERN_ERR "rtl8187: Cannot register device\n");
1446 goto err_free_dev;
1447 }
7dcdd073 1448 mutex_init(&priv->conf_mutex);
3517afde 1449 skb_queue_head_init(&priv->b_tx_status.queue);
605bebe2 1450
e174961c
JB		 1451 printk(KERN_INFO "%s: hwaddr %pM, %s V%d + %s\n",
1452 wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
6f7853f3 1453 chip_name, priv->asic_rev, priv->rf->name);
605bebe2
MW		 1454
1455 return 0;
1456
1457 err_free_dev:
1458 ieee80211_free_hw(dev);
1459 usb_set_intfdata(intf, NULL);
1460 usb_put_dev(udev);
1461 return err;
1462}
1463
1464static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1465{
1466 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1467 struct rtl8187_priv *priv;
1468
1469 if (!dev)
1470 return;
1471
1472 ieee80211_unregister_hw(dev);
1473
1474 priv = dev->priv;
d6e2be98 1475 usb_reset_device(priv->udev);
605bebe2
MW		 1476 usb_put_dev(interface_to_usbdev(intf));
1477 ieee80211_free_hw(dev);
1478}
1479
1480static struct usb_driver rtl8187_driver = {
1481 .name = KBUILD_MODNAME,
1482 .id_table = rtl8187_table,
1483 .probe = rtl8187_probe,
500c1197 1484 .disconnect = __devexit_p(rtl8187_disconnect),
605bebe2
MW		 1485};
1486
1487static int __init rtl8187_init(void)
1488{
1489 return usb_register(&rtl8187_driver);
1490}
1491
1492static void __exit rtl8187_exit(void)
1493{
1494 usb_deregister(&rtl8187_driver);
1495}
1496
1497module_init(rtl8187_init);
1498module_exit(rtl8187_exit);
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