]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/wireless/rt2x00/rt2800pci.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'master' of git://dev.medozas.de/linux
[net-next-2.6.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
CommitLineData
a9b3a9f7 1/*
9c9a0d14
GW		 2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7
ID		 10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
34#include <linux/crc-ccitt.h>
35#include <linux/delay.h>
36#include <linux/etherdevice.h>
37#include <linux/init.h>
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/pci.h>
41#include <linux/platform_device.h>
42#include <linux/eeprom_93cx6.h>
43
44#include "rt2x00.h"
45#include "rt2x00pci.h"
46#include "rt2x00soc.h"
7ef5cc92 47#include "rt2800lib.h"
b54f78a8 48#include "rt2800.h"
a9b3a9f7
ID		 49#include "rt2800pci.h"
50
a9b3a9f7
ID		 51/*
52 * Allow hardware encryption to be disabled.
53 */
54static int modparam_nohwcrypt = 1;
55module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
56MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57
a9b3a9f7
ID		 58static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
59{
60 unsigned int i;
61 u32 reg;
62
f18d4463
LC		 63 /*
64 * SOC devices don't support MCU requests.
65 */
66 if (rt2x00_is_soc(rt2x00dev))
67 return;
68
a9b3a9f7 69 for (i = 0; i < 200; i++) {
9ca21eb7 70 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
a9b3a9f7
ID		 71
72 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
75 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
76 break;
77
78 udelay(REGISTER_BUSY_DELAY);
79 }
80
81 if (i == 200)
82 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
83
9ca21eb7
BZ		 84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
85 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7
ID		 86}
87
00e23ce2 88#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 89static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
90{
91 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
92
93 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
94}
95#else
96static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
97{
98}
00e23ce2 99#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 100
101#ifdef CONFIG_RT2800PCI_PCI
102static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
103{
104 struct rt2x00_dev *rt2x00dev = eeprom->data;
105 u32 reg;
106
9ca21eb7 107 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 108
109 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
110 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
111 eeprom->reg_data_clock =
112 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
113 eeprom->reg_chip_select =
114 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
115}
116
117static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
118{
119 struct rt2x00_dev *rt2x00dev = eeprom->data;
120 u32 reg = 0;
121
122 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
124 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
125 !!eeprom->reg_data_clock);
126 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
127 !!eeprom->reg_chip_select);
128
9ca21eb7 129 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7
ID		 130}
131
132static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
133{
134 struct eeprom_93cx6 eeprom;
135 u32 reg;
136
9ca21eb7 137 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
a9b3a9f7
ID		 138
139 eeprom.data = rt2x00dev;
140 eeprom.register_read = rt2800pci_eepromregister_read;
141 eeprom.register_write = rt2800pci_eepromregister_write;
142 eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
143 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
144 eeprom.reg_data_in = 0;
145 eeprom.reg_data_out = 0;
146 eeprom.reg_data_clock = 0;
147 eeprom.reg_chip_select = 0;
148
149 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
150 EEPROM_SIZE / sizeof(u16));
151}
152
a6598682
GW		 153static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
154{
30e84034 155 return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7
ID		 156}
157
30e84034 158static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 159{
30e84034 160 rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7
ID		 161}
162#else
163static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
164{
165}
166
a6598682
GW		 167static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
168{
169 return 0;
170}
171
a9b3a9f7
ID		 172static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
173{
174}
175#endif /* CONFIG_RT2800PCI_PCI */
176
a9b3a9f7
ID		 177/*
178 * Firmware functions
179 */
180static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
181{
182 return FIRMWARE_RT2860;
183}
184
185static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
186 const u8 *data, const size_t len)
187{
188 u16 fw_crc;
189 u16 crc;
190
191 /*
192 * Only support 8kb firmware files.
193 */
194 if (len != 8192)
195 return FW_BAD_LENGTH;
196
197 /*
198 * The last 2 bytes in the firmware array are the crc checksum itself,
199 * this means that we should never pass those 2 bytes to the crc
200 * algorithm.
201 */
202 fw_crc = (data[len - 2] << 8 | data[len - 1]);
203
204 /*
205 * Use the crc ccitt algorithm.
206 * This will return the same value as the legacy driver which
207 * used bit ordering reversion on the both the firmware bytes
208 * before input input as well as on the final output.
209 * Obviously using crc ccitt directly is much more efficient.
210 */
211 crc = crc_ccitt(~0, data, len - 2);
212
213 /*
214 * There is a small difference between the crc-itu-t + bitrev and
215 * the crc-ccitt crc calculation. In the latter method the 2 bytes
216 * will be swapped, use swab16 to convert the crc to the correct
217 * value.
218 */
219 crc = swab16(crc);
220
221 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
222}
223
224static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
225 const u8 *data, const size_t len)
226{
227 unsigned int i;
228 u32 reg;
229
230 /*
231 * Wait for stable hardware.
232 */
233 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 234 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
a9b3a9f7
ID		 235 if (reg && reg != ~0)
236 break;
237 msleep(1);
238 }
239
240 if (i == REGISTER_BUSY_COUNT) {
241 ERROR(rt2x00dev, "Unstable hardware.\n");
242 return -EBUSY;
243 }
244
9ca21eb7
BZ		 245 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
246 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
a9b3a9f7
ID		 247
248 /*
249 * Disable DMA, will be reenabled later when enabling
250 * the radio.
251 */
9ca21eb7 252 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 253 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
254 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
255 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
256 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
257 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 258 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7
ID		 259
260 /*
261 * enable Host program ram write selection
262 */
263 reg = 0;
264 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
9ca21eb7 265 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7
ID		 266
267 /*
268 * Write firmware to device.
269 */
4f2732ce 270 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
a9b3a9f7
ID		 271 data, len);
272
9ca21eb7
BZ		 273 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
274 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7
ID		 275
276 /*
277 * Wait for device to stabilize.
278 */
279 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9ca21eb7 280 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
a9b3a9f7
ID		 281 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
282 break;
283 msleep(1);
284 }
285
286 if (i == REGISTER_BUSY_COUNT) {
287 ERROR(rt2x00dev, "PBF system register not ready.\n");
288 return -EBUSY;
289 }
290
291 /*
292 * Disable interrupts
293 */
294 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
295
296 /*
297 * Initialize BBP R/W access agent
298 */
9ca21eb7
BZ		 299 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
300 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7
ID		 301
302 return 0;
303}
304
305/*
306 * Initialization functions.
307 */
308static bool rt2800pci_get_entry_state(struct queue_entry *entry)
309{
310 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
311 u32 word;
312
313 if (entry->queue->qid == QID_RX) {
314 rt2x00_desc_read(entry_priv->desc, 1, &word);
315
316 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
317 } else {
318 rt2x00_desc_read(entry_priv->desc, 1, &word);
319
320 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
321 }
322}
323
324static void rt2800pci_clear_entry(struct queue_entry *entry)
325{
326 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
327 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
328 u32 word;
329
330 if (entry->queue->qid == QID_RX) {
331 rt2x00_desc_read(entry_priv->desc, 0, &word);
332 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
333 rt2x00_desc_write(entry_priv->desc, 0, word);
334
335 rt2x00_desc_read(entry_priv->desc, 1, &word);
336 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
337 rt2x00_desc_write(entry_priv->desc, 1, word);
338 } else {
339 rt2x00_desc_read(entry_priv->desc, 1, &word);
340 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
341 rt2x00_desc_write(entry_priv->desc, 1, word);
342 }
343}
344
345static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
346{
347 struct queue_entry_priv_pci *entry_priv;
348 u32 reg;
349
a9b3a9f7
ID		 350 /*
351 * Initialize registers.
352 */
353 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
9ca21eb7
BZ		 354 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
355 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
356 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
357 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
a9b3a9f7
ID		 358
359 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
9ca21eb7
BZ		 360 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
361 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
362 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
363 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
a9b3a9f7
ID		 364
365 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
9ca21eb7
BZ		 366 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
367 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
368 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
369 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
a9b3a9f7
ID		 370
371 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
9ca21eb7
BZ		 372 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
373 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
374 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
375 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
a9b3a9f7
ID		 376
377 entry_priv = rt2x00dev->rx->entries[0].priv_data;
9ca21eb7
BZ		 378 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
379 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
380 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
381 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
a9b3a9f7
ID		 382
383 /*
384 * Enable global DMA configuration
385 */
9ca21eb7 386 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 387 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
388 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
389 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 390 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 391
9ca21eb7 392 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
a9b3a9f7
ID		 393
394 return 0;
395}
396
a9b3a9f7
ID		 397/*
398 * Device state switch handlers.
399 */
400static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
401 enum dev_state state)
402{
403 u32 reg;
404
9ca21eb7 405 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 406 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
407 (state == STATE_RADIO_RX_ON) ||
408 (state == STATE_RADIO_RX_ON_LINK));
9ca21eb7 409 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 410}
411
412static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
413 enum dev_state state)
414{
415 int mask = (state == STATE_RADIO_IRQ_ON);
416 u32 reg;
417
418 /*
419 * When interrupts are being enabled, the interrupt registers
420 * should clear the register to assure a clean state.
421 */
422 if (state == STATE_RADIO_IRQ_ON) {
9ca21eb7
BZ		 423 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
424 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 425 }
426
9ca21eb7 427 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
a9b3a9f7
ID		 428 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
429 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
430 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
431 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
432 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
433 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
434 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
435 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
436 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
437 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
438 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
439 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
440 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
441 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
442 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
443 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
444 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
445 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
9ca21eb7 446 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
a9b3a9f7
ID		 447}
448
a9b3a9f7
ID		 449static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
450{
451 u32 reg;
452 u16 word;
453
454 /*
455 * Initialize all registers.
456 */
67a4c1e2 457 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
a9b3a9f7 458 rt2800pci_init_queues(rt2x00dev) ||
fcf51541 459 rt2800_init_registers(rt2x00dev) ||
67a4c1e2 460 rt2800_wait_wpdma_ready(rt2x00dev) ||
fcf51541
BZ		 461 rt2800_init_bbp(rt2x00dev) ||
462 rt2800_init_rfcsr(rt2x00dev)))
a9b3a9f7
ID		 463 return -EIO;
464
465 /*
466 * Send signal to firmware during boot time.
467 */
3a9e5b0f 468 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
a9b3a9f7
ID		 469
470 /*
471 * Enable RX.
472 */
9ca21eb7 473 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 474 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
475 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9ca21eb7 476 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7 477
9ca21eb7 478 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 479 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
480 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
481 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
482 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 483 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 484
9ca21eb7 485 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
a9b3a9f7
ID		 486 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
487 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9ca21eb7 488 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
a9b3a9f7
ID		 489
490 /*
491 * Initialize LED control
492 */
493 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
3a9e5b0f 494 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
a9b3a9f7
ID		 495 word & 0xff, (word >> 8) & 0xff);
496
497 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
3a9e5b0f 498 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
a9b3a9f7
ID		 499 word & 0xff, (word >> 8) & 0xff);
500
501 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
3a9e5b0f 502 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
a9b3a9f7
ID		 503 word & 0xff, (word >> 8) & 0xff);
504
505 return 0;
506}
507
508static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
509{
510 u32 reg;
511
9ca21eb7 512 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
a9b3a9f7
ID		 513 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
514 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
515 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
516 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
517 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9ca21eb7 518 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
a9b3a9f7 519
9ca21eb7
BZ		 520 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
521 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
522 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
a9b3a9f7 523
9ca21eb7 524 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
a9b3a9f7 525
9ca21eb7 526 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 527 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
528 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
529 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
530 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
531 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
532 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
533 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
9ca21eb7 534 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7 535
9ca21eb7
BZ		 536 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
537 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
a9b3a9f7
ID		 538
539 /* Wait for DMA, ignore error */
67a4c1e2 540 rt2800_wait_wpdma_ready(rt2x00dev);
a9b3a9f7
ID		 541}
542
543static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
544 enum dev_state state)
545{
546 /*
547 * Always put the device to sleep (even when we intend to wakeup!)
548 * if the device is booting and wasn't asleep it will return
549 * failure when attempting to wakeup.
550 */
3a9e5b0f 551 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
a9b3a9f7
ID		 552
553 if (state == STATE_AWAKE) {
3a9e5b0f 554 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
a9b3a9f7
ID		 555 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
556 }
557
558 return 0;
559}
560
561static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
562 enum dev_state state)
563{
564 int retval = 0;
565
566 switch (state) {
567 case STATE_RADIO_ON:
568 /*
569 * Before the radio can be enabled, the device first has
570 * to be woken up. After that it needs a bit of time
571 * to be fully awake and then the radio can be enabled.
572 */
573 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
574 msleep(1);
575 retval = rt2800pci_enable_radio(rt2x00dev);
576 break;
577 case STATE_RADIO_OFF:
578 /*
579 * After the radio has been disabled, the device should
580 * be put to sleep for powersaving.
581 */
582 rt2800pci_disable_radio(rt2x00dev);
583 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
584 break;
585 case STATE_RADIO_RX_ON:
586 case STATE_RADIO_RX_ON_LINK:
587 case STATE_RADIO_RX_OFF:
588 case STATE_RADIO_RX_OFF_LINK:
589 rt2800pci_toggle_rx(rt2x00dev, state);
590 break;
591 case STATE_RADIO_IRQ_ON:
592 case STATE_RADIO_IRQ_OFF:
593 rt2800pci_toggle_irq(rt2x00dev, state);
594 break;
595 case STATE_DEEP_SLEEP:
596 case STATE_SLEEP:
597 case STATE_STANDBY:
598 case STATE_AWAKE:
599 retval = rt2800pci_set_state(rt2x00dev, state);
600 break;
601 default:
602 retval = -ENOTSUPP;
603 break;
604 }
605
606 if (unlikely(retval))
607 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
608 state, retval);
609
610 return retval;
611}
612
613/*
614 * TX descriptor initialization
615 */
745b1ae3
HS		 616static int rt2800pci_write_tx_data(struct queue_entry* entry,
617 struct txentry_desc *txdesc)
a9b3a9f7 618{
745b1ae3
HS		 619 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
620 struct sk_buff *skb = entry->skb;
621 struct skb_frame_desc *skbdesc;
622 int ret;
623 __le32 *txwi;
a9b3a9f7
ID		 624 u32 word;
625
745b1ae3
HS		 626 ret = rt2x00pci_write_tx_data(entry, txdesc);
627 if (ret)
628 return ret;
629
630 skbdesc = get_skb_frame_desc(skb);
631 txwi = (__le32 *)(skb->data - rt2x00dev->ops->extra_tx_headroom);
632
a9b3a9f7
ID		 633 /*
634 * Initialize TX Info descriptor
635 */
636 rt2x00_desc_read(txwi, 0, &word);
637 rt2x00_set_field32(&word, TXWI_W0_FRAG,
638 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
639 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
640 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
641 rt2x00_set_field32(&word, TXWI_W0_TS,
642 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
643 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
644 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
645 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
646 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
647 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
648 rt2x00_set_field32(&word, TXWI_W0_BW,
649 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
650 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
651 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
652 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
653 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
654 rt2x00_desc_write(txwi, 0, word);
655
656 rt2x00_desc_read(txwi, 1, &word);
657 rt2x00_set_field32(&word, TXWI_W1_ACK,
658 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
659 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
660 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
661 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
662 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
663 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
f644fea1 664 txdesc->key_idx : 0xff);
a9b3a9f7 665 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
df624ca5 666 txdesc->length);
a9b3a9f7
ID		 667 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
668 skbdesc->entry->queue->qid + 1);
669 rt2x00_desc_write(txwi, 1, word);
670
671 /*
672 * Always write 0 to IV/EIV fields, hardware will insert the IV
77dba493
BZ		 673 * from the IVEIV register when TXD_W3_WIV is set to 0.
674 * When TXD_W3_WIV is set to 1 it will use the IV data
a9b3a9f7
ID		 675 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
676 * crypto entry in the registers should be used to encrypt the frame.
677 */
678 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
679 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
680
745b1ae3
HS		 681 return 0;
682}
683
684
685static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
686 struct sk_buff *skb,
687 struct txentry_desc *txdesc)
688{
689 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
690 __le32 *txd = skbdesc->desc;
691 u32 word;
692
a9b3a9f7
ID		 693 /*
694 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
695 * must contains a TXWI structure + 802.11 header + padding + 802.11
696 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
697 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
698 * data. It means that LAST_SEC0 is always 0.
699 */
700
701 /*
702 * Initialize TX descriptor
703 */
704 rt2x00_desc_read(txd, 0, &word);
705 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
706 rt2x00_desc_write(txd, 0, word);
707
708 rt2x00_desc_read(txd, 1, &word);
709 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
710 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
711 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
712 rt2x00_set_field32(&word, TXD_W1_BURST,
713 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
714 rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
e6218cc4 715 rt2x00dev->ops->extra_tx_headroom);
a9b3a9f7
ID		 716 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
717 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
718 rt2x00_desc_write(txd, 1, word);
719
720 rt2x00_desc_read(txd, 2, &word);
721 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
e6218cc4 722 skbdesc->skb_dma + rt2x00dev->ops->extra_tx_headroom);
a9b3a9f7
ID		 723 rt2x00_desc_write(txd, 2, word);
724
725 rt2x00_desc_read(txd, 3, &word);
726 rt2x00_set_field32(&word, TXD_W3_WIV,
727 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
728 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
729 rt2x00_desc_write(txd, 3, word);
730}
731
732/*
733 * TX data initialization
734 */
735static void rt2800pci_write_beacon(struct queue_entry *entry)
736{
737 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
738 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
739 unsigned int beacon_base;
740 u32 reg;
741
742 /*
743 * Disable beaconing while we are reloading the beacon data,
744 * otherwise we might be sending out invalid data.
745 */
9ca21eb7 746 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7 747 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
9ca21eb7 748 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7
ID		 749
750 /*
751 * Write entire beacon with descriptor to register.
752 */
753 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
4f2732ce 754 rt2800_register_multiwrite(rt2x00dev,
a9b3a9f7
ID		 755 beacon_base,
756 skbdesc->desc, skbdesc->desc_len);
4f2732ce 757 rt2800_register_multiwrite(rt2x00dev,
a9b3a9f7
ID		 758 beacon_base + skbdesc->desc_len,
759 entry->skb->data, entry->skb->len);
760
761 /*
762 * Clean up beacon skb.
763 */
764 dev_kfree_skb_any(entry->skb);
765 entry->skb = NULL;
766}
767
768static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
769 const enum data_queue_qid queue_idx)
770{
771 struct data_queue *queue;
772 unsigned int idx, qidx = 0;
773 u32 reg;
774
775 if (queue_idx == QID_BEACON) {
9ca21eb7 776 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
a9b3a9f7
ID		 777 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
778 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
779 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
780 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
9ca21eb7 781 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
a9b3a9f7
ID		 782 }
783 return;
784 }
785
786 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
787 return;
788
789 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
790 idx = queue->index[Q_INDEX];
791
792 if (queue_idx == QID_MGMT)
793 qidx = 5;
794 else
795 qidx = queue_idx;
796
9ca21eb7 797 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
a9b3a9f7
ID		 798}
799
800static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
801 const enum data_queue_qid qid)
802{
803 u32 reg;
804
805 if (qid == QID_BEACON) {
9ca21eb7 806 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
a9b3a9f7
ID		 807 return;
808 }
809
9ca21eb7 810 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
a9b3a9f7
ID		 811 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
812 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
813 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
814 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
9ca21eb7 815 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
a9b3a9f7
ID		 816}
817
818/*
819 * RX control handlers
820 */
821static void rt2800pci_fill_rxdone(struct queue_entry *entry,
822 struct rxdone_entry_desc *rxdesc)
823{
824 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a9b3a9f7
ID		 825 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
826 __le32 *rxd = entry_priv->desc;
827 __le32 *rxwi = (__le32 *)entry->skb->data;
828 u32 rxd3;
829 u32 rxwi0;
830 u32 rxwi1;
831 u32 rxwi2;
832 u32 rxwi3;
833
834 rt2x00_desc_read(rxd, 3, &rxd3);
835 rt2x00_desc_read(rxwi, 0, &rxwi0);
836 rt2x00_desc_read(rxwi, 1, &rxwi1);
837 rt2x00_desc_read(rxwi, 2, &rxwi2);
838 rt2x00_desc_read(rxwi, 3, &rxwi3);
839
840 if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
841 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
842
843 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
844 /*
845 * Unfortunately we don't know the cipher type used during
846 * decryption. This prevents us from correct providing
847 * correct statistics through debugfs.
848 */
849 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
850 rxdesc->cipher_status =
851 rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
852 }
853
854 if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
855 /*
856 * Hardware has stripped IV/EIV data from 802.11 frame during
857 * decryption. Unfortunately the descriptor doesn't contain
858 * any fields with the EIV/IV data either, so they can't
859 * be restored by rt2x00lib.
860 */
861 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
862
863 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
864 rxdesc->flags |= RX_FLAG_DECRYPTED;
865 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
866 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
867 }
868
869 if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
870 rxdesc->dev_flags |= RXDONE_MY_BSS;
871
354e39db 872 if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
a9b3a9f7 873 rxdesc->dev_flags |= RXDONE_L2PAD;
a9b3a9f7
ID		 874
875 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
876 rxdesc->flags |= RX_FLAG_SHORT_GI;
877
878 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
879 rxdesc->flags |= RX_FLAG_40MHZ;
880
881 /*
882 * Detect RX rate, always use MCS as signal type.
883 */
884 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
885 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
886 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
887
888 /*
889 * Mask of 0x8 bit to remove the short preamble flag.
890 */
891 if (rxdesc->rate_mode == RATE_MODE_CCK)
892 rxdesc->signal &= ~0x8;
893
894 rxdesc->rssi =
895 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
896 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
897
a9b3a9f7
ID		 898 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
899
900 /*
901 * Set RX IDX in register to inform hardware that we have handled
902 * this entry and it is available for reuse again.
903 */
9ca21eb7 904 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
a9b3a9f7
ID		 905
906 /*
907 * Remove TXWI descriptor from start of buffer.
908 */
909 skb_pull(entry->skb, RXWI_DESC_SIZE);
a9b3a9f7
ID		 910}
911
912/*
913 * Interrupt functions.
914 */
915static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
916{
917 struct data_queue *queue;
918 struct queue_entry *entry;
632dd959 919 __le32 *txwi;
a9b3a9f7
ID		 920 struct txdone_entry_desc txdesc;
921 u32 word;
922 u32 reg;
923 u32 old_reg;
632dd959 924 int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
a9b3a9f7
ID		 925 u16 mcs, real_mcs;
926
927 /*
928 * During each loop we will compare the freshly read
929 * TX_STA_FIFO register value with the value read from
930 * the previous loop. If the 2 values are equal then
931 * we should stop processing because the chance it
932 * quite big that the device has been unplugged and
933 * we risk going into an endless loop.
934 */
935 old_reg = 0;
936
937 while (1) {
9ca21eb7 938 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
a9b3a9f7
ID		 939 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
940 break;
941
942 if (old_reg == reg)
943 break;
944 old_reg = reg;
945
632dd959
AB		 946 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
947 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
948 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
949
a9b3a9f7
ID		 950 /*
951 * Skip this entry when it contains an invalid
952 * queue identication number.
953 */
632dd959 954 if (pid <= 0 || pid > QID_RX)
a9b3a9f7
ID		 955 continue;
956
632dd959 957 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
a9b3a9f7
ID		 958 if (unlikely(!queue))
959 continue;
960
961 /*
632dd959
AB		 962 * Inside each queue, we process each entry in a chronological
963 * order. We first check that the queue is not empty.
a9b3a9f7 964 */
632dd959 965 if (rt2x00queue_empty(queue))
a9b3a9f7 966 continue;
632dd959 967 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
a9b3a9f7 968
632dd959
AB		 969 /* Check if we got a match by looking at WCID/ACK/PID
970 * fields */
971 txwi = (__le32 *)(entry->skb->data -
972 rt2x00dev->ops->extra_tx_headroom);
973
974 rt2x00_desc_read(txwi, 1, &word);
975 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
976 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
977 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
978
979 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
980 WARNING(rt2x00dev, "invalid TX_STA_FIFO content\n");
a9b3a9f7
ID		 981
982 /*
983 * Obtain the status about this packet.
984 */
985 txdesc.flags = 0;
bf18723d
AB		 986 rt2x00_desc_read(txwi, 0, &word);
987 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
988 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
a9b3a9f7
ID		 989
990 /*
991 * Ralink has a retry mechanism using a global fallback
bf18723d
AB		 992 * table. We setup this fallback table to try the immediate
993 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
994 * always contains the MCS used for the last transmission, be
995 * it successful or not.
a9b3a9f7 996 */
bf18723d
AB		 997 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
998 /*
999 * Transmission succeeded. The number of retries is
1000 * mcs - real_mcs
1001 */
1002 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1003 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1004 } else {
1005 /*
1006 * Transmission failed. The number of retries is
1007 * always 7 in this case (for a total number of 8
1008 * frames sent).
1009 */
1010 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1011 txdesc.retry = 7;
1012 }
1013
a9b3a9f7 1014 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
bf18723d 1015
a9b3a9f7
ID		 1016
1017 rt2x00lib_txdone(entry, &txdesc);
1018 }
1019}
1020
4d66edc8
GW		 1021static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
1022{
1023 struct ieee80211_conf conf = { .flags = 0 };
1024 struct rt2x00lib_conf libconf = { .conf = &conf };
1025
1026 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
1027}
1028
a9b3a9f7
ID		 1029static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1030{
1031 struct rt2x00_dev *rt2x00dev = dev_instance;
1032 u32 reg;
1033
1034 /* Read status and ACK all interrupts */
9ca21eb7
BZ		 1035 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1036 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
a9b3a9f7
ID		 1037
1038 if (!reg)
1039 return IRQ_NONE;
1040
1041 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1042 return IRQ_HANDLED;
1043
1044 /*
1045 * 1 - Rx ring done interrupt.
1046 */
1047 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1048 rt2x00pci_rxdone(rt2x00dev);
1049
1050 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1051 rt2800pci_txdone(rt2x00dev);
1052
4d66edc8
GW		 1053 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
1054 rt2800pci_wakeup(rt2x00dev);
1055
a9b3a9f7
ID		 1056 return IRQ_HANDLED;
1057}
1058
1059/*
1060 * Device probe functions.
1061 */
7ab71325
BZ		 1062static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1063{
1064 /*
1065 * Read EEPROM into buffer
1066 */
cea90e55 1067 if (rt2x00_is_soc(rt2x00dev))
7ab71325 1068 rt2800pci_read_eeprom_soc(rt2x00dev);
cea90e55
GW		 1069 else if (rt2800pci_efuse_detect(rt2x00dev))
1070 rt2800pci_read_eeprom_efuse(rt2x00dev);
1071 else
1072 rt2800pci_read_eeprom_pci(rt2x00dev);
7ab71325
BZ		 1073
1074 return rt2800_validate_eeprom(rt2x00dev);
1075}
1076
b0a1edab
BZ		 1077static const struct rt2800_ops rt2800pci_rt2800_ops = {
1078 .register_read = rt2x00pci_register_read,
31a4cf1f 1079 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
b0a1edab
BZ		 1080 .register_write = rt2x00pci_register_write,
1081 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1082
1083 .register_multiread = rt2x00pci_register_multiread,
1084 .register_multiwrite = rt2x00pci_register_multiwrite,
1085
1086 .regbusy_read = rt2x00pci_regbusy_read,
1087};
1088
a9b3a9f7
ID		 1089static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1090{
1091 int retval;
1092
b0a1edab
BZ		 1093 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1094
a9b3a9f7
ID		 1095 /*
1096 * Allocate eeprom data.
1097 */
1098 retval = rt2800pci_validate_eeprom(rt2x00dev);
1099 if (retval)
1100 return retval;
1101
38bd7b8a 1102 retval = rt2800_init_eeprom(rt2x00dev);
a9b3a9f7
ID		 1103 if (retval)
1104 return retval;
1105
1106 /*
1107 * Initialize hw specifications.
1108 */
4da2933f 1109 retval = rt2800_probe_hw_mode(rt2x00dev);
a9b3a9f7
ID		 1110 if (retval)
1111 return retval;
1112
1113 /*
1114 * This device has multiple filters for control frames
1115 * and has a separate filter for PS Poll frames.
1116 */
1117 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1118 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1119
1120 /*
1121 * This device requires firmware.
1122 */
cea90e55 1123 if (!rt2x00_is_soc(rt2x00dev))
a9b3a9f7
ID		 1124 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1125 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1126 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1127 if (!modparam_nohwcrypt)
1128 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1129
1130 /*
1131 * Set the rssi offset.
1132 */
1133 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1134
1135 return 0;
1136}
1137
a9b3a9f7
ID		 1138static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1139 .irq_handler = rt2800pci_interrupt,
1140 .probe_hw = rt2800pci_probe_hw,
1141 .get_firmware_name = rt2800pci_get_firmware_name,
1142 .check_firmware = rt2800pci_check_firmware,
1143 .load_firmware = rt2800pci_load_firmware,
1144 .initialize = rt2x00pci_initialize,
1145 .uninitialize = rt2x00pci_uninitialize,
1146 .get_entry_state = rt2800pci_get_entry_state,
1147 .clear_entry = rt2800pci_clear_entry,
1148 .set_device_state = rt2800pci_set_device_state,
f4450616
BZ		 1149 .rfkill_poll = rt2800_rfkill_poll,
1150 .link_stats = rt2800_link_stats,
1151 .reset_tuner = rt2800_reset_tuner,
1152 .link_tuner = rt2800_link_tuner,
a9b3a9f7 1153 .write_tx_desc = rt2800pci_write_tx_desc,
745b1ae3 1154 .write_tx_data = rt2800pci_write_tx_data,
a9b3a9f7
ID		 1155 .write_beacon = rt2800pci_write_beacon,
1156 .kick_tx_queue = rt2800pci_kick_tx_queue,
1157 .kill_tx_queue = rt2800pci_kill_tx_queue,
1158 .fill_rxdone = rt2800pci_fill_rxdone,
f4450616
BZ		 1159 .config_shared_key = rt2800_config_shared_key,
1160 .config_pairwise_key = rt2800_config_pairwise_key,
1161 .config_filter = rt2800_config_filter,
1162 .config_intf = rt2800_config_intf,
1163 .config_erp = rt2800_config_erp,
1164 .config_ant = rt2800_config_ant,
1165 .config = rt2800_config,
a9b3a9f7
ID		 1166};
1167
1168static const struct data_queue_desc rt2800pci_queue_rx = {
1169 .entry_num = RX_ENTRIES,
1170 .data_size = AGGREGATION_SIZE,
1171 .desc_size = RXD_DESC_SIZE,
1172 .priv_size = sizeof(struct queue_entry_priv_pci),
1173};
1174
1175static const struct data_queue_desc rt2800pci_queue_tx = {
1176 .entry_num = TX_ENTRIES,
1177 .data_size = AGGREGATION_SIZE,
1178 .desc_size = TXD_DESC_SIZE,
1179 .priv_size = sizeof(struct queue_entry_priv_pci),
1180};
1181
1182static const struct data_queue_desc rt2800pci_queue_bcn = {
1183 .entry_num = 8 * BEACON_ENTRIES,
1184 .data_size = 0, /* No DMA required for beacons */
1185 .desc_size = TXWI_DESC_SIZE,
1186 .priv_size = sizeof(struct queue_entry_priv_pci),
1187};
1188
1189static const struct rt2x00_ops rt2800pci_ops = {
04d0362e
GW		 1190 .name = KBUILD_MODNAME,
1191 .max_sta_intf = 1,
1192 .max_ap_intf = 8,
1193 .eeprom_size = EEPROM_SIZE,
1194 .rf_size = RF_SIZE,
1195 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1196 .extra_tx_headroom = TXWI_DESC_SIZE,
04d0362e
GW		 1197 .rx = &rt2800pci_queue_rx,
1198 .tx = &rt2800pci_queue_tx,
1199 .bcn = &rt2800pci_queue_bcn,
1200 .lib = &rt2800pci_rt2x00_ops,
1201 .hw = &rt2800_mac80211_ops,
a9b3a9f7 1202#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1203 .debugfs = &rt2800_rt2x00debug,
a9b3a9f7
ID		 1204#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1205};
1206
1207/*
1208 * RT2800pci module information.
1209 */
d6e36ec1 1210#ifdef CONFIG_RT2800PCI_PCI
a3aa1884 1211static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
de1ebdce
GW		 1212 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1213 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1214 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1215 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1216 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1217 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1218 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1219 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1220 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1221 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1222 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1223 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1224#ifdef CONFIG_RT2800PCI_RT30XX
a9b3a9f7
ID		 1225 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1226 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1227 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce
GW		 1228 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1229#endif
1230#ifdef CONFIG_RT2800PCI_RT35XX
1231 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1232 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
a9b3a9f7
ID		 1233 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1234 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
6424bf70 1235 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
de1ebdce 1236#endif
a9b3a9f7
ID		 1237 { 0, }
1238};
d6e36ec1 1239#endif /* CONFIG_RT2800PCI_PCI */
a9b3a9f7
ID		 1240
1241MODULE_AUTHOR(DRV_PROJECT);
1242MODULE_VERSION(DRV_VERSION);
1243MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1244MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1245#ifdef CONFIG_RT2800PCI_PCI
1246MODULE_FIRMWARE(FIRMWARE_RT2860);
1247MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1248#endif /* CONFIG_RT2800PCI_PCI */
1249MODULE_LICENSE("GPL");
1250
00e23ce2 1251#ifdef CONFIG_RT2800PCI_SOC
714fa663
GW		 1252static int rt2800soc_probe(struct platform_device *pdev)
1253{
6e93d719 1254 return rt2x00soc_probe(pdev, &rt2800pci_ops);
714fa663 1255}
a9b3a9f7
ID		 1256
1257static struct platform_driver rt2800soc_driver = {
1258 .driver = {
1259 .name = "rt2800_wmac",
1260 .owner = THIS_MODULE,
1261 .mod_name = KBUILD_MODNAME,
1262 },
714fa663 1263 .probe = rt2800soc_probe,
a9b3a9f7
ID		 1264 .remove = __devexit_p(rt2x00soc_remove),
1265 .suspend = rt2x00soc_suspend,
1266 .resume = rt2x00soc_resume,
1267};
00e23ce2 1268#endif /* CONFIG_RT2800PCI_SOC */
a9b3a9f7
ID		 1269
1270#ifdef CONFIG_RT2800PCI_PCI
1271static struct pci_driver rt2800pci_driver = {
1272 .name = KBUILD_MODNAME,
1273 .id_table = rt2800pci_device_table,
1274 .probe = rt2x00pci_probe,
1275 .remove = __devexit_p(rt2x00pci_remove),
1276 .suspend = rt2x00pci_suspend,
1277 .resume = rt2x00pci_resume,
1278};
1279#endif /* CONFIG_RT2800PCI_PCI */
1280
1281static int __init rt2800pci_init(void)
1282{
1283 int ret = 0;
1284
00e23ce2 1285#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1286 ret = platform_driver_register(&rt2800soc_driver);
1287 if (ret)
1288 return ret;
1289#endif
1290#ifdef CONFIG_RT2800PCI_PCI
1291 ret = pci_register_driver(&rt2800pci_driver);
1292 if (ret) {
00e23ce2 1293#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1294 platform_driver_unregister(&rt2800soc_driver);
1295#endif
1296 return ret;
1297 }
1298#endif
1299
1300 return ret;
1301}
1302
1303static void __exit rt2800pci_exit(void)
1304{
1305#ifdef CONFIG_RT2800PCI_PCI
1306 pci_unregister_driver(&rt2800pci_driver);
1307#endif
00e23ce2 1308#ifdef CONFIG_RT2800PCI_SOC
a9b3a9f7
ID		 1309 platform_driver_unregister(&rt2800soc_driver);
1310#endif
1311}
1312
1313module_init(rt2800pci_init);
1314module_exit(rt2800pci_exit);
Clone of davem's net-next-2.6 tree