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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
280 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
281 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
282 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
283 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
284 return 0;
285
286 msleep(1);
287 }
288
289 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
290 return -EACCES;
291}
292EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
293
f31c9a8c
ID		 294static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
295{
296 u16 fw_crc;
297 u16 crc;
298
299 /*
300 * The last 2 bytes in the firmware array are the crc checksum itself,
301 * this means that we should never pass those 2 bytes to the crc
302 * algorithm.
303 */
304 fw_crc = (data[len - 2] << 8 | data[len - 1]);
305
306 /*
307 * Use the crc ccitt algorithm.
308 * This will return the same value as the legacy driver which
309 * used bit ordering reversion on the both the firmware bytes
310 * before input input as well as on the final output.
311 * Obviously using crc ccitt directly is much more efficient.
312 */
313 crc = crc_ccitt(~0, data, len - 2);
314
315 /*
316 * There is a small difference between the crc-itu-t + bitrev and
317 * the crc-ccitt crc calculation. In the latter method the 2 bytes
318 * will be swapped, use swab16 to convert the crc to the correct
319 * value.
320 */
321 crc = swab16(crc);
322
323 return fw_crc == crc;
324}
325
326int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
327 const u8 *data, const size_t len)
328{
329 size_t offset = 0;
330 size_t fw_len;
331 bool multiple;
332
333 /*
334 * PCI(e) & SOC devices require firmware with a length
335 * of 8kb. USB devices require firmware files with a length
336 * of 4kb. Certain USB chipsets however require different firmware,
337 * which Ralink only provides attached to the original firmware
338 * file. Thus for USB devices, firmware files have a length
339 * which is a multiple of 4kb.
340 */
341 if (rt2x00_is_usb(rt2x00dev)) {
342 fw_len = 4096;
343 multiple = true;
344 } else {
345 fw_len = 8192;
346 multiple = true;
347 }
348
349 /*
350 * Validate the firmware length
351 */
352 if (len != fw_len && (!multiple || (len % fw_len) != 0))
353 return FW_BAD_LENGTH;
354
355 /*
356 * Check if the chipset requires one of the upper parts
357 * of the firmware.
358 */
359 if (rt2x00_is_usb(rt2x00dev) &&
360 !rt2x00_rt(rt2x00dev, RT2860) &&
361 !rt2x00_rt(rt2x00dev, RT2872) &&
362 !rt2x00_rt(rt2x00dev, RT3070) &&
363 ((len / fw_len) == 1))
364 return FW_BAD_VERSION;
365
366 /*
367 * 8kb firmware files must be checked as if it were
368 * 2 separate firmware files.
369 */
370 while (offset < len) {
371 if (!rt2800_check_firmware_crc(data + offset, fw_len))
372 return FW_BAD_CRC;
373
374 offset += fw_len;
375 }
376
377 return FW_OK;
378}
379EXPORT_SYMBOL_GPL(rt2800_check_firmware);
380
381int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
382 const u8 *data, const size_t len)
383{
384 unsigned int i;
385 u32 reg;
386
387 /*
b9eca242
ID		 388 * If driver doesn't wake up firmware here,
389 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 390 */
b9eca242 391 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 392
f31c9a8c
ID		 393 /*
394 * Wait for stable hardware.
395 */
5ffddc49 396 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 397 return -EBUSY;
f31c9a8c
ID		 398
399 if (rt2x00_is_pci(rt2x00dev))
400 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
401
402 /*
403 * Disable DMA, will be reenabled later when enabling
404 * the radio.
405 */
406 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
407 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
408 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
409 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
410 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
411 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
412 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
413
414 /*
415 * Write firmware to the device.
416 */
417 rt2800_drv_write_firmware(rt2x00dev, data, len);
418
419 /*
420 * Wait for device to stabilize.
421 */
422 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
423 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
424 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
425 break;
426 msleep(1);
427 }
428
429 if (i == REGISTER_BUSY_COUNT) {
430 ERROR(rt2x00dev, "PBF system register not ready.\n");
431 return -EBUSY;
432 }
433
434 /*
435 * Initialize firmware.
436 */
437 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
438 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
439 msleep(1);
440
441 return 0;
442}
443EXPORT_SYMBOL_GPL(rt2800_load_firmware);
444
0c5879bc
ID		 445void rt2800_write_tx_data(struct queue_entry *entry,
446 struct txentry_desc *txdesc)
59679b91 447{
0c5879bc 448 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 449 u32 word;
450
451 /*
452 * Initialize TX Info descriptor
453 */
454 rt2x00_desc_read(txwi, 0, &word);
455 rt2x00_set_field32(&word, TXWI_W0_FRAG,
456 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 457 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
458 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 459 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
460 rt2x00_set_field32(&word, TXWI_W0_TS,
461 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
462 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
463 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
464 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
465 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
466 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
467 rt2x00_set_field32(&word, TXWI_W0_BW,
468 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
469 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
470 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
471 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
472 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
473 rt2x00_desc_write(txwi, 0, word);
474
475 rt2x00_desc_read(txwi, 1, &word);
476 rt2x00_set_field32(&word, TXWI_W1_ACK,
477 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
478 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
479 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
480 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
481 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
482 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
483 txdesc->key_idx : 0xff);
484 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
485 txdesc->length);
a908a743 486 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->qid + 1);
59679b91
GW		 487 rt2x00_desc_write(txwi, 1, word);
488
489 /*
490 * Always write 0 to IV/EIV fields, hardware will insert the IV
491 * from the IVEIV register when TXD_W3_WIV is set to 0.
492 * When TXD_W3_WIV is set to 1 it will use the IV data
493 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
494 * crypto entry in the registers should be used to encrypt the frame.
495 */
496 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
497 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
498}
0c5879bc 499EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 500
74861922 501static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
2de64dd2 502{
74861922
ID		 503 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
504 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
505 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
506 u16 eeprom;
507 u8 offset0;
508 u8 offset1;
509 u8 offset2;
510
e5ef5bad 511 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 512 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
513 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
514 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
515 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
516 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
517 } else {
518 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
519 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
520 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
521 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
522 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
523 }
524
525 /*
526 * Convert the value from the descriptor into the RSSI value
527 * If the value in the descriptor is 0, it is considered invalid
528 * and the default (extremely low) rssi value is assumed
529 */
530 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
531 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
532 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
533
534 /*
535 * mac80211 only accepts a single RSSI value. Calculating the
536 * average doesn't deliver a fair answer either since -60:-60 would
537 * be considered equally good as -50:-70 while the second is the one
538 * which gives less energy...
539 */
540 rssi0 = max(rssi0, rssi1);
541 return max(rssi0, rssi2);
542}
543
544void rt2800_process_rxwi(struct queue_entry *entry,
545 struct rxdone_entry_desc *rxdesc)
546{
547 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 548 u32 word;
549
550 rt2x00_desc_read(rxwi, 0, &word);
551
552 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
553 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
554
555 rt2x00_desc_read(rxwi, 1, &word);
556
557 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
558 rxdesc->flags |= RX_FLAG_SHORT_GI;
559
560 if (rt2x00_get_field32(word, RXWI_W1_BW))
561 rxdesc->flags |= RX_FLAG_40MHZ;
562
563 /*
564 * Detect RX rate, always use MCS as signal type.
565 */
566 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
567 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
568 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
569
570 /*
571 * Mask of 0x8 bit to remove the short preamble flag.
572 */
573 if (rxdesc->rate_mode == RATE_MODE_CCK)
574 rxdesc->signal &= ~0x8;
575
576 rt2x00_desc_read(rxwi, 2, &word);
577
74861922
ID		 578 /*
579 * Convert descriptor AGC value to RSSI value.
580 */
581 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 582
583 /*
584 * Remove RXWI descriptor from start of buffer.
585 */
74861922 586 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 587}
588EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
589
3613884d
ID		 590static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
591{
592 __le32 *txwi;
593 u32 word;
594 int wcid, ack, pid;
595 int tx_wcid, tx_ack, tx_pid;
596
597 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
598 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
599 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
600
601 /*
602 * This frames has returned with an IO error,
603 * so the status report is not intended for this
604 * frame.
605 */
606 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
607 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
608 return false;
609 }
610
611 /*
612 * Validate if this TX status report is intended for
613 * this entry by comparing the WCID/ACK/PID fields.
614 */
615 txwi = rt2800_drv_get_txwi(entry);
616
617 rt2x00_desc_read(txwi, 1, &word);
618 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
619 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
620 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
621
622 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
623 WARNING(entry->queue->rt2x00dev,
624 "TX status report missed for queue %d entry %d\n",
625 entry->queue->qid, entry->entry_idx);
626 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
627 return false;
628 }
629
630 return true;
631}
632
96481b20
ID		 633void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
634{
635 struct data_queue *queue;
636 struct queue_entry *entry;
637 __le32 *txwi;
638 struct txdone_entry_desc txdesc;
639 u32 word;
640 u32 reg;
96481b20 641 u16 mcs, real_mcs;
3613884d 642 u8 pid;
96481b20
ID		 643 int i;
644
645 /*
646 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
647 * at most X times and also stop processing once the TX_STA_FIFO_VALID
648 * flag is not set anymore.
649 *
650 * The legacy drivers use X=TX_RING_SIZE but state in a comment
651 * that the TX_STA_FIFO stack has a size of 16. We stick to our
652 * tx ring size for now.
653 */
654 for (i = 0; i < TX_ENTRIES; i++) {
655 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
656 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
657 break;
658
96481b20
ID		 659 /*
660 * Skip this entry when it contains an invalid
661 * queue identication number.
662 */
3613884d
ID		 663 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
664 if (pid >= QID_RX)
96481b20
ID		 665 continue;
666
3613884d 667 queue = rt2x00queue_get_queue(rt2x00dev, pid);
96481b20
ID		 668 if (unlikely(!queue))
669 continue;
670
671 /*
672 * Inside each queue, we process each entry in a chronological
673 * order. We first check that the queue is not empty.
674 */
675 entry = NULL;
3613884d 676 txwi = NULL;
96481b20
ID		 677 while (!rt2x00queue_empty(queue)) {
678 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
3613884d 679 if (rt2800_txdone_entry_check(entry, reg))
96481b20 680 break;
96481b20
ID		 681 }
682
683 if (!entry || rt2x00queue_empty(queue))
684 break;
685
96481b20
ID		 686
687 /*
688 * Obtain the status about this packet.
689 */
690 txdesc.flags = 0;
3613884d 691 txwi = rt2800_drv_get_txwi(entry);
96481b20
ID		 692 rt2x00_desc_read(txwi, 0, &word);
693 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
96481b20
ID		 694 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
695
696 /*
697 * Ralink has a retry mechanism using a global fallback
698 * table. We setup this fallback table to try the immediate
699 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
700 * always contains the MCS used for the last transmission, be
701 * it successful or not.
702 */
703 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
704 /*
705 * Transmission succeeded. The number of retries is
706 * mcs - real_mcs
707 */
708 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
709 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
710 } else {
711 /*
712 * Transmission failed. The number of retries is
713 * always 7 in this case (for a total number of 8
714 * frames sent).
715 */
716 __set_bit(TXDONE_FAILURE, &txdesc.flags);
717 txdesc.retry = rt2x00dev->long_retry;
718 }
719
720 /*
721 * the frame was retried at least once
722 * -> hw used fallback rates
723 */
724 if (txdesc.retry)
725 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
726
727 rt2x00lib_txdone(entry, &txdesc);
728 }
729}
730EXPORT_SYMBOL_GPL(rt2800_txdone);
731
f0194b2d
GW		 732void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
733{
734 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
735 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
736 unsigned int beacon_base;
737 u32 reg;
738
739 /*
740 * Disable beaconing while we are reloading the beacon data,
741 * otherwise we might be sending out invalid data.
742 */
743 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
744 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
745 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
746
747 /*
748 * Add space for the TXWI in front of the skb.
749 */
750 skb_push(entry->skb, TXWI_DESC_SIZE);
751 memset(entry->skb, 0, TXWI_DESC_SIZE);
752
753 /*
754 * Register descriptor details in skb frame descriptor.
755 */
756 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
757 skbdesc->desc = entry->skb->data;
758 skbdesc->desc_len = TXWI_DESC_SIZE;
759
760 /*
761 * Add the TXWI for the beacon to the skb.
762 */
0c5879bc 763 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 764
765 /*
766 * Dump beacon to userspace through debugfs.
767 */
768 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
769
770 /*
771 * Write entire beacon with TXWI to register.
772 */
773 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
774 rt2800_register_multiwrite(rt2x00dev, beacon_base,
775 entry->skb->data, entry->skb->len);
776
777 /*
778 * Enable beaconing again.
779 */
780 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
781 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
782 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
783 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
784
785 /*
786 * Clean up beacon skb.
787 */
788 dev_kfree_skb_any(entry->skb);
789 entry->skb = NULL;
790}
50e888ea 791EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 792
fdb87251
HS		 793static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
794 unsigned int beacon_base)
795{
796 int i;
797
798 /*
799 * For the Beacon base registers we only need to clear
800 * the whole TXWI which (when set to 0) will invalidate
801 * the entire beacon.
802 */
803 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
804 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
805}
806
f4450616
BZ		 807#ifdef CONFIG_RT2X00_LIB_DEBUGFS
808const struct rt2x00debug rt2800_rt2x00debug = {
809 .owner = THIS_MODULE,
810 .csr = {
811 .read = rt2800_register_read,
812 .write = rt2800_register_write,
813 .flags = RT2X00DEBUGFS_OFFSET,
814 .word_base = CSR_REG_BASE,
815 .word_size = sizeof(u32),
816 .word_count = CSR_REG_SIZE / sizeof(u32),
817 },
818 .eeprom = {
819 .read = rt2x00_eeprom_read,
820 .write = rt2x00_eeprom_write,
821 .word_base = EEPROM_BASE,
822 .word_size = sizeof(u16),
823 .word_count = EEPROM_SIZE / sizeof(u16),
824 },
825 .bbp = {
826 .read = rt2800_bbp_read,
827 .write = rt2800_bbp_write,
828 .word_base = BBP_BASE,
829 .word_size = sizeof(u8),
830 .word_count = BBP_SIZE / sizeof(u8),
831 },
832 .rf = {
833 .read = rt2x00_rf_read,
834 .write = rt2800_rf_write,
835 .word_base = RF_BASE,
836 .word_size = sizeof(u32),
837 .word_count = RF_SIZE / sizeof(u32),
838 },
839};
840EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
841#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
842
843int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
844{
845 u32 reg;
846
847 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
848 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
849}
850EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
851
852#ifdef CONFIG_RT2X00_LIB_LEDS
853static void rt2800_brightness_set(struct led_classdev *led_cdev,
854 enum led_brightness brightness)
855{
856 struct rt2x00_led *led =
857 container_of(led_cdev, struct rt2x00_led, led_dev);
858 unsigned int enabled = brightness != LED_OFF;
859 unsigned int bg_mode =
860 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
861 unsigned int polarity =
862 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
863 EEPROM_FREQ_LED_POLARITY);
864 unsigned int ledmode =
865 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
866 EEPROM_FREQ_LED_MODE);
867
868 if (led->type == LED_TYPE_RADIO) {
869 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
870 enabled ? 0x20 : 0);
871 } else if (led->type == LED_TYPE_ASSOC) {
872 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
873 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
874 } else if (led->type == LED_TYPE_QUALITY) {
875 /*
876 * The brightness is divided into 6 levels (0 - 5),
877 * The specs tell us the following levels:
878 * 0, 1 ,3, 7, 15, 31
879 * to determine the level in a simple way we can simply
880 * work with bitshifting:
881 * (1 << level) - 1
882 */
883 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
884 (1 << brightness / (LED_FULL / 6)) - 1,
885 polarity);
886 }
887}
888
889static int rt2800_blink_set(struct led_classdev *led_cdev,
890 unsigned long *delay_on, unsigned long *delay_off)
891{
892 struct rt2x00_led *led =
893 container_of(led_cdev, struct rt2x00_led, led_dev);
894 u32 reg;
895
896 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
897 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
898 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 899 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
900
901 return 0;
902}
903
b3579d6a 904static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 905 struct rt2x00_led *led, enum led_type type)
906{
907 led->rt2x00dev = rt2x00dev;
908 led->type = type;
909 led->led_dev.brightness_set = rt2800_brightness_set;
910 led->led_dev.blink_set = rt2800_blink_set;
911 led->flags = LED_INITIALIZED;
912}
f4450616
BZ		 913#endif /* CONFIG_RT2X00_LIB_LEDS */
914
915/*
916 * Configuration handlers.
917 */
918static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
919 struct rt2x00lib_crypto *crypto,
920 struct ieee80211_key_conf *key)
921{
922 struct mac_wcid_entry wcid_entry;
923 struct mac_iveiv_entry iveiv_entry;
924 u32 offset;
925 u32 reg;
926
927 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
928
e4a0ab34
ID		 929 if (crypto->cmd == SET_KEY) {
930 rt2800_register_read(rt2x00dev, offset, &reg);
931 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
932 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
933 /*
934 * Both the cipher as the BSS Idx numbers are split in a main
935 * value of 3 bits, and a extended field for adding one additional
936 * bit to the value.
937 */
938 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
939 (crypto->cipher & 0x7));
940 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
941 (crypto->cipher & 0x8) >> 3);
942 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
943 (crypto->bssidx & 0x7));
944 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
945 (crypto->bssidx & 0x8) >> 3);
946 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
947 rt2800_register_write(rt2x00dev, offset, reg);
948 } else {
949 rt2800_register_write(rt2x00dev, offset, 0);
950 }
f4450616
BZ		 951
952 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
953
954 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
955 if ((crypto->cipher == CIPHER_TKIP) ||
956 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
957 (crypto->cipher == CIPHER_AES))
958 iveiv_entry.iv[3] |= 0x20;
959 iveiv_entry.iv[3] |= key->keyidx << 6;
960 rt2800_register_multiwrite(rt2x00dev, offset,
961 &iveiv_entry, sizeof(iveiv_entry));
962
963 offset = MAC_WCID_ENTRY(key->hw_key_idx);
964
965 memset(&wcid_entry, 0, sizeof(wcid_entry));
966 if (crypto->cmd == SET_KEY)
967 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
968 rt2800_register_multiwrite(rt2x00dev, offset,
969 &wcid_entry, sizeof(wcid_entry));
970}
971
972int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
973 struct rt2x00lib_crypto *crypto,
974 struct ieee80211_key_conf *key)
975{
976 struct hw_key_entry key_entry;
977 struct rt2x00_field32 field;
978 u32 offset;
979 u32 reg;
980
981 if (crypto->cmd == SET_KEY) {
982 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
983
984 memcpy(key_entry.key, crypto->key,
985 sizeof(key_entry.key));
986 memcpy(key_entry.tx_mic, crypto->tx_mic,
987 sizeof(key_entry.tx_mic));
988 memcpy(key_entry.rx_mic, crypto->rx_mic,
989 sizeof(key_entry.rx_mic));
990
991 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
992 rt2800_register_multiwrite(rt2x00dev, offset,
993 &key_entry, sizeof(key_entry));
994 }
995
996 /*
997 * The cipher types are stored over multiple registers
998 * starting with SHARED_KEY_MODE_BASE each word will have
999 * 32 bits and contains the cipher types for 2 bssidx each.
1000 * Using the correct defines correctly will cause overhead,
1001 * so just calculate the correct offset.
1002 */
1003 field.bit_offset = 4 * (key->hw_key_idx % 8);
1004 field.bit_mask = 0x7 << field.bit_offset;
1005
1006 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1007
1008 rt2800_register_read(rt2x00dev, offset, &reg);
1009 rt2x00_set_field32(&reg, field,
1010 (crypto->cmd == SET_KEY) * crypto->cipher);
1011 rt2800_register_write(rt2x00dev, offset, reg);
1012
1013 /*
1014 * Update WCID information
1015 */
1016 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1017
1018 return 0;
1019}
1020EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1021
1022int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1023 struct rt2x00lib_crypto *crypto,
1024 struct ieee80211_key_conf *key)
1025{
1026 struct hw_key_entry key_entry;
1027 u32 offset;
1028
1029 if (crypto->cmd == SET_KEY) {
1030 /*
1031 * 1 pairwise key is possible per AID, this means that the AID
1032 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1033 * last possible shared key entry.
1034 */
1035 if (crypto->aid > (256 - 32))
1036 return -ENOSPC;
1037
1038 key->hw_key_idx = 32 + crypto->aid;
1039
1040 memcpy(key_entry.key, crypto->key,
1041 sizeof(key_entry.key));
1042 memcpy(key_entry.tx_mic, crypto->tx_mic,
1043 sizeof(key_entry.tx_mic));
1044 memcpy(key_entry.rx_mic, crypto->rx_mic,
1045 sizeof(key_entry.rx_mic));
1046
1047 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1048 rt2800_register_multiwrite(rt2x00dev, offset,
1049 &key_entry, sizeof(key_entry));
1050 }
1051
1052 /*
1053 * Update WCID information
1054 */
1055 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1056
1057 return 0;
1058}
1059EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1060
1061void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1062 const unsigned int filter_flags)
1063{
1064 u32 reg;
1065
1066 /*
1067 * Start configuration steps.
1068 * Note that the version error will always be dropped
1069 * and broadcast frames will always be accepted since
1070 * there is no filter for it at this time.
1071 */
1072 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1073 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1074 !(filter_flags & FIF_FCSFAIL));
1075 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1076 !(filter_flags & FIF_PLCPFAIL));
1077 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1078 !(filter_flags & FIF_PROMISC_IN_BSS));
1079 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1080 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1081 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1082 !(filter_flags & FIF_ALLMULTI));
1083 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1084 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1085 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1086 !(filter_flags & FIF_CONTROL));
1087 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1088 !(filter_flags & FIF_CONTROL));
1089 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1090 !(filter_flags & FIF_CONTROL));
1091 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1092 !(filter_flags & FIF_CONTROL));
1093 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1094 !(filter_flags & FIF_CONTROL));
1095 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1096 !(filter_flags & FIF_PSPOLL));
1097 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1098 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1099 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1100 !(filter_flags & FIF_CONTROL));
1101 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1102}
1103EXPORT_SYMBOL_GPL(rt2800_config_filter);
1104
1105void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1106 struct rt2x00intf_conf *conf, const unsigned int flags)
1107{
f4450616
BZ		 1108 u32 reg;
1109
1110 if (flags & CONFIG_UPDATE_TYPE) {
1111 /*
1112 * Clear current synchronisation setup.
f4450616 1113 */
fdb87251
HS		 1114 rt2800_clear_beacon(rt2x00dev,
1115 HW_BEACON_OFFSET(intf->beacon->entry_idx));
f4450616
BZ		 1116 /*
1117 * Enable synchronisation.
1118 */
1119 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1120 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1121 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef 1122 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
ab8966dd
HS		 1123 (conf->sync == TSF_SYNC_ADHOC ||
1124 conf->sync == TSF_SYNC_AP_NONE));
f4450616 1125 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
9f926fb5
HS		 1126
1127 /*
1128 * Enable pre tbtt interrupt for beaconing modes
1129 */
1130 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1131 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
ab8966dd 1132 (conf->sync == TSF_SYNC_AP_NONE));
9f926fb5
HS		 1133 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1134
f4450616
BZ		 1135 }
1136
1137 if (flags & CONFIG_UPDATE_MAC) {
c600c826
ID		 1138 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1139 reg = le32_to_cpu(conf->mac[1]);
1140 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1141 conf->mac[1] = cpu_to_le32(reg);
1142 }
f4450616
BZ		 1143
1144 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1145 conf->mac, sizeof(conf->mac));
1146 }
1147
1148 if (flags & CONFIG_UPDATE_BSSID) {
c600c826
ID		 1149 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1150 reg = le32_to_cpu(conf->bssid[1]);
1151 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1152 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1153 conf->bssid[1] = cpu_to_le32(reg);
1154 }
f4450616
BZ		 1155
1156 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1157 conf->bssid, sizeof(conf->bssid));
1158 }
1159}
1160EXPORT_SYMBOL_GPL(rt2800_config_intf);
1161
02044643
HS		 1162void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1163 u32 changed)
f4450616
BZ		 1164{
1165 u32 reg;
1166
02044643
HS		 1167 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1168 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1169 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1170 !!erp->short_preamble);
1171 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1172 !!erp->short_preamble);
1173 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1174 }
f4450616 1175
02044643
HS		 1176 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1177 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1178 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1179 erp->cts_protection ? 2 : 0);
1180 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1181 }
f4450616 1182
02044643
HS		 1183 if (changed & BSS_CHANGED_BASIC_RATES) {
1184 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1185 erp->basic_rates);
1186 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1187 }
f4450616 1188
02044643
HS		 1189 if (changed & BSS_CHANGED_ERP_SLOT) {
1190 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1191 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1192 erp->slot_time);
1193 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1194
02044643
HS		 1195 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1196 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1197 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1198 }
f4450616 1199
02044643
HS		 1200 if (changed & BSS_CHANGED_BEACON_INT) {
1201 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1202 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1203 erp->beacon_int * 16);
1204 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1205 }
f4450616
BZ		 1206}
1207EXPORT_SYMBOL_GPL(rt2800_config_erp);
1208
1209void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1210{
1211 u8 r1;
1212 u8 r3;
1213
1214 rt2800_bbp_read(rt2x00dev, 1, &r1);
1215 rt2800_bbp_read(rt2x00dev, 3, &r3);
1216
1217 /*
1218 * Configure the TX antenna.
1219 */
1220 switch ((int)ant->tx) {
1221 case 1:
1222 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1223 break;
1224 case 2:
1225 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1226 break;
1227 case 3:
e22557f2 1228 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1229 break;
1230 }
1231
1232 /*
1233 * Configure the RX antenna.
1234 */
1235 switch ((int)ant->rx) {
1236 case 1:
1237 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1238 break;
1239 case 2:
1240 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1241 break;
1242 case 3:
1243 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1244 break;
1245 }
1246
1247 rt2800_bbp_write(rt2x00dev, 3, r3);
1248 rt2800_bbp_write(rt2x00dev, 1, r1);
1249}
1250EXPORT_SYMBOL_GPL(rt2800_config_ant);
1251
1252static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1253 struct rt2x00lib_conf *libconf)
1254{
1255 u16 eeprom;
1256 short lna_gain;
1257
1258 if (libconf->rf.channel <= 14) {
1259 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1260 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1261 } else if (libconf->rf.channel <= 64) {
1262 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1263 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1264 } else if (libconf->rf.channel <= 128) {
1265 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1266 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1267 } else {
1268 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1269 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1270 }
1271
1272 rt2x00dev->lna_gain = lna_gain;
1273}
1274
06855ef4
GW		 1275static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1276 struct ieee80211_conf *conf,
1277 struct rf_channel *rf,
1278 struct channel_info *info)
f4450616
BZ		 1279{
1280 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1281
1282 if (rt2x00dev->default_ant.tx == 1)
1283 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1284
1285 if (rt2x00dev->default_ant.rx == 1) {
1286 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1287 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1288 } else if (rt2x00dev->default_ant.rx == 2)
1289 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1290
1291 if (rf->channel > 14) {
1292 /*
1293 * When TX power is below 0, we should increase it by 7 to
1294 * make it a positive value (Minumum value is -7).
1295 * However this means that values between 0 and 7 have
1296 * double meaning, and we should set a 7DBm boost flag.
1297 */
1298 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1299 (info->default_power1 >= 0));
f4450616 1300
8d1331b3
ID		 1301 if (info->default_power1 < 0)
1302 info->default_power1 += 7;
f4450616 1303
8d1331b3 1304 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1305
1306 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1307 (info->default_power2 >= 0));
f4450616 1308
8d1331b3
ID		 1309 if (info->default_power2 < 0)
1310 info->default_power2 += 7;
f4450616 1311
8d1331b3 1312 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1313 } else {
8d1331b3
ID		 1314 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1315 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1316 }
1317
1318 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1319
1320 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1321 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1322 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1323 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1324
1325 udelay(200);
1326
1327 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1328 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1329 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1330 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1331
1332 udelay(200);
1333
1334 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1335 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1336 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1337 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1338}
1339
06855ef4
GW		 1340static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1341 struct ieee80211_conf *conf,
1342 struct rf_channel *rf,
1343 struct channel_info *info)
f4450616
BZ		 1344{
1345 u8 rfcsr;
1346
1347 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1348 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1349
1350 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1351 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1352 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1353
1354 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1355 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1356 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1357
5a673964 1358 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1359 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1360 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1361
f4450616
BZ		 1362 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1363 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1364 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1365
1366 rt2800_rfcsr_write(rt2x00dev, 24,
1367 rt2x00dev->calibration[conf_is_ht40(conf)]);
1368
71976907 1369 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1370 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1371 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1372}
1373
1374static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1375 struct ieee80211_conf *conf,
1376 struct rf_channel *rf,
1377 struct channel_info *info)
1378{
1379 u32 reg;
1380 unsigned int tx_pin;
1381 u8 bbp;
1382
46323e11 1383 if (rf->channel <= 14) {
8d1331b3
ID		 1384 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1385 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1386 } else {
8d1331b3
ID		 1387 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1388 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1389 }
1390
06855ef4
GW		 1391 if (rt2x00_rf(rt2x00dev, RF2020) ||
1392 rt2x00_rf(rt2x00dev, RF3020) ||
1393 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11
ID		 1394 rt2x00_rf(rt2x00dev, RF3022) ||
1395 rt2x00_rf(rt2x00dev, RF3052))
06855ef4 1396 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1397 else
06855ef4 1398 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1399
1400 /*
1401 * Change BBP settings
1402 */
1403 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1404 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1405 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1406 rt2800_bbp_write(rt2x00dev, 86, 0);
1407
1408 if (rf->channel <= 14) {
1409 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1410 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1411 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1412 } else {
1413 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1414 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1415 }
1416 } else {
1417 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1418
1419 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1420 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1421 else
1422 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1423 }
1424
1425 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1426 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1427 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1428 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1429 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1430
1431 tx_pin = 0;
1432
1433 /* Turn on unused PA or LNA when not using 1T or 1R */
1434 if (rt2x00dev->default_ant.tx != 1) {
1435 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1436 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1437 }
1438
1439 /* Turn on unused PA or LNA when not using 1T or 1R */
1440 if (rt2x00dev->default_ant.rx != 1) {
1441 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1442 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1443 }
1444
1445 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1446 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1447 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1448 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1449 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1450 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1451
1452 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1453
1454 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1455 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1456 rt2800_bbp_write(rt2x00dev, 4, bbp);
1457
1458 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1459 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1460 rt2800_bbp_write(rt2x00dev, 3, bbp);
1461
8d0c9b65 1462 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1463 if (conf_is_ht40(conf)) {
1464 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1465 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1466 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1467 } else {
1468 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1469 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1470 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1471 }
1472 }
1473
1474 msleep(1);
1475}
1476
1477static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5e846004 1478 const int max_txpower)
f4450616 1479{
5e846004
HS		 1480 u8 txpower;
1481 u8 max_value = (u8)max_txpower;
1482 u16 eeprom;
1483 int i;
f4450616 1484 u32 reg;
f4450616 1485 u8 r1;
5e846004 1486 u32 offset;
f4450616 1487
5e846004
HS		 1488 /*
1489 * set to normal tx power mode: +/- 0dBm
1490 */
f4450616 1491 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1492 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1493 rt2800_bbp_write(rt2x00dev, 1, r1);
1494
5e846004
HS		 1495 /*
1496 * The eeprom contains the tx power values for each rate. These
1497 * values map to 100% tx power. Each 16bit word contains four tx
1498 * power values and the order is the same as used in the TX_PWR_CFG
1499 * registers.
1500 */
1501 offset = TX_PWR_CFG_0;
1502
1503 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1504 /* just to be safe */
1505 if (offset > TX_PWR_CFG_4)
1506 break;
1507
1508 rt2800_register_read(rt2x00dev, offset, &reg);
1509
1510 /* read the next four txpower values */
1511 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1512 &eeprom);
1513
1514 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1515 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1516 * TX_PWR_CFG_4: unknown */
1517 txpower = rt2x00_get_field16(eeprom,
1518 EEPROM_TXPOWER_BYRATE_RATE0);
1519 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1520 min(txpower, max_value));
1521
1522 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1523 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1524 * TX_PWR_CFG_4: unknown */
1525 txpower = rt2x00_get_field16(eeprom,
1526 EEPROM_TXPOWER_BYRATE_RATE1);
1527 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1528 min(txpower, max_value));
1529
1530 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1531 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1532 * TX_PWR_CFG_4: unknown */
1533 txpower = rt2x00_get_field16(eeprom,
1534 EEPROM_TXPOWER_BYRATE_RATE2);
1535 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1536 min(txpower, max_value));
1537
1538 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1539 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1540 * TX_PWR_CFG_4: unknown */
1541 txpower = rt2x00_get_field16(eeprom,
1542 EEPROM_TXPOWER_BYRATE_RATE3);
1543 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1544 min(txpower, max_value));
1545
1546 /* read the next four txpower values */
1547 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1548 &eeprom);
1549
1550 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1551 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1552 * TX_PWR_CFG_4: unknown */
1553 txpower = rt2x00_get_field16(eeprom,
1554 EEPROM_TXPOWER_BYRATE_RATE0);
1555 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1556 min(txpower, max_value));
1557
1558 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1559 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1560 * TX_PWR_CFG_4: unknown */
1561 txpower = rt2x00_get_field16(eeprom,
1562 EEPROM_TXPOWER_BYRATE_RATE1);
1563 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1564 min(txpower, max_value));
1565
1566 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1567 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1568 * TX_PWR_CFG_4: unknown */
1569 txpower = rt2x00_get_field16(eeprom,
1570 EEPROM_TXPOWER_BYRATE_RATE2);
1571 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1572 min(txpower, max_value));
1573
1574 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1575 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1576 * TX_PWR_CFG_4: unknown */
1577 txpower = rt2x00_get_field16(eeprom,
1578 EEPROM_TXPOWER_BYRATE_RATE3);
1579 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1580 min(txpower, max_value));
1581
1582 rt2800_register_write(rt2x00dev, offset, reg);
1583
1584 /* next TX_PWR_CFG register */
1585 offset += 4;
1586 }
f4450616
BZ		 1587}
1588
1589static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1590 struct rt2x00lib_conf *libconf)
1591{
1592 u32 reg;
1593
1594 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1595 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1596 libconf->conf->short_frame_max_tx_count);
1597 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1598 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1599 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1600}
1601
1602static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1603 struct rt2x00lib_conf *libconf)
1604{
1605 enum dev_state state =
1606 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1607 STATE_SLEEP : STATE_AWAKE;
1608 u32 reg;
1609
1610 if (state == STATE_SLEEP) {
1611 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1612
1613 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1614 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1615 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1616 libconf->conf->listen_interval - 1);
1617 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1618 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1619
1620 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1621 } else {
f4450616
BZ		 1622 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1623 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1624 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1625 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1626 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1627
1628 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1629 }
1630}
1631
1632void rt2800_config(struct rt2x00_dev *rt2x00dev,
1633 struct rt2x00lib_conf *libconf,
1634 const unsigned int flags)
1635{
1636 /* Always recalculate LNA gain before changing configuration */
1637 rt2800_config_lna_gain(rt2x00dev, libconf);
1638
1639 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1640 rt2800_config_channel(rt2x00dev, libconf->conf,
1641 &libconf->rf, &libconf->channel);
1642 if (flags & IEEE80211_CONF_CHANGE_POWER)
1643 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1644 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1645 rt2800_config_retry_limit(rt2x00dev, libconf);
1646 if (flags & IEEE80211_CONF_CHANGE_PS)
1647 rt2800_config_ps(rt2x00dev, libconf);
1648}
1649EXPORT_SYMBOL_GPL(rt2800_config);
1650
1651/*
1652 * Link tuning
1653 */
1654void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1655{
1656 u32 reg;
1657
1658 /*
1659 * Update FCS error count from register.
1660 */
1661 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1662 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1663}
1664EXPORT_SYMBOL_GPL(rt2800_link_stats);
1665
1666static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1667{
1668 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1669 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1670 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1671 rt2x00_rt(rt2x00dev, RT3090) ||
1672 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1673 return 0x1c + (2 * rt2x00dev->lna_gain);
1674 else
1675 return 0x2e + rt2x00dev->lna_gain;
1676 }
1677
1678 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1679 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1680 else
1681 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1682}
1683
1684static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1685 struct link_qual *qual, u8 vgc_level)
1686{
1687 if (qual->vgc_level != vgc_level) {
1688 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1689 qual->vgc_level = vgc_level;
1690 qual->vgc_level_reg = vgc_level;
1691 }
1692}
1693
1694void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1695{
1696 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1697}
1698EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1699
1700void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1701 const u32 count)
1702{
8d0c9b65 1703 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1704 return;
1705
1706 /*
1707 * When RSSI is better then -80 increase VGC level with 0x10
1708 */
1709 rt2800_set_vgc(rt2x00dev, qual,
1710 rt2800_get_default_vgc(rt2x00dev) +
1711 ((qual->rssi > -80) * 0x10));
1712}
1713EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1714
1715/*
1716 * Initialization functions.
1717 */
b9a07ae9 1718static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 1719{
1720 u32 reg;
d5385bfc 1721 u16 eeprom;
fcf51541 1722 unsigned int i;
e3a896b9 1723 int ret;
fcf51541 1724
a9dce149
GW		 1725 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1726 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1727 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1728 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1729 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1730 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1731 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1732
e3a896b9
GW		 1733 ret = rt2800_drv_init_registers(rt2x00dev);
1734 if (ret)
1735 return ret;
fcf51541
BZ		 1736
1737 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1738 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1739 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1740 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1741 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1742 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1743
1744 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1745 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1746 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1747 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1748 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1749 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1750
1751 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1752 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1753
1754 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1755
1756 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 1757 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 1758 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1759 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1760 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1761 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1762 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1763 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1764
a9dce149
GW		 1765 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1766
1767 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1768 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1769 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1770 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1771
64522957 1772 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1773 rt2x00_rt(rt2x00dev, RT3090) ||
1774 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1775 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1776 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1777 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1778 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1779 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1780 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1781 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1782 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1783 0x0000002c);
1784 else
1785 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1786 0x0000000f);
1787 } else {
1788 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1789 }
d5385bfc 1790 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1791 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1792
1793 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1794 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1795 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1796 } else {
1797 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1798 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1799 }
c295a81d
HS		 1800 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1801 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1802 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1803 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1804 } else {
1805 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1806 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1807 }
1808
1809 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1810 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1811 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1812 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1813 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1814 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1815 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1816 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1817 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1818 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1819
1820 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1821 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1822 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1823 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1824 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1825
1826 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1827 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1828 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1829 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1830 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1831 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1832 else
1833 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1834 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1835 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1836 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1837
a9dce149
GW		 1838 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1839 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1840 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1841 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1842 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1843 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1844 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1845 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1846 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1847
fcf51541
BZ		 1848 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1849
a9dce149
GW		 1850 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1851 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1852 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1853 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1854 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1855 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1856 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1857 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1858
fcf51541
BZ		 1859 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1860 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1861 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1862 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1863 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1864 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1865 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1866 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1867 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1868
1869 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1870 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1871 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1872 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1873 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1874 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1875 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1876 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1877 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1878 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1879 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1880 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1881
1882 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1883 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1884 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1885 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1886 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1887 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1888 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1889 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1890 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1891 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1892 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1893 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1894
1895 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1896 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1897 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1898 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1899 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1900 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1901 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1902 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1903 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1904 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1905 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1906 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1907
1908 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1909 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
a9dce149
GW		 1910 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1911 !rt2x00_is_usb(rt2x00dev));
fcf51541
BZ		 1912 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1913 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1914 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1915 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1916 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1917 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1918 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1919 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1920 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1921
1922 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1923 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1924 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1925 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1926 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1927 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1928 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1929 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1930 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1931 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1932 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1933 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1934
1935 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1936 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1937 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1938 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1939 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1940 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1941 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1942 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1943 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1944 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1945 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1946 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1947
cea90e55 1948 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1949 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1950
1951 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1952 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1953 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1954 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1955 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1956 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1957 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1958 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1959 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1960 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1961 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1962 }
1963
1964 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1965 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1966
1967 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1968 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1969 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1970 IEEE80211_MAX_RTS_THRESHOLD);
1971 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1972 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1973
1974 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 1975
a21c2ab4
HS		 1976 /*
1977 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1978 * time should be set to 16. However, the original Ralink driver uses
1979 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1980 * connection problems with 11g + CTS protection. Hence, use the same
1981 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1982 */
a9dce149 1983 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 1984 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1985 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 1986 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1987 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1988 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1989 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1990
fcf51541
BZ		 1991 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1992
1993 /*
1994 * ASIC will keep garbage value after boot, clear encryption keys.
1995 */
1996 for (i = 0; i < 4; i++)
1997 rt2800_register_write(rt2x00dev,
1998 SHARED_KEY_MODE_ENTRY(i), 0);
1999
2000 for (i = 0; i < 256; i++) {
2001 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2002 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2003 wcid, sizeof(wcid));
2004
2005 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2006 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2007 }
2008
2009 /*
2010 * Clear all beacons
fcf51541 2011 */
fdb87251
HS		 2012 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
2013 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
2014 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
2015 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2016 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2017 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2018 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2019 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2020
cea90e55 2021 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2022 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2023 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2024 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2025 }
2026
2027 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2028 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2029 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2030 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2031 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2032 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2033 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2034 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2035 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2036 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2037
2038 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2039 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2040 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2041 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2042 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2043 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2044 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2045 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2046 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2047 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2048
2049 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2050 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2051 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2052 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2053 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2054 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2055 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2056 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2057 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2058 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2059
2060 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2061 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2062 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2063 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2064 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2065 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2066
47ee3eb1
HS		 2067 /*
2068 * Do not force the BA window size, we use the TXWI to set it
2069 */
2070 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2071 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2072 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2073 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2074
fcf51541
BZ		 2075 /*
2076 * We must clear the error counters.
2077 * These registers are cleared on read,
2078 * so we may pass a useless variable to store the value.
2079 */
2080 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2081 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2082 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2083 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2084 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2085 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2086
9f926fb5
HS		 2087 /*
2088 * Setup leadtime for pre tbtt interrupt to 6ms
2089 */
2090 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2091 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2092 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2093
fcf51541
BZ		 2094 return 0;
2095}
fcf51541
BZ		 2096
2097static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2098{
2099 unsigned int i;
2100 u32 reg;
2101
2102 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2103 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2104 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2105 return 0;
2106
2107 udelay(REGISTER_BUSY_DELAY);
2108 }
2109
2110 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2111 return -EACCES;
2112}
2113
2114static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2115{
2116 unsigned int i;
2117 u8 value;
2118
2119 /*
2120 * BBP was enabled after firmware was loaded,
2121 * but we need to reactivate it now.
2122 */
2123 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2124 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2125 msleep(1);
2126
2127 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2128 rt2800_bbp_read(rt2x00dev, 0, &value);
2129 if ((value != 0xff) && (value != 0x00))
2130 return 0;
2131 udelay(REGISTER_BUSY_DELAY);
2132 }
2133
2134 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2135 return -EACCES;
2136}
2137
b9a07ae9 2138static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2139{
2140 unsigned int i;
2141 u16 eeprom;
2142 u8 reg_id;
2143 u8 value;
2144
2145 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2146 rt2800_wait_bbp_ready(rt2x00dev)))
2147 return -EACCES;
2148
baff8006
HS		 2149 if (rt2800_is_305x_soc(rt2x00dev))
2150 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2151
fcf51541
BZ		 2152 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2153 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 2154
2155 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2156 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2157 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2158 } else {
2159 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2160 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2161 }
2162
fcf51541 2163 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2164
d5385bfc 2165 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2166 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2167 rt2x00_rt(rt2x00dev, RT3090) ||
2168 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 2169 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2170 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2171 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2172 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2173 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2174 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2175 } else {
2176 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2177 }
2178
fcf51541
BZ		 2179 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2180 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2181
5ed8f458 2182 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 2183 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2184 else
2185 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2186
fcf51541
BZ		 2187 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2188 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2189 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2190
d5385bfc 2191 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2192 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2193 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 2194 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2195 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2196 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2197 else
2198 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2199
baff8006
HS		 2200 if (rt2800_is_305x_soc(rt2x00dev))
2201 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2202 else
2203 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 2204 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 2205
64522957 2206 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2207 rt2x00_rt(rt2x00dev, RT3090) ||
2208 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 2209 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2210
d5385bfc
GW		 2211 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2212 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2213 value |= 0x20;
2214 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2215 value &= ~0x02;
fcf51541 2216
d5385bfc 2217 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2218 }
2219
fcf51541
BZ		 2220
2221 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2222 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2223
2224 if (eeprom != 0xffff && eeprom != 0x0000) {
2225 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2226 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2227 rt2800_bbp_write(rt2x00dev, reg_id, value);
2228 }
2229 }
2230
2231 return 0;
2232}
fcf51541
BZ		 2233
2234static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2235 bool bw40, u8 rfcsr24, u8 filter_target)
2236{
2237 unsigned int i;
2238 u8 bbp;
2239 u8 rfcsr;
2240 u8 passband;
2241 u8 stopband;
2242 u8 overtuned = 0;
2243
2244 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2245
2246 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2247 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2248 rt2800_bbp_write(rt2x00dev, 4, bbp);
2249
2250 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2251 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2252 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2253
2254 /*
2255 * Set power & frequency of passband test tone
2256 */
2257 rt2800_bbp_write(rt2x00dev, 24, 0);
2258
2259 for (i = 0; i < 100; i++) {
2260 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2261 msleep(1);
2262
2263 rt2800_bbp_read(rt2x00dev, 55, &passband);
2264 if (passband)
2265 break;
2266 }
2267
2268 /*
2269 * Set power & frequency of stopband test tone
2270 */
2271 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2272
2273 for (i = 0; i < 100; i++) {
2274 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2275 msleep(1);
2276
2277 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2278
2279 if ((passband - stopband) <= filter_target) {
2280 rfcsr24++;
2281 overtuned += ((passband - stopband) == filter_target);
2282 } else
2283 break;
2284
2285 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2286 }
2287
2288 rfcsr24 -= !!overtuned;
2289
2290 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2291 return rfcsr24;
2292}
2293
b9a07ae9 2294static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2295{
2296 u8 rfcsr;
2297 u8 bbp;
8cdd15e0
GW		 2298 u32 reg;
2299 u16 eeprom;
fcf51541 2300
d5385bfc 2301 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2302 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2303 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2304 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 2305 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2306 return 0;
2307
fcf51541
BZ		 2308 /*
2309 * Init RF calibration.
2310 */
2311 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2312 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2313 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2314 msleep(1);
2315 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2316 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2317
d5385bfc 2318 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2319 rt2x00_rt(rt2x00dev, RT3071) ||
2320 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2321 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2322 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2323 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2324 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2325 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2326 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2327 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2328 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2329 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2330 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2331 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2332 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2333 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2334 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2335 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2336 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2337 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2338 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2339 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2340 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2341 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2342 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2343 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2344 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2345 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2346 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2347 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2348 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2349 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2350 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2351 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2352 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2353 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2354 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2355 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2356 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2357 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2358 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2359 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2360 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2361 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2362 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2363 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2364 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2365 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2366 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2367 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2368 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2369 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2370 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2371 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2372 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2373 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2374 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2375 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2376 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2377 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2378 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2379 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2380 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2381 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2382 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2383 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2384 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2385 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2386 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2387 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2388 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2389 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2390 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2391 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2392 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2393 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2394 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2395 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2396 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2397 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2398 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2399 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2400 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2401 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2402 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2403 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2404 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2405 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2406 return 0;
8cdd15e0
GW		 2407 }
2408
2409 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2410 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2411 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2412 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2413 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2414 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2415 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 2416 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2417 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2418 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2419
2420 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2421
2422 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2423 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2424 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2425 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 2426 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2427 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2428 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2429 else
2430 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2431 }
2432 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 2433 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2434 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2435 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2436 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2437 }
2438
2439 /*
2440 * Set RX Filter calibration for 20MHz and 40MHz
2441 */
8cdd15e0
GW		 2442 if (rt2x00_rt(rt2x00dev, RT3070)) {
2443 rt2x00dev->calibration[0] =
2444 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2445 rt2x00dev->calibration[1] =
2446 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2447 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2448 rt2x00_rt(rt2x00dev, RT3090) ||
2449 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2450 rt2x00dev->calibration[0] =
2451 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2452 rt2x00dev->calibration[1] =
2453 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2454 }
fcf51541
BZ		 2455
2456 /*
2457 * Set back to initial state
2458 */
2459 rt2800_bbp_write(rt2x00dev, 24, 0);
2460
2461 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2462 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2463 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2464
2465 /*
2466 * set BBP back to BW20
2467 */
2468 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2469 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2470 rt2800_bbp_write(rt2x00dev, 4, bbp);
2471
d5385bfc 2472 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2473 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2474 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2475 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2476 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2477
2478 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2479 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2480 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2481
2482 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2483 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2484 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2485 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2486 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
8440c292 2487 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2488 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2489 }
8cdd15e0
GW		 2490 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2491 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2492 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2493 rt2x00_get_field16(eeprom,
2494 EEPROM_TXMIXER_GAIN_BG_VAL));
2495 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2496
64522957
GW		 2497 if (rt2x00_rt(rt2x00dev, RT3090)) {
2498 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2499
2500 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2501 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2502 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2503 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2504 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2505
2506 rt2800_bbp_write(rt2x00dev, 138, bbp);
2507 }
2508
2509 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2510 rt2x00_rt(rt2x00dev, RT3090) ||
2511 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2512 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2513 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2514 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2515 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2516 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2517 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2518 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2519
2520 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2521 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2522 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2523
2524 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2525 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2526 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2527
2528 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2529 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2530 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2531 }
2532
2533 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2534 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2535 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2536 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2537 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2538 else
2539 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2540 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2541 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2542 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2543 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2544 }
2545
fcf51541
BZ		 2546 return 0;
2547}
b9a07ae9
ID		 2548
2549int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2550{
2551 u32 reg;
2552 u16 word;
2553
2554 /*
2555 * Initialize all registers.
2556 */
2557 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2558 rt2800_init_registers(rt2x00dev) ||
2559 rt2800_init_bbp(rt2x00dev) ||
2560 rt2800_init_rfcsr(rt2x00dev)))
2561 return -EIO;
2562
2563 /*
2564 * Send signal to firmware during boot time.
2565 */
2566 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2567
2568 if (rt2x00_is_usb(rt2x00dev) &&
2569 (rt2x00_rt(rt2x00dev, RT3070) ||
2570 rt2x00_rt(rt2x00dev, RT3071) ||
2571 rt2x00_rt(rt2x00dev, RT3572))) {
2572 udelay(200);
2573 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2574 udelay(10);
2575 }
2576
2577 /*
2578 * Enable RX.
2579 */
2580 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2581 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2582 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2583 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2584
2585 udelay(50);
2586
2587 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2588 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2589 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2590 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2591 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2592 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2593
2594 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2595 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2596 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2597 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2598
2599 /*
2600 * Initialize LED control
2601 */
2602 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2603 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2604 word & 0xff, (word >> 8) & 0xff);
2605
2606 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2607 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2608 word & 0xff, (word >> 8) & 0xff);
2609
2610 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2611 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2612 word & 0xff, (word >> 8) & 0xff);
2613
2614 return 0;
2615}
2616EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2617
2618void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2619{
2620 u32 reg;
2621
2622 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2623 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2624 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2625 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2626 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2627 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2628 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2629
2630 /* Wait for DMA, ignore error */
2631 rt2800_wait_wpdma_ready(rt2x00dev);
2632
2633 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2634 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2635 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2636 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2637
2638 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2639 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2640}
2641EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 2642
30e84034
BZ		 2643int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2644{
2645 u32 reg;
2646
2647 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2648
2649 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2650}
2651EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2652
2653static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2654{
2655 u32 reg;
2656
31a4cf1f
GW		 2657 mutex_lock(&rt2x00dev->csr_mutex);
2658
2659 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2660 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2661 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2662 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2663 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2664
2665 /* Wait until the EEPROM has been loaded */
2666 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2667
2668 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2669 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2670 (u32 *)&rt2x00dev->eeprom[i]);
2671 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2672 (u32 *)&rt2x00dev->eeprom[i + 2]);
2673 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2674 (u32 *)&rt2x00dev->eeprom[i + 4]);
2675 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2676 (u32 *)&rt2x00dev->eeprom[i + 6]);
2677
2678 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2679}
2680
2681void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2682{
2683 unsigned int i;
2684
2685 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2686 rt2800_efuse_read(rt2x00dev, i);
2687}
2688EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2689
38bd7b8a
BZ		 2690int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2691{
2692 u16 word;
2693 u8 *mac;
2694 u8 default_lna_gain;
2695
2696 /*
2697 * Start validation of the data that has been read.
2698 */
2699 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2700 if (!is_valid_ether_addr(mac)) {
2701 random_ether_addr(mac);
2702 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2703 }
2704
2705 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2706 if (word == 0xffff) {
2707 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2708 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2709 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2710 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2711 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2712 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2713 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2714 /*
2715 * There is a max of 2 RX streams for RT28x0 series
2716 */
2717 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2718 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2719 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2720 }
2721
2722 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2723 if (word == 0xffff) {
2724 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2725 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2726 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2727 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2728 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2729 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2730 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2731 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2732 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2733 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
ec2d1791
GW		 2734 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2735 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
38bd7b8a
BZ		 2736 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2737 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2738 }
2739
2740 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2741 if ((word & 0x00ff) == 0x00ff) {
2742 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 2743 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2744 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2745 }
2746 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 2747 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2748 LED_MODE_TXRX_ACTIVITY);
2749 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2750 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2751 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2752 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2753 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
ec2d1791 2754 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 2755 }
2756
2757 /*
2758 * During the LNA validation we are going to use
2759 * lna0 as correct value. Note that EEPROM_LNA
2760 * is never validated.
2761 */
2762 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2763 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2764
2765 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2766 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2767 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2768 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2769 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2770 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2771
2772 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2773 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2774 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2775 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2776 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2777 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2778 default_lna_gain);
2779 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2780
2781 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2782 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2783 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2784 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2785 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2786 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2787
2788 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2789 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2790 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2791 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2792 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2793 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2794 default_lna_gain);
2795 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2796
8d1331b3
ID		 2797 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2798 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2799 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2800 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2801 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2802 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2803
38bd7b8a
BZ		 2804 return 0;
2805}
2806EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2807
2808int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2809{
2810 u32 reg;
2811 u16 value;
2812 u16 eeprom;
2813
2814 /*
2815 * Read EEPROM word for configuration.
2816 */
2817 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2818
2819 /*
2820 * Identify RF chipset.
2821 */
2822 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2823 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2824
49e721ec
GW		 2825 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2826 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2827
2828 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 2829 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2830 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2831 !rt2x00_rt(rt2x00dev, RT3070) &&
2832 !rt2x00_rt(rt2x00dev, RT3071) &&
2833 !rt2x00_rt(rt2x00dev, RT3090) &&
2834 !rt2x00_rt(rt2x00dev, RT3390) &&
2835 !rt2x00_rt(rt2x00dev, RT3572)) {
2836 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2837 return -ENODEV;
f273fe55 2838 }
714fa663 2839
5122d898
GW		 2840 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2841 !rt2x00_rf(rt2x00dev, RF2850) &&
2842 !rt2x00_rf(rt2x00dev, RF2720) &&
2843 !rt2x00_rf(rt2x00dev, RF2750) &&
2844 !rt2x00_rf(rt2x00dev, RF3020) &&
2845 !rt2x00_rf(rt2x00dev, RF2020) &&
2846 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2847 !rt2x00_rf(rt2x00dev, RF3022) &&
2848 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2849 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2850 return -ENODEV;
2851 }
2852
2853 /*
2854 * Identify default antenna configuration.
2855 */
2856 rt2x00dev->default_ant.tx =
2857 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2858 rt2x00dev->default_ant.rx =
2859 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2860
2861 /*
2862 * Read frequency offset and RF programming sequence.
2863 */
2864 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2865 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2866
2867 /*
2868 * Read external LNA informations.
2869 */
2870 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2871
2872 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2873 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2874 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2875 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2876
2877 /*
2878 * Detect if this device has an hardware controlled radio.
2879 */
2880 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2881 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2882
2883 /*
2884 * Store led settings, for correct led behaviour.
2885 */
2886#ifdef CONFIG_RT2X00_LIB_LEDS
2887 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2888 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2889 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2890
2891 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2892#endif /* CONFIG_RT2X00_LIB_LEDS */
2893
2894 return 0;
2895}
2896EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2897
4da2933f 2898/*
55f9321a 2899 * RF value list for rt28xx
4da2933f
BZ		 2900 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2901 */
2902static const struct rf_channel rf_vals[] = {
2903 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2904 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2905 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2906 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2907 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2908 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2909 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2910 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2911 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2912 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2913 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2914 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2915 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2916 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2917
2918 /* 802.11 UNI / HyperLan 2 */
2919 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2920 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2921 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2922 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2923 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2924 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2925 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2926 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2927 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2928 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2929 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2930 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2931
2932 /* 802.11 HyperLan 2 */
2933 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2934 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2935 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2936 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2937 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2938 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2939 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2940 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2941 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2942 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2943 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2944 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2945 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2946 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2947 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2948 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2949
2950 /* 802.11 UNII */
2951 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2952 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2953 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2954 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2955 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2956 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2957 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2958 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2959 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2960 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2961 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2962
2963 /* 802.11 Japan */
2964 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2965 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2966 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2967 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2968 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2969 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2970 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2971};
2972
2973/*
55f9321a
ID		 2974 * RF value list for rt3xxx
2975 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 2976 */
55f9321a 2977static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 2978 {1, 241, 2, 2 },
2979 {2, 241, 2, 7 },
2980 {3, 242, 2, 2 },
2981 {4, 242, 2, 7 },
2982 {5, 243, 2, 2 },
2983 {6, 243, 2, 7 },
2984 {7, 244, 2, 2 },
2985 {8, 244, 2, 7 },
2986 {9, 245, 2, 2 },
2987 {10, 245, 2, 7 },
2988 {11, 246, 2, 2 },
2989 {12, 246, 2, 7 },
2990 {13, 247, 2, 2 },
2991 {14, 248, 2, 4 },
55f9321a
ID		 2992
2993 /* 802.11 UNI / HyperLan 2 */
2994 {36, 0x56, 0, 4},
2995 {38, 0x56, 0, 6},
2996 {40, 0x56, 0, 8},
2997 {44, 0x57, 0, 0},
2998 {46, 0x57, 0, 2},
2999 {48, 0x57, 0, 4},
3000 {52, 0x57, 0, 8},
3001 {54, 0x57, 0, 10},
3002 {56, 0x58, 0, 0},
3003 {60, 0x58, 0, 4},
3004 {62, 0x58, 0, 6},
3005 {64, 0x58, 0, 8},
3006
3007 /* 802.11 HyperLan 2 */
3008 {100, 0x5b, 0, 8},
3009 {102, 0x5b, 0, 10},
3010 {104, 0x5c, 0, 0},
3011 {108, 0x5c, 0, 4},
3012 {110, 0x5c, 0, 6},
3013 {112, 0x5c, 0, 8},
3014 {116, 0x5d, 0, 0},
3015 {118, 0x5d, 0, 2},
3016 {120, 0x5d, 0, 4},
3017 {124, 0x5d, 0, 8},
3018 {126, 0x5d, 0, 10},
3019 {128, 0x5e, 0, 0},
3020 {132, 0x5e, 0, 4},
3021 {134, 0x5e, 0, 6},
3022 {136, 0x5e, 0, 8},
3023 {140, 0x5f, 0, 0},
3024
3025 /* 802.11 UNII */
3026 {149, 0x5f, 0, 9},
3027 {151, 0x5f, 0, 11},
3028 {153, 0x60, 0, 1},
3029 {157, 0x60, 0, 5},
3030 {159, 0x60, 0, 7},
3031 {161, 0x60, 0, 9},
3032 {165, 0x61, 0, 1},
3033 {167, 0x61, 0, 3},
3034 {169, 0x61, 0, 5},
3035 {171, 0x61, 0, 7},
3036 {173, 0x61, 0, 9},
4da2933f
BZ		 3037};
3038
3039int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3040{
4da2933f
BZ		 3041 struct hw_mode_spec *spec = &rt2x00dev->spec;
3042 struct channel_info *info;
8d1331b3
ID		 3043 char *default_power1;
3044 char *default_power2;
4da2933f 3045 unsigned int i;
8d1331b3 3046 unsigned short max_power;
4da2933f
BZ		 3047 u16 eeprom;
3048
93b6bd26
GW		 3049 /*
3050 * Disable powersaving as default on PCI devices.
3051 */
cea90e55 3052 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 3053 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3054
4da2933f
BZ		 3055 /*
3056 * Initialize all hw fields.
3057 */
3058 rt2x00dev->hw->flags =
3059 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3060 IEEE80211_HW_SIGNAL_DBM |
3061 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3062 IEEE80211_HW_PS_NULLFUNC_STACK |
3063 IEEE80211_HW_AMPDU_AGGREGATION;
4da2933f 3064
4da2933f
BZ		 3065 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3066 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3067 rt2x00_eeprom_addr(rt2x00dev,
3068 EEPROM_MAC_ADDR_0));
3069
3f2bee24
HS		 3070 /*
3071 * As rt2800 has a global fallback table we cannot specify
3072 * more then one tx rate per frame but since the hw will
3073 * try several rates (based on the fallback table) we should
3074 * still initialize max_rates to the maximum number of rates
3075 * we are going to try. Otherwise mac80211 will truncate our
3076 * reported tx rates and the rc algortihm will end up with
3077 * incorrect data.
3078 */
3079 rt2x00dev->hw->max_rates = 7;
3080 rt2x00dev->hw->max_rate_tries = 1;
3081
4da2933f
BZ		 3082 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
3083
3084 /*
3085 * Initialize hw_mode information.
3086 */
3087 spec->supported_bands = SUPPORT_BAND_2GHZ;
3088 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3089
5122d898 3090 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3091 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3092 spec->num_channels = 14;
3093 spec->channels = rf_vals;
55f9321a
ID		 3094 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3095 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3096 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3097 spec->num_channels = ARRAY_SIZE(rf_vals);
3098 spec->channels = rf_vals;
5122d898
GW		 3099 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3100 rt2x00_rf(rt2x00dev, RF2020) ||
3101 rt2x00_rf(rt2x00dev, RF3021) ||
3102 rt2x00_rf(rt2x00dev, RF3022)) {
55f9321a
ID		 3103 spec->num_channels = 14;
3104 spec->channels = rf_vals_3x;
3105 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3106 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3107 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3108 spec->channels = rf_vals_3x;
4da2933f
BZ		 3109 }
3110
3111 /*
3112 * Initialize HT information.
3113 */
5122d898 3114 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 3115 spec->ht.ht_supported = true;
3116 else
3117 spec->ht.ht_supported = false;
3118
4da2933f 3119 spec->ht.cap =
06443e46 3120 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 3121 IEEE80211_HT_CAP_GRN_FLD |
3122 IEEE80211_HT_CAP_SGI_20 |
aa674631 3123 IEEE80211_HT_CAP_SGI_40;
22cabaa6
HS		 3124
3125 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
3126 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3127
aa674631
ID		 3128 spec->ht.cap |=
3129 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
3130 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3131
4da2933f
BZ		 3132 spec->ht.ampdu_factor = 3;
3133 spec->ht.ampdu_density = 4;
3134 spec->ht.mcs.tx_params =
3135 IEEE80211_HT_MCS_TX_DEFINED |
3136 IEEE80211_HT_MCS_TX_RX_DIFF |
3137 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
3138 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3139
3140 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
3141 case 3:
3142 spec->ht.mcs.rx_mask[2] = 0xff;
3143 case 2:
3144 spec->ht.mcs.rx_mask[1] = 0xff;
3145 case 1:
3146 spec->ht.mcs.rx_mask[0] = 0xff;
3147 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3148 break;
3149 }
3150
3151 /*
3152 * Create channel information array
3153 */
baeb2ffa 3154 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 3155 if (!info)
3156 return -ENOMEM;
3157
3158 spec->channels_info = info;
3159
8d1331b3
ID		 3160 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3161 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3162 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3163 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 3164
3165 for (i = 0; i < 14; i++) {
8d1331b3
ID		 3166 info[i].max_power = max_power;
3167 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3168 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3169 }
3170
3171 if (spec->num_channels > 14) {
8d1331b3
ID		 3172 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3173 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3174 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 3175
3176 for (i = 14; i < spec->num_channels; i++) {
8d1331b3
ID		 3177 info[i].max_power = max_power;
3178 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3179 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3180 }
3181 }
3182
3183 return 0;
3184}
3185EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3186
2ce33995
BZ		 3187/*
3188 * IEEE80211 stack callback functions.
3189 */
e783619e
HS		 3190void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3191 u16 *iv16)
2ce33995
BZ		 3192{
3193 struct rt2x00_dev *rt2x00dev = hw->priv;
3194 struct mac_iveiv_entry iveiv_entry;
3195 u32 offset;
3196
3197 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3198 rt2800_register_multiread(rt2x00dev, offset,
3199 &iveiv_entry, sizeof(iveiv_entry));
3200
855da5e0
JL		 3201 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3202 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 3203}
e783619e 3204EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 3205
e783619e 3206int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 3207{
3208 struct rt2x00_dev *rt2x00dev = hw->priv;
3209 u32 reg;
3210 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3211
3212 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3213 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3214 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3215
3216 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3217 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3218 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3219
3220 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3221 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3222 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3223
3224 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3225 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3226 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3227
3228 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3229 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3230 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3231
3232 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3233 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3234 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3235
3236 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3237 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3238 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3239
3240 return 0;
3241}
e783619e 3242EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 3243
e783619e
HS		 3244int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3245 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 3246{
3247 struct rt2x00_dev *rt2x00dev = hw->priv;
3248 struct data_queue *queue;
3249 struct rt2x00_field32 field;
3250 int retval;
3251 u32 reg;
3252 u32 offset;
3253
3254 /*
3255 * First pass the configuration through rt2x00lib, that will
3256 * update the queue settings and validate the input. After that
3257 * we are free to update the registers based on the value
3258 * in the queue parameter.
3259 */
3260 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3261 if (retval)
3262 return retval;
3263
3264 /*
3265 * We only need to perform additional register initialization
3266 * for WMM queues/
3267 */
3268 if (queue_idx >= 4)
3269 return 0;
3270
3271 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3272
3273 /* Update WMM TXOP register */
3274 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3275 field.bit_offset = (queue_idx & 1) * 16;
3276 field.bit_mask = 0xffff << field.bit_offset;
3277
3278 rt2800_register_read(rt2x00dev, offset, &reg);
3279 rt2x00_set_field32(&reg, field, queue->txop);
3280 rt2800_register_write(rt2x00dev, offset, reg);
3281
3282 /* Update WMM registers */
3283 field.bit_offset = queue_idx * 4;
3284 field.bit_mask = 0xf << field.bit_offset;
3285
3286 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3287 rt2x00_set_field32(&reg, field, queue->aifs);
3288 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3289
3290 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3291 rt2x00_set_field32(&reg, field, queue->cw_min);
3292 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3293
3294 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3295 rt2x00_set_field32(&reg, field, queue->cw_max);
3296 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3297
3298 /* Update EDCA registers */
3299 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3300
3301 rt2800_register_read(rt2x00dev, offset, &reg);
3302 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3303 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3304 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3305 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3306 rt2800_register_write(rt2x00dev, offset, reg);
3307
3308 return 0;
3309}
e783619e 3310EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 3311
e783619e 3312u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 3313{
3314 struct rt2x00_dev *rt2x00dev = hw->priv;
3315 u64 tsf;
3316 u32 reg;
3317
3318 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3319 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3320 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3321 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3322
3323 return tsf;
3324}
e783619e 3325EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 3326
e783619e
HS		 3327int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3328 enum ieee80211_ampdu_mlme_action action,
3329 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1df90809 3330{
1df90809
HS		 3331 int ret = 0;
3332
3333 switch (action) {
3334 case IEEE80211_AMPDU_RX_START:
3335 case IEEE80211_AMPDU_RX_STOP:
3336 /* we don't support RX aggregation yet */
3337 ret = -ENOTSUPP;
3338 break;
3339 case IEEE80211_AMPDU_TX_START:
3340 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3341 break;
3342 case IEEE80211_AMPDU_TX_STOP:
3343 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3344 break;
3345 case IEEE80211_AMPDU_TX_OPERATIONAL:
3346 break;
3347 default:
4e9e58c6 3348 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 3349 }
3350
3351 return ret;
3352}
e783619e 3353EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02
ID		 3354
3355MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3356MODULE_VERSION(DRV_VERSION);
3357MODULE_DESCRIPTION("Ralink RT2800 library");
3358MODULE_LICENSE("GPL");
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