[net-next-2.6.git] / drivers / net / wireless / p54 / p54pci.c


/*
 * Linux device driver for PCI based Prism54
 *
 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
 * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
 *
 * Based on the islsm (softmac prism54) driver, which is:
 * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/firmware.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/completion.h>
#include <net/mac80211.h>

#include "p54.h"
#include "lmac.h"
#include "p54pci.h"

MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
MODULE_DESCRIPTION("Prism54 PCI wireless driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("prism54pci");
MODULE_FIRMWARE("isl3886pci");

static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
	/* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3890) },
	/* 3COM 3CRWE154G72 Wireless LAN adapter */
	{ PCI_DEVICE(0x10b7, 0x6001) },
	/* Intersil PRISM Indigo Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3877) },
	/* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3886) },
	/* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
	{ PCI_DEVICE(0x1260, 0xffff) },
	{ },
};

MODULE_DEVICE_TABLE(pci, p54p_table);

static int p54p_upload_firmware(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	__le32 reg;
	int err;
	__le32 *data;
	u32 remains, left, device_addr;

	P54P_WRITE(int_enable, cpu_to_le32(0));
	P54P_READ(int_enable);
	udelay(10);

	reg = P54P_READ(ctrl_stat);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
	P54P_WRITE(ctrl_stat, reg);
	P54P_READ(ctrl_stat);
	udelay(10);

	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();

	/* wait for the firmware to reset properly */
	mdelay(10);

	err = p54_parse_firmware(dev, priv->firmware);
	if (err)
		return err;

	if (priv->common.fw_interface != FW_LM86) {
		dev_err(&priv->pdev->dev, "wrong firmware, "
			"please get a LM86(PCI) firmware a try again.\n");
		return -EINVAL;
	}

	data = (__le32 *) priv->firmware->data;
	remains = priv->firmware->size;
	device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
	while (remains) {
		u32 i = 0;
		left = min((u32)0x1000, remains);
		P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
		P54P_READ(int_enable);

		device_addr += 0x1000;
		while (i < left) {
			P54P_WRITE(direct_mem_win[i], *data++);
			i += sizeof(u32);
		}

		remains -= left;
		P54P_READ(int_enable);
	}

	reg = P54P_READ(ctrl_stat);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
	P54P_WRITE(ctrl_stat, reg);
	P54P_READ(ctrl_stat);
	udelay(10);

	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	/* wait for the firmware to boot properly */
	mdelay(100);

	return 0;
}

static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	struct sk_buff **rx_buf, u32 index)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	u32 limit, idx, i;

	idx = le32_to_cpu(ring_control->host_idx[ring_index]);
	limit = idx;
	limit -= index;
	limit = ring_limit - limit;

	i = idx % ring_limit;
	while (limit-- > 1) {
		struct p54p_desc *desc = &ring[i];

		if (!desc->host_addr) {
			struct sk_buff *skb;
			dma_addr_t mapping;
			skb = dev_alloc_skb(priv->common.rx_mtu + 32);
			if (!skb)
				break;

			mapping = pci_map_single(priv->pdev,
						 skb_tail_pointer(skb),
						 priv->common.rx_mtu + 32,
						 PCI_DMA_FROMDEVICE);

			if (pci_dma_mapping_error(priv->pdev, mapping)) {
				dev_kfree_skb_any(skb);
				dev_err(&priv->pdev->dev,
					"RX DMA Mapping error\n");
				break;
			}

			desc->host_addr = cpu_to_le32(mapping);
			desc->device_addr = 0;	// FIXME: necessary?
			desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
			desc->flags = 0;
			rx_buf[i] = skb;
		}

		i++;
		idx++;
		i %= ring_limit;
	}

	wmb();
	ring_control->host_idx[ring_index] = cpu_to_le32(idx);
}

static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	struct sk_buff **rx_buf)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	struct p54p_desc *desc;
	u32 idx, i;

	i = (*index) % ring_limit;
	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
	idx %= ring_limit;
	while (i != idx) {
		u16 len;
		struct sk_buff *skb;
		desc = &ring[i];
		len = le16_to_cpu(desc->len);
		skb = rx_buf[i];

		if (!skb) {
			i++;
			i %= ring_limit;
			continue;
		}

		if (unlikely(len > priv->common.rx_mtu)) {
			if (net_ratelimit())
				dev_err(&priv->pdev->dev, "rx'd frame size "
					"exceeds length threshold.\n");

			len = priv->common.rx_mtu;
		}
		skb_put(skb, len);

		if (p54_rx(dev, skb)) {
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 priv->common.rx_mtu + 32,
					 PCI_DMA_FROMDEVICE);
			rx_buf[i] = NULL;
			desc->host_addr = 0;
		} else {
			skb_trim(skb, 0);
			desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
		}

		i++;
		i %= ring_limit;
	}

	p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
}

static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	struct sk_buff **tx_buf)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	struct p54p_desc *desc;
	struct sk_buff *skb;
	u32 idx, i;

	i = (*index) % ring_limit;
	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
	idx %= ring_limit;

	while (i != idx) {
		desc = &ring[i];

		skb = tx_buf[i];
		tx_buf[i] = NULL;

		pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
				 le16_to_cpu(desc->len), PCI_DMA_TODEVICE);

		desc->host_addr = 0;
		desc->device_addr = 0;
		desc->len = 0;
		desc->flags = 0;

		if (skb && FREE_AFTER_TX(skb))
			p54_free_skb(dev, skb);

		i++;
		i %= ring_limit;
	}
}

static void p54p_tasklet(unsigned long dev_id)
{
	struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;

	p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
			   ARRAY_SIZE(ring_control->tx_mgmt),
			   priv->tx_buf_mgmt);

	p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
			   ARRAY_SIZE(ring_control->tx_data),
			   priv->tx_buf_data);

	p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
		ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);

	p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
		ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);

	wmb();
	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
}

static irqreturn_t p54p_interrupt(int irq, void *dev_id)
{
	struct ieee80211_hw *dev = dev_id;
	struct p54p_priv *priv = dev->priv;
	__le32 reg;

	reg = P54P_READ(int_ident);
	if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
		goto out;
	}
	P54P_WRITE(int_ack, reg);

	reg &= P54P_READ(int_enable);

	if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
		tasklet_schedule(&priv->tasklet);
	else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
		complete(&priv->boot_comp);

out:
	return reg ? IRQ_HANDLED : IRQ_NONE;
}

static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
{
	unsigned long flags;
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	struct p54p_desc *desc;
	dma_addr_t mapping;
	u32 device_idx, idx, i;

	spin_lock_irqsave(&priv->lock, flags);
	device_idx = le32_to_cpu(ring_control->device_idx[1]);
	idx = le32_to_cpu(ring_control->host_idx[1]);
	i = idx % ARRAY_SIZE(ring_control->tx_data);

	mapping = pci_map_single(priv->pdev, skb->data, skb->len,
				 PCI_DMA_TODEVICE);
	if (pci_dma_mapping_error(priv->pdev, mapping)) {
		spin_unlock_irqrestore(&priv->lock, flags);
		p54_free_skb(dev, skb);
		dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
		return ;
	}
	priv->tx_buf_data[i] = skb;

	desc = &ring_control->tx_data[i];
	desc->host_addr = cpu_to_le32(mapping);
	desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
	desc->len = cpu_to_le16(skb->len);
	desc->flags = 0;

	wmb();
	ring_control->host_idx[1] = cpu_to_le32(idx + 1);
	spin_unlock_irqrestore(&priv->lock, flags);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	P54P_READ(dev_int);
}

static void p54p_stop(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	unsigned int i;
	struct p54p_desc *desc;

	P54P_WRITE(int_enable, cpu_to_le32(0));
	P54P_READ(int_enable);
	udelay(10);

	free_irq(priv->pdev->irq, dev);

	tasklet_kill(&priv->tasklet);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));

	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
		desc = &ring_control->rx_data[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 priv->common.rx_mtu + 32,
					 PCI_DMA_FROMDEVICE);
		kfree_skb(priv->rx_buf_data[i]);
		priv->rx_buf_data[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
		desc = &ring_control->rx_mgmt[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 priv->common.rx_mtu + 32,
					 PCI_DMA_FROMDEVICE);
		kfree_skb(priv->rx_buf_mgmt[i]);
		priv->rx_buf_mgmt[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
		desc = &ring_control->tx_data[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 le16_to_cpu(desc->len),
					 PCI_DMA_TODEVICE);

		p54_free_skb(dev, priv->tx_buf_data[i]);
		priv->tx_buf_data[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
		desc = &ring_control->tx_mgmt[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 le16_to_cpu(desc->len),
					 PCI_DMA_TODEVICE);

		p54_free_skb(dev, priv->tx_buf_mgmt[i]);
		priv->tx_buf_mgmt[i] = NULL;
	}

	memset(ring_control, 0, sizeof(*ring_control));
}

static int p54p_open(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	int err;

	init_completion(&priv->boot_comp);
	err = request_irq(priv->pdev->irq, p54p_interrupt,
			  IRQF_SHARED, "p54pci", dev);
	if (err) {
		dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
		return err;
	}

	memset(priv->ring_control, 0, sizeof(*priv->ring_control));
	err = p54p_upload_firmware(dev);
	if (err) {
		free_irq(priv->pdev->irq, dev);
		return err;
	}
	priv->rx_idx_data = priv->tx_idx_data = 0;
	priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;

	p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
		ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);

	p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
		ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);

	P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
	P54P_READ(ring_control_base);
	wmb();
	udelay(10);

	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
	P54P_READ(int_enable);
	wmb();
	udelay(10);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
	P54P_READ(dev_int);

	if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
		printk(KERN_ERR "%s: Cannot boot firmware!\n",
		       wiphy_name(dev->wiphy));
		p54p_stop(dev);
		return -ETIMEDOUT;
	}

	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
	P54P_READ(int_enable);
	wmb();
	udelay(10);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	P54P_READ(dev_int);
	wmb();
	udelay(10);

	return 0;
}

static int __devinit p54p_probe(struct pci_dev *pdev,
				const struct pci_device_id *id)
{
	struct p54p_priv *priv;
	struct ieee80211_hw *dev;
	unsigned long mem_addr, mem_len;
	int err;

	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "Cannot enable new PCI device\n");
		return err;
	}

	mem_addr = pci_resource_start(pdev, 0);
	mem_len = pci_resource_len(pdev, 0);
	if (mem_len < sizeof(struct p54p_csr)) {
		dev_err(&pdev->dev, "Too short PCI resources\n");
		goto err_disable_dev;
	}

	err = pci_request_regions(pdev, "p54pci");
	if (err) {
		dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
		goto err_disable_dev;
	}

	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
	    pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
		dev_err(&pdev->dev, "No suitable DMA available\n");
		goto err_free_reg;
	}

	pci_set_master(pdev);
	pci_try_set_mwi(pdev);

	pci_write_config_byte(pdev, 0x40, 0);
	pci_write_config_byte(pdev, 0x41, 0);

	dev = p54_init_common(sizeof(*priv));
	if (!dev) {
		dev_err(&pdev->dev, "ieee80211 alloc failed\n");
		err = -ENOMEM;
		goto err_free_reg;
	}

	priv = dev->priv;
	priv->pdev = pdev;

	SET_IEEE80211_DEV(dev, &pdev->dev);
	pci_set_drvdata(pdev, dev);

	priv->map = ioremap(mem_addr, mem_len);
	if (!priv->map) {
		dev_err(&pdev->dev, "Cannot map device memory\n");
		err = -ENOMEM;
		goto err_free_dev;
	}

	priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
						  &priv->ring_control_dma);
	if (!priv->ring_control) {
		dev_err(&pdev->dev, "Cannot allocate rings\n");
		err = -ENOMEM;
		goto err_iounmap;
	}
	priv->common.open = p54p_open;
	priv->common.stop = p54p_stop;
	priv->common.tx = p54p_tx;

	spin_lock_init(&priv->lock);
	tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);

	err = request_firmware(&priv->firmware, "isl3886pci",
			       &priv->pdev->dev);
	if (err) {
		dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
		err = request_firmware(&priv->firmware, "isl3886",
				       &priv->pdev->dev);
		if (err)
			goto err_free_common;
	}

	err = p54p_open(dev);
	if (err)
		goto err_free_common;
	err = p54_read_eeprom(dev);
	p54p_stop(dev);
	if (err)
		goto err_free_common;

	err = p54_register_common(dev, &pdev->dev);
	if (err)
		goto err_free_common;

	return 0;

 err_free_common:
	release_firmware(priv->firmware);
	pci_free_consistent(pdev, sizeof(*priv->ring_control),
			    priv->ring_control, priv->ring_control_dma);

 err_iounmap:
	iounmap(priv->map);

 err_free_dev:
	pci_set_drvdata(pdev, NULL);
	p54_free_common(dev);

 err_free_reg:
	pci_release_regions(pdev);
 err_disable_dev:
	pci_disable_device(pdev);
	return err;
}

static void __devexit p54p_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv;

	if (!dev)
		return;

	p54_unregister_common(dev);
	priv = dev->priv;
	release_firmware(priv->firmware);
	pci_free_consistent(pdev, sizeof(*priv->ring_control),
			    priv->ring_control, priv->ring_control_dma);
	iounmap(priv->map);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	p54_free_common(dev);
}

#ifdef CONFIG_PM
static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv = dev->priv;

	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
		ieee80211_stop_queues(dev);
		p54p_stop(dev);
	}

	pci_save_state(pdev);
	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	return 0;
}

static int p54p_resume(struct pci_dev *pdev)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv = dev->priv;

	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);

	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
		p54p_open(dev);
		ieee80211_wake_queues(dev);
	}

	return 0;
}
#endif /* CONFIG_PM */

static struct pci_driver p54p_driver = {
	.name		= "p54pci",
	.id_table	= p54p_table,
	.probe		= p54p_probe,
	.remove		= __devexit_p(p54p_remove),
#ifdef CONFIG_PM
	.suspend	= p54p_suspend,
	.resume		= p54p_resume,
#endif /* CONFIG_PM */
};

static int __init p54p_init(void)
{
	return pci_register_driver(&p54p_driver);
}

static void __exit p54p_exit(void)
{
	pci_unregister_driver(&p54p_driver);
}

module_init(p54p_init);
module_exit(p54p_exit);
Commit	Line	Data
eff1a59c MW	1
	2	/*
	3	* Linux device driver for PCI based Prism54
	4	*
	5	* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
7262d593	6	* Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
eff1a59c MW	7	*
	8	* Based on the islsm (softmac prism54) driver, which is:
	9	* Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/pci.h>
5a0e3ad6	18	#include <linux/slab.h>
eff1a59c MW	19	#include <linux/firmware.h>
	20	#include <linux/etherdevice.h>
	21	#include <linux/delay.h>
	22	#include <linux/completion.h>
	23	#include <net/mac80211.h>
	24
	25	#include "p54.h"
d8c92107	26	#include "lmac.h"
eff1a59c MW	27	#include "p54pci.h"
	28
	29	MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
	30	MODULE_DESCRIPTION("Prism54 PCI wireless driver");
	31	MODULE_LICENSE("GPL");
	32	MODULE_ALIAS("prism54pci");
9a8675d7	33	MODULE_FIRMWARE("isl3886pci");
eff1a59c	34
a3aa1884	35	static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
eff1a59c MW	36	/* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
	37	{ PCI_DEVICE(0x1260, 0x3890) },
	38	/* 3COM 3CRWE154G72 Wireless LAN adapter */
	39	{ PCI_DEVICE(0x10b7, 0x6001) },
	40	/* Intersil PRISM Indigo Wireless LAN adapter */
	41	{ PCI_DEVICE(0x1260, 0x3877) },
	42	/* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
	43	{ PCI_DEVICE(0x1260, 0x3886) },
50900f16 JA	44	/* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
50900f16 JA	45	{ PCI_DEVICE(0x1260, 0xffff) },
90f4dd0f	46	{ },
eff1a59c MW	47	};
	48
	49	MODULE_DEVICE_TABLE(pci, p54p_table);
	50
	51	static int p54p_upload_firmware(struct ieee80211_hw *dev)
	52	{
	53	struct p54p_priv *priv = dev->priv;
eff1a59c MW	54	__le32 reg;
eff1a59c MW	55	int err;
8160c031	56	__le32 *data;
eff1a59c MW	57	u32 remains, left, device_addr;
eff1a59c MW	58
8160c031	59	P54P_WRITE(int_enable, cpu_to_le32(0));
eff1a59c MW	60	P54P_READ(int_enable);
	61	udelay(10);
	62
	63	reg = P54P_READ(ctrl_stat);
	64	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	65	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
	66	P54P_WRITE(ctrl_stat, reg);
	67	P54P_READ(ctrl_stat);
	68	udelay(10);
	69
	70	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	71	P54P_WRITE(ctrl_stat, reg);
	72	wmb();
	73	udelay(10);
	74
	75	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	76	P54P_WRITE(ctrl_stat, reg);
	77	wmb();
	78
40db0b22 CL	79	/* wait for the firmware to reset properly */
40db0b22 CL	80	mdelay(10);
eff1a59c	81
40db0b22 CL	82	err = p54_parse_firmware(dev, priv->firmware);
40db0b22 CL	83	if (err)
4e416a6f	84	return err;
eff1a59c	85
e365f160 CL	86	if (priv->common.fw_interface != FW_LM86) {
	87	dev_err(&priv->pdev->dev, "wrong firmware, "
	88	"please get a LM86(PCI) firmware a try again.\n");
	89	return -EINVAL;
	90	}
	91
40db0b22 CL	92	data = (__le32 *) priv->firmware->data;
40db0b22 CL	93	remains = priv->firmware->size;
eff1a59c MW	94	device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
	95	while (remains) {
	96	u32 i = 0;
	97	left = min((u32)0x1000, remains);
	98	P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
	99	P54P_READ(int_enable);
	100
	101	device_addr += 0x1000;
	102	while (i < left) {
	103	P54P_WRITE(direct_mem_win[i], *data++);
	104	i += sizeof(u32);
	105	}
	106
	107	remains -= left;
	108	P54P_READ(int_enable);
	109	}
	110
eff1a59c MW	111	reg = P54P_READ(ctrl_stat);
	112	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
	113	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	114	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
	115	P54P_WRITE(ctrl_stat, reg);
	116	P54P_READ(ctrl_stat);
	117	udelay(10);
	118
	119	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	120	P54P_WRITE(ctrl_stat, reg);
	121	wmb();
	122	udelay(10);
	123
	124	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	125	P54P_WRITE(ctrl_stat, reg);
	126	wmb();
	127	udelay(10);
	128
7cb77072	129	/* wait for the firmware to boot properly */
eff1a59c	130	mdelay(100);
eff1a59c	131
7cb77072	132	return 0;
eff1a59c MW	133	}
eff1a59c MW	134
7262d593 CL	135	static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
7262d593 CL	136	int ring_index, struct p54p_desc *ring, u32 ring_limit,
5988f385	137	struct sk_buff **rx_buf, u32 index)
eff1a59c MW	138	{
eff1a59c MW	139	struct p54p_priv *priv = dev->priv;
eb76bf29	140	struct p54p_ring_control *ring_control = priv->ring_control;
7262d593	141	u32 limit, idx, i;
eff1a59c	142
7262d593 CL	143	idx = le32_to_cpu(ring_control->host_idx[ring_index]);
7262d593 CL	144	limit = idx;
103823db	145	limit -= index;
7262d593	146	limit = ring_limit - limit;
eff1a59c	147
7262d593	148	i = idx % ring_limit;
eff1a59c	149	while (limit-- > 1) {
7262d593	150	struct p54p_desc *desc = &ring[i];
eff1a59c MW	151
	152	if (!desc->host_addr) {
	153	struct sk_buff *skb;
	154	dma_addr_t mapping;
4e416a6f	155	skb = dev_alloc_skb(priv->common.rx_mtu + 32);
eff1a59c MW	156	if (!skb)
	157	break;
	158
	159	mapping = pci_map_single(priv->pdev,
	160	skb_tail_pointer(skb),
4e416a6f	161	priv->common.rx_mtu + 32,
eff1a59c	162	PCI_DMA_FROMDEVICE);
288c8ce8 CL	163
	164	if (pci_dma_mapping_error(priv->pdev, mapping)) {
	165	dev_kfree_skb_any(skb);
	166	dev_err(&priv->pdev->dev,
	167	"RX DMA Mapping error\n");
	168	break;
	169	}
	170
eff1a59c MW	171	desc->host_addr = cpu_to_le32(mapping);
eff1a59c MW	172	desc->device_addr = 0; // FIXME: necessary?
4e416a6f	173	desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
eff1a59c	174	desc->flags = 0;
7262d593	175	rx_buf[i] = skb;
eff1a59c MW	176	}
eff1a59c MW	177
7262d593	178	i++;
eff1a59c	179	idx++;
7262d593	180	i %= ring_limit;
eff1a59c MW	181	}
	182
	183	wmb();
7262d593 CL	184	ring_control->host_idx[ring_index] = cpu_to_le32(idx);
	185	}
	186
	187	static void p54p_check_rx_ring(struct ieee80211_hw dev, u32 index,
	188	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	189	struct sk_buff **rx_buf)
	190	{
	191	struct p54p_priv *priv = dev->priv;
	192	struct p54p_ring_control *ring_control = priv->ring_control;
	193	struct p54p_desc *desc;
	194	u32 idx, i;
	195
	196	i = (*index) % ring_limit;
	197	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
	198	idx %= ring_limit;
	199	while (i != idx) {
	200	u16 len;
	201	struct sk_buff *skb;
	202	desc = &ring[i];
	203	len = le16_to_cpu(desc->len);
	204	skb = rx_buf[i];
	205
0c25970d CL	206	if (!skb) {
	207	i++;
	208	i %= ring_limit;
7262d593	209	continue;
0c25970d	210	}
f5300e04 CL	211
	212	if (unlikely(len > priv->common.rx_mtu)) {
	213	if (net_ratelimit())
	214	dev_err(&priv->pdev->dev, "rx'd frame size "
	215	"exceeds length threshold.\n");
	216
	217	len = priv->common.rx_mtu;
	218	}
7262d593 CL	219	skb_put(skb, len);
	220
	221	if (p54_rx(dev, skb)) {
	222	pci_unmap_single(priv->pdev,
	223	le32_to_cpu(desc->host_addr),
4e416a6f CL	224	priv->common.rx_mtu + 32,
4e416a6f CL	225	PCI_DMA_FROMDEVICE);
7262d593 CL	226	rx_buf[i] = NULL;
	227	desc->host_addr = 0;
	228	} else {
	229	skb_trim(skb, 0);
4e416a6f	230	desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
7262d593 CL	231	}
	232
	233	i++;
	234	i %= ring_limit;
	235	}
	236
5988f385	237	p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
7262d593 CL	238	}
7262d593 CL	239
7262d593 CL	240	static void p54p_check_tx_ring(struct ieee80211_hw dev, u32 index,
7262d593 CL	241	int ring_index, struct p54p_desc *ring, u32 ring_limit,
d713804c	242	struct sk_buff **tx_buf)
7262d593 CL	243	{
	244	struct p54p_priv *priv = dev->priv;
	245	struct p54p_ring_control *ring_control = priv->ring_control;
	246	struct p54p_desc *desc;
d713804c	247	struct sk_buff *skb;
7262d593 CL	248	u32 idx, i;
	249
	250	i = (*index) % ring_limit;
0250ecec	251	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
7262d593 CL	252	idx %= ring_limit;
	253
	254	while (i != idx) {
	255	desc = &ring[i];
d713804c CL	256
d713804c CL	257	skb = tx_buf[i];
7262d593 CL	258	tx_buf[i] = NULL;
	259
	260	pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
	261	le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
	262
	263	desc->host_addr = 0;
	264	desc->device_addr = 0;
	265	desc->len = 0;
	266	desc->flags = 0;
	267
b92f7d30	268	if (skb && FREE_AFTER_TX(skb))
d713804c	269	p54_free_skb(dev, skb);
d713804c	270
7262d593 CL	271	i++;
	272	i %= ring_limit;
	273	}
	274	}
	275
d713804c	276	static void p54p_tasklet(unsigned long dev_id)
7262d593 CL	277	{
	278	struct ieee80211_hw dev = (struct ieee80211_hw )dev_id;
	279	struct p54p_priv *priv = dev->priv;
	280	struct p54p_ring_control *ring_control = priv->ring_control;
	281
d4cde88c HG	282	p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
	283	ARRAY_SIZE(ring_control->tx_mgmt),
	284	priv->tx_buf_mgmt);
	285
	286	p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
	287	ARRAY_SIZE(ring_control->tx_data),
	288	priv->tx_buf_data);
	289
7262d593 CL	290	p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
	291	ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
	292
	293	p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
	294	ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
	295
	296	wmb();
	297	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
eff1a59c MW	298	}
	299
	300	static irqreturn_t p54p_interrupt(int irq, void *dev_id)
	301	{
	302	struct ieee80211_hw *dev = dev_id;
	303	struct p54p_priv *priv = dev->priv;
	304	__le32 reg;
	305
eff1a59c	306	reg = P54P_READ(int_ident);
8160c031	307	if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
d713804c	308	goto out;
eff1a59c	309	}
eff1a59c MW	310	P54P_WRITE(int_ack, reg);
	311
	312	reg &= P54P_READ(int_enable);
	313
d713804c CL	314	if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
	315	tasklet_schedule(&priv->tasklet);
	316	else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
eff1a59c MW	317	complete(&priv->boot_comp);
eff1a59c MW	318
d713804c	319	out:
eff1a59c MW	320	return reg ? IRQ_HANDLED : IRQ_NONE;
	321	}
	322
0a5ec96a	323	static void p54p_tx(struct ieee80211_hw dev, struct sk_buff skb)
eff1a59c	324	{
b92f7d30	325	unsigned long flags;
eff1a59c	326	struct p54p_priv *priv = dev->priv;
eb76bf29	327	struct p54p_ring_control *ring_control = priv->ring_control;
eff1a59c MW	328	struct p54p_desc *desc;
	329	dma_addr_t mapping;
	330	u32 device_idx, idx, i;
	331
	332	spin_lock_irqsave(&priv->lock, flags);
eb76bf29 DT	333	device_idx = le32_to_cpu(ring_control->device_idx[1]);
	334	idx = le32_to_cpu(ring_control->host_idx[1]);
	335	i = idx % ARRAY_SIZE(ring_control->tx_data);
eff1a59c	336
b92f30d6 CL	337	mapping = pci_map_single(priv->pdev, skb->data, skb->len,
b92f30d6 CL	338	PCI_DMA_TODEVICE);
288c8ce8 CL	339	if (pci_dma_mapping_error(priv->pdev, mapping)) {
	340	spin_unlock_irqrestore(&priv->lock, flags);
	341	p54_free_skb(dev, skb);
	342	dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
	343	return ;
	344	}
	345	priv->tx_buf_data[i] = skb;
	346
eb76bf29	347	desc = &ring_control->tx_data[i];
eff1a59c	348	desc->host_addr = cpu_to_le32(mapping);
27df605e	349	desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
b92f30d6	350	desc->len = cpu_to_le16(skb->len);
eff1a59c MW	351	desc->flags = 0;
	352
	353	wmb();
eb76bf29	354	ring_control->host_idx[1] = cpu_to_le32(idx + 1);
eff1a59c MW	355	spin_unlock_irqrestore(&priv->lock, flags);
	356
	357	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	358	P54P_READ(dev_int);
eff1a59c MW	359	}
eff1a59c MW	360
eff1a59c MW	361	static void p54p_stop(struct ieee80211_hw *dev)
	362	{
	363	struct p54p_priv *priv = dev->priv;
eb76bf29	364	struct p54p_ring_control *ring_control = priv->ring_control;
eff1a59c MW	365	unsigned int i;
	366	struct p54p_desc *desc;
	367
8160c031	368	P54P_WRITE(int_enable, cpu_to_le32(0));
eff1a59c MW	369	P54P_READ(int_enable);
	370	udelay(10);
	371
	372	free_irq(priv->pdev->irq, dev);
	373
b92f7d30 CL	374	tasklet_kill(&priv->tasklet);
b92f7d30 CL	375
eff1a59c MW	376	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
eff1a59c MW	377
7262d593	378	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
eb76bf29	379	desc = &ring_control->rx_data[i];
eff1a59c	380	if (desc->host_addr)
7262d593 CL	381	pci_unmap_single(priv->pdev,
7262d593 CL	382	le32_to_cpu(desc->host_addr),
4e416a6f CL	383	priv->common.rx_mtu + 32,
4e416a6f CL	384	PCI_DMA_FROMDEVICE);
7262d593 CL	385	kfree_skb(priv->rx_buf_data[i]);
7262d593 CL	386	priv->rx_buf_data[i] = NULL;
eff1a59c MW	387	}
eff1a59c MW	388
7262d593 CL	389	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
	390	desc = &ring_control->rx_mgmt[i];
	391	if (desc->host_addr)
	392	pci_unmap_single(priv->pdev,
	393	le32_to_cpu(desc->host_addr),
4e416a6f CL	394	priv->common.rx_mtu + 32,
4e416a6f CL	395	PCI_DMA_FROMDEVICE);
7262d593 CL	396	kfree_skb(priv->rx_buf_mgmt[i]);
	397	priv->rx_buf_mgmt[i] = NULL;
	398	}
	399
	400	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
eb76bf29	401	desc = &ring_control->tx_data[i];
eff1a59c	402	if (desc->host_addr)
7262d593 CL	403	pci_unmap_single(priv->pdev,
	404	le32_to_cpu(desc->host_addr),
	405	le16_to_cpu(desc->len),
	406	PCI_DMA_TODEVICE);
	407
b92f30d6	408	p54_free_skb(dev, priv->tx_buf_data[i]);
7262d593 CL	409	priv->tx_buf_data[i] = NULL;
	410	}
	411
	412	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
	413	desc = &ring_control->tx_mgmt[i];
	414	if (desc->host_addr)
	415	pci_unmap_single(priv->pdev,
	416	le32_to_cpu(desc->host_addr),
	417	le16_to_cpu(desc->len),
	418	PCI_DMA_TODEVICE);
eff1a59c	419
b92f30d6	420	p54_free_skb(dev, priv->tx_buf_mgmt[i]);
7262d593	421	priv->tx_buf_mgmt[i] = NULL;
eff1a59c MW	422	}
eff1a59c MW	423
7262d593	424	memset(ring_control, 0, sizeof(*ring_control));
eff1a59c MW	425	}
eff1a59c MW	426
35961627 CL	427	static int p54p_open(struct ieee80211_hw *dev)
	428	{
	429	struct p54p_priv *priv = dev->priv;
	430	int err;
	431
	432	init_completion(&priv->boot_comp);
8fbd90b0	433	err = request_irq(priv->pdev->irq, p54p_interrupt,
35961627 CL	434	IRQF_SHARED, "p54pci", dev);
35961627 CL	435	if (err) {
ad5e72ee	436	dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
35961627 CL	437	return err;
	438	}
	439
	440	memset(priv->ring_control, 0, sizeof(*priv->ring_control));
	441	err = p54p_upload_firmware(dev);
	442	if (err) {
	443	free_irq(priv->pdev->irq, dev);
	444	return err;
	445	}
	446	priv->rx_idx_data = priv->tx_idx_data = 0;
	447	priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
	448
	449	p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
5988f385	450	ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
35961627 CL	451
35961627 CL	452	p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
5988f385	453	ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
35961627 CL	454
	455	P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
	456	P54P_READ(ring_control_base);
	457	wmb();
	458	udelay(10);
	459
	460	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
	461	P54P_READ(int_enable);
	462	wmb();
	463	udelay(10);
	464
	465	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
	466	P54P_READ(dev_int);
	467
	468	if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
	469	printk(KERN_ERR "%s: Cannot boot firmware!\n",
	470	wiphy_name(dev->wiphy));
	471	p54p_stop(dev);
	472	return -ETIMEDOUT;
	473	}
	474
	475	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
	476	P54P_READ(int_enable);
	477	wmb();
	478	udelay(10);
	479
	480	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	481	P54P_READ(dev_int);
	482	wmb();
	483	udelay(10);
	484
	485	return 0;
	486	}
	487
eff1a59c MW	488	static int __devinit p54p_probe(struct pci_dev *pdev,
	489	const struct pci_device_id *id)
	490	{
	491	struct p54p_priv *priv;
	492	struct ieee80211_hw *dev;
	493	unsigned long mem_addr, mem_len;
	494	int err;
eff1a59c MW	495
	496	err = pci_enable_device(pdev);
	497	if (err) {
ad5e72ee	498	dev_err(&pdev->dev, "Cannot enable new PCI device\n");
eff1a59c MW	499	return err;
	500	}
	501
	502	mem_addr = pci_resource_start(pdev, 0);
	503	mem_len = pci_resource_len(pdev, 0);
	504	if (mem_len < sizeof(struct p54p_csr)) {
ad5e72ee	505	dev_err(&pdev->dev, "Too short PCI resources\n");
40db0b22	506	goto err_disable_dev;
eff1a59c MW	507	}
eff1a59c MW	508
32ddf071	509	err = pci_request_regions(pdev, "p54pci");
eff1a59c	510	if (err) {
ad5e72ee	511	dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
40db0b22	512	goto err_disable_dev;
eff1a59c MW	513	}
eff1a59c MW	514
e930438c YH	515	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) \|\|
e930438c YH	516	pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
ad5e72ee	517	dev_err(&pdev->dev, "No suitable DMA available\n");
eff1a59c MW	518	goto err_free_reg;
	519	}
	520
	521	pci_set_master(pdev);
	522	pci_try_set_mwi(pdev);
	523
	524	pci_write_config_byte(pdev, 0x40, 0);
	525	pci_write_config_byte(pdev, 0x41, 0);
	526
	527	dev = p54_init_common(sizeof(*priv));
	528	if (!dev) {
ad5e72ee	529	dev_err(&pdev->dev, "ieee80211 alloc failed\n");
eff1a59c MW	530	err = -ENOMEM;
	531	goto err_free_reg;
	532	}
	533
	534	priv = dev->priv;
	535	priv->pdev = pdev;
	536
	537	SET_IEEE80211_DEV(dev, &pdev->dev);
	538	pci_set_drvdata(pdev, dev);
	539
	540	priv->map = ioremap(mem_addr, mem_len);
	541	if (!priv->map) {
ad5e72ee CL	542	dev_err(&pdev->dev, "Cannot map device memory\n");
ad5e72ee CL	543	err = -ENOMEM;
eff1a59c MW	544	goto err_free_dev;
	545	}
	546
	547	priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
	548	&priv->ring_control_dma);
	549	if (!priv->ring_control) {
ad5e72ee	550	dev_err(&pdev->dev, "Cannot allocate rings\n");
eff1a59c MW	551	err = -ENOMEM;
	552	goto err_iounmap;
	553	}
eff1a59c MW	554	priv->common.open = p54p_open;
	555	priv->common.stop = p54p_stop;
	556	priv->common.tx = p54p_tx;
	557
	558	spin_lock_init(&priv->lock);
d713804c	559	tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
eff1a59c	560
40db0b22 CL	561	err = request_firmware(&priv->firmware, "isl3886pci",
	562	&priv->pdev->dev);
	563	if (err) {
ad5e72ee	564	dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
40db0b22 CL	565	err = request_firmware(&priv->firmware, "isl3886",
	566	&priv->pdev->dev);
	567	if (err)
	568	goto err_free_common;
	569	}
	570
35961627 CL	571	err = p54p_open(dev);
	572	if (err)
	573	goto err_free_common;
7cb77072 CL	574	err = p54_read_eeprom(dev);
	575	p54p_stop(dev);
	576	if (err)
35961627	577	goto err_free_common;
7cb77072	578
2ac71072 CL	579	err = p54_register_common(dev, &pdev->dev);
2ac71072 CL	580	if (err)
eff1a59c	581	goto err_free_common;
eff1a59c	582
eff1a59c MW	583	return 0;
	584
	585	err_free_common:
40db0b22	586	release_firmware(priv->firmware);
eff1a59c MW	587	pci_free_consistent(pdev, sizeof(*priv->ring_control),
	588	priv->ring_control, priv->ring_control_dma);
	589
	590	err_iounmap:
	591	iounmap(priv->map);
	592
	593	err_free_dev:
	594	pci_set_drvdata(pdev, NULL);
d8c92107	595	p54_free_common(dev);
eff1a59c MW	596
	597	err_free_reg:
	598	pci_release_regions(pdev);
40db0b22	599	err_disable_dev:
eff1a59c MW	600	pci_disable_device(pdev);
	601	return err;
	602	}
	603
	604	static void __devexit p54p_remove(struct pci_dev *pdev)
	605	{
	606	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	607	struct p54p_priv *priv;
	608
	609	if (!dev)
	610	return;
	611
d8c92107	612	p54_unregister_common(dev);
eff1a59c	613	priv = dev->priv;
40db0b22	614	release_firmware(priv->firmware);
eff1a59c MW	615	pci_free_consistent(pdev, sizeof(*priv->ring_control),
eff1a59c MW	616	priv->ring_control, priv->ring_control_dma);
eff1a59c MW	617	iounmap(priv->map);
	618	pci_release_regions(pdev);
	619	pci_disable_device(pdev);
d8c92107	620	p54_free_common(dev);
eff1a59c MW	621	}
	622
	623	#ifdef CONFIG_PM
	624	static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
	625	{
	626	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	627	struct p54p_priv *priv = dev->priv;
	628
05c914fe	629	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
eff1a59c MW	630	ieee80211_stop_queues(dev);
	631	p54p_stop(dev);
	632	}
	633
	634	pci_save_state(pdev);
	635	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	636	return 0;
	637	}
	638
	639	static int p54p_resume(struct pci_dev *pdev)
	640	{
	641	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	642	struct p54p_priv *priv = dev->priv;
	643
	644	pci_set_power_state(pdev, PCI_D0);
	645	pci_restore_state(pdev);
	646
05c914fe	647	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
eff1a59c	648	p54p_open(dev);
36d6825b	649	ieee80211_wake_queues(dev);
eff1a59c MW	650	}
	651
	652	return 0;
	653	}
	654	#endif /* CONFIG_PM */
	655
	656	static struct pci_driver p54p_driver = {
32ddf071	657	.name = "p54pci",
eff1a59c MW	658	.id_table = p54p_table,
	659	.probe = p54p_probe,
	660	.remove = __devexit_p(p54p_remove),
	661	#ifdef CONFIG_PM
	662	.suspend = p54p_suspend,
	663	.resume = p54p_resume,
	664	#endif /* CONFIG_PM */
	665	};
	666
	667	static int __init p54p_init(void)
	668	{
	669	return pci_register_driver(&p54p_driver);
	670	}
	671
	672	static void __exit p54p_exit(void)
	673	{
	674	pci_unregister_driver(&p54p_driver);
	675	}
	676
	677	module_init(p54p_init);
	678	module_exit(p54p_exit);