[net-next-2.6.git] / drivers / net / wireless / p54 / p54pci.c


/*
 * Linux device driver for PCI based Prism54
 *
 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
 * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
 *
 * Based on the islsm (softmac prism54) driver, which is:
 * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/firmware.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/completion.h>
#include <net/mac80211.h>

#include "p54.h"
#include "lmac.h"
#include "p54pci.h"

MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
MODULE_DESCRIPTION("Prism54 PCI wireless driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("prism54pci");
MODULE_FIRMWARE("isl3886pci");

static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
	/* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3890) },
	/* 3COM 3CRWE154G72 Wireless LAN adapter */
	{ PCI_DEVICE(0x10b7, 0x6001) },
	/* Intersil PRISM Indigo Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3877) },
	/* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3886) },
	{ },
};

MODULE_DEVICE_TABLE(pci, p54p_table);

static int p54p_upload_firmware(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	__le32 reg;
	int err;
	__le32 *data;
	u32 remains, left, device_addr;

	P54P_WRITE(int_enable, cpu_to_le32(0));
	P54P_READ(int_enable);
	udelay(10);

	reg = P54P_READ(ctrl_stat);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
	P54P_WRITE(ctrl_stat, reg);
	P54P_READ(ctrl_stat);
	udelay(10);

	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();

	/* wait for the firmware to reset properly */
	mdelay(10);

	err = p54_parse_firmware(dev, priv->firmware);
	if (err)
		return err;

	if (priv->common.fw_interface != FW_LM86) {
		dev_err(&priv->pdev->dev, "wrong firmware, "
			"please get a LM86(PCI) firmware a try again.\n");
		return -EINVAL;
	}

	data = (__le32 *) priv->firmware->data;
	remains = priv->firmware->size;
	device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
	while (remains) {
		u32 i = 0;
		left = min((u32)0x1000, remains);
		P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
		P54P_READ(int_enable);

		device_addr += 0x1000;
		while (i < left) {
			P54P_WRITE(direct_mem_win[i], *data++);
			i += sizeof(u32);
		}

		remains -= left;
		P54P_READ(int_enable);
	}

	reg = P54P_READ(ctrl_stat);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
	P54P_WRITE(ctrl_stat, reg);
	P54P_READ(ctrl_stat);
	udelay(10);

	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	/* wait for the firmware to boot properly */
	mdelay(100);

	return 0;
}

static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	struct sk_buff **rx_buf, u32 index)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	u32 limit, idx, i;

	idx = le32_to_cpu(ring_control->host_idx[ring_index]);
	limit = idx;
	limit -= index;
	limit = ring_limit - limit;

	i = idx % ring_limit;
	while (limit-- > 1) {
		struct p54p_desc *desc = &ring[i];

		if (!desc->host_addr) {
			struct sk_buff *skb;
			dma_addr_t mapping;
			skb = dev_alloc_skb(priv->common.rx_mtu + 32);
			if (!skb)
				break;

			mapping = pci_map_single(priv->pdev,
						 skb_tail_pointer(skb),
						 priv->common.rx_mtu + 32,
						 PCI_DMA_FROMDEVICE);

			if (pci_dma_mapping_error(priv->pdev, mapping)) {
				dev_kfree_skb_any(skb);
				dev_err(&priv->pdev->dev,
					"RX DMA Mapping error\n");
				break;
			}

			desc->host_addr = cpu_to_le32(mapping);
			desc->device_addr = 0;	// FIXME: necessary?
			desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
			desc->flags = 0;
			rx_buf[i] = skb;
		}

		i++;
		idx++;
		i %= ring_limit;
	}

	wmb();
	ring_control->host_idx[ring_index] = cpu_to_le32(idx);
}

static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	struct sk_buff **rx_buf)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	struct p54p_desc *desc;
	u32 idx, i;

	i = (*index) % ring_limit;
	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
	idx %= ring_limit;
	while (i != idx) {
		u16 len;
		struct sk_buff *skb;
		desc = &ring[i];
		len = le16_to_cpu(desc->len);
		skb = rx_buf[i];

		if (!skb) {
			i++;
			i %= ring_limit;
			continue;
		}

		if (unlikely(len > priv->common.rx_mtu)) {
			if (net_ratelimit())
				dev_err(&priv->pdev->dev, "rx'd frame size "
					"exceeds length threshold.\n");

			len = priv->common.rx_mtu;
		}
		skb_put(skb, len);

		if (p54_rx(dev, skb)) {
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 priv->common.rx_mtu + 32,
					 PCI_DMA_FROMDEVICE);
			rx_buf[i] = NULL;
			desc->host_addr = 0;
		} else {
			skb_trim(skb, 0);
			desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
		}

		i++;
		i %= ring_limit;
	}

	p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
}

static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	struct sk_buff **tx_buf)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	struct p54p_desc *desc;
	struct sk_buff *skb;
	u32 idx, i;

	i = (*index) % ring_limit;
	(*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
	idx %= ring_limit;

	while (i != idx) {
		desc = &ring[i];

		skb = tx_buf[i];
		tx_buf[i] = NULL;

		pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
				 le16_to_cpu(desc->len), PCI_DMA_TODEVICE);

		desc->host_addr = 0;
		desc->device_addr = 0;
		desc->len = 0;
		desc->flags = 0;

		if (skb && FREE_AFTER_TX(skb))
			p54_free_skb(dev, skb);

		i++;
		i %= ring_limit;
	}
}

static void p54p_tasklet(unsigned long dev_id)
{
	struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;

	p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
		ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);

	p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
		ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);

	wmb();
	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));

	p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
			   ARRAY_SIZE(ring_control->tx_mgmt),
			   priv->tx_buf_mgmt);

	p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
			   ARRAY_SIZE(ring_control->tx_data),
			   priv->tx_buf_data);
}

static irqreturn_t p54p_interrupt(int irq, void *dev_id)
{
	struct ieee80211_hw *dev = dev_id;
	struct p54p_priv *priv = dev->priv;
	__le32 reg;

	reg = P54P_READ(int_ident);
	if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
		goto out;
	}
	P54P_WRITE(int_ack, reg);

	reg &= P54P_READ(int_enable);

	if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
		tasklet_schedule(&priv->tasklet);
	else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
		complete(&priv->boot_comp);

out:
	return reg ? IRQ_HANDLED : IRQ_NONE;
}

static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
{
	unsigned long flags;
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	struct p54p_desc *desc;
	dma_addr_t mapping;
	u32 device_idx, idx, i;

	spin_lock_irqsave(&priv->lock, flags);
	device_idx = le32_to_cpu(ring_control->device_idx[1]);
	idx = le32_to_cpu(ring_control->host_idx[1]);
	i = idx % ARRAY_SIZE(ring_control->tx_data);

	mapping = pci_map_single(priv->pdev, skb->data, skb->len,
				 PCI_DMA_TODEVICE);
	if (pci_dma_mapping_error(priv->pdev, mapping)) {
		spin_unlock_irqrestore(&priv->lock, flags);
		p54_free_skb(dev, skb);
		dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
		return ;
	}
	priv->tx_buf_data[i] = skb;

	desc = &ring_control->tx_data[i];
	desc->host_addr = cpu_to_le32(mapping);
	desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
	desc->len = cpu_to_le16(skb->len);
	desc->flags = 0;

	wmb();
	ring_control->host_idx[1] = cpu_to_le32(idx + 1);
	spin_unlock_irqrestore(&priv->lock, flags);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	P54P_READ(dev_int);
}

static void p54p_stop(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	unsigned int i;
	struct p54p_desc *desc;

	P54P_WRITE(int_enable, cpu_to_le32(0));
	P54P_READ(int_enable);
	udelay(10);

	free_irq(priv->pdev->irq, dev);

	tasklet_kill(&priv->tasklet);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));

	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
		desc = &ring_control->rx_data[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 priv->common.rx_mtu + 32,
					 PCI_DMA_FROMDEVICE);
		kfree_skb(priv->rx_buf_data[i]);
		priv->rx_buf_data[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
		desc = &ring_control->rx_mgmt[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 priv->common.rx_mtu + 32,
					 PCI_DMA_FROMDEVICE);
		kfree_skb(priv->rx_buf_mgmt[i]);
		priv->rx_buf_mgmt[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
		desc = &ring_control->tx_data[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 le16_to_cpu(desc->len),
					 PCI_DMA_TODEVICE);

		p54_free_skb(dev, priv->tx_buf_data[i]);
		priv->tx_buf_data[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
		desc = &ring_control->tx_mgmt[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 le16_to_cpu(desc->len),
					 PCI_DMA_TODEVICE);

		p54_free_skb(dev, priv->tx_buf_mgmt[i]);
		priv->tx_buf_mgmt[i] = NULL;
	}

	memset(ring_control, 0, sizeof(*ring_control));
}

static int p54p_open(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	int err;

	init_completion(&priv->boot_comp);
	err = request_irq(priv->pdev->irq, p54p_interrupt,
			  IRQF_SHARED, "p54pci", dev);
	if (err) {
		dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
		return err;
	}

	memset(priv->ring_control, 0, sizeof(*priv->ring_control));
	err = p54p_upload_firmware(dev);
	if (err) {
		free_irq(priv->pdev->irq, dev);
		return err;
	}
	priv->rx_idx_data = priv->tx_idx_data = 0;
	priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;

	p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
		ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);

	p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
		ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);

	P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
	P54P_READ(ring_control_base);
	wmb();
	udelay(10);

	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
	P54P_READ(int_enable);
	wmb();
	udelay(10);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
	P54P_READ(dev_int);

	if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
		printk(KERN_ERR "%s: Cannot boot firmware!\n",
		       wiphy_name(dev->wiphy));
		p54p_stop(dev);
		return -ETIMEDOUT;
	}

	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
	P54P_READ(int_enable);
	wmb();
	udelay(10);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	P54P_READ(dev_int);
	wmb();
	udelay(10);

	return 0;
}

static int __devinit p54p_probe(struct pci_dev *pdev,
				const struct pci_device_id *id)
{
	struct p54p_priv *priv;
	struct ieee80211_hw *dev;
	unsigned long mem_addr, mem_len;
	int err;

	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "Cannot enable new PCI device\n");
		return err;
	}

	mem_addr = pci_resource_start(pdev, 0);
	mem_len = pci_resource_len(pdev, 0);
	if (mem_len < sizeof(struct p54p_csr)) {
		dev_err(&pdev->dev, "Too short PCI resources\n");
		goto err_disable_dev;
	}

	err = pci_request_regions(pdev, "p54pci");
	if (err) {
		dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
		goto err_disable_dev;
	}

	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
	    pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
		dev_err(&pdev->dev, "No suitable DMA available\n");
		goto err_free_reg;
	}

	pci_set_master(pdev);
	pci_try_set_mwi(pdev);

	pci_write_config_byte(pdev, 0x40, 0);
	pci_write_config_byte(pdev, 0x41, 0);

	dev = p54_init_common(sizeof(*priv));
	if (!dev) {
		dev_err(&pdev->dev, "ieee80211 alloc failed\n");
		err = -ENOMEM;
		goto err_free_reg;
	}

	priv = dev->priv;
	priv->pdev = pdev;

	SET_IEEE80211_DEV(dev, &pdev->dev);
	pci_set_drvdata(pdev, dev);

	priv->map = ioremap(mem_addr, mem_len);
	if (!priv->map) {
		dev_err(&pdev->dev, "Cannot map device memory\n");
		err = -ENOMEM;
		goto err_free_dev;
	}

	priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
						  &priv->ring_control_dma);
	if (!priv->ring_control) {
		dev_err(&pdev->dev, "Cannot allocate rings\n");
		err = -ENOMEM;
		goto err_iounmap;
	}
	priv->common.open = p54p_open;
	priv->common.stop = p54p_stop;
	priv->common.tx = p54p_tx;

	spin_lock_init(&priv->lock);
	tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);

	err = request_firmware(&priv->firmware, "isl3886pci",
			       &priv->pdev->dev);
	if (err) {
		dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
		err = request_firmware(&priv->firmware, "isl3886",
				       &priv->pdev->dev);
		if (err)
			goto err_free_common;
	}

	err = p54p_open(dev);
	if (err)
		goto err_free_common;
	err = p54_read_eeprom(dev);
	p54p_stop(dev);
	if (err)
		goto err_free_common;

	err = p54_register_common(dev, &pdev->dev);
	if (err)
		goto err_free_common;

	return 0;

 err_free_common:
	release_firmware(priv->firmware);
	pci_free_consistent(pdev, sizeof(*priv->ring_control),
			    priv->ring_control, priv->ring_control_dma);

 err_iounmap:
	iounmap(priv->map);

 err_free_dev:
	pci_set_drvdata(pdev, NULL);
	p54_free_common(dev);

 err_free_reg:
	pci_release_regions(pdev);
 err_disable_dev:
	pci_disable_device(pdev);
	return err;
}

static void __devexit p54p_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv;

	if (!dev)
		return;

	p54_unregister_common(dev);
	priv = dev->priv;
	release_firmware(priv->firmware);
	pci_free_consistent(pdev, sizeof(*priv->ring_control),
			    priv->ring_control, priv->ring_control_dma);
	iounmap(priv->map);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	p54_free_common(dev);
}

#ifdef CONFIG_PM
static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv = dev->priv;

	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
		ieee80211_stop_queues(dev);
		p54p_stop(dev);
	}

	pci_save_state(pdev);
	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	return 0;
}

static int p54p_resume(struct pci_dev *pdev)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv = dev->priv;

	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);

	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
		p54p_open(dev);
		ieee80211_wake_queues(dev);
	}

	return 0;
}
#endif /* CONFIG_PM */

static struct pci_driver p54p_driver = {
	.name		= "p54pci",
	.id_table	= p54p_table,
	.probe		= p54p_probe,
	.remove		= __devexit_p(p54p_remove),
#ifdef CONFIG_PM
	.suspend	= p54p_suspend,
	.resume		= p54p_resume,
#endif /* CONFIG_PM */
};

static int __init p54p_init(void)
{
	return pci_register_driver(&p54p_driver);
}

static void __exit p54p_exit(void)
{
	pci_unregister_driver(&p54p_driver);
}

module_init(p54p_init);
module_exit(p54p_exit);
Commit	Line	Data
eff1a59c MW	1
	2	/*
	3	* Linux device driver for PCI based Prism54
	4	*
	5	* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
7262d593	6	* Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
eff1a59c MW	7	*
	8	* Based on the islsm (softmac prism54) driver, which is:
	9	* Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/pci.h>
	18	#include <linux/firmware.h>
	19	#include <linux/etherdevice.h>
	20	#include <linux/delay.h>
	21	#include <linux/completion.h>
	22	#include <net/mac80211.h>
	23
	24	#include "p54.h"
d8c92107	25	#include "lmac.h"
eff1a59c MW	26	#include "p54pci.h"
	27
	28	MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
	29	MODULE_DESCRIPTION("Prism54 PCI wireless driver");
	30	MODULE_LICENSE("GPL");
	31	MODULE_ALIAS("prism54pci");
9a8675d7	32	MODULE_FIRMWARE("isl3886pci");
eff1a59c	33
a3aa1884	34	static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
eff1a59c MW	35	/* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
	36	{ PCI_DEVICE(0x1260, 0x3890) },
	37	/* 3COM 3CRWE154G72 Wireless LAN adapter */
	38	{ PCI_DEVICE(0x10b7, 0x6001) },
	39	/* Intersil PRISM Indigo Wireless LAN adapter */
	40	{ PCI_DEVICE(0x1260, 0x3877) },
	41	/* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
	42	{ PCI_DEVICE(0x1260, 0x3886) },
90f4dd0f	43	{ },
eff1a59c MW	44	};
	45
	46	MODULE_DEVICE_TABLE(pci, p54p_table);
	47
	48	static int p54p_upload_firmware(struct ieee80211_hw *dev)
	49	{
	50	struct p54p_priv *priv = dev->priv;
eff1a59c MW	51	__le32 reg;
eff1a59c MW	52	int err;
8160c031	53	__le32 *data;
eff1a59c MW	54	u32 remains, left, device_addr;
eff1a59c MW	55
8160c031	56	P54P_WRITE(int_enable, cpu_to_le32(0));
eff1a59c MW	57	P54P_READ(int_enable);
	58	udelay(10);
	59
	60	reg = P54P_READ(ctrl_stat);
	61	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	62	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
	63	P54P_WRITE(ctrl_stat, reg);
	64	P54P_READ(ctrl_stat);
	65	udelay(10);
	66
	67	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	68	P54P_WRITE(ctrl_stat, reg);
	69	wmb();
	70	udelay(10);
	71
	72	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	73	P54P_WRITE(ctrl_stat, reg);
	74	wmb();
	75
40db0b22 CL	76	/* wait for the firmware to reset properly */
40db0b22 CL	77	mdelay(10);
eff1a59c	78
40db0b22 CL	79	err = p54_parse_firmware(dev, priv->firmware);
40db0b22 CL	80	if (err)
4e416a6f	81	return err;
eff1a59c	82
e365f160 CL	83	if (priv->common.fw_interface != FW_LM86) {
	84	dev_err(&priv->pdev->dev, "wrong firmware, "
	85	"please get a LM86(PCI) firmware a try again.\n");
	86	return -EINVAL;
	87	}
	88
40db0b22 CL	89	data = (__le32 *) priv->firmware->data;
40db0b22 CL	90	remains = priv->firmware->size;
eff1a59c MW	91	device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
	92	while (remains) {
	93	u32 i = 0;
	94	left = min((u32)0x1000, remains);
	95	P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
	96	P54P_READ(int_enable);
	97
	98	device_addr += 0x1000;
	99	while (i < left) {
	100	P54P_WRITE(direct_mem_win[i], *data++);
	101	i += sizeof(u32);
	102	}
	103
	104	remains -= left;
	105	P54P_READ(int_enable);
	106	}
	107
eff1a59c MW	108	reg = P54P_READ(ctrl_stat);
	109	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
	110	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	111	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
	112	P54P_WRITE(ctrl_stat, reg);
	113	P54P_READ(ctrl_stat);
	114	udelay(10);
	115
	116	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	117	P54P_WRITE(ctrl_stat, reg);
	118	wmb();
	119	udelay(10);
	120
	121	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	122	P54P_WRITE(ctrl_stat, reg);
	123	wmb();
	124	udelay(10);
	125
7cb77072	126	/* wait for the firmware to boot properly */
eff1a59c	127	mdelay(100);
eff1a59c	128
7cb77072	129	return 0;
eff1a59c MW	130	}
eff1a59c MW	131
7262d593 CL	132	static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
7262d593 CL	133	int ring_index, struct p54p_desc *ring, u32 ring_limit,
5988f385	134	struct sk_buff **rx_buf, u32 index)
eff1a59c MW	135	{
eff1a59c MW	136	struct p54p_priv *priv = dev->priv;
eb76bf29	137	struct p54p_ring_control *ring_control = priv->ring_control;
7262d593	138	u32 limit, idx, i;
eff1a59c	139
7262d593 CL	140	idx = le32_to_cpu(ring_control->host_idx[ring_index]);
7262d593 CL	141	limit = idx;
103823db	142	limit -= index;
7262d593	143	limit = ring_limit - limit;
eff1a59c	144
7262d593	145	i = idx % ring_limit;
eff1a59c	146	while (limit-- > 1) {
7262d593	147	struct p54p_desc *desc = &ring[i];
eff1a59c MW	148
	149	if (!desc->host_addr) {
	150	struct sk_buff *skb;
	151	dma_addr_t mapping;
4e416a6f	152	skb = dev_alloc_skb(priv->common.rx_mtu + 32);
eff1a59c MW	153	if (!skb)
	154	break;
	155
	156	mapping = pci_map_single(priv->pdev,
	157	skb_tail_pointer(skb),
4e416a6f	158	priv->common.rx_mtu + 32,
eff1a59c	159	PCI_DMA_FROMDEVICE);
288c8ce8 CL	160
	161	if (pci_dma_mapping_error(priv->pdev, mapping)) {
	162	dev_kfree_skb_any(skb);
	163	dev_err(&priv->pdev->dev,
	164	"RX DMA Mapping error\n");
	165	break;
	166	}
	167
eff1a59c MW	168	desc->host_addr = cpu_to_le32(mapping);
eff1a59c MW	169	desc->device_addr = 0; // FIXME: necessary?
4e416a6f	170	desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
eff1a59c	171	desc->flags = 0;
7262d593	172	rx_buf[i] = skb;
eff1a59c MW	173	}
eff1a59c MW	174
7262d593	175	i++;
eff1a59c	176	idx++;
7262d593	177	i %= ring_limit;
eff1a59c MW	178	}
	179
	180	wmb();
7262d593 CL	181	ring_control->host_idx[ring_index] = cpu_to_le32(idx);
	182	}
	183
	184	static void p54p_check_rx_ring(struct ieee80211_hw dev, u32 index,
	185	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	186	struct sk_buff **rx_buf)
	187	{
	188	struct p54p_priv *priv = dev->priv;
	189	struct p54p_ring_control *ring_control = priv->ring_control;
	190	struct p54p_desc *desc;
	191	u32 idx, i;
	192
	193	i = (*index) % ring_limit;
	194	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
	195	idx %= ring_limit;
	196	while (i != idx) {
	197	u16 len;
	198	struct sk_buff *skb;
	199	desc = &ring[i];
	200	len = le16_to_cpu(desc->len);
	201	skb = rx_buf[i];
	202
0c25970d CL	203	if (!skb) {
	204	i++;
	205	i %= ring_limit;
7262d593	206	continue;
0c25970d	207	}
f5300e04 CL	208
	209	if (unlikely(len > priv->common.rx_mtu)) {
	210	if (net_ratelimit())
	211	dev_err(&priv->pdev->dev, "rx'd frame size "
	212	"exceeds length threshold.\n");
	213
	214	len = priv->common.rx_mtu;
	215	}
7262d593 CL	216	skb_put(skb, len);
	217
	218	if (p54_rx(dev, skb)) {
	219	pci_unmap_single(priv->pdev,
	220	le32_to_cpu(desc->host_addr),
4e416a6f CL	221	priv->common.rx_mtu + 32,
4e416a6f CL	222	PCI_DMA_FROMDEVICE);
7262d593 CL	223	rx_buf[i] = NULL;
	224	desc->host_addr = 0;
	225	} else {
	226	skb_trim(skb, 0);
4e416a6f	227	desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
7262d593 CL	228	}
	229
	230	i++;
	231	i %= ring_limit;
	232	}
	233
5988f385	234	p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
7262d593 CL	235	}
7262d593 CL	236
7262d593 CL	237	static void p54p_check_tx_ring(struct ieee80211_hw dev, u32 index,
7262d593 CL	238	int ring_index, struct p54p_desc *ring, u32 ring_limit,
d713804c	239	struct sk_buff **tx_buf)
7262d593 CL	240	{
	241	struct p54p_priv *priv = dev->priv;
	242	struct p54p_ring_control *ring_control = priv->ring_control;
	243	struct p54p_desc *desc;
d713804c	244	struct sk_buff *skb;
7262d593 CL	245	u32 idx, i;
	246
	247	i = (*index) % ring_limit;
	248	(*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
	249	idx %= ring_limit;
	250
	251	while (i != idx) {
	252	desc = &ring[i];
d713804c CL	253
d713804c CL	254	skb = tx_buf[i];
7262d593 CL	255	tx_buf[i] = NULL;
	256
	257	pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
	258	le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
	259
	260	desc->host_addr = 0;
	261	desc->device_addr = 0;
	262	desc->len = 0;
	263	desc->flags = 0;
	264
b92f7d30	265	if (skb && FREE_AFTER_TX(skb))
d713804c	266	p54_free_skb(dev, skb);
d713804c	267
7262d593 CL	268	i++;
	269	i %= ring_limit;
	270	}
	271	}
	272
d713804c	273	static void p54p_tasklet(unsigned long dev_id)
7262d593 CL	274	{
	275	struct ieee80211_hw dev = (struct ieee80211_hw )dev_id;
	276	struct p54p_priv *priv = dev->priv;
	277	struct p54p_ring_control *ring_control = priv->ring_control;
	278
	279	p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
	280	ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
	281
	282	p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
	283	ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
	284
	285	wmb();
	286	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
5988f385 QP	287
	288	p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
	289	ARRAY_SIZE(ring_control->tx_mgmt),
	290	priv->tx_buf_mgmt);
	291
	292	p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
	293	ARRAY_SIZE(ring_control->tx_data),
	294	priv->tx_buf_data);
eff1a59c MW	295	}
	296
	297	static irqreturn_t p54p_interrupt(int irq, void *dev_id)
	298	{
	299	struct ieee80211_hw *dev = dev_id;
	300	struct p54p_priv *priv = dev->priv;
	301	__le32 reg;
	302
eff1a59c	303	reg = P54P_READ(int_ident);
8160c031	304	if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
d713804c	305	goto out;
eff1a59c	306	}
eff1a59c MW	307	P54P_WRITE(int_ack, reg);
	308
	309	reg &= P54P_READ(int_enable);
	310
d713804c CL	311	if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
	312	tasklet_schedule(&priv->tasklet);
	313	else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
eff1a59c MW	314	complete(&priv->boot_comp);
eff1a59c MW	315
d713804c	316	out:
eff1a59c MW	317	return reg ? IRQ_HANDLED : IRQ_NONE;
	318	}
	319
0a5ec96a	320	static void p54p_tx(struct ieee80211_hw dev, struct sk_buff skb)
eff1a59c	321	{
b92f7d30	322	unsigned long flags;
eff1a59c	323	struct p54p_priv *priv = dev->priv;
eb76bf29	324	struct p54p_ring_control *ring_control = priv->ring_control;
eff1a59c MW	325	struct p54p_desc *desc;
	326	dma_addr_t mapping;
	327	u32 device_idx, idx, i;
	328
	329	spin_lock_irqsave(&priv->lock, flags);
eb76bf29 DT	330	device_idx = le32_to_cpu(ring_control->device_idx[1]);
	331	idx = le32_to_cpu(ring_control->host_idx[1]);
	332	i = idx % ARRAY_SIZE(ring_control->tx_data);
eff1a59c	333
b92f30d6 CL	334	mapping = pci_map_single(priv->pdev, skb->data, skb->len,
b92f30d6 CL	335	PCI_DMA_TODEVICE);
288c8ce8 CL	336	if (pci_dma_mapping_error(priv->pdev, mapping)) {
	337	spin_unlock_irqrestore(&priv->lock, flags);
	338	p54_free_skb(dev, skb);
	339	dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
	340	return ;
	341	}
	342	priv->tx_buf_data[i] = skb;
	343
eb76bf29	344	desc = &ring_control->tx_data[i];
eff1a59c	345	desc->host_addr = cpu_to_le32(mapping);
27df605e	346	desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
b92f30d6	347	desc->len = cpu_to_le16(skb->len);
eff1a59c MW	348	desc->flags = 0;
	349
	350	wmb();
eb76bf29	351	ring_control->host_idx[1] = cpu_to_le32(idx + 1);
eff1a59c MW	352	spin_unlock_irqrestore(&priv->lock, flags);
	353
	354	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	355	P54P_READ(dev_int);
eff1a59c MW	356	}
eff1a59c MW	357
eff1a59c MW	358	static void p54p_stop(struct ieee80211_hw *dev)
	359	{
	360	struct p54p_priv *priv = dev->priv;
eb76bf29	361	struct p54p_ring_control *ring_control = priv->ring_control;
eff1a59c MW	362	unsigned int i;
	363	struct p54p_desc *desc;
	364
8160c031	365	P54P_WRITE(int_enable, cpu_to_le32(0));
eff1a59c MW	366	P54P_READ(int_enable);
	367	udelay(10);
	368
	369	free_irq(priv->pdev->irq, dev);
	370
b92f7d30 CL	371	tasklet_kill(&priv->tasklet);
b92f7d30 CL	372
eff1a59c MW	373	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
eff1a59c MW	374
7262d593	375	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
eb76bf29	376	desc = &ring_control->rx_data[i];
eff1a59c	377	if (desc->host_addr)
7262d593 CL	378	pci_unmap_single(priv->pdev,
7262d593 CL	379	le32_to_cpu(desc->host_addr),
4e416a6f CL	380	priv->common.rx_mtu + 32,
4e416a6f CL	381	PCI_DMA_FROMDEVICE);
7262d593 CL	382	kfree_skb(priv->rx_buf_data[i]);
7262d593 CL	383	priv->rx_buf_data[i] = NULL;
eff1a59c MW	384	}
eff1a59c MW	385
7262d593 CL	386	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
	387	desc = &ring_control->rx_mgmt[i];
	388	if (desc->host_addr)
	389	pci_unmap_single(priv->pdev,
	390	le32_to_cpu(desc->host_addr),
4e416a6f CL	391	priv->common.rx_mtu + 32,
4e416a6f CL	392	PCI_DMA_FROMDEVICE);
7262d593 CL	393	kfree_skb(priv->rx_buf_mgmt[i]);
	394	priv->rx_buf_mgmt[i] = NULL;
	395	}
	396
	397	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
eb76bf29	398	desc = &ring_control->tx_data[i];
eff1a59c	399	if (desc->host_addr)
7262d593 CL	400	pci_unmap_single(priv->pdev,
	401	le32_to_cpu(desc->host_addr),
	402	le16_to_cpu(desc->len),
	403	PCI_DMA_TODEVICE);
	404
b92f30d6	405	p54_free_skb(dev, priv->tx_buf_data[i]);
7262d593 CL	406	priv->tx_buf_data[i] = NULL;
	407	}
	408
	409	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
	410	desc = &ring_control->tx_mgmt[i];
	411	if (desc->host_addr)
	412	pci_unmap_single(priv->pdev,
	413	le32_to_cpu(desc->host_addr),
	414	le16_to_cpu(desc->len),
	415	PCI_DMA_TODEVICE);
eff1a59c	416
b92f30d6	417	p54_free_skb(dev, priv->tx_buf_mgmt[i]);
7262d593	418	priv->tx_buf_mgmt[i] = NULL;
eff1a59c MW	419	}
eff1a59c MW	420
7262d593	421	memset(ring_control, 0, sizeof(*ring_control));
eff1a59c MW	422	}
eff1a59c MW	423
35961627 CL	424	static int p54p_open(struct ieee80211_hw *dev)
	425	{
	426	struct p54p_priv *priv = dev->priv;
	427	int err;
	428
	429	init_completion(&priv->boot_comp);
8fbd90b0	430	err = request_irq(priv->pdev->irq, p54p_interrupt,
35961627 CL	431	IRQF_SHARED, "p54pci", dev);
35961627 CL	432	if (err) {
ad5e72ee	433	dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
35961627 CL	434	return err;
	435	}
	436
	437	memset(priv->ring_control, 0, sizeof(*priv->ring_control));
	438	err = p54p_upload_firmware(dev);
	439	if (err) {
	440	free_irq(priv->pdev->irq, dev);
	441	return err;
	442	}
	443	priv->rx_idx_data = priv->tx_idx_data = 0;
	444	priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
	445
	446	p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
5988f385	447	ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
35961627 CL	448
35961627 CL	449	p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
5988f385	450	ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
35961627 CL	451
	452	P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
	453	P54P_READ(ring_control_base);
	454	wmb();
	455	udelay(10);
	456
	457	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
	458	P54P_READ(int_enable);
	459	wmb();
	460	udelay(10);
	461
	462	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
	463	P54P_READ(dev_int);
	464
	465	if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
	466	printk(KERN_ERR "%s: Cannot boot firmware!\n",
	467	wiphy_name(dev->wiphy));
	468	p54p_stop(dev);
	469	return -ETIMEDOUT;
	470	}
	471
	472	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
	473	P54P_READ(int_enable);
	474	wmb();
	475	udelay(10);
	476
	477	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	478	P54P_READ(dev_int);
	479	wmb();
	480	udelay(10);
	481
	482	return 0;
	483	}
	484
eff1a59c MW	485	static int __devinit p54p_probe(struct pci_dev *pdev,
	486	const struct pci_device_id *id)
	487	{
	488	struct p54p_priv *priv;
	489	struct ieee80211_hw *dev;
	490	unsigned long mem_addr, mem_len;
	491	int err;
eff1a59c MW	492
	493	err = pci_enable_device(pdev);
	494	if (err) {
ad5e72ee	495	dev_err(&pdev->dev, "Cannot enable new PCI device\n");
eff1a59c MW	496	return err;
	497	}
	498
	499	mem_addr = pci_resource_start(pdev, 0);
	500	mem_len = pci_resource_len(pdev, 0);
	501	if (mem_len < sizeof(struct p54p_csr)) {
ad5e72ee	502	dev_err(&pdev->dev, "Too short PCI resources\n");
40db0b22	503	goto err_disable_dev;
eff1a59c MW	504	}
eff1a59c MW	505
32ddf071	506	err = pci_request_regions(pdev, "p54pci");
eff1a59c	507	if (err) {
ad5e72ee	508	dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
40db0b22	509	goto err_disable_dev;
eff1a59c MW	510	}
eff1a59c MW	511
e930438c YH	512	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) \|\|
e930438c YH	513	pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
ad5e72ee	514	dev_err(&pdev->dev, "No suitable DMA available\n");
eff1a59c MW	515	goto err_free_reg;
	516	}
	517
	518	pci_set_master(pdev);
	519	pci_try_set_mwi(pdev);
	520
	521	pci_write_config_byte(pdev, 0x40, 0);
	522	pci_write_config_byte(pdev, 0x41, 0);
	523
	524	dev = p54_init_common(sizeof(*priv));
	525	if (!dev) {
ad5e72ee	526	dev_err(&pdev->dev, "ieee80211 alloc failed\n");
eff1a59c MW	527	err = -ENOMEM;
	528	goto err_free_reg;
	529	}
	530
	531	priv = dev->priv;
	532	priv->pdev = pdev;
	533
	534	SET_IEEE80211_DEV(dev, &pdev->dev);
	535	pci_set_drvdata(pdev, dev);
	536
	537	priv->map = ioremap(mem_addr, mem_len);
	538	if (!priv->map) {
ad5e72ee CL	539	dev_err(&pdev->dev, "Cannot map device memory\n");
ad5e72ee CL	540	err = -ENOMEM;
eff1a59c MW	541	goto err_free_dev;
	542	}
	543
	544	priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
	545	&priv->ring_control_dma);
	546	if (!priv->ring_control) {
ad5e72ee	547	dev_err(&pdev->dev, "Cannot allocate rings\n");
eff1a59c MW	548	err = -ENOMEM;
	549	goto err_iounmap;
	550	}
eff1a59c MW	551	priv->common.open = p54p_open;
	552	priv->common.stop = p54p_stop;
	553	priv->common.tx = p54p_tx;
	554
	555	spin_lock_init(&priv->lock);
d713804c	556	tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
eff1a59c	557
40db0b22 CL	558	err = request_firmware(&priv->firmware, "isl3886pci",
	559	&priv->pdev->dev);
	560	if (err) {
ad5e72ee	561	dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
40db0b22 CL	562	err = request_firmware(&priv->firmware, "isl3886",
	563	&priv->pdev->dev);
	564	if (err)
	565	goto err_free_common;
	566	}
	567
35961627 CL	568	err = p54p_open(dev);
	569	if (err)
	570	goto err_free_common;
7cb77072 CL	571	err = p54_read_eeprom(dev);
	572	p54p_stop(dev);
	573	if (err)
35961627	574	goto err_free_common;
7cb77072	575
2ac71072 CL	576	err = p54_register_common(dev, &pdev->dev);
2ac71072 CL	577	if (err)
eff1a59c	578	goto err_free_common;
eff1a59c	579
eff1a59c MW	580	return 0;
	581
	582	err_free_common:
40db0b22	583	release_firmware(priv->firmware);
eff1a59c MW	584	pci_free_consistent(pdev, sizeof(*priv->ring_control),
	585	priv->ring_control, priv->ring_control_dma);
	586
	587	err_iounmap:
	588	iounmap(priv->map);
	589
	590	err_free_dev:
	591	pci_set_drvdata(pdev, NULL);
d8c92107	592	p54_free_common(dev);
eff1a59c MW	593
	594	err_free_reg:
	595	pci_release_regions(pdev);
40db0b22	596	err_disable_dev:
eff1a59c MW	597	pci_disable_device(pdev);
	598	return err;
	599	}
	600
	601	static void __devexit p54p_remove(struct pci_dev *pdev)
	602	{
	603	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	604	struct p54p_priv *priv;
	605
	606	if (!dev)
	607	return;
	608
d8c92107	609	p54_unregister_common(dev);
eff1a59c	610	priv = dev->priv;
40db0b22	611	release_firmware(priv->firmware);
eff1a59c MW	612	pci_free_consistent(pdev, sizeof(*priv->ring_control),
eff1a59c MW	613	priv->ring_control, priv->ring_control_dma);
eff1a59c MW	614	iounmap(priv->map);
	615	pci_release_regions(pdev);
	616	pci_disable_device(pdev);
d8c92107	617	p54_free_common(dev);
eff1a59c MW	618	}
	619
	620	#ifdef CONFIG_PM
	621	static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
	622	{
	623	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	624	struct p54p_priv *priv = dev->priv;
	625
05c914fe	626	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
eff1a59c MW	627	ieee80211_stop_queues(dev);
	628	p54p_stop(dev);
	629	}
	630
	631	pci_save_state(pdev);
	632	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	633	return 0;
	634	}
	635
	636	static int p54p_resume(struct pci_dev *pdev)
	637	{
	638	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	639	struct p54p_priv *priv = dev->priv;
	640
	641	pci_set_power_state(pdev, PCI_D0);
	642	pci_restore_state(pdev);
	643
05c914fe	644	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
eff1a59c	645	p54p_open(dev);
36d6825b	646	ieee80211_wake_queues(dev);
eff1a59c MW	647	}
	648
	649	return 0;
	650	}
	651	#endif /* CONFIG_PM */
	652
	653	static struct pci_driver p54p_driver = {
32ddf071	654	.name = "p54pci",
eff1a59c MW	655	.id_table = p54p_table,
	656	.probe = p54p_probe,
	657	.remove = __devexit_p(p54p_remove),
	658	#ifdef CONFIG_PM
	659	.suspend = p54p_suspend,
	660	.resume = p54p_resume,
	661	#endif /* CONFIG_PM */
	662	};
	663
	664	static int __init p54p_init(void)
	665	{
	666	return pci_register_driver(&p54p_driver);
	667	}
	668
	669	static void __exit p54p_exit(void)
	670	{
	671	pci_unregister_driver(&p54p_driver);
	672	}
	673
	674	module_init(p54p_init);
	675	module_exit(p54p_exit);