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mac80211: dont allow fragmentation and requeuing on A-MPDU queues
[net-next-2.6.git] / drivers / net / wireless / p54 / p54common.c
CommitLineData
eff1a59c
MW		 1
2/*
3 * Common code for mac80211 Prism54 drivers
4 *
5 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
7 *
8 * Based on the islsm (softmac prism54) driver, which is:
9 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/firmware.h>
18#include <linux/etherdevice.h>
19
20#include <net/mac80211.h>
21
22#include "p54.h"
23#include "p54common.h"
24
25MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
26MODULE_DESCRIPTION("Softmac Prism54 common code");
27MODULE_LICENSE("GPL");
28MODULE_ALIAS("prism54common");
29
8318d78a
JB		 30static struct ieee80211_rate p54_rates[] = {
31 { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
32 { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
33 { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
34 { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
35 { .bitrate = 60, .hw_value = 4, },
36 { .bitrate = 90, .hw_value = 5, },
37 { .bitrate = 120, .hw_value = 6, },
38 { .bitrate = 180, .hw_value = 7, },
39 { .bitrate = 240, .hw_value = 8, },
40 { .bitrate = 360, .hw_value = 9, },
41 { .bitrate = 480, .hw_value = 10, },
42 { .bitrate = 540, .hw_value = 11, },
43};
44
45static struct ieee80211_channel p54_channels[] = {
46 { .center_freq = 2412, .hw_value = 1, },
47 { .center_freq = 2417, .hw_value = 2, },
48 { .center_freq = 2422, .hw_value = 3, },
49 { .center_freq = 2427, .hw_value = 4, },
50 { .center_freq = 2432, .hw_value = 5, },
51 { .center_freq = 2437, .hw_value = 6, },
52 { .center_freq = 2442, .hw_value = 7, },
53 { .center_freq = 2447, .hw_value = 8, },
54 { .center_freq = 2452, .hw_value = 9, },
55 { .center_freq = 2457, .hw_value = 10, },
56 { .center_freq = 2462, .hw_value = 11, },
57 { .center_freq = 2467, .hw_value = 12, },
58 { .center_freq = 2472, .hw_value = 13, },
59 { .center_freq = 2484, .hw_value = 14, },
60};
61
c2976ab0 62static struct ieee80211_supported_band band_2GHz = {
8318d78a
JB		 63 .channels = p54_channels,
64 .n_channels = ARRAY_SIZE(p54_channels),
65 .bitrates = p54_rates,
66 .n_bitrates = ARRAY_SIZE(p54_rates),
67};
68
69
eff1a59c
MW		 70void p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
71{
72 struct p54_common *priv = dev->priv;
73 struct bootrec_exp_if *exp_if;
74 struct bootrec *bootrec;
75 u32 *data = (u32 *)fw->data;
76 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
77 u8 *fw_version = NULL;
78 size_t len;
79 int i;
80
81 if (priv->rx_start)
82 return;
83
84 while (data < end_data && *data)
85 data++;
86
87 while (data < end_data && !*data)
88 data++;
89
90 bootrec = (struct bootrec *) data;
91
92 while (bootrec->data <= end_data &&
93 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
94 u32 code = le32_to_cpu(bootrec->code);
95 switch (code) {
96 case BR_CODE_COMPONENT_ID:
dc73c623 97 switch (be32_to_cpu(*(__be32 *)bootrec->data)) {
eff1a59c
MW		 98 case FW_FMAC:
99 printk(KERN_INFO "p54: FreeMAC firmware\n");
100 break;
101 case FW_LM20:
102 printk(KERN_INFO "p54: LM20 firmware\n");
103 break;
104 case FW_LM86:
105 printk(KERN_INFO "p54: LM86 firmware\n");
106 break;
107 case FW_LM87:
108 printk(KERN_INFO "p54: LM87 firmware - not supported yet!\n");
109 break;
110 default:
111 printk(KERN_INFO "p54: unknown firmware\n");
112 break;
113 }
114 break;
115 case BR_CODE_COMPONENT_VERSION:
116 /* 24 bytes should be enough for all firmwares */
117 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
118 fw_version = (unsigned char*)bootrec->data;
119 break;
120 case BR_CODE_DESCR:
dc73c623 121 priv->rx_start = le32_to_cpu(((__le32 *)bootrec->data)[1]);
eff1a59c 122 /* FIXME add sanity checking */
dc73c623 123 priv->rx_end = le32_to_cpu(((__le32 *)bootrec->data)[2]) - 0x3500;
eff1a59c
MW		 124 break;
125 case BR_CODE_EXPOSED_IF:
126 exp_if = (struct bootrec_exp_if *) bootrec->data;
127 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
dc73c623 128 if (exp_if[i].if_id == cpu_to_le16(0x1a))
eff1a59c
MW		 129 priv->fw_var = le16_to_cpu(exp_if[i].variant);
130 break;
131 case BR_CODE_DEPENDENT_IF:
132 break;
133 case BR_CODE_END_OF_BRA:
134 case LEGACY_BR_CODE_END_OF_BRA:
135 end_data = NULL;
136 break;
137 default:
138 break;
139 }
140 bootrec = (struct bootrec *)&bootrec->data[len];
141 }
142
143 if (fw_version)
144 printk(KERN_INFO "p54: FW rev %s - Softmac protocol %x.%x\n",
145 fw_version, priv->fw_var >> 8, priv->fw_var & 0xff);
146
147 if (priv->fw_var >= 0x300) {
148 /* Firmware supports QoS, use it! */
57ffc589
JB		 149 priv->tx_stats[0].limit = 3;
150 priv->tx_stats[1].limit = 4;
151 priv->tx_stats[2].limit = 3;
152 priv->tx_stats[3].limit = 1;
eff1a59c
MW		 153 dev->queues = 4;
154 }
155}
156EXPORT_SYMBOL_GPL(p54_parse_firmware);
157
158static int p54_convert_rev0_to_rev1(struct ieee80211_hw *dev,
159 struct pda_pa_curve_data *curve_data)
160{
161 struct p54_common *priv = dev->priv;
162 struct pda_pa_curve_data_sample_rev1 *rev1;
163 struct pda_pa_curve_data_sample_rev0 *rev0;
164 size_t cd_len = sizeof(*curve_data) +
165 (curve_data->points_per_channel*sizeof(*rev1) + 2) *
166 curve_data->channels;
167 unsigned int i, j;
168 void *source, *target;
169
170 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
171 if (!priv->curve_data)
172 return -ENOMEM;
173
174 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
175 source = curve_data->data;
176 target = priv->curve_data->data;
177 for (i = 0; i < curve_data->channels; i++) {
178 __le16 *freq = source;
179 source += sizeof(__le16);
180 *((__le16 *)target) = *freq;
181 target += sizeof(__le16);
182 for (j = 0; j < curve_data->points_per_channel; j++) {
183 rev1 = target;
184 rev0 = source;
185
186 rev1->rf_power = rev0->rf_power;
187 rev1->pa_detector = rev0->pa_detector;
188 rev1->data_64qam = rev0->pcv;
189 /* "invent" the points for the other modulations */
190#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
191 rev1->data_16qam = SUB(rev0->pcv, 12);
192 rev1->data_qpsk = SUB(rev1->data_16qam, 12);
193 rev1->data_bpsk = SUB(rev1->data_qpsk, 12);
194 rev1->data_barker= SUB(rev1->data_bpsk, 14);
195#undef SUB
196 target += sizeof(*rev1);
197 source += sizeof(*rev0);
198 }
199 }
200
201 return 0;
202}
203
204int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
205{
206 struct p54_common *priv = dev->priv;
207 struct eeprom_pda_wrap *wrap = NULL;
208 struct pda_entry *entry;
eff1a59c
MW		 209 unsigned int data_len, entry_len;
210 void *tmp;
211 int err;
c2f2d3a0 212 u8 *end = (u8 *)eeprom + len;
eff1a59c
MW		 213
214 wrap = (struct eeprom_pda_wrap *) eeprom;
8c28293f 215 entry = (void *)wrap->data + le16_to_cpu(wrap->len);
c2f2d3a0
JB		 216
217 /* verify that at least the entry length/code fits */
218 while ((u8 *)entry <= end - sizeof(*entry)) {
eff1a59c
MW		 219 entry_len = le16_to_cpu(entry->len);
220 data_len = ((entry_len - 1) << 1);
c2f2d3a0
JB		 221
222 /* abort if entry exceeds whole structure */
223 if ((u8 *)entry + sizeof(*entry) + data_len > end)
224 break;
225
eff1a59c
MW		 226 switch (le16_to_cpu(entry->code)) {
227 case PDR_MAC_ADDRESS:
228 SET_IEEE80211_PERM_ADDR(dev, entry->data);
229 break;
230 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
231 if (data_len < 2) {
232 err = -EINVAL;
233 goto err;
234 }
235
236 if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
237 err = -EINVAL;
238 goto err;
239 }
240
241 priv->output_limit = kmalloc(entry->data[1] *
242 sizeof(*priv->output_limit), GFP_KERNEL);
243
244 if (!priv->output_limit) {
245 err = -ENOMEM;
246 goto err;
247 }
248
249 memcpy(priv->output_limit, &entry->data[2],
250 entry->data[1]*sizeof(*priv->output_limit));
251 priv->output_limit_len = entry->data[1];
252 break;
253 case PDR_PRISM_PA_CAL_CURVE_DATA:
254 if (data_len < sizeof(struct pda_pa_curve_data)) {
255 err = -EINVAL;
256 goto err;
257 }
258
259 if (((struct pda_pa_curve_data *)entry->data)->cal_method_rev) {
260 priv->curve_data = kmalloc(data_len, GFP_KERNEL);
261 if (!priv->curve_data) {
262 err = -ENOMEM;
263 goto err;
264 }
265
266 memcpy(priv->curve_data, entry->data, data_len);
267 } else {
268 err = p54_convert_rev0_to_rev1(dev, (struct pda_pa_curve_data *)entry->data);
269 if (err)
270 goto err;
271 }
272
273 break;
274 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
275 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
276 if (!priv->iq_autocal) {
277 err = -ENOMEM;
278 goto err;
279 }
280
281 memcpy(priv->iq_autocal, entry->data, data_len);
282 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
283 break;
284 case PDR_INTERFACE_LIST:
285 tmp = entry->data;
286 while ((u8 *)tmp < entry->data + data_len) {
287 struct bootrec_exp_if *exp_if = tmp;
288 if (le16_to_cpu(exp_if->if_id) == 0xF)
289 priv->rxhw = exp_if->variant & cpu_to_le16(0x07);
290 tmp += sizeof(struct bootrec_exp_if);
291 }
292 break;
293 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
294 priv->version = *(u8 *)(entry->data + 1);
295 break;
296 case PDR_END:
c2f2d3a0
JB		 297 /* make it overrun */
298 entry_len = len;
eff1a59c 299 break;
58e30739
FF		 300 default:
301 printk(KERN_INFO "p54: unknown eeprom code : 0x%x\n",
302 le16_to_cpu(entry->code));
303 break;
eff1a59c
MW		 304 }
305
306 entry = (void *)entry + (entry_len + 1)*2;
eff1a59c
MW		 307 }
308
309 if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) {
310 printk(KERN_ERR "p54: not all required entries found in eeprom!\n");
311 err = -EINVAL;
312 goto err;
313 }
314
315 return 0;
316
317 err:
318 if (priv->iq_autocal) {
319 kfree(priv->iq_autocal);
320 priv->iq_autocal = NULL;
321 }
322
323 if (priv->output_limit) {
324 kfree(priv->output_limit);
325 priv->output_limit = NULL;
326 }
327
328 if (priv->curve_data) {
329 kfree(priv->curve_data);
330 priv->curve_data = NULL;
331 }
332
333 printk(KERN_ERR "p54: eeprom parse failed!\n");
334 return err;
335}
336EXPORT_SYMBOL_GPL(p54_parse_eeprom);
337
338void p54_fill_eeprom_readback(struct p54_control_hdr *hdr)
339{
340 struct p54_eeprom_lm86 *eeprom_hdr;
341
342 hdr->magic1 = cpu_to_le16(0x8000);
343 hdr->len = cpu_to_le16(sizeof(*eeprom_hdr) + 0x2000);
344 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_EEPROM_READBACK);
345 hdr->retry1 = hdr->retry2 = 0;
346 eeprom_hdr = (struct p54_eeprom_lm86 *) hdr->data;
347 eeprom_hdr->offset = 0x0;
348 eeprom_hdr->len = cpu_to_le16(0x2000);
349}
350EXPORT_SYMBOL_GPL(p54_fill_eeprom_readback);
351
352static void p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
353{
354 struct p54_rx_hdr *hdr = (struct p54_rx_hdr *) skb->data;
355 struct ieee80211_rx_status rx_status = {0};
356 u16 freq = le16_to_cpu(hdr->freq);
357
566bfe5a 358 rx_status.signal = hdr->rssi;
8318d78a
JB		 359 /* XX correct? */
360 rx_status.rate_idx = hdr->rate & 0xf;
eff1a59c 361 rx_status.freq = freq;
8318d78a 362 rx_status.band = IEEE80211_BAND_2GHZ;
eff1a59c
MW		 363 rx_status.antenna = hdr->antenna;
364 rx_status.mactime = le64_to_cpu(hdr->timestamp);
03bffc13 365 rx_status.flag |= RX_FLAG_TSFT;
eff1a59c
MW		 366
367 skb_pull(skb, sizeof(*hdr));
368 skb_trim(skb, le16_to_cpu(hdr->len));
369
370 ieee80211_rx_irqsafe(dev, skb, &rx_status);
371}
372
373static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
374{
375 struct p54_common *priv = dev->priv;
376 int i;
377
eff1a59c 378 for (i = 0; i < dev->queues; i++)
57ffc589 379 if (priv->tx_stats[i].len < priv->tx_stats[i].limit)
eff1a59c
MW		 380 ieee80211_wake_queue(dev, i);
381}
382
383static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
384{
385 struct p54_common *priv = dev->priv;
386 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
387 struct p54_frame_sent_hdr *payload = (struct p54_frame_sent_hdr *) hdr->data;
388 struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
389 u32 addr = le32_to_cpu(hdr->req_id) - 0x70;
390 struct memrecord *range = NULL;
391 u32 freed = 0;
392 u32 last_addr = priv->rx_start;
393
394 while (entry != (struct sk_buff *)&priv->tx_queue) {
395 range = (struct memrecord *)&entry->cb;
396 if (range->start_addr == addr) {
e039fa4a 397 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
eff1a59c
MW		 398 struct p54_control_hdr *entry_hdr;
399 struct p54_tx_control_allocdata *entry_data;
400 int pad = 0;
401
402 if (entry->next != (struct sk_buff *)&priv->tx_queue)
403 freed = ((struct memrecord *)&entry->next->cb)->start_addr - last_addr;
404 else
405 freed = priv->rx_end - last_addr;
406
407 last_addr = range->end_addr;
408 __skb_unlink(entry, &priv->tx_queue);
e039fa4a
JB		 409 memset(&info->status, 0, sizeof(info->status));
410 priv->tx_stats[info->queue].len--;
eff1a59c
MW		 411 entry_hdr = (struct p54_control_hdr *) entry->data;
412 entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data;
413 if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0)
414 pad = entry_data->align[0];
415
e039fa4a 416 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
eff1a59c 417 if (!(payload->status & 0x01))
e039fa4a 418 info->flags |= IEEE80211_TX_STAT_ACK;
eff1a59c 419 else
e039fa4a 420 info->status.excessive_retries = 1;
eff1a59c 421 }
e039fa4a
JB		 422 info->status.retry_count = payload->retries - 1;
423 info->status.ack_signal = le16_to_cpu(payload->ack_rssi);
eff1a59c 424 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
e039fa4a 425 ieee80211_tx_status_irqsafe(dev, entry);
eff1a59c
MW		 426 break;
427 } else
428 last_addr = range->end_addr;
429 entry = entry->next;
430 }
431
432 if (freed >= IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
433 sizeof(struct p54_control_hdr))
434 p54_wake_free_queues(dev);
435}
436
437static void p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
438{
439 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
440
441 switch (le16_to_cpu(hdr->type)) {
442 case P54_CONTROL_TYPE_TXDONE:
443 p54_rx_frame_sent(dev, skb);
444 break;
445 case P54_CONTROL_TYPE_BBP:
446 break;
447 default:
448 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
449 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
450 break;
451 }
452}
453
454/* returns zero if skb can be reused */
455int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
456{
457 u8 type = le16_to_cpu(*((__le16 *)skb->data)) >> 8;
458 switch (type) {
459 case 0x00:
460 case 0x01:
461 p54_rx_data(dev, skb);
462 return -1;
463 case 0x4d:
464 /* TODO: do something better... but then again, I've never seen this happen */
465 printk(KERN_ERR "%s: Received fault. Probably need to restart hardware now..\n",
466 wiphy_name(dev->wiphy));
467 break;
468 case 0x80:
469 p54_rx_control(dev, skb);
470 break;
471 default:
472 printk(KERN_ERR "%s: unknown frame RXed (0x%02x)\n",
473 wiphy_name(dev->wiphy), type);
474 break;
475 }
476 return 0;
477}
478EXPORT_SYMBOL_GPL(p54_rx);
479
480/*
481 * So, the firmware is somewhat stupid and doesn't know what places in its
482 * memory incoming data should go to. By poking around in the firmware, we
483 * can find some unused memory to upload our packets to. However, data that we
484 * want the card to TX needs to stay intact until the card has told us that
485 * it is done with it. This function finds empty places we can upload to and
486 * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
487 * allocated areas.
488 */
489static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
e039fa4a 490 struct p54_control_hdr *data, u32 len)
eff1a59c
MW		 491{
492 struct p54_common *priv = dev->priv;
493 struct sk_buff *entry = priv->tx_queue.next;
494 struct sk_buff *target_skb = NULL;
eff1a59c
MW		 495 u32 last_addr = priv->rx_start;
496 u32 largest_hole = 0;
497 u32 target_addr = priv->rx_start;
498 unsigned long flags;
499 unsigned int left;
500 len = (len + 0x170 + 3) & ~0x3; /* 0x70 headroom, 0x100 tailroom */
501
502 spin_lock_irqsave(&priv->tx_queue.lock, flags);
503 left = skb_queue_len(&priv->tx_queue);
504 while (left--) {
505 u32 hole_size;
e039fa4a
JB		 506 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
507 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW		 508 hole_size = range->start_addr - last_addr;
509 if (!target_skb && hole_size >= len) {
510 target_skb = entry->prev;
511 hole_size -= len;
512 target_addr = last_addr;
513 }
514 largest_hole = max(largest_hole, hole_size);
515 last_addr = range->end_addr;
516 entry = entry->next;
517 }
518 if (!target_skb && priv->rx_end - last_addr >= len) {
519 target_skb = priv->tx_queue.prev;
520 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
521 if (!skb_queue_empty(&priv->tx_queue)) {
e039fa4a
JB		 522 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(target_skb);
523 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW		 524 target_addr = range->end_addr;
525 }
526 } else
527 largest_hole = max(largest_hole, priv->rx_end - last_addr);
528
529 if (skb) {
e039fa4a
JB		 530 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
531 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW		 532 range->start_addr = target_addr;
533 range->end_addr = target_addr + len;
eff1a59c
MW		 534 __skb_queue_after(&priv->tx_queue, target_skb, skb);
535 if (largest_hole < IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
536 sizeof(struct p54_control_hdr))
537 ieee80211_stop_queues(dev);
538 }
539 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
540
541 data->req_id = cpu_to_le32(target_addr + 0x70);
542}
543
e039fa4a 544static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 545{
e039fa4a 546 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
57ffc589 547 struct ieee80211_tx_queue_stats *current_queue;
eff1a59c
MW		 548 struct p54_common *priv = dev->priv;
549 struct p54_control_hdr *hdr;
550 struct p54_tx_control_allocdata *txhdr;
eff1a59c
MW		 551 size_t padding, len;
552 u8 rate;
553
e039fa4a 554 current_queue = &priv->tx_stats[info->queue];
eff1a59c
MW		 555 if (unlikely(current_queue->len > current_queue->limit))
556 return NETDEV_TX_BUSY;
557 current_queue->len++;
558 current_queue->count++;
559 if (current_queue->len == current_queue->limit)
e039fa4a 560 ieee80211_stop_queue(dev, info->queue);
eff1a59c
MW		 561
562 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
563 len = skb->len;
564
eff1a59c
MW		 565 txhdr = (struct p54_tx_control_allocdata *)
566 skb_push(skb, sizeof(*txhdr) + padding);
567 hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr));
568
569 if (padding)
570 hdr->magic1 = cpu_to_le16(0x4010);
571 else
572 hdr->magic1 = cpu_to_le16(0x0010);
573 hdr->len = cpu_to_le16(len);
e039fa4a
JB		 574 hdr->type = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 0 : cpu_to_le16(1);
575 hdr->retry1 = hdr->retry2 = info->control.retry_limit;
eff1a59c
MW		 576
577 memset(txhdr->wep_key, 0x0, 16);
578 txhdr->padding = 0;
579 txhdr->padding2 = 0;
580
581 /* TODO: add support for alternate retry TX rates */
e039fa4a
JB		 582 rate = ieee80211_get_tx_rate(dev, info)->hw_value;
583 if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE)
8318d78a 584 rate |= 0x10;
e039fa4a 585 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
eff1a59c 586 rate |= 0x40;
e039fa4a 587 else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT)
eff1a59c
MW		 588 rate |= 0x20;
589 memset(txhdr->rateset, rate, 8);
590 txhdr->wep_key_present = 0;
591 txhdr->wep_key_len = 0;
e039fa4a 592 txhdr->frame_type = cpu_to_le32(info->queue + 4);
eff1a59c 593 txhdr->magic4 = 0;
e039fa4a
JB		 594 txhdr->antenna = (info->antenna_sel_tx == 0) ?
595 2 : info->antenna_sel_tx - 1;
eff1a59c 596 txhdr->output_power = 0x7f; // HW Maximum
e039fa4a 597 txhdr->magic5 = (info->flags & IEEE80211_TX_CTL_NO_ACK) ?
eff1a59c
MW		 598 0 : ((rate > 0x3) ? cpu_to_le32(0x33) : cpu_to_le32(0x23));
599 if (padding)
600 txhdr->align[0] = padding;
601
e039fa4a
JB		 602 /* modifies skb->cb and with it info, so must be last! */
603 p54_assign_address(dev, skb, hdr, skb->len);
604
eff1a59c
MW		 605 priv->tx(dev, hdr, skb->len, 0);
606 return 0;
607}
608
609static int p54_set_filter(struct ieee80211_hw *dev, u16 filter_type,
610 const u8 *dst, const u8 *src, u8 antenna,
611 u32 magic3, u32 magic8, u32 magic9)
612{
613 struct p54_common *priv = dev->priv;
614 struct p54_control_hdr *hdr;
615 struct p54_tx_control_filter *filter;
616
617 hdr = kzalloc(sizeof(*hdr) + sizeof(*filter) +
ba8007ce 618 priv->tx_hdr_len, GFP_ATOMIC);
eff1a59c
MW		 619 if (!hdr)
620 return -ENOMEM;
621
622 hdr = (void *)hdr + priv->tx_hdr_len;
623
624 filter = (struct p54_tx_control_filter *) hdr->data;
625 hdr->magic1 = cpu_to_le16(0x8001);
626 hdr->len = cpu_to_le16(sizeof(*filter));
e039fa4a 627 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*filter));
eff1a59c
MW		 628 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET);
629
630 filter->filter_type = cpu_to_le16(filter_type);
631 memcpy(filter->dst, dst, ETH_ALEN);
632 if (!src)
633 memset(filter->src, ~0, ETH_ALEN);
634 else
635 memcpy(filter->src, src, ETH_ALEN);
636 filter->antenna = antenna;
637 filter->magic3 = cpu_to_le32(magic3);
638 filter->rx_addr = cpu_to_le32(priv->rx_end);
639 filter->max_rx = cpu_to_le16(0x0620); /* FIXME: for usb ver 1.. maybe */
640 filter->rxhw = priv->rxhw;
641 filter->magic8 = cpu_to_le16(magic8);
642 filter->magic9 = cpu_to_le16(magic9);
643
644 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*filter), 1);
645 return 0;
646}
647
648static int p54_set_freq(struct ieee80211_hw *dev, __le16 freq)
649{
650 struct p54_common *priv = dev->priv;
651 struct p54_control_hdr *hdr;
652 struct p54_tx_control_channel *chan;
653 unsigned int i;
654 size_t payload_len = sizeof(*chan) + sizeof(u32)*2 +
655 sizeof(*chan->curve_data) *
656 priv->curve_data->points_per_channel;
657 void *entry;
658
659 hdr = kzalloc(sizeof(*hdr) + payload_len +
660 priv->tx_hdr_len, GFP_KERNEL);
661 if (!hdr)
662 return -ENOMEM;
663
664 hdr = (void *)hdr + priv->tx_hdr_len;
665
666 chan = (struct p54_tx_control_channel *) hdr->data;
667
668 hdr->magic1 = cpu_to_le16(0x8001);
669 hdr->len = cpu_to_le16(sizeof(*chan));
670 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE);
e039fa4a 671 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + payload_len);
eff1a59c
MW		 672
673 chan->magic1 = cpu_to_le16(0x1);
674 chan->magic2 = cpu_to_le16(0x0);
675
676 for (i = 0; i < priv->iq_autocal_len; i++) {
677 if (priv->iq_autocal[i].freq != freq)
678 continue;
679
680 memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
681 sizeof(*priv->iq_autocal));
682 break;
683 }
684 if (i == priv->iq_autocal_len)
685 goto err;
686
687 for (i = 0; i < priv->output_limit_len; i++) {
688 if (priv->output_limit[i].freq != freq)
689 continue;
690
691 chan->val_barker = 0x38;
692 chan->val_bpsk = priv->output_limit[i].val_bpsk;
693 chan->val_qpsk = priv->output_limit[i].val_qpsk;
694 chan->val_16qam = priv->output_limit[i].val_16qam;
695 chan->val_64qam = priv->output_limit[i].val_64qam;
696 break;
697 }
698 if (i == priv->output_limit_len)
699 goto err;
700
701 chan->pa_points_per_curve = priv->curve_data->points_per_channel;
702
703 entry = priv->curve_data->data;
704 for (i = 0; i < priv->curve_data->channels; i++) {
705 if (*((__le16 *)entry) != freq) {
706 entry += sizeof(__le16);
707 entry += sizeof(struct pda_pa_curve_data_sample_rev1) *
708 chan->pa_points_per_curve;
709 continue;
710 }
711
712 entry += sizeof(__le16);
713 memcpy(chan->curve_data, entry, sizeof(*chan->curve_data) *
714 chan->pa_points_per_curve);
715 break;
716 }
717
718 memcpy(hdr->data + payload_len - 4, &chan->val_bpsk, 4);
719
720 priv->tx(dev, hdr, sizeof(*hdr) + payload_len, 1);
721 return 0;
722
723 err:
724 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
725 kfree(hdr);
726 return -EINVAL;
727}
728
729static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
730{
731 struct p54_common *priv = dev->priv;
732 struct p54_control_hdr *hdr;
733 struct p54_tx_control_led *led;
734
735 hdr = kzalloc(sizeof(*hdr) + sizeof(*led) +
736 priv->tx_hdr_len, GFP_KERNEL);
737 if (!hdr)
738 return -ENOMEM;
739
740 hdr = (void *)hdr + priv->tx_hdr_len;
741 hdr->magic1 = cpu_to_le16(0x8001);
742 hdr->len = cpu_to_le16(sizeof(*led));
743 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED);
e039fa4a 744 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led));
eff1a59c
MW		 745
746 led = (struct p54_tx_control_led *) hdr->data;
747 led->mode = cpu_to_le16(mode);
748 led->led_permanent = cpu_to_le16(link);
749 led->led_temporary = cpu_to_le16(act);
750 led->duration = cpu_to_le16(1000);
751
752 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*led), 1);
753
754 return 0;
755}
756
3330d7be 757#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \
eff1a59c
MW		 758do { \
759 queue.aifs = cpu_to_le16(ai_fs); \
760 queue.cwmin = cpu_to_le16(cw_min); \
761 queue.cwmax = cpu_to_le16(cw_max); \
3330d7be 762 queue.txop = cpu_to_le16(_txop); \
eff1a59c
MW		 763} while(0)
764
765static void p54_init_vdcf(struct ieee80211_hw *dev)
766{
767 struct p54_common *priv = dev->priv;
768 struct p54_control_hdr *hdr;
769 struct p54_tx_control_vdcf *vdcf;
770
771 /* all USB V1 adapters need a extra headroom */
772 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
773 hdr->magic1 = cpu_to_le16(0x8001);
774 hdr->len = cpu_to_le16(sizeof(*vdcf));
775 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_DCFINIT);
776 hdr->req_id = cpu_to_le32(priv->rx_start);
777
778 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
779
3330d7be
JB		 780 P54_SET_QUEUE(vdcf->queue[0], 0x0002, 0x0003, 0x0007, 47);
781 P54_SET_QUEUE(vdcf->queue[1], 0x0002, 0x0007, 0x000f, 94);
5200e8cd 782 P54_SET_QUEUE(vdcf->queue[2], 0x0003, 0x000f, 0x03ff, 0);
3330d7be 783 P54_SET_QUEUE(vdcf->queue[3], 0x0007, 0x000f, 0x03ff, 0);
eff1a59c
MW		 784}
785
786static void p54_set_vdcf(struct ieee80211_hw *dev)
787{
788 struct p54_common *priv = dev->priv;
789 struct p54_control_hdr *hdr;
790 struct p54_tx_control_vdcf *vdcf;
791
792 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
793
e039fa4a 794 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf));
eff1a59c
MW		 795
796 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
797
798 if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
799 vdcf->slottime = 9;
800 vdcf->magic1 = 0x00;
801 vdcf->magic2 = 0x10;
802 } else {
803 vdcf->slottime = 20;
804 vdcf->magic1 = 0x0a;
805 vdcf->magic2 = 0x06;
806 }
807
808 /* (see prism54/isl_oid.h for further details) */
809 vdcf->frameburst = cpu_to_le16(0);
810
811 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*vdcf), 0);
812}
813
4150c572
JB		 814static int p54_start(struct ieee80211_hw *dev)
815{
816 struct p54_common *priv = dev->priv;
817 int err;
818
819 err = priv->open(dev);
820 if (!err)
821 priv->mode = IEEE80211_IF_TYPE_MNTR;
822
823 return err;
824}
825
826static void p54_stop(struct ieee80211_hw *dev)
827{
828 struct p54_common *priv = dev->priv;
829 struct sk_buff *skb;
e039fa4a 830 while ((skb = skb_dequeue(&priv->tx_queue)))
4150c572 831 kfree_skb(skb);
4150c572 832 priv->stop(dev);
a2897552 833 priv->mode = IEEE80211_IF_TYPE_INVALID;
4150c572
JB		 834}
835
eff1a59c
MW		 836static int p54_add_interface(struct ieee80211_hw *dev,
837 struct ieee80211_if_init_conf *conf)
838{
839 struct p54_common *priv = dev->priv;
eff1a59c 840
4150c572
JB		 841 if (priv->mode != IEEE80211_IF_TYPE_MNTR)
842 return -EOPNOTSUPP;
eff1a59c
MW		 843
844 switch (conf->type) {
845 case IEEE80211_IF_TYPE_STA:
846 priv->mode = conf->type;
847 break;
848 default:
849 return -EOPNOTSUPP;
850 }
851
4150c572 852 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
eff1a59c
MW		 853
854 p54_set_filter(dev, 0, priv->mac_addr, NULL, 0, 1, 0, 0xF642);
855 p54_set_filter(dev, 0, priv->mac_addr, NULL, 1, 0, 0, 0xF642);
eff1a59c
MW		 856
857 switch (conf->type) {
858 case IEEE80211_IF_TYPE_STA:
859 p54_set_filter(dev, 1, priv->mac_addr, NULL, 0, 0x15F, 0x1F4, 0);
860 break;
4150c572
JB		 861 default:
862 BUG(); /* impossible */
863 break;
eff1a59c
MW		 864 }
865
866 p54_set_leds(dev, 1, 0, 0);
867
868 return 0;
869}
870
871static void p54_remove_interface(struct ieee80211_hw *dev,
872 struct ieee80211_if_init_conf *conf)
873{
874 struct p54_common *priv = dev->priv;
4150c572
JB		 875 priv->mode = IEEE80211_IF_TYPE_MNTR;
876 memset(priv->mac_addr, 0, ETH_ALEN);
877 p54_set_filter(dev, 0, priv->mac_addr, NULL, 2, 0, 0, 0);
eff1a59c
MW		 878}
879
880static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
881{
882 int ret;
883
8318d78a 884 ret = p54_set_freq(dev, cpu_to_le16(conf->channel->center_freq));
eff1a59c
MW		 885 p54_set_vdcf(dev);
886 return ret;
887}
888
32bfd35d
JB		 889static int p54_config_interface(struct ieee80211_hw *dev,
890 struct ieee80211_vif *vif,
eff1a59c
MW		 891 struct ieee80211_if_conf *conf)
892{
893 struct p54_common *priv = dev->priv;
894
895 p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 0, 1, 0, 0xF642);
896 p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 2, 0, 0, 0);
897 p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0);
4150c572 898 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
eff1a59c
MW		 899 return 0;
900}
901
4150c572
JB		 902static void p54_configure_filter(struct ieee80211_hw *dev,
903 unsigned int changed_flags,
904 unsigned int *total_flags,
905 int mc_count, struct dev_mc_list *mclist)
906{
907 struct p54_common *priv = dev->priv;
908
909 *total_flags &= FIF_BCN_PRBRESP_PROMISC;
910
911 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
912 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
913 p54_set_filter(dev, 0, priv->mac_addr,
914 NULL, 2, 0, 0, 0);
915 else
916 p54_set_filter(dev, 0, priv->mac_addr,
917 priv->bssid, 2, 0, 0, 0);
918 }
919}
920
e100bb64 921static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue,
eff1a59c
MW		 922 const struct ieee80211_tx_queue_params *params)
923{
924 struct p54_common *priv = dev->priv;
925 struct p54_tx_control_vdcf *vdcf;
926
927 vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *)
928 ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data);
929
3df5ee60 930 if ((params) && !(queue > 4)) {
eff1a59c 931 P54_SET_QUEUE(vdcf->queue[queue], params->aifs,
3330d7be 932 params->cw_min, params->cw_max, params->txop);
eff1a59c
MW		 933 } else
934 return -EINVAL;
935
936 p54_set_vdcf(dev);
937
938 return 0;
939}
940
941static int p54_get_stats(struct ieee80211_hw *dev,
942 struct ieee80211_low_level_stats *stats)
943{
944 /* TODO */
945 return 0;
946}
947
948static int p54_get_tx_stats(struct ieee80211_hw *dev,
949 struct ieee80211_tx_queue_stats *stats)
950{
951 struct p54_common *priv = dev->priv;
eff1a59c 952
57ffc589 953 memcpy(stats, &priv->tx_stats, sizeof(stats[0]) * dev->queues);
eff1a59c
MW		 954
955 return 0;
956}
957
958static const struct ieee80211_ops p54_ops = {
959 .tx = p54_tx,
4150c572
JB		 960 .start = p54_start,
961 .stop = p54_stop,
eff1a59c
MW		 962 .add_interface = p54_add_interface,
963 .remove_interface = p54_remove_interface,
964 .config = p54_config,
965 .config_interface = p54_config_interface,
4150c572 966 .configure_filter = p54_configure_filter,
eff1a59c
MW		 967 .conf_tx = p54_conf_tx,
968 .get_stats = p54_get_stats,
969 .get_tx_stats = p54_get_tx_stats
970};
971
972struct ieee80211_hw *p54_init_common(size_t priv_data_len)
973{
974 struct ieee80211_hw *dev;
975 struct p54_common *priv;
eff1a59c
MW		 976
977 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
978 if (!dev)
979 return NULL;
980
981 priv = dev->priv;
a2897552 982 priv->mode = IEEE80211_IF_TYPE_INVALID;
eff1a59c 983 skb_queue_head_init(&priv->tx_queue);
8318d78a 984 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz;
eff1a59c 985 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */
566bfe5a
BR		 986 IEEE80211_HW_RX_INCLUDES_FCS |
987 IEEE80211_HW_SIGNAL_UNSPEC;
eff1a59c 988 dev->channel_change_time = 1000; /* TODO: find actual value */
566bfe5a 989 dev->max_signal = 127;
eff1a59c 990
57ffc589 991 priv->tx_stats[0].limit = 5;
eff1a59c
MW		 992 dev->queues = 1;
993
994 dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 +
995 sizeof(struct p54_tx_control_allocdata);
996
997 priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf) +
998 priv->tx_hdr_len + sizeof(struct p54_control_hdr), GFP_KERNEL);
999
1000 if (!priv->cached_vdcf) {
1001 ieee80211_free_hw(dev);
1002 return NULL;
1003 }
1004
1005 p54_init_vdcf(dev);
1006
eff1a59c
MW		 1007 return dev;
1008}
1009EXPORT_SYMBOL_GPL(p54_init_common);
1010
1011void p54_free_common(struct ieee80211_hw *dev)
1012{
1013 struct p54_common *priv = dev->priv;
1014 kfree(priv->iq_autocal);
1015 kfree(priv->output_limit);
1016 kfree(priv->curve_data);
1017 kfree(priv->cached_vdcf);
1018}
1019EXPORT_SYMBOL_GPL(p54_free_common);
1020
1021static int __init p54_init(void)
1022{
1023 return 0;
1024}
1025
1026static void __exit p54_exit(void)
1027{
1028}
1029
1030module_init(p54_init);
1031module_exit(p54_exit);
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