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p54: more definitions form lmac_longbow.h and pda.h
[net-next-2.6.git] / drivers / net / wireless / p54 / p54common.c
CommitLineData
eff1a59c
MW
1/*
2 * Common code for mac80211 Prism54 drivers
3 *
4 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
5 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
c12abae3 6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
eff1a59c 7 *
27df605e
JL
8 * Based on:
9 * - the islsm (softmac prism54) driver, which is:
10 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
11 * - stlc45xx driver
12 * C\ 2 Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
eff1a59c
MW
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/init.h>
20#include <linux/firmware.h>
21#include <linux/etherdevice.h>
22
23#include <net/mac80211.h>
24
25#include "p54.h"
26#include "p54common.h"
27
28MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
29MODULE_DESCRIPTION("Softmac Prism54 common code");
30MODULE_LICENSE("GPL");
31MODULE_ALIAS("prism54common");
32
1b997534 33static struct ieee80211_rate p54_bgrates[] = {
8318d78a
JB
34 { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
35 { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
36 { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
37 { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
38 { .bitrate = 60, .hw_value = 4, },
39 { .bitrate = 90, .hw_value = 5, },
40 { .bitrate = 120, .hw_value = 6, },
41 { .bitrate = 180, .hw_value = 7, },
42 { .bitrate = 240, .hw_value = 8, },
43 { .bitrate = 360, .hw_value = 9, },
44 { .bitrate = 480, .hw_value = 10, },
45 { .bitrate = 540, .hw_value = 11, },
46};
47
1b997534 48static struct ieee80211_channel p54_bgchannels[] = {
8318d78a
JB
49 { .center_freq = 2412, .hw_value = 1, },
50 { .center_freq = 2417, .hw_value = 2, },
51 { .center_freq = 2422, .hw_value = 3, },
52 { .center_freq = 2427, .hw_value = 4, },
53 { .center_freq = 2432, .hw_value = 5, },
54 { .center_freq = 2437, .hw_value = 6, },
55 { .center_freq = 2442, .hw_value = 7, },
56 { .center_freq = 2447, .hw_value = 8, },
57 { .center_freq = 2452, .hw_value = 9, },
58 { .center_freq = 2457, .hw_value = 10, },
59 { .center_freq = 2462, .hw_value = 11, },
60 { .center_freq = 2467, .hw_value = 12, },
61 { .center_freq = 2472, .hw_value = 13, },
62 { .center_freq = 2484, .hw_value = 14, },
63};
64
c2976ab0 65static struct ieee80211_supported_band band_2GHz = {
1b997534
CL
66 .channels = p54_bgchannels,
67 .n_channels = ARRAY_SIZE(p54_bgchannels),
68 .bitrates = p54_bgrates,
69 .n_bitrates = ARRAY_SIZE(p54_bgrates),
70};
71
72static struct ieee80211_rate p54_arates[] = {
73 { .bitrate = 60, .hw_value = 4, },
74 { .bitrate = 90, .hw_value = 5, },
75 { .bitrate = 120, .hw_value = 6, },
76 { .bitrate = 180, .hw_value = 7, },
77 { .bitrate = 240, .hw_value = 8, },
78 { .bitrate = 360, .hw_value = 9, },
79 { .bitrate = 480, .hw_value = 10, },
80 { .bitrate = 540, .hw_value = 11, },
81};
82
83static struct ieee80211_channel p54_achannels[] = {
84 { .center_freq = 4920 },
85 { .center_freq = 4940 },
86 { .center_freq = 4960 },
87 { .center_freq = 4980 },
88 { .center_freq = 5040 },
89 { .center_freq = 5060 },
90 { .center_freq = 5080 },
91 { .center_freq = 5170 },
92 { .center_freq = 5180 },
93 { .center_freq = 5190 },
94 { .center_freq = 5200 },
95 { .center_freq = 5210 },
96 { .center_freq = 5220 },
97 { .center_freq = 5230 },
98 { .center_freq = 5240 },
99 { .center_freq = 5260 },
100 { .center_freq = 5280 },
101 { .center_freq = 5300 },
102 { .center_freq = 5320 },
103 { .center_freq = 5500 },
104 { .center_freq = 5520 },
105 { .center_freq = 5540 },
106 { .center_freq = 5560 },
107 { .center_freq = 5580 },
108 { .center_freq = 5600 },
109 { .center_freq = 5620 },
110 { .center_freq = 5640 },
111 { .center_freq = 5660 },
112 { .center_freq = 5680 },
113 { .center_freq = 5700 },
114 { .center_freq = 5745 },
115 { .center_freq = 5765 },
116 { .center_freq = 5785 },
117 { .center_freq = 5805 },
118 { .center_freq = 5825 },
119};
120
121static struct ieee80211_supported_band band_5GHz = {
122 .channels = p54_achannels,
123 .n_channels = ARRAY_SIZE(p54_achannels),
124 .bitrates = p54_arates,
125 .n_bitrates = ARRAY_SIZE(p54_arates),
8318d78a
JB
126};
127
4e416a6f 128int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
eff1a59c
MW
129{
130 struct p54_common *priv = dev->priv;
131 struct bootrec_exp_if *exp_if;
132 struct bootrec *bootrec;
133 u32 *data = (u32 *)fw->data;
134 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
135 u8 *fw_version = NULL;
136 size_t len;
137 int i;
138
139 if (priv->rx_start)
4e416a6f 140 return 0;
eff1a59c
MW
141
142 while (data < end_data && *data)
143 data++;
144
145 while (data < end_data && !*data)
146 data++;
147
148 bootrec = (struct bootrec *) data;
149
150 while (bootrec->data <= end_data &&
151 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
152 u32 code = le32_to_cpu(bootrec->code);
153 switch (code) {
154 case BR_CODE_COMPONENT_ID:
1f1c0e33
LF
155 priv->fw_interface = be32_to_cpup((__be32 *)
156 bootrec->data);
2b80848e 157 switch (priv->fw_interface) {
eff1a59c
MW
158 case FW_FMAC:
159 printk(KERN_INFO "p54: FreeMAC firmware\n");
160 break;
161 case FW_LM20:
162 printk(KERN_INFO "p54: LM20 firmware\n");
163 break;
164 case FW_LM86:
165 printk(KERN_INFO "p54: LM86 firmware\n");
166 break;
167 case FW_LM87:
2b80848e 168 printk(KERN_INFO "p54: LM87 firmware\n");
eff1a59c
MW
169 break;
170 default:
171 printk(KERN_INFO "p54: unknown firmware\n");
172 break;
173 }
174 break;
175 case BR_CODE_COMPONENT_VERSION:
176 /* 24 bytes should be enough for all firmwares */
177 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
178 fw_version = (unsigned char*)bootrec->data;
179 break;
4e416a6f
CL
180 case BR_CODE_DESCR: {
181 struct bootrec_desc *desc =
182 (struct bootrec_desc *)bootrec->data;
183 priv->rx_start = le32_to_cpu(desc->rx_start);
eff1a59c 184 /* FIXME add sanity checking */
4e416a6f
CL
185 priv->rx_end = le32_to_cpu(desc->rx_end) - 0x3500;
186 priv->headroom = desc->headroom;
187 priv->tailroom = desc->tailroom;
1f1c0e33 188 if (le32_to_cpu(bootrec->len) == 11)
2e20cc39 189 priv->rx_mtu = le16_to_cpu(desc->rx_mtu);
4e416a6f
CL
190 else
191 priv->rx_mtu = (size_t)
192 0x620 - priv->tx_hdr_len;
eff1a59c 193 break;
4e416a6f 194 }
eff1a59c
MW
195 case BR_CODE_EXPOSED_IF:
196 exp_if = (struct bootrec_exp_if *) bootrec->data;
197 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
dc73c623 198 if (exp_if[i].if_id == cpu_to_le16(0x1a))
eff1a59c
MW
199 priv->fw_var = le16_to_cpu(exp_if[i].variant);
200 break;
201 case BR_CODE_DEPENDENT_IF:
202 break;
203 case BR_CODE_END_OF_BRA:
204 case LEGACY_BR_CODE_END_OF_BRA:
205 end_data = NULL;
206 break;
207 default:
208 break;
209 }
210 bootrec = (struct bootrec *)&bootrec->data[len];
211 }
212
213 if (fw_version)
214 printk(KERN_INFO "p54: FW rev %s - Softmac protocol %x.%x\n",
215 fw_version, priv->fw_var >> 8, priv->fw_var & 0xff);
216
9a8675d7
CL
217 if (priv->fw_var < 0x500)
218 printk(KERN_INFO "p54: you are using an obsolete firmware. "
219 "visit http://wireless.kernel.org/en/users/Drivers/p54 "
220 "and grab one for \"kernel >= 2.6.28\"!\n");
221
eff1a59c
MW
222 if (priv->fw_var >= 0x300) {
223 /* Firmware supports QoS, use it! */
9e7f3f8e
CL
224 priv->tx_stats[4].limit = 3; /* AC_VO */
225 priv->tx_stats[5].limit = 4; /* AC_VI */
226 priv->tx_stats[6].limit = 3; /* AC_BE */
227 priv->tx_stats[7].limit = 2; /* AC_BK */
eff1a59c
MW
228 dev->queues = 4;
229 }
4e416a6f
CL
230
231 return 0;
eff1a59c
MW
232}
233EXPORT_SYMBOL_GPL(p54_parse_firmware);
234
154e3af1
CL
235static int p54_convert_rev0(struct ieee80211_hw *dev,
236 struct pda_pa_curve_data *curve_data)
eff1a59c
MW
237{
238 struct p54_common *priv = dev->priv;
154e3af1
CL
239 struct p54_pa_curve_data_sample *dst;
240 struct pda_pa_curve_data_sample_rev0 *src;
eff1a59c 241 size_t cd_len = sizeof(*curve_data) +
154e3af1 242 (curve_data->points_per_channel*sizeof(*dst) + 2) *
eff1a59c
MW
243 curve_data->channels;
244 unsigned int i, j;
245 void *source, *target;
246
247 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
248 if (!priv->curve_data)
249 return -ENOMEM;
250
251 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
252 source = curve_data->data;
253 target = priv->curve_data->data;
254 for (i = 0; i < curve_data->channels; i++) {
255 __le16 *freq = source;
256 source += sizeof(__le16);
257 *((__le16 *)target) = *freq;
258 target += sizeof(__le16);
259 for (j = 0; j < curve_data->points_per_channel; j++) {
154e3af1
CL
260 dst = target;
261 src = source;
eff1a59c 262
154e3af1
CL
263 dst->rf_power = src->rf_power;
264 dst->pa_detector = src->pa_detector;
265 dst->data_64qam = src->pcv;
eff1a59c
MW
266 /* "invent" the points for the other modulations */
267#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
154e3af1
CL
268 dst->data_16qam = SUB(src->pcv, 12);
269 dst->data_qpsk = SUB(dst->data_16qam, 12);
270 dst->data_bpsk = SUB(dst->data_qpsk, 12);
271 dst->data_barker = SUB(dst->data_bpsk, 14);
eff1a59c 272#undef SUB
154e3af1
CL
273 target += sizeof(*dst);
274 source += sizeof(*src);
eff1a59c
MW
275 }
276 }
277
278 return 0;
279}
280
154e3af1
CL
281static int p54_convert_rev1(struct ieee80211_hw *dev,
282 struct pda_pa_curve_data *curve_data)
283{
284 struct p54_common *priv = dev->priv;
285 struct p54_pa_curve_data_sample *dst;
286 struct pda_pa_curve_data_sample_rev1 *src;
287 size_t cd_len = sizeof(*curve_data) +
288 (curve_data->points_per_channel*sizeof(*dst) + 2) *
289 curve_data->channels;
290 unsigned int i, j;
291 void *source, *target;
292
293 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
294 if (!priv->curve_data)
295 return -ENOMEM;
296
297 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
298 source = curve_data->data;
299 target = priv->curve_data->data;
300 for (i = 0; i < curve_data->channels; i++) {
301 __le16 *freq = source;
302 source += sizeof(__le16);
303 *((__le16 *)target) = *freq;
304 target += sizeof(__le16);
305 for (j = 0; j < curve_data->points_per_channel; j++) {
306 memcpy(target, source, sizeof(*src));
307
308 target += sizeof(*dst);
309 source += sizeof(*src);
310 }
311 source++;
312 }
313
314 return 0;
315}
316
4cc683c9
CL
317static const char *p54_rf_chips[] = { "NULL", "Duette3", "Duette2",
318 "Frisbee", "Xbow", "Longbow", "NULL", "NULL" };
1b997534 319static int p54_init_xbow_synth(struct ieee80211_hw *dev);
7cb77072 320
1f1c0e33 321static int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
eff1a59c
MW
322{
323 struct p54_common *priv = dev->priv;
324 struct eeprom_pda_wrap *wrap = NULL;
325 struct pda_entry *entry;
eff1a59c
MW
326 unsigned int data_len, entry_len;
327 void *tmp;
328 int err;
c2f2d3a0 329 u8 *end = (u8 *)eeprom + len;
f2c2e255 330 u16 synth = 0;
eff1a59c
MW
331
332 wrap = (struct eeprom_pda_wrap *) eeprom;
8c28293f 333 entry = (void *)wrap->data + le16_to_cpu(wrap->len);
c2f2d3a0
JB
334
335 /* verify that at least the entry length/code fits */
336 while ((u8 *)entry <= end - sizeof(*entry)) {
eff1a59c
MW
337 entry_len = le16_to_cpu(entry->len);
338 data_len = ((entry_len - 1) << 1);
c2f2d3a0
JB
339
340 /* abort if entry exceeds whole structure */
341 if ((u8 *)entry + sizeof(*entry) + data_len > end)
342 break;
343
eff1a59c
MW
344 switch (le16_to_cpu(entry->code)) {
345 case PDR_MAC_ADDRESS:
346 SET_IEEE80211_PERM_ADDR(dev, entry->data);
347 break;
348 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
349 if (data_len < 2) {
350 err = -EINVAL;
351 goto err;
352 }
353
354 if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
355 err = -EINVAL;
356 goto err;
357 }
358
359 priv->output_limit = kmalloc(entry->data[1] *
360 sizeof(*priv->output_limit), GFP_KERNEL);
361
362 if (!priv->output_limit) {
363 err = -ENOMEM;
364 goto err;
365 }
366
367 memcpy(priv->output_limit, &entry->data[2],
368 entry->data[1]*sizeof(*priv->output_limit));
369 priv->output_limit_len = entry->data[1];
370 break;
154e3af1
CL
371 case PDR_PRISM_PA_CAL_CURVE_DATA: {
372 struct pda_pa_curve_data *curve_data =
373 (struct pda_pa_curve_data *)entry->data;
374 if (data_len < sizeof(*curve_data)) {
eff1a59c
MW
375 err = -EINVAL;
376 goto err;
377 }
378
154e3af1
CL
379 switch (curve_data->cal_method_rev) {
380 case 0:
381 err = p54_convert_rev0(dev, curve_data);
382 break;
383 case 1:
384 err = p54_convert_rev1(dev, curve_data);
385 break;
386 default:
387 printk(KERN_ERR "p54: unknown curve data "
388 "revision %d\n",
389 curve_data->cal_method_rev);
390 err = -ENODEV;
391 break;
eff1a59c 392 }
154e3af1
CL
393 if (err)
394 goto err;
eff1a59c 395
154e3af1 396 }
eff1a59c
MW
397 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
398 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
399 if (!priv->iq_autocal) {
400 err = -ENOMEM;
401 goto err;
402 }
403
404 memcpy(priv->iq_autocal, entry->data, data_len);
405 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
406 break;
407 case PDR_INTERFACE_LIST:
408 tmp = entry->data;
409 while ((u8 *)tmp < entry->data + data_len) {
410 struct bootrec_exp_if *exp_if = tmp;
4cc683c9
CL
411 if (le16_to_cpu(exp_if->if_id) == 0xf)
412 synth = le16_to_cpu(exp_if->variant);
eff1a59c
MW
413 tmp += sizeof(struct bootrec_exp_if);
414 }
415 break;
416 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
417 priv->version = *(u8 *)(entry->data + 1);
418 break;
419 case PDR_END:
c2f2d3a0
JB
420 /* make it overrun */
421 entry_len = len;
eff1a59c 422 break;
58e30739
FF
423 default:
424 printk(KERN_INFO "p54: unknown eeprom code : 0x%x\n",
425 le16_to_cpu(entry->code));
426 break;
eff1a59c
MW
427 }
428
429 entry = (void *)entry + (entry_len + 1)*2;
eff1a59c
MW
430 }
431
f2c2e255
CL
432 if (!synth || !priv->iq_autocal || !priv->output_limit ||
433 !priv->curve_data) {
eff1a59c
MW
434 printk(KERN_ERR "p54: not all required entries found in eeprom!\n");
435 err = -EINVAL;
436 goto err;
437 }
438
9e7f3f8e 439 priv->rxhw = synth & PDR_SYNTH_FRONTEND_MASK;
4cc683c9 440 if (priv->rxhw == 4)
1b997534 441 p54_init_xbow_synth(dev);
9e7f3f8e 442 if (!(synth & PDR_SYNTH_24_GHZ_DISABLED))
1b997534 443 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz;
9e7f3f8e 444 if (!(synth & PDR_SYNTH_5_GHZ_DISABLED))
4cc683c9 445 dev->wiphy->bands[IEEE80211_BAND_5GHZ] = &band_5GHz;
7cb77072
CL
446
447 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
448 u8 perm_addr[ETH_ALEN];
449
450 printk(KERN_WARNING "%s: Invalid hwaddr! Using randomly generated MAC addr\n",
451 wiphy_name(dev->wiphy));
452 random_ether_addr(perm_addr);
453 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
454 }
455
e174961c 456 printk(KERN_INFO "%s: hwaddr %pM, MAC:isl38%02x RF:%s\n",
7cb77072 457 wiphy_name(dev->wiphy),
e174961c 458 dev->wiphy->perm_addr,
7cb77072
CL
459 priv->version, p54_rf_chips[priv->rxhw]);
460
eff1a59c
MW
461 return 0;
462
463 err:
464 if (priv->iq_autocal) {
465 kfree(priv->iq_autocal);
466 priv->iq_autocal = NULL;
467 }
468
469 if (priv->output_limit) {
470 kfree(priv->output_limit);
471 priv->output_limit = NULL;
472 }
473
474 if (priv->curve_data) {
475 kfree(priv->curve_data);
476 priv->curve_data = NULL;
477 }
478
479 printk(KERN_ERR "p54: eeprom parse failed!\n");
480 return err;
481}
eff1a59c 482
cc6de669
CL
483static int p54_rssi_to_dbm(struct ieee80211_hw *dev, int rssi)
484{
485 /* TODO: get the rssi_add & rssi_mul data from the eeprom */
486 return ((rssi * 0x83) / 64 - 400) / 4;
487}
488
19c19d54 489static int p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 490{
a0db663f 491 struct p54_common *priv = dev->priv;
27df605e 492 struct p54_rx_data *hdr = (struct p54_rx_data *) skb->data;
eff1a59c
MW
493 struct ieee80211_rx_status rx_status = {0};
494 u16 freq = le16_to_cpu(hdr->freq);
19c19d54 495 size_t header_len = sizeof(*hdr);
a0db663f 496 u32 tsf32;
eff1a59c 497
27df605e 498 if (!(hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_IN_FCS_GOOD))) {
78d57eb2
CL
499 if (priv->filter_flags & FIF_FCSFAIL)
500 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
501 else
502 return 0;
503 }
504
cc6de669
CL
505 rx_status.signal = p54_rssi_to_dbm(dev, hdr->rssi);
506 rx_status.noise = priv->noise;
8318d78a 507 /* XX correct? */
18d72605 508 rx_status.qual = (100 * hdr->rssi) / 127;
cf3e74c2
CL
509 rx_status.rate_idx = (dev->conf.channel->band == IEEE80211_BAND_2GHZ ?
510 hdr->rate : (hdr->rate - 4)) & 0xf;
eff1a59c 511 rx_status.freq = freq;
cf3e74c2 512 rx_status.band = dev->conf.channel->band;
eff1a59c 513 rx_status.antenna = hdr->antenna;
a0db663f
CL
514
515 tsf32 = le32_to_cpu(hdr->tsf32);
516 if (tsf32 < priv->tsf_low32)
517 priv->tsf_high32++;
518 rx_status.mactime = ((u64)priv->tsf_high32) << 32 | tsf32;
519 priv->tsf_low32 = tsf32;
520
03bffc13 521 rx_status.flag |= RX_FLAG_TSFT;
eff1a59c 522
27df605e 523 if (hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_ALIGN))
19c19d54
CL
524 header_len += hdr->align[0];
525
526 skb_pull(skb, header_len);
eff1a59c
MW
527 skb_trim(skb, le16_to_cpu(hdr->len));
528
529 ieee80211_rx_irqsafe(dev, skb, &rx_status);
19c19d54
CL
530
531 return -1;
eff1a59c
MW
532}
533
534static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
535{
536 struct p54_common *priv = dev->priv;
537 int i;
538
b92f30d6
CL
539 if (priv->mode == NL80211_IFTYPE_UNSPECIFIED)
540 return ;
541
eff1a59c 542 for (i = 0; i < dev->queues; i++)
84df3ed3 543 if (priv->tx_stats[i + 4].len < priv->tx_stats[i + 4].limit)
eff1a59c
MW
544 ieee80211_wake_queue(dev, i);
545}
546
b92f30d6
CL
547void p54_free_skb(struct ieee80211_hw *dev, struct sk_buff *skb)
548{
549 struct p54_common *priv = dev->priv;
550 struct ieee80211_tx_info *info;
551 struct memrecord *range;
552 unsigned long flags;
553 u32 freed = 0, last_addr = priv->rx_start;
554
555 if (!skb || !dev)
556 return;
557
558 spin_lock_irqsave(&priv->tx_queue.lock, flags);
559 info = IEEE80211_SKB_CB(skb);
560 range = (void *)info->rate_driver_data;
561 if (skb->prev != (struct sk_buff *)&priv->tx_queue) {
562 struct ieee80211_tx_info *ni;
563 struct memrecord *mr;
564
565 ni = IEEE80211_SKB_CB(skb->prev);
566 mr = (struct memrecord *)ni->rate_driver_data;
567 last_addr = mr->end_addr;
568 }
569 if (skb->next != (struct sk_buff *)&priv->tx_queue) {
570 struct ieee80211_tx_info *ni;
571 struct memrecord *mr;
572
573 ni = IEEE80211_SKB_CB(skb->next);
574 mr = (struct memrecord *)ni->rate_driver_data;
575 freed = mr->start_addr - last_addr;
576 } else
577 freed = priv->rx_end - last_addr;
578 __skb_unlink(skb, &priv->tx_queue);
579 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
580 kfree_skb(skb);
581
27df605e 582 if (freed >= priv->headroom + sizeof(struct p54_hdr) + 48 +
b92f30d6
CL
583 IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
584 p54_wake_free_queues(dev);
585}
586EXPORT_SYMBOL_GPL(p54_free_skb);
587
eff1a59c
MW
588static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
589{
590 struct p54_common *priv = dev->priv;
27df605e
JL
591 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
592 struct p54_frame_sent *payload = (struct p54_frame_sent *) hdr->data;
eff1a59c 593 struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
4e416a6f 594 u32 addr = le32_to_cpu(hdr->req_id) - priv->headroom;
eff1a59c
MW
595 struct memrecord *range = NULL;
596 u32 freed = 0;
597 u32 last_addr = priv->rx_start;
031d10ee 598 unsigned long flags;
c12abae3 599 int count, idx;
eff1a59c 600
031d10ee 601 spin_lock_irqsave(&priv->tx_queue.lock, flags);
eff1a59c 602 while (entry != (struct sk_buff *)&priv->tx_queue) {
552fe53f 603 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
27df605e
JL
604 struct p54_hdr *entry_hdr;
605 struct p54_tx_data *entry_data;
9de5776f 606 int pad = 0;
eff1a59c 607
9de5776f
CL
608 range = (void *)info->rate_driver_data;
609 if (range->start_addr != addr) {
610 last_addr = range->end_addr;
611 entry = entry->next;
612 continue;
613 }
552fe53f 614
9de5776f
CL
615 if (entry->next != (struct sk_buff *)&priv->tx_queue) {
616 struct ieee80211_tx_info *ni;
617 struct memrecord *mr;
eff1a59c 618
9de5776f
CL
619 ni = IEEE80211_SKB_CB(entry->next);
620 mr = (struct memrecord *)ni->rate_driver_data;
621 freed = mr->start_addr - last_addr;
622 } else
623 freed = priv->rx_end - last_addr;
624
625 last_addr = range->end_addr;
626 __skb_unlink(entry, &priv->tx_queue);
627 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
628
629 /*
630 * Clear manually, ieee80211_tx_info_clear_status would
631 * clear the counts too and we need them.
632 */
633 memset(&info->status.ampdu_ack_len, 0,
634 sizeof(struct ieee80211_tx_info) -
635 offsetof(struct ieee80211_tx_info, status.ampdu_ack_len));
636 BUILD_BUG_ON(offsetof(struct ieee80211_tx_info,
637 status.ampdu_ack_len) != 23);
638
27df605e
JL
639 entry_hdr = (struct p54_hdr *) entry->data;
640 entry_data = (struct p54_tx_data *) entry_hdr->data;
641 if (entry_hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_ALIGN))
9de5776f
CL
642 pad = entry_data->align[0];
643
644 /* walk through the rates array and adjust the counts */
27df605e 645 count = payload->tries;
9de5776f
CL
646 for (idx = 0; idx < 4; idx++) {
647 if (count >= info->status.rates[idx].count) {
648 count -= info->status.rates[idx].count;
649 } else if (count > 0) {
650 info->status.rates[idx].count = count;
651 count = 0;
652 } else {
653 info->status.rates[idx].idx = -1;
654 info->status.rates[idx].count = 0;
eff1a59c 655 }
9de5776f 656 }
c12abae3 657
9de5776f
CL
658 priv->tx_stats[entry_data->hw_queue].len--;
659 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
660 (!payload->status))
661 info->flags |= IEEE80211_TX_STAT_ACK;
9e7f3f8e 662 if (payload->status & P54_TX_PSM_CANCELLED)
9de5776f
CL
663 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
664 info->status.ack_signal = p54_rssi_to_dbm(dev,
27df605e 665 (int)payload->ack_rssi);
9de5776f
CL
666 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
667 ieee80211_tx_status_irqsafe(dev, entry);
668 goto out;
eff1a59c 669 }
031d10ee 670 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
eff1a59c 671
031d10ee 672out:
27df605e 673 if (freed >= priv->headroom + sizeof(struct p54_hdr) + 48 +
9de5776f 674 IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
eff1a59c
MW
675 p54_wake_free_queues(dev);
676}
677
7cb77072
CL
678static void p54_rx_eeprom_readback(struct ieee80211_hw *dev,
679 struct sk_buff *skb)
680{
27df605e 681 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
7cb77072
CL
682 struct p54_eeprom_lm86 *eeprom = (struct p54_eeprom_lm86 *) hdr->data;
683 struct p54_common *priv = dev->priv;
684
685 if (!priv->eeprom)
686 return ;
687
1f1c0e33 688 memcpy(priv->eeprom, eeprom->data, le16_to_cpu(eeprom->len));
7cb77072
CL
689
690 complete(&priv->eeprom_comp);
691}
692
cc6de669
CL
693static void p54_rx_stats(struct ieee80211_hw *dev, struct sk_buff *skb)
694{
695 struct p54_common *priv = dev->priv;
27df605e 696 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
cc6de669
CL
697 struct p54_statistics *stats = (struct p54_statistics *) hdr->data;
698 u32 tsf32 = le32_to_cpu(stats->tsf32);
699
700 if (tsf32 < priv->tsf_low32)
701 priv->tsf_high32++;
702 priv->tsf_low32 = tsf32;
703
704 priv->stats.dot11RTSFailureCount = le32_to_cpu(stats->rts_fail);
705 priv->stats.dot11RTSSuccessCount = le32_to_cpu(stats->rts_success);
706 priv->stats.dot11FCSErrorCount = le32_to_cpu(stats->rx_bad_fcs);
707
708 priv->noise = p54_rssi_to_dbm(dev, le32_to_cpu(stats->noise));
709 complete(&priv->stats_comp);
710
711 mod_timer(&priv->stats_timer, jiffies + 5 * HZ);
712}
713
19c19d54 714static int p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 715{
27df605e 716 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
eff1a59c
MW
717
718 switch (le16_to_cpu(hdr->type)) {
719 case P54_CONTROL_TYPE_TXDONE:
720 p54_rx_frame_sent(dev, skb);
721 break;
722 case P54_CONTROL_TYPE_BBP:
723 break;
cc6de669
CL
724 case P54_CONTROL_TYPE_STAT_READBACK:
725 p54_rx_stats(dev, skb);
726 break;
7cb77072
CL
727 case P54_CONTROL_TYPE_EEPROM_READBACK:
728 p54_rx_eeprom_readback(dev, skb);
729 break;
eff1a59c
MW
730 default:
731 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
732 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
733 break;
734 }
19c19d54
CL
735
736 return 0;
eff1a59c
MW
737}
738
739/* returns zero if skb can be reused */
740int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
741{
9e7f3f8e 742 u16 type = le16_to_cpu(*((__le16 *)skb->data));
19c19d54 743
9e7f3f8e 744 if (type & P54_HDR_FLAG_CONTROL)
19c19d54
CL
745 return p54_rx_control(dev, skb);
746 else
747 return p54_rx_data(dev, skb);
eff1a59c
MW
748}
749EXPORT_SYMBOL_GPL(p54_rx);
750
751/*
752 * So, the firmware is somewhat stupid and doesn't know what places in its
753 * memory incoming data should go to. By poking around in the firmware, we
754 * can find some unused memory to upload our packets to. However, data that we
755 * want the card to TX needs to stay intact until the card has told us that
756 * it is done with it. This function finds empty places we can upload to and
757 * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
758 * allocated areas.
759 */
b92f30d6 760static int p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
27df605e 761 struct p54_hdr *data, u32 len)
eff1a59c
MW
762{
763 struct p54_common *priv = dev->priv;
764 struct sk_buff *entry = priv->tx_queue.next;
765 struct sk_buff *target_skb = NULL;
b92f30d6
CL
766 struct ieee80211_tx_info *info;
767 struct memrecord *range;
eff1a59c
MW
768 u32 last_addr = priv->rx_start;
769 u32 largest_hole = 0;
770 u32 target_addr = priv->rx_start;
771 unsigned long flags;
772 unsigned int left;
4e416a6f 773 len = (len + priv->headroom + priv->tailroom + 3) & ~0x3;
eff1a59c 774
b92f30d6
CL
775 if (!skb)
776 return -EINVAL;
777
eff1a59c
MW
778 spin_lock_irqsave(&priv->tx_queue.lock, flags);
779 left = skb_queue_len(&priv->tx_queue);
780 while (left--) {
781 u32 hole_size;
b92f30d6
CL
782 info = IEEE80211_SKB_CB(entry);
783 range = (void *)info->rate_driver_data;
eff1a59c
MW
784 hole_size = range->start_addr - last_addr;
785 if (!target_skb && hole_size >= len) {
786 target_skb = entry->prev;
787 hole_size -= len;
788 target_addr = last_addr;
789 }
790 largest_hole = max(largest_hole, hole_size);
791 last_addr = range->end_addr;
792 entry = entry->next;
793 }
794 if (!target_skb && priv->rx_end - last_addr >= len) {
795 target_skb = priv->tx_queue.prev;
796 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
797 if (!skb_queue_empty(&priv->tx_queue)) {
b92f30d6
CL
798 info = IEEE80211_SKB_CB(target_skb);
799 range = (void *)info->rate_driver_data;
eff1a59c
MW
800 target_addr = range->end_addr;
801 }
802 } else
803 largest_hole = max(largest_hole, priv->rx_end - last_addr);
804
b92f30d6
CL
805 if (!target_skb) {
806 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
807 ieee80211_stop_queues(dev);
808 return -ENOMEM;
eff1a59c 809 }
b92f30d6
CL
810
811 info = IEEE80211_SKB_CB(skb);
812 range = (void *)info->rate_driver_data;
813 range->start_addr = target_addr;
814 range->end_addr = target_addr + len;
815 __skb_queue_after(&priv->tx_queue, target_skb, skb);
eff1a59c
MW
816 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
817
27df605e 818 if (largest_hole < priv->headroom + sizeof(struct p54_hdr) +
b92f30d6
CL
819 48 + IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
820 ieee80211_stop_queues(dev);
821
4e416a6f 822 data->req_id = cpu_to_le32(target_addr + priv->headroom);
b92f30d6
CL
823 return 0;
824}
825
826static struct sk_buff *p54_alloc_skb(struct ieee80211_hw *dev,
827 u16 hdr_flags, u16 len, u16 type, gfp_t memflags)
828{
829 struct p54_common *priv = dev->priv;
27df605e 830 struct p54_hdr *hdr;
b92f30d6
CL
831 struct sk_buff *skb;
832
833 skb = __dev_alloc_skb(len + priv->tx_hdr_len, memflags);
834 if (!skb)
835 return NULL;
836 skb_reserve(skb, priv->tx_hdr_len);
837
27df605e
JL
838 hdr = (struct p54_hdr *) skb_put(skb, sizeof(*hdr));
839 hdr->flags = cpu_to_le16(hdr_flags);
b92f30d6
CL
840 hdr->len = cpu_to_le16(len - sizeof(*hdr));
841 hdr->type = cpu_to_le16(type);
27df605e 842 hdr->tries = hdr->rts_tries = 0;
b92f30d6
CL
843
844 if (unlikely(p54_assign_address(dev, skb, hdr, len))) {
845 kfree_skb(skb);
846 return NULL;
847 }
848 return skb;
eff1a59c
MW
849}
850
7cb77072
CL
851int p54_read_eeprom(struct ieee80211_hw *dev)
852{
853 struct p54_common *priv = dev->priv;
27df605e 854 struct p54_hdr *hdr = NULL;
7cb77072 855 struct p54_eeprom_lm86 *eeprom_hdr;
b92f30d6 856 struct sk_buff *skb;
7cb77072
CL
857 size_t eeprom_size = 0x2020, offset = 0, blocksize;
858 int ret = -ENOMEM;
859 void *eeprom = NULL;
860
b92f30d6
CL
861 skb = p54_alloc_skb(dev, 0x8000, sizeof(*hdr) + sizeof(*eeprom_hdr) +
862 EEPROM_READBACK_LEN,
863 P54_CONTROL_TYPE_EEPROM_READBACK, GFP_KERNEL);
864 if (!skb)
7cb77072 865 goto free;
7cb77072
CL
866 priv->eeprom = kzalloc(EEPROM_READBACK_LEN, GFP_KERNEL);
867 if (!priv->eeprom)
868 goto free;
7cb77072
CL
869 eeprom = kzalloc(eeprom_size, GFP_KERNEL);
870 if (!eeprom)
871 goto free;
872
b92f30d6
CL
873 eeprom_hdr = (struct p54_eeprom_lm86 *) skb_put(skb,
874 sizeof(*eeprom_hdr) + EEPROM_READBACK_LEN);
7cb77072
CL
875
876 while (eeprom_size) {
877 blocksize = min(eeprom_size, (size_t)EEPROM_READBACK_LEN);
7cb77072
CL
878 eeprom_hdr->offset = cpu_to_le16(offset);
879 eeprom_hdr->len = cpu_to_le16(blocksize);
b92f30d6 880 priv->tx(dev, skb, 0);
7cb77072
CL
881
882 if (!wait_for_completion_interruptible_timeout(&priv->eeprom_comp, HZ)) {
883 printk(KERN_ERR "%s: device does not respond!\n",
884 wiphy_name(dev->wiphy));
885 ret = -EBUSY;
886 goto free;
887 }
888
889 memcpy(eeprom + offset, priv->eeprom, blocksize);
890 offset += blocksize;
891 eeprom_size -= blocksize;
892 }
893
894 ret = p54_parse_eeprom(dev, eeprom, offset);
895free:
896 kfree(priv->eeprom);
897 priv->eeprom = NULL;
b92f30d6 898 p54_free_skb(dev, skb);
7cb77072
CL
899 kfree(eeprom);
900
901 return ret;
902}
903EXPORT_SYMBOL_GPL(p54_read_eeprom);
904
e039fa4a 905static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 906{
e039fa4a 907 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
9e7f3f8e 908 struct ieee80211_tx_queue_stats *current_queue = NULL;
eff1a59c 909 struct p54_common *priv = dev->priv;
27df605e
JL
910 struct p54_hdr *hdr;
911 struct p54_tx_data *txhdr;
eff1a59c 912 size_t padding, len;
c12abae3 913 int i, j, ridx;
9e7f3f8e 914 u16 hdr_flags = 0;
eff1a59c 915 u8 rate;
aaa15535 916 u8 cts_rate = 0x20;
e6a9854b 917 u8 rc_flags;
c12abae3
JB
918 u8 calculated_tries[4];
919 u8 nrates = 0, nremaining = 8;
eff1a59c 920
84df3ed3 921 current_queue = &priv->tx_stats[skb_get_queue_mapping(skb) + 4];
eff1a59c
MW
922 if (unlikely(current_queue->len > current_queue->limit))
923 return NETDEV_TX_BUSY;
924 current_queue->len++;
925 current_queue->count++;
926 if (current_queue->len == current_queue->limit)
e2530083 927 ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
eff1a59c
MW
928
929 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
930 len = skb->len;
931
27df605e
JL
932 txhdr = (struct p54_tx_data *) skb_push(skb, sizeof(*txhdr) + padding);
933 hdr = (struct p54_hdr *) skb_push(skb, sizeof(*hdr));
eff1a59c
MW
934
935 if (padding)
9e7f3f8e 936 hdr_flags |= P54_HDR_FLAG_DATA_ALIGN;
eff1a59c 937 hdr->len = cpu_to_le16(len);
e039fa4a 938 hdr->type = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 0 : cpu_to_le16(1);
27df605e 939 hdr->rts_tries = info->control.rates[0].count;
c12abae3
JB
940
941 /*
942 * we register the rates in perfect order, and
943 * RTS/CTS won't happen on 5 GHz
944 */
945 cts_rate = info->control.rts_cts_rate_idx;
946
947 memset(&txhdr->rateset, 0, sizeof(txhdr->rateset));
948
949 /* see how many rates got used */
950 for (i = 0; i < 4; i++) {
951 if (info->control.rates[i].idx < 0)
952 break;
953 nrates++;
954 }
955
956 /* limit tries to 8/nrates per rate */
957 for (i = 0; i < nrates; i++) {
958 /*
959 * The magic expression here is equivalent to 8/nrates for
960 * all values that matter, but avoids division and jumps.
961 * Note that nrates can only take the values 1 through 4.
962 */
963 calculated_tries[i] = min_t(int, ((15 >> nrates) | 1) + 1,
964 info->control.rates[i].count);
965 nremaining -= calculated_tries[i];
aaa15535 966 }
c12abae3
JB
967
968 /* if there are tries left, distribute from back to front */
969 for (i = nrates - 1; nremaining > 0 && i >= 0; i--) {
970 int tmp = info->control.rates[i].count - calculated_tries[i];
971
972 if (tmp <= 0)
973 continue;
974 /* RC requested more tries at this rate */
975
976 tmp = min_t(int, tmp, nremaining);
977 calculated_tries[i] += tmp;
978 nremaining -= tmp;
aaa15535 979 }
c12abae3
JB
980
981 ridx = 0;
982 for (i = 0; i < nrates && ridx < 8; i++) {
983 /* we register the rates in perfect order */
984 rate = info->control.rates[i].idx;
985 if (info->band == IEEE80211_BAND_5GHZ)
986 rate += 4;
987
988 /* store the count we actually calculated for TX status */
989 info->control.rates[i].count = calculated_tries[i];
990
991 rc_flags = info->control.rates[i].flags;
992 if (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) {
993 rate |= 0x10;
994 cts_rate |= 0x10;
995 }
996 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
997 rate |= 0x40;
998 else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
999 rate |= 0x20;
1000 for (j = 0; j < calculated_tries[i] && ridx < 8; j++) {
1001 txhdr->rateset[ridx] = rate;
1002 ridx++;
1003 }
1004 }
9e7f3f8e
CL
1005
1006 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
1007 hdr_flags |= P54_HDR_FLAG_DATA_OUT_SEQNR;
1008
1009 /* TODO: enable bursting */
1010 hdr->flags = cpu_to_le16(hdr_flags);
27df605e
JL
1011 hdr->tries = ridx;
1012 txhdr->crypt_offset = 0;
1013 txhdr->rts_rate_idx = 0;
aaa15535
CL
1014 txhdr->key_type = 0;
1015 txhdr->key_len = 0;
1016 txhdr->hw_queue = skb_get_queue_mapping(skb) + 4;
27df605e
JL
1017 txhdr->backlog = 32;
1018 memset(txhdr->durations, 0, sizeof(txhdr->durations));
aaa15535 1019 txhdr->tx_antenna = (info->antenna_sel_tx == 0) ?
e039fa4a 1020 2 : info->antenna_sel_tx - 1;
09adf284 1021 txhdr->output_power = priv->output_power;
27df605e 1022 txhdr->cts_rate = cts_rate;
eff1a59c
MW
1023 if (padding)
1024 txhdr->align[0] = padding;
1025
e039fa4a 1026 /* modifies skb->cb and with it info, so must be last! */
b92f30d6
CL
1027 if (unlikely(p54_assign_address(dev, skb, hdr, skb->len))) {
1028 skb_pull(skb, sizeof(*hdr) + sizeof(*txhdr) + padding);
9e7f3f8e
CL
1029 if (current_queue) {
1030 current_queue->len--;
1031 current_queue->count--;
1032 }
b92f30d6
CL
1033 return NETDEV_TX_BUSY;
1034 }
1035 priv->tx(dev, skb, 0);
eff1a59c
MW
1036 return 0;
1037}
1038
5e73444e 1039static int p54_setup_mac(struct ieee80211_hw *dev, u16 mode, const u8 *bssid)
eff1a59c
MW
1040{
1041 struct p54_common *priv = dev->priv;
b92f30d6 1042 struct sk_buff *skb;
5e73444e 1043 struct p54_setup_mac *setup;
eff1a59c 1044
27df605e
JL
1045 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*setup) +
1046 sizeof(struct p54_hdr), P54_CONTROL_TYPE_SETUP,
b92f30d6
CL
1047 GFP_ATOMIC);
1048 if (!skb)
1049 return -ENOMEM;
eff1a59c 1050
5e73444e
CL
1051 setup = (struct p54_setup_mac *) skb_put(skb, sizeof(*setup));
1052 priv->mac_mode = mode;
1053 setup->mac_mode = cpu_to_le16(mode);
1054 memcpy(setup->mac_addr, priv->mac_addr, ETH_ALEN);
e0a58eac 1055 if (!bssid)
5e73444e 1056 memset(setup->bssid, ~0, ETH_ALEN);
eff1a59c 1057 else
5e73444e
CL
1058 memcpy(setup->bssid, bssid, ETH_ALEN);
1059 setup->rx_antenna = priv->rx_antenna;
19c19d54 1060 if (priv->fw_var < 0x500) {
5e73444e
CL
1061 setup->v1.basic_rate_mask = cpu_to_le32(0x15f);
1062 setup->v1.rx_addr = cpu_to_le32(priv->rx_end);
1063 setup->v1.max_rx = cpu_to_le16(priv->rx_mtu);
1064 setup->v1.rxhw = cpu_to_le16(priv->rxhw);
1065 setup->v1.wakeup_timer = cpu_to_le16(500);
1066 setup->v1.unalloc0 = cpu_to_le16(0);
19c19d54 1067 } else {
5e73444e
CL
1068 setup->v2.rx_addr = cpu_to_le32(priv->rx_end);
1069 setup->v2.max_rx = cpu_to_le16(priv->rx_mtu);
1070 setup->v2.rxhw = cpu_to_le16(priv->rxhw);
1071 setup->v2.timer = cpu_to_le16(1000);
1072 setup->v2.truncate = cpu_to_le16(48896);
1073 setup->v2.basic_rate_mask = cpu_to_le32(0x15f);
1074 setup->v2.sbss_offset = 0;
1075 setup->v2.mcast_window = 0;
1076 setup->v2.rx_rssi_threshold = 0;
1077 setup->v2.rx_ed_threshold = 0;
1078 setup->v2.ref_clock = cpu_to_le32(644245094);
1079 setup->v2.lpf_bandwidth = cpu_to_le16(65535);
1080 setup->v2.osc_start_delay = cpu_to_le16(65535);
19c19d54 1081 }
b92f30d6 1082 priv->tx(dev, skb, 1);
eff1a59c
MW
1083 return 0;
1084}
1085
9e7f3f8e 1086static int p54_set_freq(struct ieee80211_hw *dev, u16 frequency)
eff1a59c
MW
1087{
1088 struct p54_common *priv = dev->priv;
b92f30d6 1089 struct sk_buff *skb;
27df605e 1090 struct p54_scan *chan;
eff1a59c 1091 unsigned int i;
eff1a59c 1092 void *entry;
9e7f3f8e 1093 __le16 freq = cpu_to_le16(frequency);
eff1a59c 1094
27df605e
JL
1095 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*chan) +
1096 sizeof(struct p54_hdr), P54_CONTROL_TYPE_SCAN,
1097 GFP_ATOMIC);
b92f30d6 1098 if (!skb)
eff1a59c
MW
1099 return -ENOMEM;
1100
27df605e 1101 chan = (struct p54_scan *) skb_put(skb, sizeof(*chan));
b92f30d6 1102 memset(chan->padding1, 0, sizeof(chan->padding1));
27df605e 1103 chan->mode = cpu_to_le16(P54_SCAN_EXIT);
154e3af1 1104 chan->dwell = cpu_to_le16(0x0);
eff1a59c
MW
1105
1106 for (i = 0; i < priv->iq_autocal_len; i++) {
1107 if (priv->iq_autocal[i].freq != freq)
1108 continue;
1109
1110 memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
1111 sizeof(*priv->iq_autocal));
1112 break;
1113 }
1114 if (i == priv->iq_autocal_len)
1115 goto err;
1116
1117 for (i = 0; i < priv->output_limit_len; i++) {
1118 if (priv->output_limit[i].freq != freq)
1119 continue;
1120
1121 chan->val_barker = 0x38;
154e3af1
CL
1122 chan->val_bpsk = chan->dup_bpsk =
1123 priv->output_limit[i].val_bpsk;
1124 chan->val_qpsk = chan->dup_qpsk =
1125 priv->output_limit[i].val_qpsk;
1126 chan->val_16qam = chan->dup_16qam =
1127 priv->output_limit[i].val_16qam;
1128 chan->val_64qam = chan->dup_64qam =
1129 priv->output_limit[i].val_64qam;
eff1a59c
MW
1130 break;
1131 }
1132 if (i == priv->output_limit_len)
1133 goto err;
1134
eff1a59c
MW
1135 entry = priv->curve_data->data;
1136 for (i = 0; i < priv->curve_data->channels; i++) {
1137 if (*((__le16 *)entry) != freq) {
1138 entry += sizeof(__le16);
154e3af1
CL
1139 entry += sizeof(struct p54_pa_curve_data_sample) *
1140 priv->curve_data->points_per_channel;
eff1a59c
MW
1141 continue;
1142 }
1143
1144 entry += sizeof(__le16);
154e3af1
CL
1145 chan->pa_points_per_curve =
1146 min(priv->curve_data->points_per_channel, (u8) 8);
1147
eff1a59c
MW
1148 memcpy(chan->curve_data, entry, sizeof(*chan->curve_data) *
1149 chan->pa_points_per_curve);
1150 break;
1151 }
1152
19c19d54 1153 if (priv->fw_var < 0x500) {
19c19d54
CL
1154 chan->v1.rssical_mul = cpu_to_le16(130);
1155 chan->v1.rssical_add = cpu_to_le16(0xfe70);
1156 } else {
19c19d54
CL
1157 chan->v2.rssical_mul = cpu_to_le16(130);
1158 chan->v2.rssical_add = cpu_to_le16(0xfe70);
1159 chan->v2.basic_rate_mask = cpu_to_le32(0x15f);
27df605e 1160 memset(chan->v2.rts_rates, 0, 8);
19c19d54 1161 }
b92f30d6 1162 priv->tx(dev, skb, 1);
eff1a59c
MW
1163 return 0;
1164
1165 err:
1166 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
b92f30d6 1167 kfree_skb(skb);
eff1a59c
MW
1168 return -EINVAL;
1169}
1170
1171static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
1172{
1173 struct p54_common *priv = dev->priv;
b92f30d6 1174 struct sk_buff *skb;
27df605e 1175 struct p54_led *led;
eff1a59c 1176
27df605e
JL
1177 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*led) +
1178 sizeof(struct p54_hdr), P54_CONTROL_TYPE_LED,
1179 GFP_ATOMIC);
b92f30d6 1180 if (!skb)
eff1a59c
MW
1181 return -ENOMEM;
1182
27df605e 1183 led = (struct p54_led *)skb_put(skb, sizeof(*led));
eff1a59c
MW
1184 led->mode = cpu_to_le16(mode);
1185 led->led_permanent = cpu_to_le16(link);
1186 led->led_temporary = cpu_to_le16(act);
1187 led->duration = cpu_to_le16(1000);
b92f30d6 1188 priv->tx(dev, skb, 1);
eff1a59c
MW
1189 return 0;
1190}
1191
3330d7be 1192#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \
eff1a59c
MW
1193do { \
1194 queue.aifs = cpu_to_le16(ai_fs); \
1195 queue.cwmin = cpu_to_le16(cw_min); \
1196 queue.cwmax = cpu_to_le16(cw_max); \
3330d7be 1197 queue.txop = cpu_to_le16(_txop); \
eff1a59c
MW
1198} while(0)
1199
0fdd7c5d 1200static int p54_set_edcf(struct ieee80211_hw *dev)
eff1a59c
MW
1201{
1202 struct p54_common *priv = dev->priv;
b92f30d6 1203 struct sk_buff *skb;
0fdd7c5d 1204 struct p54_edcf *edcf;
eff1a59c 1205
27df605e
JL
1206 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*edcf) +
1207 sizeof(struct p54_hdr), P54_CONTROL_TYPE_DCFINIT,
1208 GFP_ATOMIC);
b92f30d6 1209 if (!skb)
0fdd7c5d
CL
1210 return -ENOMEM;
1211
b92f30d6 1212 edcf = (struct p54_edcf *)skb_put(skb, sizeof(*edcf));
40333e4f 1213 if (priv->use_short_slot) {
0fdd7c5d
CL
1214 edcf->slottime = 9;
1215 edcf->sifs = 0x10;
1216 edcf->eofpad = 0x00;
eff1a59c 1217 } else {
0fdd7c5d
CL
1218 edcf->slottime = 20;
1219 edcf->sifs = 0x0a;
1220 edcf->eofpad = 0x06;
eff1a59c 1221 }
eff1a59c 1222 /* (see prism54/isl_oid.h for further details) */
0fdd7c5d
CL
1223 edcf->frameburst = cpu_to_le16(0);
1224 edcf->round_trip_delay = cpu_to_le16(0);
1225 memset(edcf->mapping, 0, sizeof(edcf->mapping));
1226 memcpy(edcf->queue, priv->qos_params, sizeof(edcf->queue));
b92f30d6 1227 priv->tx(dev, skb, 1);
0fdd7c5d 1228 return 0;
eff1a59c
MW
1229}
1230
0f1be978 1231static int p54_init_stats(struct ieee80211_hw *dev)
4150c572
JB
1232{
1233 struct p54_common *priv = dev->priv;
cc6de669 1234
27df605e
JL
1235 priv->cached_stats = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL,
1236 sizeof(struct p54_hdr) + sizeof(struct p54_statistics),
1237 P54_CONTROL_TYPE_STAT_READBACK, GFP_KERNEL);
0f1be978 1238 if (!priv->cached_stats)
cc6de669 1239 return -ENOMEM;
0f1be978 1240
0f1be978
CL
1241 mod_timer(&priv->stats_timer, jiffies + HZ);
1242 return 0;
1243}
1244
1245static int p54_start(struct ieee80211_hw *dev)
1246{
1247 struct p54_common *priv = dev->priv;
1248 int err;
cc6de669 1249
9e7f3f8e 1250 mutex_lock(&priv->conf_mutex);
4150c572
JB
1251 err = priv->open(dev);
1252 if (!err)
05c914fe 1253 priv->mode = NL80211_IFTYPE_MONITOR;
0fdd7c5d
CL
1254 P54_SET_QUEUE(priv->qos_params[0], 0x0002, 0x0003, 0x0007, 47);
1255 P54_SET_QUEUE(priv->qos_params[1], 0x0002, 0x0007, 0x000f, 94);
1256 P54_SET_QUEUE(priv->qos_params[2], 0x0003, 0x000f, 0x03ff, 0);
1257 P54_SET_QUEUE(priv->qos_params[3], 0x0007, 0x000f, 0x03ff, 0);
1258 err = p54_set_edcf(dev);
1259 if (!err)
0f1be978 1260 err = p54_init_stats(dev);
4150c572 1261
9e7f3f8e 1262 mutex_unlock(&priv->conf_mutex);
4150c572
JB
1263 return err;
1264}
1265
1266static void p54_stop(struct ieee80211_hw *dev)
1267{
1268 struct p54_common *priv = dev->priv;
1269 struct sk_buff *skb;
cc6de669 1270
9e7f3f8e 1271 mutex_lock(&priv->conf_mutex);
cc6de669 1272 del_timer(&priv->stats_timer);
b92f30d6 1273 p54_free_skb(dev, priv->cached_stats);
0f1be978 1274 priv->cached_stats = NULL;
e039fa4a 1275 while ((skb = skb_dequeue(&priv->tx_queue)))
4150c572 1276 kfree_skb(skb);
b92f30d6 1277
4150c572 1278 priv->stop(dev);
a0db663f 1279 priv->tsf_high32 = priv->tsf_low32 = 0;
05c914fe 1280 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
9e7f3f8e 1281 mutex_unlock(&priv->conf_mutex);
4150c572
JB
1282}
1283
eff1a59c
MW
1284static int p54_add_interface(struct ieee80211_hw *dev,
1285 struct ieee80211_if_init_conf *conf)
1286{
1287 struct p54_common *priv = dev->priv;
eff1a59c 1288
9e7f3f8e
CL
1289 mutex_lock(&priv->conf_mutex);
1290 if (priv->mode != NL80211_IFTYPE_MONITOR) {
1291 mutex_unlock(&priv->conf_mutex);
4150c572 1292 return -EOPNOTSUPP;
9e7f3f8e 1293 }
eff1a59c
MW
1294
1295 switch (conf->type) {
05c914fe 1296 case NL80211_IFTYPE_STATION:
eff1a59c
MW
1297 priv->mode = conf->type;
1298 break;
1299 default:
9e7f3f8e 1300 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW
1301 return -EOPNOTSUPP;
1302 }
1303
4150c572 1304 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
eff1a59c 1305
27df605e 1306 p54_setup_mac(dev, P54_FILTER_TYPE_NONE, NULL);
eff1a59c
MW
1307
1308 switch (conf->type) {
05c914fe 1309 case NL80211_IFTYPE_STATION:
27df605e 1310 p54_setup_mac(dev, P54_FILTER_TYPE_STATION, NULL);
eff1a59c 1311 break;
4150c572
JB
1312 default:
1313 BUG(); /* impossible */
1314 break;
eff1a59c
MW
1315 }
1316
1317 p54_set_leds(dev, 1, 0, 0);
1318
9e7f3f8e 1319 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW
1320 return 0;
1321}
1322
1323static void p54_remove_interface(struct ieee80211_hw *dev,
1324 struct ieee80211_if_init_conf *conf)
1325{
1326 struct p54_common *priv = dev->priv;
9e7f3f8e
CL
1327
1328 mutex_lock(&priv->conf_mutex);
1329 p54_setup_mac(dev, P54_FILTER_TYPE_NONE, NULL);
05c914fe 1330 priv->mode = NL80211_IFTYPE_MONITOR;
4150c572 1331 memset(priv->mac_addr, 0, ETH_ALEN);
9e7f3f8e 1332 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW
1333}
1334
e8975581 1335static int p54_config(struct ieee80211_hw *dev, u32 changed)
eff1a59c
MW
1336{
1337 int ret;
6041e2a0 1338 struct p54_common *priv = dev->priv;
e8975581 1339 struct ieee80211_conf *conf = &dev->conf;
eff1a59c 1340
6041e2a0 1341 mutex_lock(&priv->conf_mutex);
0f4ac38b 1342 priv->rx_antenna = 2; /* automatic */
09adf284 1343 priv->output_power = conf->power_level << 2;
9e7f3f8e 1344 ret = p54_set_freq(dev, conf->channel->center_freq);
0fdd7c5d
CL
1345 if (!ret)
1346 ret = p54_set_edcf(dev);
6041e2a0 1347 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW
1348 return ret;
1349}
1350
32bfd35d
JB
1351static int p54_config_interface(struct ieee80211_hw *dev,
1352 struct ieee80211_vif *vif,
eff1a59c
MW
1353 struct ieee80211_if_conf *conf)
1354{
1355 struct p54_common *priv = dev->priv;
1356
6041e2a0 1357 mutex_lock(&priv->conf_mutex);
27df605e 1358 p54_setup_mac(dev, P54_FILTER_TYPE_STATION, conf->bssid);
eff1a59c 1359 p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0);
4150c572 1360 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6041e2a0 1361 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW
1362 return 0;
1363}
1364
4150c572
JB
1365static void p54_configure_filter(struct ieee80211_hw *dev,
1366 unsigned int changed_flags,
1367 unsigned int *total_flags,
1368 int mc_count, struct dev_mc_list *mclist)
1369{
1370 struct p54_common *priv = dev->priv;
1371
78d57eb2
CL
1372 *total_flags &= FIF_BCN_PRBRESP_PROMISC |
1373 FIF_PROMISC_IN_BSS |
1374 FIF_FCSFAIL;
1375
1376 priv->filter_flags = *total_flags;
4150c572
JB
1377
1378 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1379 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5e73444e 1380 p54_setup_mac(dev, priv->mac_mode, NULL);
78d57eb2 1381 else
5e73444e 1382 p54_setup_mac(dev, priv->mac_mode, priv->bssid);
78d57eb2
CL
1383 }
1384
1385 if (changed_flags & FIF_PROMISC_IN_BSS) {
1386 if (*total_flags & FIF_PROMISC_IN_BSS)
5e73444e 1387 p54_setup_mac(dev, priv->mac_mode | 0x8, NULL);
4150c572 1388 else
5e73444e 1389 p54_setup_mac(dev, priv->mac_mode & ~0x8, priv->bssid);
4150c572
JB
1390 }
1391}
1392
e100bb64 1393static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue,
eff1a59c
MW
1394 const struct ieee80211_tx_queue_params *params)
1395{
1396 struct p54_common *priv = dev->priv;
9e7f3f8e 1397 int ret;
eff1a59c 1398
9e7f3f8e 1399 mutex_lock(&priv->conf_mutex);
3df5ee60 1400 if ((params) && !(queue > 4)) {
0fdd7c5d 1401 P54_SET_QUEUE(priv->qos_params[queue], params->aifs,
3330d7be 1402 params->cw_min, params->cw_max, params->txop);
eff1a59c 1403 } else
9e7f3f8e
CL
1404 ret = -EINVAL;
1405 if (!ret)
1406 ret = p54_set_edcf(dev);
1407 mutex_unlock(&priv->conf_mutex);
1408 return ret;
eff1a59c
MW
1409}
1410
1b997534
CL
1411static int p54_init_xbow_synth(struct ieee80211_hw *dev)
1412{
1413 struct p54_common *priv = dev->priv;
b92f30d6 1414 struct sk_buff *skb;
27df605e 1415 struct p54_xbow_synth *xbow;
1b997534 1416
27df605e
JL
1417 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*xbow) +
1418 sizeof(struct p54_hdr),
1419 P54_CONTROL_TYPE_XBOW_SYNTH_CFG,
b92f30d6
CL
1420 GFP_KERNEL);
1421 if (!skb)
1b997534
CL
1422 return -ENOMEM;
1423
27df605e 1424 xbow = (struct p54_xbow_synth *)skb_put(skb, sizeof(*xbow));
1b997534
CL
1425 xbow->magic1 = cpu_to_le16(0x1);
1426 xbow->magic2 = cpu_to_le16(0x2);
1427 xbow->freq = cpu_to_le16(5390);
b92f30d6
CL
1428 memset(xbow->padding, 0, sizeof(xbow->padding));
1429 priv->tx(dev, skb, 1);
1b997534
CL
1430 return 0;
1431}
1432
cc6de669
CL
1433static void p54_statistics_timer(unsigned long data)
1434{
1435 struct ieee80211_hw *dev = (struct ieee80211_hw *) data;
1436 struct p54_common *priv = dev->priv;
cc6de669
CL
1437
1438 BUG_ON(!priv->cached_stats);
cc6de669 1439
b92f30d6 1440 priv->tx(dev, priv->cached_stats, 0);
cc6de669
CL
1441}
1442
eff1a59c
MW
1443static int p54_get_stats(struct ieee80211_hw *dev,
1444 struct ieee80211_low_level_stats *stats)
1445{
cc6de669
CL
1446 struct p54_common *priv = dev->priv;
1447
1448 del_timer(&priv->stats_timer);
1449 p54_statistics_timer((unsigned long)dev);
1450
1451 if (!wait_for_completion_interruptible_timeout(&priv->stats_comp, HZ)) {
1452 printk(KERN_ERR "%s: device does not respond!\n",
1453 wiphy_name(dev->wiphy));
1454 return -EBUSY;
1455 }
1456
1457 memcpy(stats, &priv->stats, sizeof(*stats));
1458
eff1a59c
MW
1459 return 0;
1460}
1461
1462static int p54_get_tx_stats(struct ieee80211_hw *dev,
1463 struct ieee80211_tx_queue_stats *stats)
1464{
1465 struct p54_common *priv = dev->priv;
eff1a59c 1466
84df3ed3 1467 memcpy(stats, &priv->tx_stats[4], sizeof(stats[0]) * dev->queues);
eff1a59c
MW
1468
1469 return 0;
1470}
1471
40333e4f
CL
1472static void p54_bss_info_changed(struct ieee80211_hw *dev,
1473 struct ieee80211_vif *vif,
1474 struct ieee80211_bss_conf *info,
1475 u32 changed)
1476{
1477 struct p54_common *priv = dev->priv;
1478
1479 if (changed & BSS_CHANGED_ERP_SLOT) {
1480 priv->use_short_slot = info->use_short_slot;
0fdd7c5d 1481 p54_set_edcf(dev);
40333e4f
CL
1482 }
1483}
1484
eff1a59c
MW
1485static const struct ieee80211_ops p54_ops = {
1486 .tx = p54_tx,
4150c572
JB
1487 .start = p54_start,
1488 .stop = p54_stop,
eff1a59c
MW
1489 .add_interface = p54_add_interface,
1490 .remove_interface = p54_remove_interface,
1491 .config = p54_config,
1492 .config_interface = p54_config_interface,
40333e4f 1493 .bss_info_changed = p54_bss_info_changed,
4150c572 1494 .configure_filter = p54_configure_filter,
eff1a59c
MW
1495 .conf_tx = p54_conf_tx,
1496 .get_stats = p54_get_stats,
1497 .get_tx_stats = p54_get_tx_stats
1498};
1499
1500struct ieee80211_hw *p54_init_common(size_t priv_data_len)
1501{
1502 struct ieee80211_hw *dev;
1503 struct p54_common *priv;
eff1a59c
MW
1504
1505 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
1506 if (!dev)
1507 return NULL;
1508
1509 priv = dev->priv;
05c914fe 1510 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
eff1a59c 1511 skb_queue_head_init(&priv->tx_queue);
eff1a59c 1512 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */
566bfe5a 1513 IEEE80211_HW_RX_INCLUDES_FCS |
cc6de669
CL
1514 IEEE80211_HW_SIGNAL_DBM |
1515 IEEE80211_HW_NOISE_DBM;
f59ac048
LR
1516
1517 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1518
eff1a59c 1519 dev->channel_change_time = 1000; /* TODO: find actual value */
9e7f3f8e
CL
1520 priv->tx_stats[0].limit = 1; /* Beacon queue */
1521 priv->tx_stats[1].limit = 1; /* Probe queue for HW scan */
1522 priv->tx_stats[2].limit = 3; /* queue for MLMEs */
1523 priv->tx_stats[3].limit = 3; /* Broadcast / MC queue */
1524 priv->tx_stats[4].limit = 5; /* Data */
eff1a59c 1525 dev->queues = 1;
cc6de669 1526 priv->noise = -94;
c12abae3
JB
1527 /*
1528 * We support at most 8 tries no matter which rate they're at,
1529 * we cannot support max_rates * max_rate_tries as we set it
1530 * here, but setting it correctly to 4/2 or so would limit us
1531 * artificially if the RC algorithm wants just two rates, so
1532 * let's say 4/7, we'll redistribute it at TX time, see the
1533 * comments there.
1534 */
1535 dev->max_rates = 4;
1536 dev->max_rate_tries = 7;
27df605e
JL
1537 dev->extra_tx_headroom = sizeof(struct p54_hdr) + 4 +
1538 sizeof(struct p54_tx_data);
eff1a59c 1539
6041e2a0 1540 mutex_init(&priv->conf_mutex);
7cb77072 1541 init_completion(&priv->eeprom_comp);
cc6de669
CL
1542 init_completion(&priv->stats_comp);
1543 setup_timer(&priv->stats_timer, p54_statistics_timer,
1544 (unsigned long)dev);
eff1a59c 1545
eff1a59c
MW
1546 return dev;
1547}
1548EXPORT_SYMBOL_GPL(p54_init_common);
1549
1550void p54_free_common(struct ieee80211_hw *dev)
1551{
1552 struct p54_common *priv = dev->priv;
b92f30d6
CL
1553 del_timer(&priv->stats_timer);
1554 kfree_skb(priv->cached_stats);
eff1a59c
MW
1555 kfree(priv->iq_autocal);
1556 kfree(priv->output_limit);
1557 kfree(priv->curve_data);
eff1a59c
MW
1558}
1559EXPORT_SYMBOL_GPL(p54_free_common);
1560
1561static int __init p54_init(void)
1562{
1563 return 0;
1564}
1565
1566static void __exit p54_exit(void)
1567{
1568}
1569
1570module_init(p54_init);
1571module_exit(p54_exit);