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p54usb: Fix to prevent SKB memory allocation errors with 4K page size
[net-next-2.6.git] / drivers / net / wireless / p54 / p54common.c
CommitLineData
eff1a59c
MW		 1/*
2 * Common code for mac80211 Prism54 drivers
3 *
4 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
5 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
c12abae3 6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
eff1a59c 7 *
27df605e
JL		 8 * Based on:
9 * - the islsm (softmac prism54) driver, which is:
10 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
11 * - stlc45xx driver
9483407d 12 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
eff1a59c
MW		 13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/init.h>
20#include <linux/firmware.h>
21#include <linux/etherdevice.h>
22
23#include <net/mac80211.h>
24
25#include "p54.h"
26#include "p54common.h"
27
25900ef0
CL		 28static int modparam_nohwcrypt;
29module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
eff1a59c
MW		 31MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
32MODULE_DESCRIPTION("Softmac Prism54 common code");
33MODULE_LICENSE("GPL");
34MODULE_ALIAS("prism54common");
35
1b997534 36static struct ieee80211_rate p54_bgrates[] = {
8318d78a
JB		 37 { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
38 { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
39 { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
40 { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
41 { .bitrate = 60, .hw_value = 4, },
42 { .bitrate = 90, .hw_value = 5, },
43 { .bitrate = 120, .hw_value = 6, },
44 { .bitrate = 180, .hw_value = 7, },
45 { .bitrate = 240, .hw_value = 8, },
46 { .bitrate = 360, .hw_value = 9, },
47 { .bitrate = 480, .hw_value = 10, },
48 { .bitrate = 540, .hw_value = 11, },
49};
50
1b997534 51static struct ieee80211_channel p54_bgchannels[] = {
8318d78a
JB		 52 { .center_freq = 2412, .hw_value = 1, },
53 { .center_freq = 2417, .hw_value = 2, },
54 { .center_freq = 2422, .hw_value = 3, },
55 { .center_freq = 2427, .hw_value = 4, },
56 { .center_freq = 2432, .hw_value = 5, },
57 { .center_freq = 2437, .hw_value = 6, },
58 { .center_freq = 2442, .hw_value = 7, },
59 { .center_freq = 2447, .hw_value = 8, },
60 { .center_freq = 2452, .hw_value = 9, },
61 { .center_freq = 2457, .hw_value = 10, },
62 { .center_freq = 2462, .hw_value = 11, },
63 { .center_freq = 2467, .hw_value = 12, },
64 { .center_freq = 2472, .hw_value = 13, },
65 { .center_freq = 2484, .hw_value = 14, },
66};
67
c2976ab0 68static struct ieee80211_supported_band band_2GHz = {
1b997534
CL		 69 .channels = p54_bgchannels,
70 .n_channels = ARRAY_SIZE(p54_bgchannels),
71 .bitrates = p54_bgrates,
72 .n_bitrates = ARRAY_SIZE(p54_bgrates),
73};
74
75static struct ieee80211_rate p54_arates[] = {
76 { .bitrate = 60, .hw_value = 4, },
77 { .bitrate = 90, .hw_value = 5, },
78 { .bitrate = 120, .hw_value = 6, },
79 { .bitrate = 180, .hw_value = 7, },
80 { .bitrate = 240, .hw_value = 8, },
81 { .bitrate = 360, .hw_value = 9, },
82 { .bitrate = 480, .hw_value = 10, },
83 { .bitrate = 540, .hw_value = 11, },
84};
85
86static struct ieee80211_channel p54_achannels[] = {
87 { .center_freq = 4920 },
88 { .center_freq = 4940 },
89 { .center_freq = 4960 },
90 { .center_freq = 4980 },
91 { .center_freq = 5040 },
92 { .center_freq = 5060 },
93 { .center_freq = 5080 },
94 { .center_freq = 5170 },
95 { .center_freq = 5180 },
96 { .center_freq = 5190 },
97 { .center_freq = 5200 },
98 { .center_freq = 5210 },
99 { .center_freq = 5220 },
100 { .center_freq = 5230 },
101 { .center_freq = 5240 },
102 { .center_freq = 5260 },
103 { .center_freq = 5280 },
104 { .center_freq = 5300 },
105 { .center_freq = 5320 },
106 { .center_freq = 5500 },
107 { .center_freq = 5520 },
108 { .center_freq = 5540 },
109 { .center_freq = 5560 },
110 { .center_freq = 5580 },
111 { .center_freq = 5600 },
112 { .center_freq = 5620 },
113 { .center_freq = 5640 },
114 { .center_freq = 5660 },
115 { .center_freq = 5680 },
116 { .center_freq = 5700 },
117 { .center_freq = 5745 },
118 { .center_freq = 5765 },
119 { .center_freq = 5785 },
120 { .center_freq = 5805 },
121 { .center_freq = 5825 },
122};
123
124static struct ieee80211_supported_band band_5GHz = {
125 .channels = p54_achannels,
126 .n_channels = ARRAY_SIZE(p54_achannels),
127 .bitrates = p54_arates,
128 .n_bitrates = ARRAY_SIZE(p54_arates),
8318d78a
JB		 129};
130
4e416a6f 131int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
eff1a59c
MW		 132{
133 struct p54_common *priv = dev->priv;
134 struct bootrec_exp_if *exp_if;
135 struct bootrec *bootrec;
136 u32 *data = (u32 *)fw->data;
137 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
138 u8 *fw_version = NULL;
139 size_t len;
140 int i;
51fb80fe 141 int maxlen;
eff1a59c
MW		 142
143 if (priv->rx_start)
4e416a6f 144 return 0;
eff1a59c
MW		 145
146 while (data < end_data && *data)
147 data++;
148
149 while (data < end_data && !*data)
150 data++;
151
152 bootrec = (struct bootrec *) data;
153
154 while (bootrec->data <= end_data &&
155 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
156 u32 code = le32_to_cpu(bootrec->code);
157 switch (code) {
158 case BR_CODE_COMPONENT_ID:
1f1c0e33
LF		 159 priv->fw_interface = be32_to_cpup((__be32 *)
160 bootrec->data);
2b80848e 161 switch (priv->fw_interface) {
eff1a59c 162 case FW_LM86:
02e37ba1
CL		 163 case FW_LM20:
164 case FW_LM87: {
165 char *iftype = (char *)bootrec->data;
166 printk(KERN_INFO "%s: p54 detected a LM%c%c "
167 "firmware\n",
168 wiphy_name(dev->wiphy),
169 iftype[2], iftype[3]);
eff1a59c 170 break;
02e37ba1
CL		 171 }
172 case FW_FMAC:
eff1a59c 173 default:
02e37ba1
CL		 174 printk(KERN_ERR "%s: unsupported firmware\n",
175 wiphy_name(dev->wiphy));
176 return -ENODEV;
eff1a59c
MW		 177 }
178 break;
179 case BR_CODE_COMPONENT_VERSION:
180 /* 24 bytes should be enough for all firmwares */
181 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
182 fw_version = (unsigned char*)bootrec->data;
183 break;
4e416a6f
CL		 184 case BR_CODE_DESCR: {
185 struct bootrec_desc *desc =
186 (struct bootrec_desc *)bootrec->data;
187 priv->rx_start = le32_to_cpu(desc->rx_start);
eff1a59c 188 /* FIXME add sanity checking */
4e416a6f
CL		 189 priv->rx_end = le32_to_cpu(desc->rx_end) - 0x3500;
190 priv->headroom = desc->headroom;
191 priv->tailroom = desc->tailroom;
25900ef0
CL		 192 priv->privacy_caps = desc->privacy_caps;
193 priv->rx_keycache_size = desc->rx_keycache_size;
1f1c0e33 194 if (le32_to_cpu(bootrec->len) == 11)
2e20cc39 195 priv->rx_mtu = le16_to_cpu(desc->rx_mtu);
4e416a6f
CL		 196 else
197 priv->rx_mtu = (size_t)
198 0x620 - priv->tx_hdr_len;
51fb80fe
LF		 199 maxlen = priv->tx_hdr_len + /* USB devices */
200 sizeof(struct p54_rx_data) +
201 4 + /* rx alignment */
202 IEEE80211_MAX_FRAG_THRESHOLD;
203 if (priv->rx_mtu > maxlen && PAGE_SIZE == 4096) {
204 printk(KERN_INFO "p54: rx_mtu reduced from %d "
205 "to %d\n", priv->rx_mtu,
206 maxlen);
207 priv->rx_mtu = maxlen;
208 }
eff1a59c 209 break;
4e416a6f 210 }
eff1a59c
MW		 211 case BR_CODE_EXPOSED_IF:
212 exp_if = (struct bootrec_exp_if *) bootrec->data;
213 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
dc73c623 214 if (exp_if[i].if_id == cpu_to_le16(0x1a))
eff1a59c
MW		 215 priv->fw_var = le16_to_cpu(exp_if[i].variant);
216 break;
217 case BR_CODE_DEPENDENT_IF:
218 break;
219 case BR_CODE_END_OF_BRA:
220 case LEGACY_BR_CODE_END_OF_BRA:
221 end_data = NULL;
222 break;
223 default:
224 break;
225 }
226 bootrec = (struct bootrec *)&bootrec->data[len];
227 }
228
229 if (fw_version)
02e37ba1
CL		 230 printk(KERN_INFO "%s: FW rev %s - Softmac protocol %x.%x\n",
231 wiphy_name(dev->wiphy), fw_version,
232 priv->fw_var >> 8, priv->fw_var & 0xff);
eff1a59c 233
9a8675d7 234 if (priv->fw_var < 0x500)
02e37ba1 235 printk(KERN_INFO "%s: you are using an obsolete firmware. "
9a8675d7 236 "visit http://wireless.kernel.org/en/users/Drivers/p54 "
02e37ba1
CL		 237 "and grab one for \"kernel >= 2.6.28\"!\n",
238 wiphy_name(dev->wiphy));
9a8675d7 239
eff1a59c
MW		 240 if (priv->fw_var >= 0x300) {
241 /* Firmware supports QoS, use it! */
9e7f3f8e
CL		 242 priv->tx_stats[4].limit = 3; /* AC_VO */
243 priv->tx_stats[5].limit = 4; /* AC_VI */
244 priv->tx_stats[6].limit = 3; /* AC_BE */
245 priv->tx_stats[7].limit = 2; /* AC_BK */
eff1a59c
MW		 246 dev->queues = 4;
247 }
4e416a6f 248
25900ef0
CL		 249 if (!modparam_nohwcrypt)
250 printk(KERN_INFO "%s: cryptographic accelerator "
251 "WEP:%s, TKIP:%s, CCMP:%s\n",
252 wiphy_name(dev->wiphy),
253 (priv->privacy_caps & BR_DESC_PRIV_CAP_WEP) ? "YES" :
254 "no", (priv->privacy_caps & (BR_DESC_PRIV_CAP_TKIP |
255 BR_DESC_PRIV_CAP_MICHAEL)) ? "YES" : "no",
256 (priv->privacy_caps & BR_DESC_PRIV_CAP_AESCCMP) ?
257 "YES" : "no");
258
4e416a6f 259 return 0;
eff1a59c
MW		 260}
261EXPORT_SYMBOL_GPL(p54_parse_firmware);
262
154e3af1
CL		 263static int p54_convert_rev0(struct ieee80211_hw *dev,
264 struct pda_pa_curve_data *curve_data)
eff1a59c
MW		 265{
266 struct p54_common *priv = dev->priv;
154e3af1
CL		 267 struct p54_pa_curve_data_sample *dst;
268 struct pda_pa_curve_data_sample_rev0 *src;
eff1a59c 269 size_t cd_len = sizeof(*curve_data) +
154e3af1 270 (curve_data->points_per_channel*sizeof(*dst) + 2) *
eff1a59c
MW		 271 curve_data->channels;
272 unsigned int i, j;
273 void *source, *target;
274
275 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
276 if (!priv->curve_data)
277 return -ENOMEM;
278
279 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
280 source = curve_data->data;
281 target = priv->curve_data->data;
282 for (i = 0; i < curve_data->channels; i++) {
283 __le16 *freq = source;
284 source += sizeof(__le16);
285 *((__le16 *)target) = *freq;
286 target += sizeof(__le16);
287 for (j = 0; j < curve_data->points_per_channel; j++) {
154e3af1
CL		 288 dst = target;
289 src = source;
eff1a59c 290
154e3af1
CL		 291 dst->rf_power = src->rf_power;
292 dst->pa_detector = src->pa_detector;
293 dst->data_64qam = src->pcv;
eff1a59c
MW		 294 /* "invent" the points for the other modulations */
295#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
154e3af1
CL		 296 dst->data_16qam = SUB(src->pcv, 12);
297 dst->data_qpsk = SUB(dst->data_16qam, 12);
298 dst->data_bpsk = SUB(dst->data_qpsk, 12);
299 dst->data_barker = SUB(dst->data_bpsk, 14);
eff1a59c 300#undef SUB
154e3af1
CL		 301 target += sizeof(*dst);
302 source += sizeof(*src);
eff1a59c
MW		 303 }
304 }
305
306 return 0;
307}
308
154e3af1
CL		 309static int p54_convert_rev1(struct ieee80211_hw *dev,
310 struct pda_pa_curve_data *curve_data)
311{
312 struct p54_common *priv = dev->priv;
313 struct p54_pa_curve_data_sample *dst;
314 struct pda_pa_curve_data_sample_rev1 *src;
315 size_t cd_len = sizeof(*curve_data) +
316 (curve_data->points_per_channel*sizeof(*dst) + 2) *
317 curve_data->channels;
318 unsigned int i, j;
319 void *source, *target;
320
321 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
322 if (!priv->curve_data)
323 return -ENOMEM;
324
325 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
326 source = curve_data->data;
327 target = priv->curve_data->data;
328 for (i = 0; i < curve_data->channels; i++) {
329 __le16 *freq = source;
330 source += sizeof(__le16);
331 *((__le16 *)target) = *freq;
332 target += sizeof(__le16);
333 for (j = 0; j < curve_data->points_per_channel; j++) {
334 memcpy(target, source, sizeof(*src));
335
336 target += sizeof(*dst);
337 source += sizeof(*src);
338 }
339 source++;
340 }
341
342 return 0;
343}
344
4cc683c9
CL		 345static const char *p54_rf_chips[] = { "NULL", "Duette3", "Duette2",
346 "Frisbee", "Xbow", "Longbow", "NULL", "NULL" };
1b997534 347static int p54_init_xbow_synth(struct ieee80211_hw *dev);
7cb77072 348
69ba3e5d
CL		 349static void p54_parse_rssical(struct ieee80211_hw *dev, void *data, int len,
350 u16 type)
351{
352 struct p54_common *priv = dev->priv;
353 int offset = (type == PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED) ? 2 : 0;
354 int entry_size = sizeof(struct pda_rssi_cal_entry) + offset;
355 int num_entries = (type == PDR_RSSI_LINEAR_APPROXIMATION) ? 1 : 2;
356 int i;
357
358 if (len != (entry_size * num_entries)) {
359 printk(KERN_ERR "%s: unknown rssi calibration data packing "
360 " type:(%x) len:%d.\n",
361 wiphy_name(dev->wiphy), type, len);
362
363 print_hex_dump_bytes("rssical:", DUMP_PREFIX_NONE,
364 data, len);
365
366 printk(KERN_ERR "%s: please report this issue.\n",
367 wiphy_name(dev->wiphy));
368 return;
369 }
370
371 for (i = 0; i < num_entries; i++) {
372 struct pda_rssi_cal_entry *cal = data +
373 (offset + i * entry_size);
374 priv->rssical_db[i].mul = (s16) le16_to_cpu(cal->mul);
375 priv->rssical_db[i].add = (s16) le16_to_cpu(cal->add);
376 }
377}
378
1f1c0e33 379static int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
eff1a59c
MW		 380{
381 struct p54_common *priv = dev->priv;
382 struct eeprom_pda_wrap *wrap = NULL;
383 struct pda_entry *entry;
eff1a59c
MW		 384 unsigned int data_len, entry_len;
385 void *tmp;
386 int err;
c2f2d3a0 387 u8 *end = (u8 *)eeprom + len;
f2c2e255 388 u16 synth = 0;
eff1a59c
MW		 389
390 wrap = (struct eeprom_pda_wrap *) eeprom;
8c28293f 391 entry = (void *)wrap->data + le16_to_cpu(wrap->len);
c2f2d3a0
JB		 392
393 /* verify that at least the entry length/code fits */
394 while ((u8 *)entry <= end - sizeof(*entry)) {
eff1a59c
MW		 395 entry_len = le16_to_cpu(entry->len);
396 data_len = ((entry_len - 1) << 1);
c2f2d3a0
JB		 397
398 /* abort if entry exceeds whole structure */
399 if ((u8 *)entry + sizeof(*entry) + data_len > end)
400 break;
401
eff1a59c
MW		 402 switch (le16_to_cpu(entry->code)) {
403 case PDR_MAC_ADDRESS:
404 SET_IEEE80211_PERM_ADDR(dev, entry->data);
405 break;
406 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
407 if (data_len < 2) {
408 err = -EINVAL;
409 goto err;
410 }
411
412 if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
413 err = -EINVAL;
414 goto err;
415 }
416
417 priv->output_limit = kmalloc(entry->data[1] *
418 sizeof(*priv->output_limit), GFP_KERNEL);
419
420 if (!priv->output_limit) {
421 err = -ENOMEM;
422 goto err;
423 }
424
425 memcpy(priv->output_limit, &entry->data[2],
426 entry->data[1]*sizeof(*priv->output_limit));
427 priv->output_limit_len = entry->data[1];
428 break;
154e3af1
CL		 429 case PDR_PRISM_PA_CAL_CURVE_DATA: {
430 struct pda_pa_curve_data *curve_data =
431 (struct pda_pa_curve_data *)entry->data;
432 if (data_len < sizeof(*curve_data)) {
eff1a59c
MW		 433 err = -EINVAL;
434 goto err;
435 }
436
154e3af1
CL		 437 switch (curve_data->cal_method_rev) {
438 case 0:
439 err = p54_convert_rev0(dev, curve_data);
440 break;
441 case 1:
442 err = p54_convert_rev1(dev, curve_data);
443 break;
444 default:
02e37ba1 445 printk(KERN_ERR "%s: unknown curve data "
154e3af1 446 "revision %d\n",
02e37ba1 447 wiphy_name(dev->wiphy),
154e3af1
CL		 448 curve_data->cal_method_rev);
449 err = -ENODEV;
450 break;
eff1a59c 451 }
154e3af1
CL		 452 if (err)
453 goto err;
eff1a59c 454
154e3af1 455 }
eff1a59c
MW		 456 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
457 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
458 if (!priv->iq_autocal) {
459 err = -ENOMEM;
460 goto err;
461 }
462
463 memcpy(priv->iq_autocal, entry->data, data_len);
464 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
465 break;
466 case PDR_INTERFACE_LIST:
467 tmp = entry->data;
468 while ((u8 *)tmp < entry->data + data_len) {
469 struct bootrec_exp_if *exp_if = tmp;
4cc683c9
CL		 470 if (le16_to_cpu(exp_if->if_id) == 0xf)
471 synth = le16_to_cpu(exp_if->variant);
eff1a59c
MW		 472 tmp += sizeof(struct bootrec_exp_if);
473 }
474 break;
475 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
476 priv->version = *(u8 *)(entry->data + 1);
477 break;
69ba3e5d
CL		 478 case PDR_RSSI_LINEAR_APPROXIMATION:
479 case PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND:
480 case PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED:
481 p54_parse_rssical(dev, entry->data, data_len,
482 le16_to_cpu(entry->code));
483 break;
eff1a59c 484 case PDR_END:
c2f2d3a0
JB		 485 /* make it overrun */
486 entry_len = len;
eff1a59c 487 break;
c8034c44
PR		 488 case PDR_MANUFACTURING_PART_NUMBER:
489 case PDR_PDA_VERSION:
490 case PDR_NIC_SERIAL_NUMBER:
491 case PDR_REGULATORY_DOMAIN_LIST:
492 case PDR_TEMPERATURE_TYPE:
493 case PDR_PRISM_PCI_IDENTIFIER:
494 case PDR_COUNTRY_INFORMATION:
495 case PDR_OEM_NAME:
496 case PDR_PRODUCT_NAME:
497 case PDR_UTF8_OEM_NAME:
498 case PDR_UTF8_PRODUCT_NAME:
499 case PDR_COUNTRY_LIST:
500 case PDR_DEFAULT_COUNTRY:
501 case PDR_ANTENNA_GAIN:
502 case PDR_PRISM_INDIGO_PA_CALIBRATION_DATA:
c8034c44 503 case PDR_REGULATORY_POWER_LIMITS:
c8034c44
PR		 504 case PDR_RADIATED_TRANSMISSION_CORRECTION:
505 case PDR_PRISM_TX_IQ_CALIBRATION:
506 case PDR_BASEBAND_REGISTERS:
507 case PDR_PER_CHANNEL_BASEBAND_REGISTERS:
508 break;
58e30739 509 default:
02e37ba1
CL		 510 printk(KERN_INFO "%s: unknown eeprom code : 0x%x\n",
511 wiphy_name(dev->wiphy),
58e30739
FF		 512 le16_to_cpu(entry->code));
513 break;
eff1a59c
MW		 514 }
515
516 entry = (void *)entry + (entry_len + 1)*2;
eff1a59c
MW		 517 }
518
f2c2e255
CL		 519 if (!synth || !priv->iq_autocal || !priv->output_limit ||
520 !priv->curve_data) {
02e37ba1
CL		 521 printk(KERN_ERR "%s: not all required entries found in eeprom!\n",
522 wiphy_name(dev->wiphy));
eff1a59c
MW		 523 err = -EINVAL;
524 goto err;
525 }
526
9e7f3f8e 527 priv->rxhw = synth & PDR_SYNTH_FRONTEND_MASK;
4cc683c9 528 if (priv->rxhw == 4)
1b997534 529 p54_init_xbow_synth(dev);
9e7f3f8e 530 if (!(synth & PDR_SYNTH_24_GHZ_DISABLED))
1b997534 531 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz;
9e7f3f8e 532 if (!(synth & PDR_SYNTH_5_GHZ_DISABLED))
4cc683c9 533 dev->wiphy->bands[IEEE80211_BAND_5GHZ] = &band_5GHz;
7cb77072
CL		 534
535 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
536 u8 perm_addr[ETH_ALEN];
537
538 printk(KERN_WARNING "%s: Invalid hwaddr! Using randomly generated MAC addr\n",
539 wiphy_name(dev->wiphy));
540 random_ether_addr(perm_addr);
541 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
542 }
543
e174961c 544 printk(KERN_INFO "%s: hwaddr %pM, MAC:isl38%02x RF:%s\n",
7cb77072 545 wiphy_name(dev->wiphy),
e174961c 546 dev->wiphy->perm_addr,
7cb77072
CL		 547 priv->version, p54_rf_chips[priv->rxhw]);
548
eff1a59c
MW		 549 return 0;
550
551 err:
552 if (priv->iq_autocal) {
553 kfree(priv->iq_autocal);
554 priv->iq_autocal = NULL;
555 }
556
557 if (priv->output_limit) {
558 kfree(priv->output_limit);
559 priv->output_limit = NULL;
560 }
561
562 if (priv->curve_data) {
563 kfree(priv->curve_data);
564 priv->curve_data = NULL;
565 }
566
02e37ba1
CL		 567 printk(KERN_ERR "%s: eeprom parse failed!\n",
568 wiphy_name(dev->wiphy));
eff1a59c
MW		 569 return err;
570}
eff1a59c 571
cc6de669
CL		 572static int p54_rssi_to_dbm(struct ieee80211_hw *dev, int rssi)
573{
69ba3e5d
CL		 574 struct p54_common *priv = dev->priv;
575 int band = dev->conf.channel->band;
576
577 return ((rssi * priv->rssical_db[band].mul) / 64 +
578 priv->rssical_db[band].add) / 4;
cc6de669
CL		 579}
580
19c19d54 581static int p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 582{
a0db663f 583 struct p54_common *priv = dev->priv;
27df605e 584 struct p54_rx_data *hdr = (struct p54_rx_data *) skb->data;
eff1a59c
MW		 585 struct ieee80211_rx_status rx_status = {0};
586 u16 freq = le16_to_cpu(hdr->freq);
19c19d54 587 size_t header_len = sizeof(*hdr);
a0db663f 588 u32 tsf32;
eff1a59c 589
59651e89
CL		 590 /*
591 * If the device is in a unspecified state we have to
592 * ignore all data frames. Else we could end up with a
593 * nasty crash.
594 */
595 if (unlikely(priv->mode == NL80211_IFTYPE_UNSPECIFIED))
596 return 0;
597
27df605e 598 if (!(hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_IN_FCS_GOOD))) {
78d57eb2
CL		 599 if (priv->filter_flags & FIF_FCSFAIL)
600 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
601 else
602 return 0;
603 }
604
25900ef0
CL		 605 if (hdr->decrypt_status == P54_DECRYPT_OK)
606 rx_status.flag |= RX_FLAG_DECRYPTED;
607 if ((hdr->decrypt_status == P54_DECRYPT_FAIL_MICHAEL) ||
608 (hdr->decrypt_status == P54_DECRYPT_FAIL_TKIP))
609 rx_status.flag |= RX_FLAG_MMIC_ERROR;
610
cc6de669
CL		 611 rx_status.signal = p54_rssi_to_dbm(dev, hdr->rssi);
612 rx_status.noise = priv->noise;
8318d78a 613 /* XX correct? */
18d72605 614 rx_status.qual = (100 * hdr->rssi) / 127;
ffed7858
CL		 615 if (hdr->rate & 0x10)
616 rx_status.flag |= RX_FLAG_SHORTPRE;
cf3e74c2
CL		 617 rx_status.rate_idx = (dev->conf.channel->band == IEEE80211_BAND_2GHZ ?
618 hdr->rate : (hdr->rate - 4)) & 0xf;
eff1a59c 619 rx_status.freq = freq;
cf3e74c2 620 rx_status.band = dev->conf.channel->band;
eff1a59c 621 rx_status.antenna = hdr->antenna;
a0db663f
CL		 622
623 tsf32 = le32_to_cpu(hdr->tsf32);
624 if (tsf32 < priv->tsf_low32)
625 priv->tsf_high32++;
626 rx_status.mactime = ((u64)priv->tsf_high32) << 32 | tsf32;
627 priv->tsf_low32 = tsf32;
628
03bffc13 629 rx_status.flag |= RX_FLAG_TSFT;
eff1a59c 630
27df605e 631 if (hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_ALIGN))
19c19d54
CL		 632 header_len += hdr->align[0];
633
634 skb_pull(skb, header_len);
eff1a59c
MW		 635 skb_trim(skb, le16_to_cpu(hdr->len));
636
637 ieee80211_rx_irqsafe(dev, skb, &rx_status);
19c19d54 638
54fdb040
CL		 639 queue_delayed_work(dev->workqueue, &priv->work,
640 msecs_to_jiffies(P54_STATISTICS_UPDATE));
641
19c19d54 642 return -1;
eff1a59c
MW		 643}
644
645static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
646{
647 struct p54_common *priv = dev->priv;
648 int i;
649
b92f30d6
CL		 650 if (priv->mode == NL80211_IFTYPE_UNSPECIFIED)
651 return ;
652
eff1a59c 653 for (i = 0; i < dev->queues; i++)
84df3ed3 654 if (priv->tx_stats[i + 4].len < priv->tx_stats[i + 4].limit)
eff1a59c
MW		 655 ieee80211_wake_queue(dev, i);
656}
657
b92f30d6
CL		 658void p54_free_skb(struct ieee80211_hw *dev, struct sk_buff *skb)
659{
660 struct p54_common *priv = dev->priv;
661 struct ieee80211_tx_info *info;
662 struct memrecord *range;
663 unsigned long flags;
664 u32 freed = 0, last_addr = priv->rx_start;
665
ffed7858 666 if (unlikely(!skb || !dev || !skb_queue_len(&priv->tx_queue)))
b92f30d6
CL		 667 return;
668
59651e89
CL		 669 /*
670 * don't try to free an already unlinked skb
671 */
672 if (unlikely((!skb->next) || (!skb->prev)))
673 return;
674
b92f30d6
CL		 675 spin_lock_irqsave(&priv->tx_queue.lock, flags);
676 info = IEEE80211_SKB_CB(skb);
677 range = (void *)info->rate_driver_data;
678 if (skb->prev != (struct sk_buff *)&priv->tx_queue) {
679 struct ieee80211_tx_info *ni;
680 struct memrecord *mr;
681
682 ni = IEEE80211_SKB_CB(skb->prev);
683 mr = (struct memrecord *)ni->rate_driver_data;
684 last_addr = mr->end_addr;
685 }
686 if (skb->next != (struct sk_buff *)&priv->tx_queue) {
687 struct ieee80211_tx_info *ni;
688 struct memrecord *mr;
689
690 ni = IEEE80211_SKB_CB(skb->next);
691 mr = (struct memrecord *)ni->rate_driver_data;
692 freed = mr->start_addr - last_addr;
693 } else
694 freed = priv->rx_end - last_addr;
695 __skb_unlink(skb, &priv->tx_queue);
696 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
0a5ec96a 697 dev_kfree_skb_any(skb);
b92f30d6 698
27df605e 699 if (freed >= priv->headroom + sizeof(struct p54_hdr) + 48 +
b92f30d6
CL		 700 IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
701 p54_wake_free_queues(dev);
702}
703EXPORT_SYMBOL_GPL(p54_free_skb);
704
54fdb040
CL		 705static struct sk_buff *p54_find_tx_entry(struct ieee80211_hw *dev,
706 __le32 req_id)
707{
708 struct p54_common *priv = dev->priv;
709 struct sk_buff *entry = priv->tx_queue.next;
710 unsigned long flags;
711
712 spin_lock_irqsave(&priv->tx_queue.lock, flags);
713 while (entry != (struct sk_buff *)&priv->tx_queue) {
714 struct p54_hdr *hdr = (struct p54_hdr *) entry->data;
715
716 if (hdr->req_id == req_id) {
717 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
718 return entry;
719 }
720 entry = entry->next;
721 }
722 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
723 return NULL;
724}
725
eff1a59c
MW		 726static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
727{
728 struct p54_common *priv = dev->priv;
27df605e
JL		 729 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
730 struct p54_frame_sent *payload = (struct p54_frame_sent *) hdr->data;
eff1a59c 731 struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
4e416a6f 732 u32 addr = le32_to_cpu(hdr->req_id) - priv->headroom;
eff1a59c
MW		 733 struct memrecord *range = NULL;
734 u32 freed = 0;
735 u32 last_addr = priv->rx_start;
031d10ee 736 unsigned long flags;
c12abae3 737 int count, idx;
eff1a59c 738
031d10ee 739 spin_lock_irqsave(&priv->tx_queue.lock, flags);
eff1a59c 740 while (entry != (struct sk_buff *)&priv->tx_queue) {
552fe53f 741 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
27df605e
JL		 742 struct p54_hdr *entry_hdr;
743 struct p54_tx_data *entry_data;
9de5776f 744 int pad = 0;
eff1a59c 745
9de5776f
CL		 746 range = (void *)info->rate_driver_data;
747 if (range->start_addr != addr) {
748 last_addr = range->end_addr;
749 entry = entry->next;
750 continue;
751 }
552fe53f 752
9de5776f
CL		 753 if (entry->next != (struct sk_buff *)&priv->tx_queue) {
754 struct ieee80211_tx_info *ni;
755 struct memrecord *mr;
eff1a59c 756
9de5776f
CL		 757 ni = IEEE80211_SKB_CB(entry->next);
758 mr = (struct memrecord *)ni->rate_driver_data;
759 freed = mr->start_addr - last_addr;
760 } else
761 freed = priv->rx_end - last_addr;
762
763 last_addr = range->end_addr;
764 __skb_unlink(entry, &priv->tx_queue);
765 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
766
c772a08b
CL		 767 entry_hdr = (struct p54_hdr *) entry->data;
768 entry_data = (struct p54_tx_data *) entry_hdr->data;
769 priv->tx_stats[entry_data->hw_queue].len--;
ee370ced 770 priv->stats.dot11ACKFailureCount += payload->tries - 1;
c772a08b 771
e5ea92a7
CL		 772 if (unlikely(entry == priv->cached_beacon)) {
773 kfree_skb(entry);
774 priv->cached_beacon = NULL;
775 goto out;
776 }
777
9de5776f
CL		 778 /*
779 * Clear manually, ieee80211_tx_info_clear_status would
780 * clear the counts too and we need them.
781 */
782 memset(&info->status.ampdu_ack_len, 0,
783 sizeof(struct ieee80211_tx_info) -
784 offsetof(struct ieee80211_tx_info, status.ampdu_ack_len));
785 BUILD_BUG_ON(offsetof(struct ieee80211_tx_info,
786 status.ampdu_ack_len) != 23);
787
27df605e 788 if (entry_hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_ALIGN))
9de5776f
CL		 789 pad = entry_data->align[0];
790
791 /* walk through the rates array and adjust the counts */
27df605e 792 count = payload->tries;
9de5776f
CL		 793 for (idx = 0; idx < 4; idx++) {
794 if (count >= info->status.rates[idx].count) {
795 count -= info->status.rates[idx].count;
796 } else if (count > 0) {
797 info->status.rates[idx].count = count;
798 count = 0;
799 } else {
800 info->status.rates[idx].idx = -1;
801 info->status.rates[idx].count = 0;
eff1a59c 802 }
9de5776f 803 }
c12abae3 804
9de5776f
CL		 805 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
806 (!payload->status))
807 info->flags |= IEEE80211_TX_STAT_ACK;
9e7f3f8e 808 if (payload->status & P54_TX_PSM_CANCELLED)
9de5776f
CL		 809 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
810 info->status.ack_signal = p54_rssi_to_dbm(dev,
27df605e 811 (int)payload->ack_rssi);
9de5776f
CL		 812 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
813 ieee80211_tx_status_irqsafe(dev, entry);
814 goto out;
eff1a59c 815 }
031d10ee 816 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
eff1a59c 817
031d10ee 818out:
27df605e 819 if (freed >= priv->headroom + sizeof(struct p54_hdr) + 48 +
9de5776f 820 IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
eff1a59c
MW		 821 p54_wake_free_queues(dev);
822}
823
7cb77072
CL		 824static void p54_rx_eeprom_readback(struct ieee80211_hw *dev,
825 struct sk_buff *skb)
826{
27df605e 827 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
7cb77072
CL		 828 struct p54_eeprom_lm86 *eeprom = (struct p54_eeprom_lm86 *) hdr->data;
829 struct p54_common *priv = dev->priv;
830
831 if (!priv->eeprom)
832 return ;
833
64c354dd
CL		 834 if (priv->fw_var >= 0x509) {
835 memcpy(priv->eeprom, eeprom->v2.data,
836 le16_to_cpu(eeprom->v2.len));
837 } else {
838 memcpy(priv->eeprom, eeprom->v1.data,
839 le16_to_cpu(eeprom->v1.len));
840 }
7cb77072
CL		 841
842 complete(&priv->eeprom_comp);
843}
844
cc6de669
CL		 845static void p54_rx_stats(struct ieee80211_hw *dev, struct sk_buff *skb)
846{
847 struct p54_common *priv = dev->priv;
27df605e 848 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
cc6de669 849 struct p54_statistics *stats = (struct p54_statistics *) hdr->data;
54fdb040
CL		 850 u32 tsf32;
851
852 if (unlikely(priv->mode == NL80211_IFTYPE_UNSPECIFIED))
853 return ;
cc6de669 854
54fdb040 855 tsf32 = le32_to_cpu(stats->tsf32);
cc6de669
CL		 856 if (tsf32 < priv->tsf_low32)
857 priv->tsf_high32++;
858 priv->tsf_low32 = tsf32;
859
860 priv->stats.dot11RTSFailureCount = le32_to_cpu(stats->rts_fail);
861 priv->stats.dot11RTSSuccessCount = le32_to_cpu(stats->rts_success);
862 priv->stats.dot11FCSErrorCount = le32_to_cpu(stats->rx_bad_fcs);
863
864 priv->noise = p54_rssi_to_dbm(dev, le32_to_cpu(stats->noise));
cc6de669 865
54fdb040 866 p54_free_skb(dev, p54_find_tx_entry(dev, hdr->req_id));
cc6de669
CL		 867}
868
e5ea92a7
CL		 869static void p54_rx_trap(struct ieee80211_hw *dev, struct sk_buff *skb)
870{
871 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
872 struct p54_trap *trap = (struct p54_trap *) hdr->data;
873 u16 event = le16_to_cpu(trap->event);
874 u16 freq = le16_to_cpu(trap->frequency);
875
876 switch (event) {
877 case P54_TRAP_BEACON_TX:
878 break;
879 case P54_TRAP_RADAR:
880 printk(KERN_INFO "%s: radar (freq:%d MHz)\n",
881 wiphy_name(dev->wiphy), freq);
882 break;
883 case P54_TRAP_NO_BEACON:
884 break;
885 case P54_TRAP_SCAN:
886 break;
887 case P54_TRAP_TBTT:
888 break;
889 case P54_TRAP_TIMER:
890 break;
891 default:
892 printk(KERN_INFO "%s: received event:%x freq:%d\n",
893 wiphy_name(dev->wiphy), event, freq);
894 break;
895 }
896}
897
19c19d54 898static int p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 899{
27df605e 900 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
eff1a59c
MW		 901
902 switch (le16_to_cpu(hdr->type)) {
903 case P54_CONTROL_TYPE_TXDONE:
904 p54_rx_frame_sent(dev, skb);
905 break;
e5ea92a7
CL		 906 case P54_CONTROL_TYPE_TRAP:
907 p54_rx_trap(dev, skb);
908 break;
eff1a59c
MW		 909 case P54_CONTROL_TYPE_BBP:
910 break;
cc6de669
CL		 911 case P54_CONTROL_TYPE_STAT_READBACK:
912 p54_rx_stats(dev, skb);
913 break;
7cb77072
CL		 914 case P54_CONTROL_TYPE_EEPROM_READBACK:
915 p54_rx_eeprom_readback(dev, skb);
916 break;
eff1a59c
MW		 917 default:
918 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
919 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
920 break;
921 }
19c19d54
CL		 922
923 return 0;
eff1a59c
MW		 924}
925
926/* returns zero if skb can be reused */
927int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
928{
9e7f3f8e 929 u16 type = le16_to_cpu(*((__le16 *)skb->data));
19c19d54 930
9e7f3f8e 931 if (type & P54_HDR_FLAG_CONTROL)
19c19d54
CL		 932 return p54_rx_control(dev, skb);
933 else
934 return p54_rx_data(dev, skb);
eff1a59c
MW		 935}
936EXPORT_SYMBOL_GPL(p54_rx);
937
938/*
939 * So, the firmware is somewhat stupid and doesn't know what places in its
940 * memory incoming data should go to. By poking around in the firmware, we
941 * can find some unused memory to upload our packets to. However, data that we
942 * want the card to TX needs to stay intact until the card has told us that
943 * it is done with it. This function finds empty places we can upload to and
944 * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
945 * allocated areas.
946 */
b92f30d6 947static int p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
27df605e 948 struct p54_hdr *data, u32 len)
eff1a59c
MW		 949{
950 struct p54_common *priv = dev->priv;
951 struct sk_buff *entry = priv->tx_queue.next;
952 struct sk_buff *target_skb = NULL;
b92f30d6
CL		 953 struct ieee80211_tx_info *info;
954 struct memrecord *range;
eff1a59c
MW		 955 u32 last_addr = priv->rx_start;
956 u32 largest_hole = 0;
957 u32 target_addr = priv->rx_start;
958 unsigned long flags;
959 unsigned int left;
4e416a6f 960 len = (len + priv->headroom + priv->tailroom + 3) & ~0x3;
eff1a59c 961
b92f30d6
CL		 962 if (!skb)
963 return -EINVAL;
964
eff1a59c 965 spin_lock_irqsave(&priv->tx_queue.lock, flags);
39ca5bb7 966
eff1a59c 967 left = skb_queue_len(&priv->tx_queue);
39ca5bb7
CL		 968 if (unlikely(left >= 28)) {
969 /*
970 * The tx_queue is nearly full!
971 * We have throttle normal data traffic, because we must
972 * have a few spare slots for control frames left.
973 */
974 ieee80211_stop_queues(dev);
54fdb040
CL		 975 queue_delayed_work(dev->workqueue, &priv->work,
976 msecs_to_jiffies(P54_TX_TIMEOUT));
39ca5bb7
CL		 977
978 if (unlikely(left == 32)) {
979 /*
980 * The tx_queue is now really full.
981 *
982 * TODO: check if the device has crashed and reset it.
983 */
984 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
985 return -ENOSPC;
986 }
987 }
988
eff1a59c
MW		 989 while (left--) {
990 u32 hole_size;
b92f30d6
CL		 991 info = IEEE80211_SKB_CB(entry);
992 range = (void *)info->rate_driver_data;
eff1a59c
MW		 993 hole_size = range->start_addr - last_addr;
994 if (!target_skb && hole_size >= len) {
995 target_skb = entry->prev;
996 hole_size -= len;
997 target_addr = last_addr;
998 }
999 largest_hole = max(largest_hole, hole_size);
1000 last_addr = range->end_addr;
1001 entry = entry->next;
1002 }
1003 if (!target_skb && priv->rx_end - last_addr >= len) {
1004 target_skb = priv->tx_queue.prev;
1005 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
1006 if (!skb_queue_empty(&priv->tx_queue)) {
b92f30d6
CL		 1007 info = IEEE80211_SKB_CB(target_skb);
1008 range = (void *)info->rate_driver_data;
eff1a59c
MW		 1009 target_addr = range->end_addr;
1010 }
1011 } else
1012 largest_hole = max(largest_hole, priv->rx_end - last_addr);
1013
b92f30d6
CL		 1014 if (!target_skb) {
1015 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
1016 ieee80211_stop_queues(dev);
39ca5bb7 1017 return -ENOSPC;
eff1a59c 1018 }
b92f30d6
CL		 1019
1020 info = IEEE80211_SKB_CB(skb);
1021 range = (void *)info->rate_driver_data;
1022 range->start_addr = target_addr;
1023 range->end_addr = target_addr + len;
1024 __skb_queue_after(&priv->tx_queue, target_skb, skb);
eff1a59c
MW		 1025 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
1026
27df605e 1027 if (largest_hole < priv->headroom + sizeof(struct p54_hdr) +
b92f30d6
CL		 1028 48 + IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
1029 ieee80211_stop_queues(dev);
1030
4e416a6f 1031 data->req_id = cpu_to_le32(target_addr + priv->headroom);
b92f30d6
CL		 1032 return 0;
1033}
1034
1035static struct sk_buff *p54_alloc_skb(struct ieee80211_hw *dev,
1036 u16 hdr_flags, u16 len, u16 type, gfp_t memflags)
1037{
1038 struct p54_common *priv = dev->priv;
27df605e 1039 struct p54_hdr *hdr;
b92f30d6
CL		 1040 struct sk_buff *skb;
1041
1042 skb = __dev_alloc_skb(len + priv->tx_hdr_len, memflags);
1043 if (!skb)
1044 return NULL;
1045 skb_reserve(skb, priv->tx_hdr_len);
1046
27df605e
JL		 1047 hdr = (struct p54_hdr *) skb_put(skb, sizeof(*hdr));
1048 hdr->flags = cpu_to_le16(hdr_flags);
b92f30d6
CL		 1049 hdr->len = cpu_to_le16(len - sizeof(*hdr));
1050 hdr->type = cpu_to_le16(type);
27df605e 1051 hdr->tries = hdr->rts_tries = 0;
b92f30d6
CL		 1052
1053 if (unlikely(p54_assign_address(dev, skb, hdr, len))) {
1054 kfree_skb(skb);
1055 return NULL;
1056 }
1057 return skb;
eff1a59c
MW		 1058}
1059
7cb77072
CL		 1060int p54_read_eeprom(struct ieee80211_hw *dev)
1061{
1062 struct p54_common *priv = dev->priv;
27df605e 1063 struct p54_hdr *hdr = NULL;
7cb77072 1064 struct p54_eeprom_lm86 *eeprom_hdr;
b92f30d6 1065 struct sk_buff *skb;
64c354dd 1066 size_t eeprom_size = 0x2020, offset = 0, blocksize, maxblocksize;
7cb77072
CL		 1067 int ret = -ENOMEM;
1068 void *eeprom = NULL;
1069
64c354dd
CL		 1070 maxblocksize = EEPROM_READBACK_LEN;
1071 if (priv->fw_var >= 0x509)
1072 maxblocksize -= 0xc;
1073 else
1074 maxblocksize -= 0x4;
1075
1076 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL, sizeof(*hdr) +
1077 sizeof(*eeprom_hdr) + maxblocksize,
b92f30d6
CL		 1078 P54_CONTROL_TYPE_EEPROM_READBACK, GFP_KERNEL);
1079 if (!skb)
7cb77072 1080 goto free;
7cb77072
CL		 1081 priv->eeprom = kzalloc(EEPROM_READBACK_LEN, GFP_KERNEL);
1082 if (!priv->eeprom)
1083 goto free;
7cb77072
CL		 1084 eeprom = kzalloc(eeprom_size, GFP_KERNEL);
1085 if (!eeprom)
1086 goto free;
1087
b92f30d6 1088 eeprom_hdr = (struct p54_eeprom_lm86 *) skb_put(skb,
64c354dd 1089 sizeof(*eeprom_hdr) + maxblocksize);
7cb77072
CL		 1090
1091 while (eeprom_size) {
64c354dd
CL		 1092 blocksize = min(eeprom_size, maxblocksize);
1093 if (priv->fw_var < 0x509) {
1094 eeprom_hdr->v1.offset = cpu_to_le16(offset);
1095 eeprom_hdr->v1.len = cpu_to_le16(blocksize);
1096 } else {
1097 eeprom_hdr->v2.offset = cpu_to_le32(offset);
1098 eeprom_hdr->v2.len = cpu_to_le16(blocksize);
1099 eeprom_hdr->v2.magic2 = 0xf;
1100 memcpy(eeprom_hdr->v2.magic, (const char *)"LOCK", 4);
1101 }
0a5ec96a 1102 priv->tx(dev, skb);
7cb77072
CL		 1103
1104 if (!wait_for_completion_interruptible_timeout(&priv->eeprom_comp, HZ)) {
1105 printk(KERN_ERR "%s: device does not respond!\n",
1106 wiphy_name(dev->wiphy));
1107 ret = -EBUSY;
1108 goto free;
1109 }
1110
1111 memcpy(eeprom + offset, priv->eeprom, blocksize);
1112 offset += blocksize;
1113 eeprom_size -= blocksize;
1114 }
1115
1116 ret = p54_parse_eeprom(dev, eeprom, offset);
1117free:
1118 kfree(priv->eeprom);
1119 priv->eeprom = NULL;
b92f30d6 1120 p54_free_skb(dev, skb);
7cb77072
CL		 1121 kfree(eeprom);
1122
1123 return ret;
1124}
1125EXPORT_SYMBOL_GPL(p54_read_eeprom);
1126
e5ea92a7
CL		 1127static int p54_set_tim(struct ieee80211_hw *dev, struct ieee80211_sta *sta,
1128 bool set)
1129{
1130 struct p54_common *priv = dev->priv;
1131 struct sk_buff *skb;
1132 struct p54_tim *tim;
1133
1134 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET,
1135 sizeof(struct p54_hdr) + sizeof(*tim),
1136 P54_CONTROL_TYPE_TIM, GFP_KERNEL);
1137 if (!skb)
1138 return -ENOMEM;
1139
1140 tim = (struct p54_tim *) skb_put(skb, sizeof(*tim));
1141 tim->count = 1;
1142 tim->entry[0] = cpu_to_le16(set ? (sta->aid | 0x8000) : sta->aid);
0a5ec96a 1143 priv->tx(dev, skb);
e5ea92a7
CL		 1144 return 0;
1145}
1146
1147static int p54_sta_unlock(struct ieee80211_hw *dev, u8 *addr)
1148{
1149 struct p54_common *priv = dev->priv;
1150 struct sk_buff *skb;
1151 struct p54_sta_unlock *sta;
1152
1153 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET,
1154 sizeof(struct p54_hdr) + sizeof(*sta),
1155 P54_CONTROL_TYPE_PSM_STA_UNLOCK, GFP_ATOMIC);
1156 if (!skb)
1157 return -ENOMEM;
1158
1159 sta = (struct p54_sta_unlock *)skb_put(skb, sizeof(*sta));
1160 memcpy(sta->addr, addr, ETH_ALEN);
0a5ec96a 1161 priv->tx(dev, skb);
e5ea92a7
CL		 1162 return 0;
1163}
1164
c772a08b
CL		 1165static void p54_sta_notify(struct ieee80211_hw *dev, struct ieee80211_vif *vif,
1166 enum sta_notify_cmd notify_cmd,
1167 struct ieee80211_sta *sta)
1168{
1169 switch (notify_cmd) {
1170 case STA_NOTIFY_ADD:
1171 case STA_NOTIFY_REMOVE:
1172 /*
1173 * Notify the firmware that we don't want or we don't
1174 * need to buffer frames for this station anymore.
1175 */
1176
89fad578
CL		 1177 p54_sta_unlock(dev, sta->addr);
1178 break;
1179 case STA_NOTIFY_AWAKE:
1180 /* update the firmware's filter table */
c772a08b
CL		 1181 p54_sta_unlock(dev, sta->addr);
1182 break;
1183 default:
1184 break;
1185 }
1186}
1187
e5ea92a7
CL		 1188static int p54_tx_cancel(struct ieee80211_hw *dev, struct sk_buff *entry)
1189{
1190 struct p54_common *priv = dev->priv;
1191 struct sk_buff *skb;
1192 struct p54_hdr *hdr;
1193 struct p54_txcancel *cancel;
1194
1195 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET,
1196 sizeof(struct p54_hdr) + sizeof(*cancel),
1197 P54_CONTROL_TYPE_TXCANCEL, GFP_ATOMIC);
1198 if (!skb)
1199 return -ENOMEM;
1200
1201 hdr = (void *)entry->data;
1202 cancel = (struct p54_txcancel *)skb_put(skb, sizeof(*cancel));
1203 cancel->req_id = hdr->req_id;
0a5ec96a 1204 priv->tx(dev, skb);
e5ea92a7
CL		 1205 return 0;
1206}
1207
94585b09
CL		 1208static int p54_tx_fill(struct ieee80211_hw *dev, struct sk_buff *skb,
1209 struct ieee80211_tx_info *info, u8 *queue, size_t *extra_len,
1210 u16 *flags, u16 *aid)
1211{
1212 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1213 struct p54_common *priv = dev->priv;
1214 int ret = 0;
1215
1216 if (unlikely(ieee80211_is_mgmt(hdr->frame_control))) {
1217 if (ieee80211_is_beacon(hdr->frame_control)) {
1218 *aid = 0;
1219 *queue = 0;
1220 *extra_len = IEEE80211_MAX_TIM_LEN;
1221 *flags = P54_HDR_FLAG_DATA_OUT_TIMESTAMP;
1222 return 0;
1223 } else if (ieee80211_is_probe_resp(hdr->frame_control)) {
1224 *aid = 0;
1225 *queue = 2;
1226 *flags = P54_HDR_FLAG_DATA_OUT_TIMESTAMP |
1227 P54_HDR_FLAG_DATA_OUT_NOCANCEL;
1228 return 0;
1229 } else {
1230 *queue = 2;
1231 ret = 0;
1232 }
1233 } else {
1234 *queue += 4;
1235 ret = 1;
1236 }
1237
1238 switch (priv->mode) {
1239 case NL80211_IFTYPE_STATION:
1240 *aid = 1;
1241 break;
1242 case NL80211_IFTYPE_AP:
1243 case NL80211_IFTYPE_ADHOC:
d131bb59 1244 case NL80211_IFTYPE_MESH_POINT:
94585b09
CL		 1245 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1246 *aid = 0;
1247 *queue = 3;
1248 return 0;
1249 }
1250 if (info->control.sta)
1251 *aid = info->control.sta->aid;
1252 else
c772a08b 1253 *flags |= P54_HDR_FLAG_DATA_OUT_NOCANCEL;
94585b09
CL		 1254 }
1255 return ret;
1256}
1257
25900ef0
CL		 1258static u8 p54_convert_algo(enum ieee80211_key_alg alg)
1259{
1260 switch (alg) {
1261 case ALG_WEP:
1262 return P54_CRYPTO_WEP;
1263 case ALG_TKIP:
1264 return P54_CRYPTO_TKIPMICHAEL;
1265 case ALG_CCMP:
1266 return P54_CRYPTO_AESCCMP;
1267 default:
1268 return 0;
1269 }
1270}
1271
e039fa4a 1272static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 1273{
e039fa4a 1274 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
9e7f3f8e 1275 struct ieee80211_tx_queue_stats *current_queue = NULL;
eff1a59c 1276 struct p54_common *priv = dev->priv;
27df605e
JL		 1277 struct p54_hdr *hdr;
1278 struct p54_tx_data *txhdr;
db4186cf 1279 size_t padding, len, tim_len = 0;
c772a08b 1280 int i, j, ridx, ret;
94585b09 1281 u16 hdr_flags = 0, aid = 0;
25900ef0 1282 u8 rate, queue, crypt_offset = 0;
aaa15535 1283 u8 cts_rate = 0x20;
e6a9854b 1284 u8 rc_flags;
c12abae3
JB		 1285 u8 calculated_tries[4];
1286 u8 nrates = 0, nremaining = 8;
eff1a59c 1287
94585b09
CL		 1288 queue = skb_get_queue_mapping(skb);
1289
c772a08b
CL		 1290 ret = p54_tx_fill(dev, skb, info, &queue, &tim_len, &hdr_flags, &aid);
1291 current_queue = &priv->tx_stats[queue];
1292 if (unlikely((current_queue->len > current_queue->limit) && ret))
1293 return NETDEV_TX_BUSY;
1294 current_queue->len++;
1295 current_queue->count++;
1296 if ((current_queue->len == current_queue->limit) && ret)
1297 ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
eff1a59c
MW		 1298
1299 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
1300 len = skb->len;
1301
25900ef0
CL		 1302 if (info->control.hw_key) {
1303 crypt_offset = ieee80211_get_hdrlen_from_skb(skb);
1304 if (info->control.hw_key->alg == ALG_TKIP) {
1305 u8 *iv = (u8 *)(skb->data + crypt_offset);
1306 /*
1307 * The firmware excepts that the IV has to have
1308 * this special format
1309 */
1310 iv[1] = iv[0];
1311 iv[0] = iv[2];
1312 iv[2] = 0;
1313 }
1314 }
1315
27df605e
JL		 1316 txhdr = (struct p54_tx_data *) skb_push(skb, sizeof(*txhdr) + padding);
1317 hdr = (struct p54_hdr *) skb_push(skb, sizeof(*hdr));
eff1a59c
MW		 1318
1319 if (padding)
9e7f3f8e 1320 hdr_flags |= P54_HDR_FLAG_DATA_ALIGN;
94585b09 1321 hdr->type = cpu_to_le16(aid);
27df605e 1322 hdr->rts_tries = info->control.rates[0].count;
c12abae3
JB		 1323
1324 /*
1325 * we register the rates in perfect order, and
1326 * RTS/CTS won't happen on 5 GHz
1327 */
1328 cts_rate = info->control.rts_cts_rate_idx;
1329
1330 memset(&txhdr->rateset, 0, sizeof(txhdr->rateset));
1331
1332 /* see how many rates got used */
1333 for (i = 0; i < 4; i++) {
1334 if (info->control.rates[i].idx < 0)
1335 break;
1336 nrates++;
1337 }
1338
1339 /* limit tries to 8/nrates per rate */
1340 for (i = 0; i < nrates; i++) {
1341 /*
1342 * The magic expression here is equivalent to 8/nrates for
1343 * all values that matter, but avoids division and jumps.
1344 * Note that nrates can only take the values 1 through 4.
1345 */
1346 calculated_tries[i] = min_t(int, ((15 >> nrates) | 1) + 1,
1347 info->control.rates[i].count);
1348 nremaining -= calculated_tries[i];
aaa15535 1349 }
c12abae3
JB		 1350
1351 /* if there are tries left, distribute from back to front */
1352 for (i = nrates - 1; nremaining > 0 && i >= 0; i--) {
1353 int tmp = info->control.rates[i].count - calculated_tries[i];
1354
1355 if (tmp <= 0)
1356 continue;
1357 /* RC requested more tries at this rate */
1358
1359 tmp = min_t(int, tmp, nremaining);
1360 calculated_tries[i] += tmp;
1361 nremaining -= tmp;
aaa15535 1362 }
c12abae3
JB		 1363
1364 ridx = 0;
1365 for (i = 0; i < nrates && ridx < 8; i++) {
1366 /* we register the rates in perfect order */
1367 rate = info->control.rates[i].idx;
1368 if (info->band == IEEE80211_BAND_5GHZ)
1369 rate += 4;
1370
1371 /* store the count we actually calculated for TX status */
1372 info->control.rates[i].count = calculated_tries[i];
1373
1374 rc_flags = info->control.rates[i].flags;
1375 if (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) {
1376 rate |= 0x10;
1377 cts_rate |= 0x10;
1378 }
1379 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1380 rate |= 0x40;
1381 else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1382 rate |= 0x20;
1383 for (j = 0; j < calculated_tries[i] && ridx < 8; j++) {
1384 txhdr->rateset[ridx] = rate;
1385 ridx++;
1386 }
1387 }
9e7f3f8e
CL		 1388
1389 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
1390 hdr_flags |= P54_HDR_FLAG_DATA_OUT_SEQNR;
1391
1392 /* TODO: enable bursting */
1393 hdr->flags = cpu_to_le16(hdr_flags);
27df605e 1394 hdr->tries = ridx;
27df605e 1395 txhdr->rts_rate_idx = 0;
25900ef0
CL		 1396 if (info->control.hw_key) {
1397 crypt_offset += info->control.hw_key->iv_len;
1398 txhdr->key_type = p54_convert_algo(info->control.hw_key->alg);
1399 txhdr->key_len = min((u8)16, info->control.hw_key->keylen);
1400 memcpy(txhdr->key, info->control.hw_key->key, txhdr->key_len);
1401 if (info->control.hw_key->alg == ALG_TKIP) {
1402 if (unlikely(skb_tailroom(skb) < 12))
1403 goto err;
1404 /* reserve space for the MIC key */
1405 len += 8;
1406 memcpy(skb_put(skb, 8), &(info->control.hw_key->key
1407 [NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY]), 8);
1408 }
1409 /* reserve some space for ICV */
1410 len += info->control.hw_key->icv_len;
1411 } else {
1412 txhdr->key_type = 0;
1413 txhdr->key_len = 0;
1414 }
1415 txhdr->crypt_offset = crypt_offset;
94585b09 1416 txhdr->hw_queue = queue;
ffed7858
CL		 1417 if (current_queue)
1418 txhdr->backlog = current_queue->len;
1419 else
1420 txhdr->backlog = 0;
27df605e 1421 memset(txhdr->durations, 0, sizeof(txhdr->durations));
aaa15535 1422 txhdr->tx_antenna = (info->antenna_sel_tx == 0) ?
e039fa4a 1423 2 : info->antenna_sel_tx - 1;
09adf284 1424 txhdr->output_power = priv->output_power;
27df605e 1425 txhdr->cts_rate = cts_rate;
eff1a59c
MW		 1426 if (padding)
1427 txhdr->align[0] = padding;
1428
25900ef0 1429 hdr->len = cpu_to_le16(len);
e039fa4a 1430 /* modifies skb->cb and with it info, so must be last! */
25900ef0
CL		 1431 if (unlikely(p54_assign_address(dev, skb, hdr, skb->len + tim_len)))
1432 goto err;
0a5ec96a 1433 priv->tx(dev, skb);
54fdb040
CL		 1434
1435 queue_delayed_work(dev->workqueue, &priv->work,
1436 msecs_to_jiffies(P54_TX_FRAME_LIFETIME));
1437
eff1a59c 1438 return 0;
25900ef0
CL		 1439
1440 err:
1441 skb_pull(skb, sizeof(*hdr) + sizeof(*txhdr) + padding);
1442 if (current_queue) {
1443 current_queue->len--;
1444 current_queue->count--;
1445 }
1446 return NETDEV_TX_BUSY;
eff1a59c
MW		 1447}
1448
b2023ddc 1449static int p54_setup_mac(struct ieee80211_hw *dev)
eff1a59c
MW		 1450{
1451 struct p54_common *priv = dev->priv;
b92f30d6 1452 struct sk_buff *skb;
5e73444e 1453 struct p54_setup_mac *setup;
b2023ddc 1454 u16 mode;
eff1a59c 1455
27df605e
JL		 1456 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*setup) +
1457 sizeof(struct p54_hdr), P54_CONTROL_TYPE_SETUP,
b92f30d6
CL		 1458 GFP_ATOMIC);
1459 if (!skb)
1460 return -ENOMEM;
eff1a59c 1461
5e73444e 1462 setup = (struct p54_setup_mac *) skb_put(skb, sizeof(*setup));
b2023ddc
CL		 1463 if (dev->conf.radio_enabled) {
1464 switch (priv->mode) {
1465 case NL80211_IFTYPE_STATION:
1466 mode = P54_FILTER_TYPE_STATION;
1467 break;
1468 case NL80211_IFTYPE_AP:
1469 mode = P54_FILTER_TYPE_AP;
1470 break;
1471 case NL80211_IFTYPE_ADHOC:
1472 case NL80211_IFTYPE_MESH_POINT:
1473 mode = P54_FILTER_TYPE_IBSS;
1474 break;
1475 default:
1476 mode = P54_FILTER_TYPE_NONE;
1477 break;
1478 }
1479 if (priv->filter_flags & FIF_PROMISC_IN_BSS)
1480 mode |= P54_FILTER_TYPE_TRANSPARENT;
1481 } else
1482 mode = P54_FILTER_TYPE_RX_DISABLED;
1483
5e73444e
CL		 1484 setup->mac_mode = cpu_to_le16(mode);
1485 memcpy(setup->mac_addr, priv->mac_addr, ETH_ALEN);
b2023ddc
CL		 1486 memcpy(setup->bssid, priv->bssid, ETH_ALEN);
1487 setup->rx_antenna = 2; /* automatic */
9483407d 1488 setup->rx_align = 0;
19c19d54 1489 if (priv->fw_var < 0x500) {
ced09574 1490 setup->v1.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
9483407d 1491 memset(setup->v1.rts_rates, 0, 8);
5e73444e
CL		 1492 setup->v1.rx_addr = cpu_to_le32(priv->rx_end);
1493 setup->v1.max_rx = cpu_to_le16(priv->rx_mtu);
1494 setup->v1.rxhw = cpu_to_le16(priv->rxhw);
ced09574 1495 setup->v1.wakeup_timer = cpu_to_le16(priv->wakeup_timer);
5e73444e 1496 setup->v1.unalloc0 = cpu_to_le16(0);
19c19d54 1497 } else {
5e73444e
CL		 1498 setup->v2.rx_addr = cpu_to_le32(priv->rx_end);
1499 setup->v2.max_rx = cpu_to_le16(priv->rx_mtu);
1500 setup->v2.rxhw = cpu_to_le16(priv->rxhw);
ced09574 1501 setup->v2.timer = cpu_to_le16(priv->wakeup_timer);
5e73444e 1502 setup->v2.truncate = cpu_to_le16(48896);
ced09574 1503 setup->v2.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
5e73444e
CL		 1504 setup->v2.sbss_offset = 0;
1505 setup->v2.mcast_window = 0;
1506 setup->v2.rx_rssi_threshold = 0;
1507 setup->v2.rx_ed_threshold = 0;
1508 setup->v2.ref_clock = cpu_to_le32(644245094);
1509 setup->v2.lpf_bandwidth = cpu_to_le16(65535);
1510 setup->v2.osc_start_delay = cpu_to_le16(65535);
19c19d54 1511 }
0a5ec96a 1512 priv->tx(dev, skb);
eff1a59c
MW		 1513 return 0;
1514}
1515
69ba3e5d 1516static int p54_scan(struct ieee80211_hw *dev, u16 mode, u16 dwell)
eff1a59c
MW		 1517{
1518 struct p54_common *priv = dev->priv;
b92f30d6 1519 struct sk_buff *skb;
27df605e 1520 struct p54_scan *chan;
eff1a59c 1521 unsigned int i;
eff1a59c 1522 void *entry;
69ba3e5d
CL		 1523 __le16 freq = cpu_to_le16(dev->conf.channel->center_freq);
1524 int band = dev->conf.channel->band;
eff1a59c 1525
27df605e
JL		 1526 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*chan) +
1527 sizeof(struct p54_hdr), P54_CONTROL_TYPE_SCAN,
1528 GFP_ATOMIC);
b92f30d6 1529 if (!skb)
eff1a59c
MW		 1530 return -ENOMEM;
1531
27df605e 1532 chan = (struct p54_scan *) skb_put(skb, sizeof(*chan));
b92f30d6 1533 memset(chan->padding1, 0, sizeof(chan->padding1));
b2023ddc
CL		 1534 chan->mode = cpu_to_le16(mode);
1535 chan->dwell = cpu_to_le16(dwell);
eff1a59c
MW		 1536
1537 for (i = 0; i < priv->iq_autocal_len; i++) {
1538 if (priv->iq_autocal[i].freq != freq)
1539 continue;
1540
1541 memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
1542 sizeof(*priv->iq_autocal));
1543 break;
1544 }
1545 if (i == priv->iq_autocal_len)
1546 goto err;
1547
1548 for (i = 0; i < priv->output_limit_len; i++) {
1549 if (priv->output_limit[i].freq != freq)
1550 continue;
1551
1552 chan->val_barker = 0x38;
154e3af1
CL		 1553 chan->val_bpsk = chan->dup_bpsk =
1554 priv->output_limit[i].val_bpsk;
1555 chan->val_qpsk = chan->dup_qpsk =
1556 priv->output_limit[i].val_qpsk;
1557 chan->val_16qam = chan->dup_16qam =
1558 priv->output_limit[i].val_16qam;
1559 chan->val_64qam = chan->dup_64qam =
1560 priv->output_limit[i].val_64qam;
eff1a59c
MW		 1561 break;
1562 }
1563 if (i == priv->output_limit_len)
1564 goto err;
1565
eff1a59c
MW		 1566 entry = priv->curve_data->data;
1567 for (i = 0; i < priv->curve_data->channels; i++) {
1568 if (*((__le16 *)entry) != freq) {
1569 entry += sizeof(__le16);
154e3af1
CL		 1570 entry += sizeof(struct p54_pa_curve_data_sample) *
1571 priv->curve_data->points_per_channel;
eff1a59c
MW		 1572 continue;
1573 }
1574
1575 entry += sizeof(__le16);
9483407d
C		 1576 chan->pa_points_per_curve = 8;
1577 memset(chan->curve_data, 0, sizeof(*chan->curve_data));
1578 memcpy(chan->curve_data, entry,
1579 sizeof(struct p54_pa_curve_data_sample) *
1580 min((u8)8, priv->curve_data->points_per_channel));
eff1a59c
MW		 1581 break;
1582 }
1583
19c19d54 1584 if (priv->fw_var < 0x500) {
69ba3e5d
CL		 1585 chan->v1_rssi.mul = cpu_to_le16(priv->rssical_db[band].mul);
1586 chan->v1_rssi.add = cpu_to_le16(priv->rssical_db[band].add);
19c19d54 1587 } else {
69ba3e5d
CL		 1588 chan->v2.rssi.mul = cpu_to_le16(priv->rssical_db[band].mul);
1589 chan->v2.rssi.add = cpu_to_le16(priv->rssical_db[band].add);
ced09574 1590 chan->v2.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
27df605e 1591 memset(chan->v2.rts_rates, 0, 8);
19c19d54 1592 }
0a5ec96a 1593 priv->tx(dev, skb);
eff1a59c
MW		 1594 return 0;
1595
1596 err:
1597 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
b92f30d6 1598 kfree_skb(skb);
eff1a59c
MW		 1599 return -EINVAL;
1600}
1601
1602static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
1603{
1604 struct p54_common *priv = dev->priv;
b92f30d6 1605 struct sk_buff *skb;
27df605e 1606 struct p54_led *led;
eff1a59c 1607
27df605e
JL		 1608 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*led) +
1609 sizeof(struct p54_hdr), P54_CONTROL_TYPE_LED,
1610 GFP_ATOMIC);
b92f30d6 1611 if (!skb)
eff1a59c
MW		 1612 return -ENOMEM;
1613
27df605e 1614 led = (struct p54_led *)skb_put(skb, sizeof(*led));
eff1a59c
MW		 1615 led->mode = cpu_to_le16(mode);
1616 led->led_permanent = cpu_to_le16(link);
1617 led->led_temporary = cpu_to_le16(act);
1618 led->duration = cpu_to_le16(1000);
0a5ec96a 1619 priv->tx(dev, skb);
eff1a59c
MW		 1620 return 0;
1621}
1622
3330d7be 1623#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \
eff1a59c
MW		 1624do { \
1625 queue.aifs = cpu_to_le16(ai_fs); \
1626 queue.cwmin = cpu_to_le16(cw_min); \
1627 queue.cwmax = cpu_to_le16(cw_max); \
3330d7be 1628 queue.txop = cpu_to_le16(_txop); \
eff1a59c
MW		 1629} while(0)
1630
0fdd7c5d 1631static int p54_set_edcf(struct ieee80211_hw *dev)
eff1a59c
MW		 1632{
1633 struct p54_common *priv = dev->priv;
b92f30d6 1634 struct sk_buff *skb;
0fdd7c5d 1635 struct p54_edcf *edcf;
eff1a59c 1636
27df605e
JL		 1637 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*edcf) +
1638 sizeof(struct p54_hdr), P54_CONTROL_TYPE_DCFINIT,
1639 GFP_ATOMIC);
b92f30d6 1640 if (!skb)
0fdd7c5d
CL		 1641 return -ENOMEM;
1642
b92f30d6 1643 edcf = (struct p54_edcf *)skb_put(skb, sizeof(*edcf));
40333e4f 1644 if (priv->use_short_slot) {
0fdd7c5d
CL		 1645 edcf->slottime = 9;
1646 edcf->sifs = 0x10;
1647 edcf->eofpad = 0x00;
eff1a59c 1648 } else {
0fdd7c5d
CL		 1649 edcf->slottime = 20;
1650 edcf->sifs = 0x0a;
1651 edcf->eofpad = 0x06;
eff1a59c 1652 }
eff1a59c 1653 /* (see prism54/isl_oid.h for further details) */
0fdd7c5d
CL		 1654 edcf->frameburst = cpu_to_le16(0);
1655 edcf->round_trip_delay = cpu_to_le16(0);
9483407d 1656 edcf->flags = 0;
0fdd7c5d
CL		 1657 memset(edcf->mapping, 0, sizeof(edcf->mapping));
1658 memcpy(edcf->queue, priv->qos_params, sizeof(edcf->queue));
0a5ec96a 1659 priv->tx(dev, skb);
0fdd7c5d 1660 return 0;
eff1a59c
MW		 1661}
1662
e5ea92a7
CL		 1663static int p54_beacon_tim(struct sk_buff *skb)
1664{
1665 /*
1666 * the good excuse for this mess is ... the firmware.
1667 * The dummy TIM MUST be at the end of the beacon frame,
1668 * because it'll be overwritten!
1669 */
1670
1671 struct ieee80211_mgmt *mgmt = (void *)skb->data;
1672 u8 *pos, *end;
1673
02e37ba1 1674 if (skb->len <= sizeof(mgmt))
e5ea92a7 1675 return -EINVAL;
e5ea92a7
CL		 1676
1677 pos = (u8 *)mgmt->u.beacon.variable;
1678 end = skb->data + skb->len;
1679 while (pos < end) {
02e37ba1 1680 if (pos + 2 + pos[1] > end)
e5ea92a7 1681 return -EINVAL;
e5ea92a7
CL		 1682
1683 if (pos[0] == WLAN_EID_TIM) {
1684 u8 dtim_len = pos[1];
1685 u8 dtim_period = pos[3];
1686 u8 *next = pos + 2 + dtim_len;
1687
02e37ba1 1688 if (dtim_len < 3)
e5ea92a7 1689 return -EINVAL;
02e37ba1 1690
e5ea92a7
CL		 1691 memmove(pos, next, end - next);
1692
1693 if (dtim_len > 3)
1694 skb_trim(skb, skb->len - (dtim_len - 3));
1695
1696 pos = end - (dtim_len + 2);
1697
1698 /* add the dummy at the end */
1699 pos[0] = WLAN_EID_TIM;
1700 pos[1] = 3;
1701 pos[2] = 0;
1702 pos[3] = dtim_period;
1703 pos[4] = 0;
1704 return 0;
1705 }
1706 pos += 2 + pos[1];
1707 }
1708 return 0;
1709}
1710
1711static int p54_beacon_update(struct ieee80211_hw *dev,
1712 struct ieee80211_vif *vif)
1713{
1714 struct p54_common *priv = dev->priv;
1715 struct sk_buff *beacon;
1716 int ret;
1717
1718 if (priv->cached_beacon) {
1719 p54_tx_cancel(dev, priv->cached_beacon);
1720 /* wait for the last beacon the be freed */
1721 msleep(10);
1722 }
1723
1724 beacon = ieee80211_beacon_get(dev, vif);
1725 if (!beacon)
1726 return -ENOMEM;
1727 ret = p54_beacon_tim(beacon);
1728 if (ret)
1729 return ret;
1730 ret = p54_tx(dev, beacon);
1731 if (ret)
1732 return ret;
1733 priv->cached_beacon = beacon;
1734 priv->tsf_high32 = 0;
1735 priv->tsf_low32 = 0;
1736
1737 return 0;
1738}
1739
0f1be978
CL		 1740static int p54_start(struct ieee80211_hw *dev)
1741{
1742 struct p54_common *priv = dev->priv;
1743 int err;
cc6de669 1744
9e7f3f8e 1745 mutex_lock(&priv->conf_mutex);
4150c572 1746 err = priv->open(dev);
40db0b22
CL		 1747 if (err)
1748 goto out;
0fdd7c5d
CL		 1749 P54_SET_QUEUE(priv->qos_params[0], 0x0002, 0x0003, 0x0007, 47);
1750 P54_SET_QUEUE(priv->qos_params[1], 0x0002, 0x0007, 0x000f, 94);
1751 P54_SET_QUEUE(priv->qos_params[2], 0x0003, 0x000f, 0x03ff, 0);
1752 P54_SET_QUEUE(priv->qos_params[3], 0x0007, 0x000f, 0x03ff, 0);
1753 err = p54_set_edcf(dev);
40db0b22
CL		 1754 if (err)
1755 goto out;
b2023ddc
CL		 1756
1757 memset(priv->bssid, ~0, ETH_ALEN);
40db0b22 1758 priv->mode = NL80211_IFTYPE_MONITOR;
b2023ddc
CL		 1759 err = p54_setup_mac(dev);
1760 if (err) {
1761 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1762 goto out;
1763 }
4150c572 1764
54fdb040
CL		 1765 queue_delayed_work(dev->workqueue, &priv->work, 0);
1766
40db0b22 1767out:
9e7f3f8e 1768 mutex_unlock(&priv->conf_mutex);
4150c572
JB		 1769 return err;
1770}
1771
1772static void p54_stop(struct ieee80211_hw *dev)
1773{
1774 struct p54_common *priv = dev->priv;
1775 struct sk_buff *skb;
cc6de669 1776
9e7f3f8e 1777 mutex_lock(&priv->conf_mutex);
59651e89 1778 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
54fdb040 1779 cancel_delayed_work_sync(&priv->work);
e5ea92a7
CL		 1780 if (priv->cached_beacon)
1781 p54_tx_cancel(dev, priv->cached_beacon);
1782
59651e89 1783 priv->stop(dev);
e039fa4a 1784 while ((skb = skb_dequeue(&priv->tx_queue)))
4150c572 1785 kfree_skb(skb);
e5ea92a7 1786 priv->cached_beacon = NULL;
a0db663f 1787 priv->tsf_high32 = priv->tsf_low32 = 0;
9e7f3f8e 1788 mutex_unlock(&priv->conf_mutex);
4150c572
JB		 1789}
1790
eff1a59c
MW		 1791static int p54_add_interface(struct ieee80211_hw *dev,
1792 struct ieee80211_if_init_conf *conf)
1793{
1794 struct p54_common *priv = dev->priv;
eff1a59c 1795
9e7f3f8e
CL		 1796 mutex_lock(&priv->conf_mutex);
1797 if (priv->mode != NL80211_IFTYPE_MONITOR) {
1798 mutex_unlock(&priv->conf_mutex);
4150c572 1799 return -EOPNOTSUPP;
9e7f3f8e 1800 }
eff1a59c
MW		 1801
1802 switch (conf->type) {
05c914fe 1803 case NL80211_IFTYPE_STATION:
e5ea92a7
CL		 1804 case NL80211_IFTYPE_ADHOC:
1805 case NL80211_IFTYPE_AP:
d131bb59 1806 case NL80211_IFTYPE_MESH_POINT:
eff1a59c
MW		 1807 priv->mode = conf->type;
1808 break;
1809 default:
9e7f3f8e 1810 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1811 return -EOPNOTSUPP;
1812 }
1813
4150c572 1814 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
b2023ddc 1815 p54_setup_mac(dev);
eff1a59c 1816 p54_set_leds(dev, 1, 0, 0);
9e7f3f8e 1817 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1818 return 0;
1819}
1820
1821static void p54_remove_interface(struct ieee80211_hw *dev,
1822 struct ieee80211_if_init_conf *conf)
1823{
1824 struct p54_common *priv = dev->priv;
9e7f3f8e
CL		 1825
1826 mutex_lock(&priv->conf_mutex);
e5ea92a7
CL		 1827 if (priv->cached_beacon)
1828 p54_tx_cancel(dev, priv->cached_beacon);
05c914fe 1829 priv->mode = NL80211_IFTYPE_MONITOR;
4150c572 1830 memset(priv->mac_addr, 0, ETH_ALEN);
b2023ddc
CL		 1831 memset(priv->bssid, 0, ETH_ALEN);
1832 p54_setup_mac(dev);
9e7f3f8e 1833 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1834}
1835
e8975581 1836static int p54_config(struct ieee80211_hw *dev, u32 changed)
eff1a59c
MW		 1837{
1838 int ret;
6041e2a0 1839 struct p54_common *priv = dev->priv;
e8975581 1840 struct ieee80211_conf *conf = &dev->conf;
eff1a59c 1841
6041e2a0 1842 mutex_lock(&priv->conf_mutex);
b2023ddc
CL		 1843 if (changed & IEEE80211_CONF_CHANGE_POWER)
1844 priv->output_power = conf->power_level << 2;
1845 if (changed & IEEE80211_CONF_CHANGE_RADIO_ENABLED) {
1846 ret = p54_setup_mac(dev);
1847 if (ret)
1848 goto out;
1849 }
1850 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
69ba3e5d 1851 ret = p54_scan(dev, P54_SCAN_EXIT, 0);
b2023ddc
CL		 1852 if (ret)
1853 goto out;
1854 }
1855
1856out:
6041e2a0 1857 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1858 return ret;
1859}
1860
32bfd35d
JB		 1861static int p54_config_interface(struct ieee80211_hw *dev,
1862 struct ieee80211_vif *vif,
eff1a59c
MW		 1863 struct ieee80211_if_conf *conf)
1864{
1865 struct p54_common *priv = dev->priv;
e5ea92a7 1866 int ret = 0;
eff1a59c 1867
6041e2a0 1868 mutex_lock(&priv->conf_mutex);
b2023ddc
CL		 1869 if (conf->changed & IEEE80211_IFCC_BSSID) {
1870 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1871 ret = p54_setup_mac(dev);
e5ea92a7
CL		 1872 if (ret)
1873 goto out;
b2023ddc
CL		 1874 }
1875
1876 if (conf->changed & IEEE80211_IFCC_BEACON) {
69ba3e5d 1877 ret = p54_scan(dev, P54_SCAN_EXIT, 0);
e5ea92a7
CL		 1878 if (ret)
1879 goto out;
b2023ddc 1880 ret = p54_setup_mac(dev);
e5ea92a7
CL		 1881 if (ret)
1882 goto out;
b2023ddc
CL		 1883 ret = p54_beacon_update(dev, vif);
1884 if (ret)
1885 goto out;
1886 ret = p54_set_edcf(dev);
e5ea92a7
CL		 1887 if (ret)
1888 goto out;
e5ea92a7 1889 }
b2023ddc
CL		 1890
1891 ret = p54_set_leds(dev, 1, !is_multicast_ether_addr(priv->bssid), 0);
1892
e5ea92a7 1893out:
6041e2a0 1894 mutex_unlock(&priv->conf_mutex);
e5ea92a7 1895 return ret;
eff1a59c
MW		 1896}
1897
4150c572
JB		 1898static void p54_configure_filter(struct ieee80211_hw *dev,
1899 unsigned int changed_flags,
1900 unsigned int *total_flags,
1901 int mc_count, struct dev_mc_list *mclist)
1902{
1903 struct p54_common *priv = dev->priv;
1904
b2023ddc
CL		 1905 *total_flags &= FIF_PROMISC_IN_BSS |
1906 (*total_flags & FIF_PROMISC_IN_BSS) ?
1907 FIF_FCSFAIL : 0;
78d57eb2
CL		 1908
1909 priv->filter_flags = *total_flags;
4150c572 1910
b2023ddc
CL		 1911 if (changed_flags & FIF_PROMISC_IN_BSS)
1912 p54_setup_mac(dev);
4150c572
JB		 1913}
1914
e100bb64 1915static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue,
eff1a59c
MW		 1916 const struct ieee80211_tx_queue_params *params)
1917{
1918 struct p54_common *priv = dev->priv;
9e7f3f8e 1919 int ret;
eff1a59c 1920
9e7f3f8e 1921 mutex_lock(&priv->conf_mutex);
3df5ee60 1922 if ((params) && !(queue > 4)) {
0fdd7c5d 1923 P54_SET_QUEUE(priv->qos_params[queue], params->aifs,
3330d7be 1924 params->cw_min, params->cw_max, params->txop);
b50563a6 1925 ret = p54_set_edcf(dev);
eff1a59c 1926 } else
9e7f3f8e 1927 ret = -EINVAL;
9e7f3f8e
CL		 1928 mutex_unlock(&priv->conf_mutex);
1929 return ret;
eff1a59c
MW		 1930}
1931
1b997534
CL		 1932static int p54_init_xbow_synth(struct ieee80211_hw *dev)
1933{
1934 struct p54_common *priv = dev->priv;
b92f30d6 1935 struct sk_buff *skb;
27df605e 1936 struct p54_xbow_synth *xbow;
1b997534 1937
27df605e
JL		 1938 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*xbow) +
1939 sizeof(struct p54_hdr),
1940 P54_CONTROL_TYPE_XBOW_SYNTH_CFG,
b92f30d6
CL		 1941 GFP_KERNEL);
1942 if (!skb)
1b997534
CL		 1943 return -ENOMEM;
1944
27df605e 1945 xbow = (struct p54_xbow_synth *)skb_put(skb, sizeof(*xbow));
1b997534
CL		 1946 xbow->magic1 = cpu_to_le16(0x1);
1947 xbow->magic2 = cpu_to_le16(0x2);
1948 xbow->freq = cpu_to_le16(5390);
b92f30d6 1949 memset(xbow->padding, 0, sizeof(xbow->padding));
0a5ec96a 1950 priv->tx(dev, skb);
1b997534
CL		 1951 return 0;
1952}
1953
54fdb040 1954static void p54_work(struct work_struct *work)
cc6de669 1955{
54fdb040
CL		 1956 struct p54_common *priv = container_of(work, struct p54_common,
1957 work.work);
1958 struct ieee80211_hw *dev = priv->hw;
1959 struct sk_buff *skb;
1960
1961 if (unlikely(priv->mode == NL80211_IFTYPE_UNSPECIFIED))
1962 return ;
1963
1964 /*
1965 * TODO: walk through tx_queue and do the following tasks
1966 * 1. initiate bursts.
1967 * 2. cancel stuck frames / reset the device if necessary.
1968 */
cc6de669 1969
54fdb040
CL		 1970 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL, sizeof(struct p54_hdr) +
1971 sizeof(struct p54_statistics),
1972 P54_CONTROL_TYPE_STAT_READBACK, GFP_KERNEL);
1973 if (!skb)
1974 return ;
cc6de669 1975
0a5ec96a 1976 priv->tx(dev, skb);
cc6de669
CL		 1977}
1978
eff1a59c
MW		 1979static int p54_get_stats(struct ieee80211_hw *dev,
1980 struct ieee80211_low_level_stats *stats)
1981{
cc6de669
CL		 1982 struct p54_common *priv = dev->priv;
1983
cc6de669 1984 memcpy(stats, &priv->stats, sizeof(*stats));
eff1a59c
MW		 1985 return 0;
1986}
1987
1988static int p54_get_tx_stats(struct ieee80211_hw *dev,
1989 struct ieee80211_tx_queue_stats *stats)
1990{
1991 struct p54_common *priv = dev->priv;
eff1a59c 1992
84df3ed3 1993 memcpy(stats, &priv->tx_stats[4], sizeof(stats[0]) * dev->queues);
eff1a59c
MW		 1994
1995 return 0;
1996}
1997
40333e4f
CL		 1998static void p54_bss_info_changed(struct ieee80211_hw *dev,
1999 struct ieee80211_vif *vif,
2000 struct ieee80211_bss_conf *info,
2001 u32 changed)
2002{
2003 struct p54_common *priv = dev->priv;
2004
2005 if (changed & BSS_CHANGED_ERP_SLOT) {
2006 priv->use_short_slot = info->use_short_slot;
0fdd7c5d 2007 p54_set_edcf(dev);
40333e4f 2008 }
ced09574
CL		 2009 if (changed & BSS_CHANGED_BASIC_RATES) {
2010 if (dev->conf.channel->band == IEEE80211_BAND_5GHZ)
2011 priv->basic_rate_mask = (info->basic_rates << 4);
2012 else
2013 priv->basic_rate_mask = info->basic_rates;
b2023ddc 2014 p54_setup_mac(dev);
ced09574 2015 if (priv->fw_var >= 0x500)
69ba3e5d 2016 p54_scan(dev, P54_SCAN_EXIT, 0);
ced09574
CL		 2017 }
2018 if (changed & BSS_CHANGED_ASSOC) {
2019 if (info->assoc) {
2020 priv->aid = info->aid;
2021 priv->wakeup_timer = info->beacon_int *
2022 info->dtim_period * 5;
b2023ddc 2023 p54_setup_mac(dev);
ced09574
CL		 2024 }
2025 }
2026
40333e4f
CL		 2027}
2028
25900ef0
CL		 2029static int p54_set_key(struct ieee80211_hw *dev, enum set_key_cmd cmd,
2030 const u8 *local_address, const u8 *address,
2031 struct ieee80211_key_conf *key)
2032{
2033 struct p54_common *priv = dev->priv;
2034 struct sk_buff *skb;
2035 struct p54_keycache *rxkey;
2036 u8 algo = 0;
2037
2038 if (modparam_nohwcrypt)
2039 return -EOPNOTSUPP;
2040
2041 if (cmd == DISABLE_KEY)
2042 algo = 0;
2043 else {
2044 switch (key->alg) {
2045 case ALG_TKIP:
2046 if (!(priv->privacy_caps & (BR_DESC_PRIV_CAP_MICHAEL |
2047 BR_DESC_PRIV_CAP_TKIP)))
2048 return -EOPNOTSUPP;
2049 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2050 algo = P54_CRYPTO_TKIPMICHAEL;
2051 break;
2052 case ALG_WEP:
2053 if (!(priv->privacy_caps & BR_DESC_PRIV_CAP_WEP))
2054 return -EOPNOTSUPP;
2055 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2056 algo = P54_CRYPTO_WEP;
2057 break;
2058 case ALG_CCMP:
2059 if (!(priv->privacy_caps & BR_DESC_PRIV_CAP_AESCCMP))
2060 return -EOPNOTSUPP;
2061 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2062 algo = P54_CRYPTO_AESCCMP;
2063 break;
2064 default:
2065 return -EINVAL;
2066 }
2067 }
2068
2069 if (key->keyidx > priv->rx_keycache_size) {
2070 /*
2071 * The device supports the choosen algorithm, but the firmware
2072 * does not provide enough key slots to store all of them.
2073 * So, incoming frames have to be decoded by the mac80211 stack,
2074 * but we can still offload encryption for outgoing frames.
2075 */
2076
2077 return 0;
2078 }
2079
2080 mutex_lock(&priv->conf_mutex);
2081 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*rxkey) +
2082 sizeof(struct p54_hdr), P54_CONTROL_TYPE_RX_KEYCACHE,
2083 GFP_ATOMIC);
2084 if (!skb) {
2085 mutex_unlock(&priv->conf_mutex);
2086 return -ENOMEM;
2087 }
2088
2089 /* TODO: some devices have 4 more free slots for rx keys */
2090 rxkey = (struct p54_keycache *)skb_put(skb, sizeof(*rxkey));
2091 rxkey->entry = key->keyidx;
2092 rxkey->key_id = key->keyidx;
2093 rxkey->key_type = algo;
2094 if (address)
2095 memcpy(rxkey->mac, address, ETH_ALEN);
2096 else
2097 memset(rxkey->mac, ~0, ETH_ALEN);
2098 if (key->alg != ALG_TKIP) {
2099 rxkey->key_len = min((u8)16, key->keylen);
2100 memcpy(rxkey->key, key->key, rxkey->key_len);
2101 } else {
2102 rxkey->key_len = 24;
2103 memcpy(rxkey->key, key->key, 16);
2104 memcpy(&(rxkey->key[16]), &(key->key
2105 [NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]), 8);
2106 }
2107
0a5ec96a 2108 priv->tx(dev, skb);
25900ef0
CL		 2109 mutex_unlock(&priv->conf_mutex);
2110 return 0;
2111}
2112
eff1a59c
MW		 2113static const struct ieee80211_ops p54_ops = {
2114 .tx = p54_tx,
4150c572
JB		 2115 .start = p54_start,
2116 .stop = p54_stop,
eff1a59c
MW		 2117 .add_interface = p54_add_interface,
2118 .remove_interface = p54_remove_interface,
e5ea92a7 2119 .set_tim = p54_set_tim,
c772a08b 2120 .sta_notify = p54_sta_notify,
25900ef0 2121 .set_key = p54_set_key,
eff1a59c
MW		 2122 .config = p54_config,
2123 .config_interface = p54_config_interface,
40333e4f 2124 .bss_info_changed = p54_bss_info_changed,
4150c572 2125 .configure_filter = p54_configure_filter,
eff1a59c
MW		 2126 .conf_tx = p54_conf_tx,
2127 .get_stats = p54_get_stats,
2128 .get_tx_stats = p54_get_tx_stats
2129};
2130
2131struct ieee80211_hw *p54_init_common(size_t priv_data_len)
2132{
2133 struct ieee80211_hw *dev;
2134 struct p54_common *priv;
eff1a59c
MW		 2135
2136 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
2137 if (!dev)
2138 return NULL;
2139
2140 priv = dev->priv;
54fdb040 2141 priv->hw = dev;
05c914fe 2142 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
ced09574 2143 priv->basic_rate_mask = 0x15f;
eff1a59c 2144 skb_queue_head_init(&priv->tx_queue);
94585b09 2145 dev->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cc6de669
CL		 2146 IEEE80211_HW_SIGNAL_DBM |
2147 IEEE80211_HW_NOISE_DBM;
f59ac048 2148
d131bb59
CL		 2149 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
2150 BIT(NL80211_IFTYPE_ADHOC) |
2151 BIT(NL80211_IFTYPE_AP) |
2152 BIT(NL80211_IFTYPE_MESH_POINT);
f59ac048 2153
eff1a59c 2154 dev->channel_change_time = 1000; /* TODO: find actual value */
9e7f3f8e
CL		 2155 priv->tx_stats[0].limit = 1; /* Beacon queue */
2156 priv->tx_stats[1].limit = 1; /* Probe queue for HW scan */
2157 priv->tx_stats[2].limit = 3; /* queue for MLMEs */
2158 priv->tx_stats[3].limit = 3; /* Broadcast / MC queue */
2159 priv->tx_stats[4].limit = 5; /* Data */
eff1a59c 2160 dev->queues = 1;
cc6de669 2161 priv->noise = -94;
c12abae3
JB		 2162 /*
2163 * We support at most 8 tries no matter which rate they're at,
2164 * we cannot support max_rates * max_rate_tries as we set it
2165 * here, but setting it correctly to 4/2 or so would limit us
2166 * artificially if the RC algorithm wants just two rates, so
2167 * let's say 4/7, we'll redistribute it at TX time, see the
2168 * comments there.
2169 */
2170 dev->max_rates = 4;
2171 dev->max_rate_tries = 7;
27df605e
JL		 2172 dev->extra_tx_headroom = sizeof(struct p54_hdr) + 4 +
2173 sizeof(struct p54_tx_data);
eff1a59c 2174
6041e2a0 2175 mutex_init(&priv->conf_mutex);
7cb77072 2176 init_completion(&priv->eeprom_comp);
54fdb040 2177 INIT_DELAYED_WORK(&priv->work, p54_work);
eff1a59c 2178
eff1a59c
MW		 2179 return dev;
2180}
2181EXPORT_SYMBOL_GPL(p54_init_common);
2182
2183void p54_free_common(struct ieee80211_hw *dev)
2184{
2185 struct p54_common *priv = dev->priv;
2186 kfree(priv->iq_autocal);
2187 kfree(priv->output_limit);
2188 kfree(priv->curve_data);
eff1a59c
MW		 2189}
2190EXPORT_SYMBOL_GPL(p54_free_common);
2191
2192static int __init p54_init(void)
2193{
2194 return 0;
2195}
2196
2197static void __exit p54_exit(void)
2198{
2199}
2200
2201module_init(p54_init);
2202module_exit(p54_exit);
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