[net-next-2.6.git] / drivers / net / wireless / orinoco / orinoco_plx.c

/* orinoco_plx.c
 *
 * Driver for Prism II devices which would usually be driven by orinoco_cs,
 * but are connected to the PCI bus by a PLX9052.
 *
 * Current maintainers are:
 * 	Pavel Roskin <proski AT gnu.org>
 * and	David Gibson <hermes AT gibson.dropbear.id.au>
 *
 * (C) Copyright David Gibson, IBM Corp. 2001-2003.
 * Copyright (C) 2001 Daniel Barlow
 *
 * The contents of this file are subject to the Mozilla Public License
 * Version 1.1 (the "License"); you may not use this file except in
 * compliance with the License. You may obtain a copy of the License
 * at http://www.mozilla.org/MPL/
 *
 * Software distributed under the License is distributed on an "AS IS"
 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
 * the License for the specific language governing rights and
 * limitations under the License.
 *
 * Alternatively, the contents of this file may be used under the
 * terms of the GNU General Public License version 2 (the "GPL"), in
 * which case the provisions of the GPL are applicable instead of the
 * above.  If you wish to allow the use of your version of this file
 * only under the terms of the GPL and not to allow others to use your
 * version of this file under the MPL, indicate your decision by
 * deleting the provisions above and replace them with the notice and
 * other provisions required by the GPL.  If you do not delete the
 * provisions above, a recipient may use your version of this file
 * under either the MPL or the GPL.
 *
 * Here's the general details on how the PLX9052 adapter works:
 *
 * - Two PCI I/O address spaces, one 0x80 long which contains the
 * PLX9052 registers, and one that's 0x40 long mapped to the PCMCIA
 * slot I/O address space.
 *
 * - One PCI memory address space, mapped to the PCMCIA attribute space
 * (containing the CIS).
 *
 * Using the later, you can read through the CIS data to make sure the
 * card is compatible with the driver. Keep in mind that the PCMCIA
 * spec specifies the CIS as the lower 8 bits of each word read from
 * the CIS, so to read the bytes of the CIS, read every other byte
 * (0,2,4,...). Passing that test, you need to enable the I/O address
 * space on the PCMCIA card via the PCMCIA COR register. This is the
 * first byte following the CIS. In my case (which may not have any
 * relation to what's on the PRISM2 cards), COR was at offset 0x800
 * within the PCI memory space. Write 0x41 to the COR register to
 * enable I/O mode and to select level triggered interrupts. To
 * confirm you actually succeeded, read the COR register back and make
 * sure it actually got set to 0x41, in case you have an unexpected
 * card inserted.
 *
 * Following that, you can treat the second PCI I/O address space (the
 * one that's not 0x80 in length) as the PCMCIA I/O space.
 *
 * Note that in the Eumitcom's source for their drivers, they register
 * the interrupt as edge triggered when registering it with the
 * Windows kernel. I don't recall how to register edge triggered on
 * Linux (if it can be done at all). But in some experimentation, I
 * don't see much operational difference between using either
 * interrupt mode. Don't mess with the interrupt mode in the COR
 * register though, as the PLX9052 wants level triggers with the way
 * the serial EEPROM configures it on the WL11000.
 *
 * There's some other little quirks related to timing that I bumped
 * into, but I don't recall right now. Also, there's two variants of
 * the WL11000 I've seen, revision A1 and T2. These seem to differ
 * slightly in the timings configured in the wait-state generator in
 * the PLX9052. There have also been some comments from Eumitcom that
 * cards shouldn't be hot swapped, apparently due to risk of cooking
 * the PLX9052. I'm unsure why they believe this, as I can't see
 * anything in the design that would really cause a problem, except
 * for crashing drivers not written to expect it. And having developed
 * drivers for the WL11000, I'd say it's quite tricky to write code
 * that will successfully deal with a hot unplug. Very odd things
 * happen on the I/O side of things. But anyway, be warned. Despite
 * that, I've hot-swapped a number of times during debugging and
 * driver development for various reasons (stuck WAIT# line after the
 * radio card's firmware locks up).
 */

#define DRIVER_NAME "orinoco_plx"
#define PFX DRIVER_NAME ": "

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <pcmcia/cisreg.h>

#include "orinoco.h"
#include "orinoco_pci.h"

#define COR_OFFSET	(0x3e0)	/* COR attribute offset of Prism2 PC card */
#define COR_VALUE	(COR_LEVEL_REQ | COR_FUNC_ENA) /* Enable PC card with interrupt in level trigger */
#define COR_RESET     (0x80)	/* reset bit in the COR register */
#define PLX_RESET_TIME	(500)	/* milliseconds */

#define PLX_INTCSR		0x4c /* Interrupt Control & Status Register */
#define PLX_INTCSR_INTEN	(1<<6) /* Interrupt Enable bit */

/*
 * Do a soft reset of the card using the Configuration Option Register
 */
static int orinoco_plx_cor_reset(struct orinoco_private *priv)
{
	hermes_t *hw = &priv->hw;
	struct orinoco_pci_card *card = priv->card;
	unsigned long timeout;
	u16 reg;

	iowrite8(COR_VALUE | COR_RESET, card->attr_io + COR_OFFSET);
	mdelay(1);

	iowrite8(COR_VALUE, card->attr_io + COR_OFFSET);
	mdelay(1);

	/* Just in case, wait more until the card is no longer busy */
	timeout = jiffies + (PLX_RESET_TIME * HZ / 1000);
	reg = hermes_read_regn(hw, CMD);
	while (time_before(jiffies, timeout) && (reg & HERMES_CMD_BUSY)) {
		mdelay(1);
		reg = hermes_read_regn(hw, CMD);
	}

	/* Still busy? */
	if (reg & HERMES_CMD_BUSY) {
		printk(KERN_ERR PFX "Busy timeout\n");
		return -ETIMEDOUT;
	}

	return 0;
}

static int orinoco_plx_hw_init(struct orinoco_pci_card *card)
{
	int i;
	u32 csr_reg;
	static const u8 cis_magic[] = {
		0x01, 0x03, 0x00, 0x00, 0xff, 0x17, 0x04, 0x67
	};

	printk(KERN_DEBUG PFX "CIS: ");
	for (i = 0; i < 16; i++)
		printk("%02X:", ioread8(card->attr_io + (i << 1)));
	printk("\n");

	/* Verify whether a supported PC card is present */
	/* FIXME: we probably need to be smarted about this */
	for (i = 0; i < sizeof(cis_magic); i++) {
		if (cis_magic[i] != ioread8(card->attr_io + (i << 1))) {
			printk(KERN_ERR PFX "The CIS value of Prism2 PC "
			       "card is unexpected\n");
			return -ENODEV;
		}
	}

	/* bjoern: We need to tell the card to enable interrupts, in
	   case the serial eprom didn't do this already.  See the
	   PLX9052 data book, p8-1 and 8-24 for reference. */
	csr_reg = ioread32(card->bridge_io + PLX_INTCSR);
	if (!(csr_reg & PLX_INTCSR_INTEN)) {
		csr_reg |= PLX_INTCSR_INTEN;
		iowrite32(csr_reg, card->bridge_io + PLX_INTCSR);
		csr_reg = ioread32(card->bridge_io + PLX_INTCSR);
		if (!(csr_reg & PLX_INTCSR_INTEN)) {
			printk(KERN_ERR PFX "Cannot enable interrupts\n");
			return -EIO;
		}
	}

	return 0;
}

static int orinoco_plx_init_one(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{
	int err;
	struct orinoco_private *priv;
	struct orinoco_pci_card *card;
	void __iomem *hermes_io, *attr_io, *bridge_io;

	err = pci_enable_device(pdev);
	if (err) {
		printk(KERN_ERR PFX "Cannot enable PCI device\n");
		return err;
	}

	err = pci_request_regions(pdev, DRIVER_NAME);
	if (err) {
		printk(KERN_ERR PFX "Cannot obtain PCI resources\n");
		goto fail_resources;
	}

	bridge_io = pci_iomap(pdev, 1, 0);
	if (!bridge_io) {
		printk(KERN_ERR PFX "Cannot map bridge registers\n");
		err = -EIO;
		goto fail_map_bridge;
	}

	attr_io = pci_iomap(pdev, 2, 0);
	if (!attr_io) {
		printk(KERN_ERR PFX "Cannot map PCMCIA attributes\n");
		err = -EIO;
		goto fail_map_attr;
	}

	hermes_io = pci_iomap(pdev, 3, 0);
	if (!hermes_io) {
		printk(KERN_ERR PFX "Cannot map chipset registers\n");
		err = -EIO;
		goto fail_map_hermes;
	}

	/* Allocate network device */
	priv = alloc_orinocodev(sizeof(*card), &pdev->dev,
				orinoco_plx_cor_reset, NULL);
	if (!priv) {
		printk(KERN_ERR PFX "Cannot allocate network device\n");
		err = -ENOMEM;
		goto fail_alloc;
	}

	card = priv->card;
	card->bridge_io = bridge_io;
	card->attr_io = attr_io;

	hermes_struct_init(&priv->hw, hermes_io, HERMES_16BIT_REGSPACING);

	err = request_irq(pdev->irq, orinoco_interrupt, IRQF_SHARED,
			  DRIVER_NAME, priv);
	if (err) {
		printk(KERN_ERR PFX "Cannot allocate IRQ %d\n", pdev->irq);
		err = -EBUSY;
		goto fail_irq;
	}

	err = orinoco_plx_hw_init(card);
	if (err) {
		printk(KERN_ERR PFX "Hardware initialization failed\n");
		goto fail;
	}

	err = orinoco_plx_cor_reset(priv);
	if (err) {
		printk(KERN_ERR PFX "Initial reset failed\n");
		goto fail;
	}

	err = orinoco_init(priv);
	if (err) {
		printk(KERN_ERR PFX "orinoco_init() failed\n");
		goto fail;
	}

	err = orinoco_if_add(priv, 0, 0, NULL);
	if (err) {
		printk(KERN_ERR PFX "orinoco_if_add() failed\n");
		goto fail;
	}

	pci_set_drvdata(pdev, priv);

	return 0;

 fail:
	free_irq(pdev->irq, priv);

 fail_irq:
	pci_set_drvdata(pdev, NULL);
	free_orinocodev(priv);

 fail_alloc:
	pci_iounmap(pdev, hermes_io);

 fail_map_hermes:
	pci_iounmap(pdev, attr_io);

 fail_map_attr:
	pci_iounmap(pdev, bridge_io);

 fail_map_bridge:
	pci_release_regions(pdev);

 fail_resources:
	pci_disable_device(pdev);

	return err;
}

static void __devexit orinoco_plx_remove_one(struct pci_dev *pdev)
{
	struct orinoco_private *priv = pci_get_drvdata(pdev);
	struct orinoco_pci_card *card = priv->card;

	orinoco_if_del(priv);
	free_irq(pdev->irq, priv);
	pci_set_drvdata(pdev, NULL);
	free_orinocodev(priv);
	pci_iounmap(pdev, priv->hw.iobase);
	pci_iounmap(pdev, card->attr_io);
	pci_iounmap(pdev, card->bridge_io);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
}

static DEFINE_PCI_DEVICE_TABLE(orinoco_plx_id_table) = {
	{0x111a, 0x1023, PCI_ANY_ID, PCI_ANY_ID,},	/* Siemens SpeedStream SS1023 */
	{0x1385, 0x4100, PCI_ANY_ID, PCI_ANY_ID,},	/* Netgear MA301 */
	{0x15e8, 0x0130, PCI_ANY_ID, PCI_ANY_ID,},	/* Correga  - does this work? */
	{0x1638, 0x1100, PCI_ANY_ID, PCI_ANY_ID,},	/* SMC EZConnect SMC2602W,
							   Eumitcom PCI WL11000,
							   Addtron AWA-100 */
	{0x16ab, 0x1100, PCI_ANY_ID, PCI_ANY_ID,},	/* Global Sun Tech GL24110P */
	{0x16ab, 0x1101, PCI_ANY_ID, PCI_ANY_ID,},	/* Reported working, but unknown */
	{0x16ab, 0x1102, PCI_ANY_ID, PCI_ANY_ID,},	/* Linksys WDT11 */
	{0x16ec, 0x3685, PCI_ANY_ID, PCI_ANY_ID,},	/* USR 2415 */
	{0xec80, 0xec00, PCI_ANY_ID, PCI_ANY_ID,},	/* Belkin F5D6000 tested by
							   Brendan W. McAdams <rit AT jacked-in.org> */
	{0x10b7, 0x7770, PCI_ANY_ID, PCI_ANY_ID,},	/* 3Com AirConnect PCI tested by
							   Damien Persohn <damien AT persohn.net> */
	{0,},
};

MODULE_DEVICE_TABLE(pci, orinoco_plx_id_table);

static struct pci_driver orinoco_plx_driver = {
	.name		= DRIVER_NAME,
	.id_table	= orinoco_plx_id_table,
	.probe		= orinoco_plx_init_one,
	.remove		= __devexit_p(orinoco_plx_remove_one),
	.suspend	= orinoco_pci_suspend,
	.resume		= orinoco_pci_resume,
};

static char version[] __initdata = DRIVER_NAME " " DRIVER_VERSION
	" (Pavel Roskin <proski@gnu.org>,"
	" David Gibson <hermes@gibson.dropbear.id.au>,"
	" Daniel Barlow <dan@telent.net>)";
MODULE_AUTHOR("Daniel Barlow <dan@telent.net>");
MODULE_DESCRIPTION("Driver for wireless LAN cards using the PLX9052 PCI bridge");
MODULE_LICENSE("Dual MPL/GPL");

static int __init orinoco_plx_init(void)
{
	printk(KERN_DEBUG "%s\n", version);
	return pci_register_driver(&orinoco_plx_driver);
}

static void __exit orinoco_plx_exit(void)
{
	pci_unregister_driver(&orinoco_plx_driver);
}

module_init(orinoco_plx_init);
module_exit(orinoco_plx_exit);

/*
 * Local variables:
 *  c-indent-level: 8
 *  c-basic-offset: 8
 *  tab-width: 8
 * End:
 */
Commit	Line	Data
1da177e4 LT	1	/* orinoco_plx.c
	2	*
	3	* Driver for Prism II devices which would usually be driven by orinoco_cs,
	4	* but are connected to the PCI bus by a PLX9052.
	5	*
dc3437d2	6	* Current maintainers are:
1da177e4 LT	7	* Pavel Roskin <proski AT gnu.org>
	8	* and David Gibson <hermes AT gibson.dropbear.id.au>
	9	*
	10	* (C) Copyright David Gibson, IBM Corp. 2001-2003.
	11	* Copyright (C) 2001 Daniel Barlow
	12	*
	13	* The contents of this file are subject to the Mozilla Public License
	14	* Version 1.1 (the "License"); you may not use this file except in
	15	* compliance with the License. You may obtain a copy of the License
	16	* at http://www.mozilla.org/MPL/
	17	*
	18	* Software distributed under the License is distributed on an "AS IS"
	19	* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
	20	* the License for the specific language governing rights and
	21	* limitations under the License.
	22	*
	23	* Alternatively, the contents of this file may be used under the
	24	* terms of the GNU General Public License version 2 (the "GPL"), in
	25	* which case the provisions of the GPL are applicable instead of the
	26	* above. If you wish to allow the use of your version of this file
	27	* only under the terms of the GPL and not to allow others to use your
	28	* version of this file under the MPL, indicate your decision by
	29	* deleting the provisions above and replace them with the notice and
	30	* other provisions required by the GPL. If you do not delete the
	31	* provisions above, a recipient may use your version of this file
	32	* under either the MPL or the GPL.
1da177e4	33	*
dc3437d2	34	* Here's the general details on how the PLX9052 adapter works:
1da177e4 LT	35	*
	36	* - Two PCI I/O address spaces, one 0x80 long which contains the
	37	* PLX9052 registers, and one that's 0x40 long mapped to the PCMCIA
	38	* slot I/O address space.
	39	*
dc3437d2	40	* - One PCI memory address space, mapped to the PCMCIA attribute space
1da177e4 LT	41	* (containing the CIS).
1da177e4 LT	42	*
dc3437d2 PR	43	* Using the later, you can read through the CIS data to make sure the
dc3437d2 PR	44	* card is compatible with the driver. Keep in mind that the PCMCIA
1da177e4 LT	45	* spec specifies the CIS as the lower 8 bits of each word read from
	46	* the CIS, so to read the bytes of the CIS, read every other byte
	47	* (0,2,4,...). Passing that test, you need to enable the I/O address
	48	* space on the PCMCIA card via the PCMCIA COR register. This is the
	49	* first byte following the CIS. In my case (which may not have any
	50	* relation to what's on the PRISM2 cards), COR was at offset 0x800
	51	* within the PCI memory space. Write 0x41 to the COR register to
	52	* enable I/O mode and to select level triggered interrupts. To
	53	* confirm you actually succeeded, read the COR register back and make
dc3437d2	54	* sure it actually got set to 0x41, in case you have an unexpected
1da177e4 LT	55	* card inserted.
	56	*
	57	* Following that, you can treat the second PCI I/O address space (the
	58	* one that's not 0x80 in length) as the PCMCIA I/O space.
	59	*
	60	* Note that in the Eumitcom's source for their drivers, they register
	61	* the interrupt as edge triggered when registering it with the
	62	* Windows kernel. I don't recall how to register edge triggered on
	63	* Linux (if it can be done at all). But in some experimentation, I
	64	* don't see much operational difference between using either
	65	* interrupt mode. Don't mess with the interrupt mode in the COR
	66	* register though, as the PLX9052 wants level triggers with the way
	67	* the serial EEPROM configures it on the WL11000.
	68	*
	69	* There's some other little quirks related to timing that I bumped
	70	* into, but I don't recall right now. Also, there's two variants of
	71	* the WL11000 I've seen, revision A1 and T2. These seem to differ
	72	* slightly in the timings configured in the wait-state generator in
	73	* the PLX9052. There have also been some comments from Eumitcom that
	74	* cards shouldn't be hot swapped, apparently due to risk of cooking
	75	* the PLX9052. I'm unsure why they believe this, as I can't see
	76	* anything in the design that would really cause a problem, except
	77	* for crashing drivers not written to expect it. And having developed
	78	* drivers for the WL11000, I'd say it's quite tricky to write code
	79	* that will successfully deal with a hot unplug. Very odd things
	80	* happen on the I/O side of things. But anyway, be warned. Despite
	81	* that, I've hot-swapped a number of times during debugging and
	82	* driver development for various reasons (stuck WAIT# line after the
	83	* radio card's firmware locks up).
1da177e4 LT	84	*/
	85
	86	#define DRIVER_NAME "orinoco_plx"
	87	#define PFX DRIVER_NAME ": "
	88
1da177e4 LT	89	#include <linux/module.h>
	90	#include <linux/kernel.h>
	91	#include <linux/init.h>
ef846bf0	92	#include <linux/delay.h>
1da177e4	93	#include <linux/pci.h>
1da177e4 LT	94	#include <pcmcia/cisreg.h>
1da177e4 LT	95
1da177e4	96	#include "orinoco.h"
b884c872	97	#include "orinoco_pci.h"
1da177e4 LT	98
	99	#define COR_OFFSET (0x3e0) /* COR attribute offset of Prism2 PC card */
	100	#define COR_VALUE (COR_LEVEL_REQ \| COR_FUNC_ENA) /* Enable PC card with interrupt in level trigger */
	101	#define COR_RESET (0x80) /* reset bit in the COR register */
	102	#define PLX_RESET_TIME (500) /* milliseconds */
	103
	104	#define PLX_INTCSR 0x4c /* Interrupt Control & Status Register */
	105	#define PLX_INTCSR_INTEN (1<<6) /* Interrupt Enable bit */
	106
1da177e4 LT	107	/*
	108	* Do a soft reset of the card using the Configuration Option Register
	109	*/
	110	static int orinoco_plx_cor_reset(struct orinoco_private *priv)
	111	{
	112	hermes_t *hw = &priv->hw;
b884c872	113	struct orinoco_pci_card *card = priv->card;
1da177e4 LT	114	unsigned long timeout;
	115	u16 reg;
	116
b884c872	117	iowrite8(COR_VALUE \| COR_RESET, card->attr_io + COR_OFFSET);
1da177e4 LT	118	mdelay(1);
1da177e4 LT	119
b884c872	120	iowrite8(COR_VALUE, card->attr_io + COR_OFFSET);
1da177e4 LT	121	mdelay(1);
	122
	123	/* Just in case, wait more until the card is no longer busy */
	124	timeout = jiffies + (PLX_RESET_TIME * HZ / 1000);
	125	reg = hermes_read_regn(hw, CMD);
	126	while (time_before(jiffies, timeout) && (reg & HERMES_CMD_BUSY)) {
	127	mdelay(1);
	128	reg = hermes_read_regn(hw, CMD);
	129	}
	130
b884c872	131	/* Still busy? */
1da177e4 LT	132	if (reg & HERMES_CMD_BUSY) {
	133	printk(KERN_ERR PFX "Busy timeout\n");
	134	return -ETIMEDOUT;
	135	}
	136
	137	return 0;
	138	}
	139
b884c872 PR	140	static int orinoco_plx_hw_init(struct orinoco_pci_card *card)
	141	{
	142	int i;
	143	u32 csr_reg;
	144	static const u8 cis_magic[] = {
	145	0x01, 0x03, 0x00, 0x00, 0xff, 0x17, 0x04, 0x67
	146	};
	147
	148	printk(KERN_DEBUG PFX "CIS: ");
d14c7c1d	149	for (i = 0; i < 16; i++)
b884c872	150	printk("%02X:", ioread8(card->attr_io + (i << 1)));
b884c872 PR	151	printk("\n");
	152
	153	/* Verify whether a supported PC card is present */
	154	/* FIXME: we probably need to be smarted about this */
	155	for (i = 0; i < sizeof(cis_magic); i++) {
	156	if (cis_magic[i] != ioread8(card->attr_io + (i << 1))) {
	157	printk(KERN_ERR PFX "The CIS value of Prism2 PC "
	158	"card is unexpected\n");
	159	return -ENODEV;
	160	}
	161	}
	162
	163	/* bjoern: We need to tell the card to enable interrupts, in
	164	case the serial eprom didn't do this already. See the
	165	PLX9052 data book, p8-1 and 8-24 for reference. */
	166	csr_reg = ioread32(card->bridge_io + PLX_INTCSR);
	167	if (!(csr_reg & PLX_INTCSR_INTEN)) {
	168	csr_reg \|= PLX_INTCSR_INTEN;
	169	iowrite32(csr_reg, card->bridge_io + PLX_INTCSR);
	170	csr_reg = ioread32(card->bridge_io + PLX_INTCSR);
	171	if (!(csr_reg & PLX_INTCSR_INTEN)) {
	172	printk(KERN_ERR PFX "Cannot enable interrupts\n");
	173	return -EIO;
	174	}
	175	}
	176
	177	return 0;
	178	}
1da177e4 LT	179
	180	static int orinoco_plx_init_one(struct pci_dev *pdev,
	181	const struct pci_device_id *ent)
	182	{
b884c872 PR	183	int err;
	184	struct orinoco_private *priv;
	185	struct orinoco_pci_card *card;
b884c872	186	void __iomem hermes_io, attr_io, *bridge_io;
1da177e4 LT	187
	188	err = pci_enable_device(pdev);
	189	if (err) {
	190	printk(KERN_ERR PFX "Cannot enable PCI device\n");
	191	return err;
	192	}
	193
	194	err = pci_request_regions(pdev, DRIVER_NAME);
b884c872	195	if (err) {
1da177e4 LT	196	printk(KERN_ERR PFX "Cannot obtain PCI resources\n");
	197	goto fail_resources;
	198	}
	199
b884c872 PR	200	bridge_io = pci_iomap(pdev, 1, 0);
	201	if (!bridge_io) {
	202	printk(KERN_ERR PFX "Cannot map bridge registers\n");
	203	err = -EIO;
	204	goto fail_map_bridge;
	205	}
1da177e4	206
b884c872 PR	207	attr_io = pci_iomap(pdev, 2, 0);
	208	if (!attr_io) {
	209	printk(KERN_ERR PFX "Cannot map PCMCIA attributes\n");
	210	err = -EIO;
1da177e4 LT	211	goto fail_map_attr;
	212	}
	213
b884c872 PR	214	hermes_io = pci_iomap(pdev, 3, 0);
	215	if (!hermes_io) {
	216	printk(KERN_ERR PFX "Cannot map chipset registers\n");
	217	err = -EIO;
	218	goto fail_map_hermes;
1da177e4 LT	219	}
	220
	221	/* Allocate network device */
a2608362 DK	222	priv = alloc_orinocodev(sizeof(*card), &pdev->dev,
	223	orinoco_plx_cor_reset, NULL);
	224	if (!priv) {
1da177e4 LT	225	printk(KERN_ERR PFX "Cannot allocate network device\n");
	226	err = -ENOMEM;
	227	goto fail_alloc;
	228	}
	229
1da177e4	230	card = priv->card;
b884c872 PR	231	card->bridge_io = bridge_io;
b884c872 PR	232	card->attr_io = attr_io;
1da177e4	233
b884c872	234	hermes_struct_init(&priv->hw, hermes_io, HERMES_16BIT_REGSPACING);
1da177e4	235
1fb9df5d	236	err = request_irq(pdev->irq, orinoco_interrupt, IRQF_SHARED,
5381956b	237	DRIVER_NAME, priv);
1da177e4 LT	238	if (err) {
	239	printk(KERN_ERR PFX "Cannot allocate IRQ %d\n", pdev->irq);
	240	err = -EBUSY;
	241	goto fail_irq;
	242	}
1da177e4	243
b884c872 PR	244	err = orinoco_plx_hw_init(card);
	245	if (err) {
	246	printk(KERN_ERR PFX "Hardware initialization failed\n");
	247	goto fail;
1da177e4 LT	248	}
	249
	250	err = orinoco_plx_cor_reset(priv);
	251	if (err) {
	252	printk(KERN_ERR PFX "Initial reset failed\n");
	253	goto fail;
	254	}
	255
8e638267 DK	256	err = orinoco_init(priv);
	257	if (err) {
	258	printk(KERN_ERR PFX "orinoco_init() failed\n");
	259	goto fail;
	260	}
	261
593ef09c	262	err = orinoco_if_add(priv, 0, 0, NULL);
1da177e4	263	if (err) {
5381956b	264	printk(KERN_ERR PFX "orinoco_if_add() failed\n");
1da177e4 LT	265	goto fail;
	266	}
	267
a2608362	268	pci_set_drvdata(pdev, priv);
1da177e4 LT	269
	270	return 0;
	271
	272	fail:
a2608362	273	free_irq(pdev->irq, priv);
1da177e4 LT	274
	275	fail_irq:
	276	pci_set_drvdata(pdev, NULL);
a2608362	277	free_orinocodev(priv);
1da177e4 LT	278
1da177e4 LT	279	fail_alloc:
b884c872	280	pci_iounmap(pdev, hermes_io);
1da177e4	281
b884c872 PR	282	fail_map_hermes:
b884c872 PR	283	pci_iounmap(pdev, attr_io);
1da177e4 LT	284
1da177e4 LT	285	fail_map_attr:
b884c872 PR	286	pci_iounmap(pdev, bridge_io);
	287
	288	fail_map_bridge:
1da177e4 LT	289	pci_release_regions(pdev);
	290
	291	fail_resources:
	292	pci_disable_device(pdev);
	293
	294	return err;
	295	}
	296
	297	static void __devexit orinoco_plx_remove_one(struct pci_dev *pdev)
	298	{
a2608362	299	struct orinoco_private *priv = pci_get_drvdata(pdev);
b884c872	300	struct orinoco_pci_card *card = priv->card;
1da177e4	301
5381956b	302	orinoco_if_del(priv);
a2608362	303	free_irq(pdev->irq, priv);
1da177e4	304	pci_set_drvdata(pdev, NULL);
a2608362	305	free_orinocodev(priv);
1da177e4	306	pci_iounmap(pdev, priv->hw.iobase);
b884c872 PR	307	pci_iounmap(pdev, card->attr_io);
b884c872 PR	308	pci_iounmap(pdev, card->bridge_io);
1da177e4 LT	309	pci_release_regions(pdev);
	310	pci_disable_device(pdev);
	311	}
	312
a3aa1884	313	static DEFINE_PCI_DEVICE_TABLE(orinoco_plx_id_table) = {
1da177e4 LT	314	{0x111a, 0x1023, PCI_ANY_ID, PCI_ANY_ID,}, /* Siemens SpeedStream SS1023 */
	315	{0x1385, 0x4100, PCI_ANY_ID, PCI_ANY_ID,}, /* Netgear MA301 */
	316	{0x15e8, 0x0130, PCI_ANY_ID, PCI_ANY_ID,}, /* Correga - does this work? */
	317	{0x1638, 0x1100, PCI_ANY_ID, PCI_ANY_ID,}, /* SMC EZConnect SMC2602W,
	318	Eumitcom PCI WL11000,
	319	Addtron AWA-100 */
	320	{0x16ab, 0x1100, PCI_ANY_ID, PCI_ANY_ID,}, /* Global Sun Tech GL24110P */
	321	{0x16ab, 0x1101, PCI_ANY_ID, PCI_ANY_ID,}, /* Reported working, but unknown */
	322	{0x16ab, 0x1102, PCI_ANY_ID, PCI_ANY_ID,}, /* Linksys WDT11 */
	323	{0x16ec, 0x3685, PCI_ANY_ID, PCI_ANY_ID,}, /* USR 2415 */
	324	{0xec80, 0xec00, PCI_ANY_ID, PCI_ANY_ID,}, /* Belkin F5D6000 tested by
	325	Brendan W. McAdams <rit AT jacked-in.org> */
	326	{0x10b7, 0x7770, PCI_ANY_ID, PCI_ANY_ID,}, /* 3Com AirConnect PCI tested by
	327	Damien Persohn <damien AT persohn.net> */
	328	{0,},
	329	};
	330
b884c872	331	MODULE_DEVICE_TABLE(pci, orinoco_plx_id_table);
1da177e4 LT	332
	333	static struct pci_driver orinoco_plx_driver = {
	334	.name = DRIVER_NAME,
b884c872	335	.id_table = orinoco_plx_id_table,
1da177e4 LT	336	.probe = orinoco_plx_init_one,
1da177e4 LT	337	.remove = __devexit_p(orinoco_plx_remove_one),
b884c872 PR	338	.suspend = orinoco_pci_suspend,
b884c872 PR	339	.resume = orinoco_pci_resume,
1da177e4 LT	340	};
	341
	342	static char version[] __initdata = DRIVER_NAME " " DRIVER_VERSION
	343	" (Pavel Roskin <proski@gnu.org>,"
	344	" David Gibson <hermes@gibson.dropbear.id.au>,"
	345	" Daniel Barlow <dan@telent.net>)";
	346	MODULE_AUTHOR("Daniel Barlow <dan@telent.net>");
	347	MODULE_DESCRIPTION("Driver for wireless LAN cards using the PLX9052 PCI bridge");
	348	MODULE_LICENSE("Dual MPL/GPL");
	349
	350	static int __init orinoco_plx_init(void)
	351	{
	352	printk(KERN_DEBUG "%s\n", version);
29917620	353	return pci_register_driver(&orinoco_plx_driver);
1da177e4 LT	354	}
	355
	356	static void __exit orinoco_plx_exit(void)
	357	{
	358	pci_unregister_driver(&orinoco_plx_driver);
1da177e4 LT	359	}
	360
	361	module_init(orinoco_plx_init);
	362	module_exit(orinoco_plx_exit);
	363
	364	/*
	365	* Local variables:
	366	* c-indent-level: 8
	367	* c-basic-offset: 8
	368	* tab-width: 8
	369	* End:
	370	*/