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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
c96c31e4 JP |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
b481de9c ZY |
32 | #include <linux/kernel.h> |
33 | #include <linux/module.h> | |
b481de9c ZY |
34 | #include <linux/init.h> |
35 | #include <linux/pci.h> | |
1a7123cd | 36 | #include <linux/pci-aspm.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
b481de9c ZY |
38 | #include <linux/dma-mapping.h> |
39 | #include <linux/delay.h> | |
d43c36dc | 40 | #include <linux/sched.h> |
b481de9c ZY |
41 | #include <linux/skbuff.h> |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/wireless.h> | |
44 | #include <linux/firmware.h> | |
b481de9c ZY |
45 | #include <linux/etherdevice.h> |
46 | #include <linux/if_arp.h> | |
47 | ||
48 | #include <net/ieee80211_radiotap.h> | |
49 | #include <net/mac80211.h> | |
50 | ||
51 | #include <asm/div64.h> | |
52 | ||
a3139c59 SO |
53 | #define DRV_NAME "iwl3945" |
54 | ||
dbb6654c WT |
55 | #include "iwl-fh.h" |
56 | #include "iwl-3945-fh.h" | |
600c0e11 | 57 | #include "iwl-commands.h" |
17f841cd | 58 | #include "iwl-sta.h" |
b481de9c | 59 | #include "iwl-3945.h" |
5747d47f | 60 | #include "iwl-core.h" |
4a6547c7 | 61 | #include "iwl-helpers.h" |
d20b3c65 | 62 | #include "iwl-dev.h" |
81963d68 | 63 | #include "iwl-spectrum.h" |
b481de9c | 64 | |
b481de9c ZY |
65 | /* |
66 | * module name, copyright, version, etc. | |
b481de9c ZY |
67 | */ |
68 | ||
69 | #define DRV_DESCRIPTION \ | |
70 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
71 | ||
d08853a3 | 72 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
73 | #define VD "d" |
74 | #else | |
75 | #define VD | |
76 | #endif | |
77 | ||
81963d68 RC |
78 | /* |
79 | * add "s" to indicate spectrum measurement included. | |
80 | * we add it here to be consistent with previous releases in which | |
81 | * this was configurable. | |
82 | */ | |
83 | #define DRV_VERSION IWLWIFI_VERSION VD "s" | |
1f447808 | 84 | #define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation" |
a7b75207 | 85 | #define DRV_AUTHOR "<ilw@linux.intel.com>" |
b481de9c ZY |
86 | |
87 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
88 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 89 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c ZY |
90 | MODULE_LICENSE("GPL"); |
91 | ||
df878d8f KA |
92 | /* module parameters */ |
93 | struct iwl_mod_params iwl3945_mod_params = { | |
9c74d9fb | 94 | .sw_crypto = 1, |
af48d048 | 95 | .restart_fw = 1, |
df878d8f KA |
96 | /* the rest are 0 by default */ |
97 | }; | |
98 | ||
7e4bca5e SO |
99 | /** |
100 | * iwl3945_get_antenna_flags - Get antenna flags for RXON command | |
101 | * @priv: eeprom and antenna fields are used to determine antenna flags | |
102 | * | |
103 | * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed | |
104 | * iwl3945_mod_params.antenna specifies the antenna diversity mode: | |
105 | * | |
106 | * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself | |
107 | * IWL_ANTENNA_MAIN - Force MAIN antenna | |
108 | * IWL_ANTENNA_AUX - Force AUX antenna | |
109 | */ | |
110 | __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv) | |
111 | { | |
112 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; | |
113 | ||
114 | switch (iwl3945_mod_params.antenna) { | |
115 | case IWL_ANTENNA_DIVERSITY: | |
116 | return 0; | |
117 | ||
118 | case IWL_ANTENNA_MAIN: | |
119 | if (eeprom->antenna_switch_type) | |
120 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
121 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
122 | ||
123 | case IWL_ANTENNA_AUX: | |
124 | if (eeprom->antenna_switch_type) | |
125 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
126 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
127 | } | |
128 | ||
129 | /* bad antenna selector value */ | |
130 | IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", | |
131 | iwl3945_mod_params.antenna); | |
132 | ||
133 | return 0; /* "diversity" is default if error */ | |
134 | } | |
135 | ||
6e21f15c | 136 | static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv, |
b481de9c ZY |
137 | struct ieee80211_key_conf *keyconf, |
138 | u8 sta_id) | |
139 | { | |
140 | unsigned long flags; | |
141 | __le16 key_flags = 0; | |
6e21f15c AK |
142 | int ret; |
143 | ||
144 | key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); | |
145 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
146 | ||
a194e324 | 147 | if (sta_id == priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id) |
6e21f15c AK |
148 | key_flags |= STA_KEY_MULTICAST_MSK; |
149 | ||
150 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
151 | keyconf->hw_key_idx = keyconf->keyidx; | |
152 | key_flags &= ~STA_KEY_FLG_INVALID; | |
b481de9c | 153 | |
b481de9c | 154 | spin_lock_irqsave(&priv->sta_lock, flags); |
97359d12 | 155 | priv->stations[sta_id].keyinfo.cipher = keyconf->cipher; |
c587de0b TW |
156 | priv->stations[sta_id].keyinfo.keylen = keyconf->keylen; |
157 | memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, | |
b481de9c ZY |
158 | keyconf->keylen); |
159 | ||
c587de0b | 160 | memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, |
b481de9c | 161 | keyconf->keylen); |
6e21f15c | 162 | |
c587de0b | 163 | if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK) |
6e21f15c | 164 | == STA_KEY_FLG_NO_ENC) |
c587de0b | 165 | priv->stations[sta_id].sta.key.key_offset = |
6e21f15c AK |
166 | iwl_get_free_ucode_key_index(priv); |
167 | /* else, we are overriding an existing key => no need to allocated room | |
168 | * in uCode. */ | |
169 | ||
c587de0b | 170 | WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, |
6e21f15c AK |
171 | "no space for a new key"); |
172 | ||
c587de0b TW |
173 | priv->stations[sta_id].sta.key.key_flags = key_flags; |
174 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
175 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c | 176 | |
6e21f15c AK |
177 | IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n"); |
178 | ||
c587de0b | 179 | ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC); |
6e21f15c | 180 | |
b481de9c ZY |
181 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
182 | ||
6e21f15c AK |
183 | return ret; |
184 | } | |
185 | ||
186 | static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv, | |
187 | struct ieee80211_key_conf *keyconf, | |
188 | u8 sta_id) | |
189 | { | |
190 | return -EOPNOTSUPP; | |
191 | } | |
192 | ||
193 | static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv, | |
194 | struct ieee80211_key_conf *keyconf, | |
195 | u8 sta_id) | |
196 | { | |
197 | return -EOPNOTSUPP; | |
b481de9c ZY |
198 | } |
199 | ||
4a8a4322 | 200 | static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id) |
b481de9c ZY |
201 | { |
202 | unsigned long flags; | |
9c5ac091 | 203 | struct iwl_addsta_cmd sta_cmd; |
b481de9c ZY |
204 | |
205 | spin_lock_irqsave(&priv->sta_lock, flags); | |
c587de0b TW |
206 | memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key)); |
207 | memset(&priv->stations[sta_id].sta.key, 0, | |
4c897253 | 208 | sizeof(struct iwl4965_keyinfo)); |
c587de0b TW |
209 | priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
210 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
211 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
9c5ac091 | 212 | memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(struct iwl_addsta_cmd)); |
b481de9c ZY |
213 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
214 | ||
e1623446 | 215 | IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n"); |
9c5ac091 | 216 | return iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC); |
b481de9c ZY |
217 | } |
218 | ||
fa11d525 | 219 | static int iwl3945_set_dynamic_key(struct iwl_priv *priv, |
6e21f15c AK |
220 | struct ieee80211_key_conf *keyconf, u8 sta_id) |
221 | { | |
222 | int ret = 0; | |
223 | ||
224 | keyconf->hw_key_idx = HW_KEY_DYNAMIC; | |
225 | ||
97359d12 JB |
226 | switch (keyconf->cipher) { |
227 | case WLAN_CIPHER_SUITE_CCMP: | |
6e21f15c AK |
228 | ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id); |
229 | break; | |
97359d12 | 230 | case WLAN_CIPHER_SUITE_TKIP: |
6e21f15c AK |
231 | ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id); |
232 | break; | |
97359d12 JB |
233 | case WLAN_CIPHER_SUITE_WEP40: |
234 | case WLAN_CIPHER_SUITE_WEP104: | |
6e21f15c AK |
235 | ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id); |
236 | break; | |
237 | default: | |
97359d12 JB |
238 | IWL_ERR(priv, "Unknown alg: %s alg=%x\n", __func__, |
239 | keyconf->cipher); | |
6e21f15c AK |
240 | ret = -EINVAL; |
241 | } | |
242 | ||
97359d12 JB |
243 | IWL_DEBUG_WEP(priv, "Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n", |
244 | keyconf->cipher, keyconf->keylen, keyconf->keyidx, | |
6e21f15c AK |
245 | sta_id, ret); |
246 | ||
247 | return ret; | |
248 | } | |
249 | ||
250 | static int iwl3945_remove_static_key(struct iwl_priv *priv) | |
251 | { | |
252 | int ret = -EOPNOTSUPP; | |
253 | ||
254 | return ret; | |
255 | } | |
256 | ||
257 | static int iwl3945_set_static_key(struct iwl_priv *priv, | |
258 | struct ieee80211_key_conf *key) | |
259 | { | |
97359d12 JB |
260 | if (key->cipher == WLAN_CIPHER_SUITE_WEP40 || |
261 | key->cipher == WLAN_CIPHER_SUITE_WEP104) | |
6e21f15c AK |
262 | return -EOPNOTSUPP; |
263 | ||
97359d12 | 264 | IWL_ERR(priv, "Static key invalid: cipher %x\n", key->cipher); |
6e21f15c AK |
265 | return -EINVAL; |
266 | } | |
267 | ||
4a8a4322 | 268 | static void iwl3945_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
269 | { |
270 | struct list_head *element; | |
271 | ||
e1623446 | 272 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
273 | priv->frames_count); |
274 | ||
275 | while (!list_empty(&priv->free_frames)) { | |
276 | element = priv->free_frames.next; | |
277 | list_del(element); | |
bb8c093b | 278 | kfree(list_entry(element, struct iwl3945_frame, list)); |
b481de9c ZY |
279 | priv->frames_count--; |
280 | } | |
281 | ||
282 | if (priv->frames_count) { | |
39aadf8c | 283 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
284 | priv->frames_count); |
285 | priv->frames_count = 0; | |
286 | } | |
287 | } | |
288 | ||
4a8a4322 | 289 | static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv) |
b481de9c | 290 | { |
bb8c093b | 291 | struct iwl3945_frame *frame; |
b481de9c ZY |
292 | struct list_head *element; |
293 | if (list_empty(&priv->free_frames)) { | |
294 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
295 | if (!frame) { | |
15b1687c | 296 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
297 | return NULL; |
298 | } | |
299 | ||
300 | priv->frames_count++; | |
301 | return frame; | |
302 | } | |
303 | ||
304 | element = priv->free_frames.next; | |
305 | list_del(element); | |
bb8c093b | 306 | return list_entry(element, struct iwl3945_frame, list); |
b481de9c ZY |
307 | } |
308 | ||
4a8a4322 | 309 | static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame) |
b481de9c ZY |
310 | { |
311 | memset(frame, 0, sizeof(*frame)); | |
312 | list_add(&frame->list, &priv->free_frames); | |
313 | } | |
314 | ||
4a8a4322 | 315 | unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv, |
b481de9c | 316 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 317 | int left) |
b481de9c ZY |
318 | { |
319 | ||
246ed355 | 320 | if (!iwl_is_associated(priv, IWL_RXON_CTX_BSS) || !priv->ibss_beacon) |
b481de9c ZY |
321 | return 0; |
322 | ||
323 | if (priv->ibss_beacon->len > left) | |
324 | return 0; | |
325 | ||
326 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
327 | ||
328 | return priv->ibss_beacon->len; | |
329 | } | |
330 | ||
4a8a4322 | 331 | static int iwl3945_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 332 | { |
bb8c093b | 333 | struct iwl3945_frame *frame; |
b481de9c ZY |
334 | unsigned int frame_size; |
335 | int rc; | |
336 | u8 rate; | |
337 | ||
bb8c093b | 338 | frame = iwl3945_get_free_frame(priv); |
b481de9c ZY |
339 | |
340 | if (!frame) { | |
15b1687c | 341 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
342 | "command.\n"); |
343 | return -ENOMEM; | |
344 | } | |
345 | ||
76d04815 JB |
346 | rate = iwl_rate_get_lowest_plcp(priv, |
347 | &priv->contexts[IWL_RXON_CTX_BSS]); | |
b481de9c | 348 | |
bb8c093b | 349 | frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 350 | |
518099a8 | 351 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
352 | &frame->u.cmd[0]); |
353 | ||
bb8c093b | 354 | iwl3945_free_frame(priv, frame); |
b481de9c ZY |
355 | |
356 | return rc; | |
357 | } | |
358 | ||
4a8a4322 | 359 | static void iwl3945_unset_hw_params(struct iwl_priv *priv) |
b481de9c | 360 | { |
ee525d13 | 361 | if (priv->_3945.shared_virt) |
f36d04ab SG |
362 | dma_free_coherent(&priv->pci_dev->dev, |
363 | sizeof(struct iwl3945_shared), | |
ee525d13 JB |
364 | priv->_3945.shared_virt, |
365 | priv->_3945.shared_phys); | |
b481de9c ZY |
366 | } |
367 | ||
4a8a4322 | 368 | static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv, |
e039fa4a | 369 | struct ieee80211_tx_info *info, |
c2acea8e | 370 | struct iwl_device_cmd *cmd, |
b481de9c | 371 | struct sk_buff *skb_frag, |
6e21f15c | 372 | int sta_id) |
b481de9c | 373 | { |
9744c91f | 374 | struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
c587de0b | 375 | struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo; |
b481de9c | 376 | |
97359d12 JB |
377 | tx_cmd->sec_ctl = 0; |
378 | ||
379 | switch (keyinfo->cipher) { | |
380 | case WLAN_CIPHER_SUITE_CCMP: | |
9744c91f AK |
381 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; |
382 | memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen); | |
e1623446 | 383 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); |
b481de9c ZY |
384 | break; |
385 | ||
97359d12 | 386 | case WLAN_CIPHER_SUITE_TKIP: |
b481de9c ZY |
387 | break; |
388 | ||
97359d12 JB |
389 | case WLAN_CIPHER_SUITE_WEP104: |
390 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
391 | /* fall through */ | |
392 | case WLAN_CIPHER_SUITE_WEP40: | |
393 | tx_cmd->sec_ctl |= TX_CMD_SEC_WEP | | |
e039fa4a | 394 | (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; |
b481de9c | 395 | |
9744c91f | 396 | memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen); |
b481de9c | 397 | |
e1623446 | 398 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " |
e039fa4a | 399 | "with key %d\n", info->control.hw_key->hw_key_idx); |
b481de9c ZY |
400 | break; |
401 | ||
b481de9c | 402 | default: |
97359d12 | 403 | IWL_ERR(priv, "Unknown encode cipher %x\n", keyinfo->cipher); |
b481de9c ZY |
404 | break; |
405 | } | |
406 | } | |
407 | ||
408 | /* | |
409 | * handle build REPLY_TX command notification. | |
410 | */ | |
4a8a4322 | 411 | static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv, |
c2acea8e | 412 | struct iwl_device_cmd *cmd, |
e039fa4a | 413 | struct ieee80211_tx_info *info, |
e52119c5 | 414 | struct ieee80211_hdr *hdr, u8 std_id) |
b481de9c | 415 | { |
9744c91f AK |
416 | struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
417 | __le32 tx_flags = tx_cmd->tx_flags; | |
fd7c8a40 | 418 | __le16 fc = hdr->frame_control; |
b481de9c | 419 | |
9744c91f | 420 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
e039fa4a | 421 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
b481de9c | 422 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 423 | if (ieee80211_is_mgmt(fc)) |
b481de9c | 424 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 425 | if (ieee80211_is_probe_resp(fc) && |
b481de9c ZY |
426 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
427 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
428 | } else { | |
429 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
430 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
431 | } | |
432 | ||
9744c91f | 433 | tx_cmd->sta_id = std_id; |
8b7b1e05 | 434 | if (ieee80211_has_morefrags(fc)) |
b481de9c ZY |
435 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
436 | ||
fd7c8a40 HH |
437 | if (ieee80211_is_data_qos(fc)) { |
438 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
9744c91f | 439 | tx_cmd->tid_tspec = qc[0] & 0xf; |
b481de9c | 440 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 441 | } else { |
b481de9c | 442 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 443 | } |
b481de9c | 444 | |
94597ab2 | 445 | priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags); |
b481de9c ZY |
446 | |
447 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
448 | if (ieee80211_is_mgmt(fc)) { |
449 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
9744c91f | 450 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 451 | else |
9744c91f | 452 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 453 | } else { |
9744c91f | 454 | tx_cmd->timeout.pm_frame_timeout = 0; |
ab53d8af | 455 | } |
b481de9c | 456 | |
9744c91f AK |
457 | tx_cmd->driver_txop = 0; |
458 | tx_cmd->tx_flags = tx_flags; | |
459 | tx_cmd->next_frame_len = 0; | |
b481de9c ZY |
460 | } |
461 | ||
b481de9c ZY |
462 | /* |
463 | * start REPLY_TX command process | |
464 | */ | |
4a8a4322 | 465 | static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
b481de9c ZY |
466 | { |
467 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 468 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
9744c91f | 469 | struct iwl3945_tx_cmd *tx_cmd; |
188cf6c7 | 470 | struct iwl_tx_queue *txq = NULL; |
d20b3c65 | 471 | struct iwl_queue *q = NULL; |
c2acea8e JB |
472 | struct iwl_device_cmd *out_cmd; |
473 | struct iwl_cmd_meta *out_meta; | |
b481de9c ZY |
474 | dma_addr_t phys_addr; |
475 | dma_addr_t txcmd_phys; | |
e52119c5 | 476 | int txq_id = skb_get_queue_mapping(skb); |
df833b1d | 477 | u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */ |
54dbb525 TW |
478 | u8 id; |
479 | u8 unicast; | |
b481de9c | 480 | u8 sta_id; |
54dbb525 | 481 | u8 tid = 0; |
fd7c8a40 | 482 | __le16 fc; |
b481de9c ZY |
483 | u8 wait_write_ptr = 0; |
484 | unsigned long flags; | |
b481de9c ZY |
485 | |
486 | spin_lock_irqsave(&priv->lock, flags); | |
775a6e27 | 487 | if (iwl_is_rfkill(priv)) { |
e1623446 | 488 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); |
b481de9c ZY |
489 | goto drop_unlock; |
490 | } | |
491 | ||
e039fa4a | 492 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) { |
15b1687c | 493 | IWL_ERR(priv, "ERROR: No TX rate available.\n"); |
b481de9c ZY |
494 | goto drop_unlock; |
495 | } | |
496 | ||
497 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
498 | id = 0; | |
499 | ||
fd7c8a40 | 500 | fc = hdr->frame_control; |
b481de9c | 501 | |
d08853a3 | 502 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c | 503 | if (ieee80211_is_auth(fc)) |
e1623446 | 504 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); |
fd7c8a40 | 505 | else if (ieee80211_is_assoc_req(fc)) |
e1623446 | 506 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); |
fd7c8a40 | 507 | else if (ieee80211_is_reassoc_req(fc)) |
e1623446 | 508 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); |
b481de9c ZY |
509 | #endif |
510 | ||
b481de9c ZY |
511 | spin_unlock_irqrestore(&priv->lock, flags); |
512 | ||
7294ec95 | 513 | hdr_len = ieee80211_hdrlen(fc); |
6440adb5 | 514 | |
2a87c26b | 515 | /* Find index into station table for destination station */ |
a194e324 JB |
516 | sta_id = iwl_sta_id_or_broadcast( |
517 | priv, &priv->contexts[IWL_RXON_CTX_BSS], | |
518 | info->control.sta); | |
b481de9c | 519 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 520 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", |
e174961c | 521 | hdr->addr1); |
b481de9c ZY |
522 | goto drop; |
523 | } | |
524 | ||
e1623446 | 525 | IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id); |
b481de9c | 526 | |
fd7c8a40 | 527 | if (ieee80211_is_data_qos(fc)) { |
f862a236 | 528 | u8 *qc = ieee80211_get_qos_ctl(hdr); |
7294ec95 | 529 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
e6a6cf4c RC |
530 | if (unlikely(tid >= MAX_TID_COUNT)) |
531 | goto drop; | |
b481de9c | 532 | } |
6440adb5 BC |
533 | |
534 | /* Descriptor for chosen Tx queue */ | |
188cf6c7 | 535 | txq = &priv->txq[txq_id]; |
b481de9c ZY |
536 | q = &txq->q; |
537 | ||
dc57a303 ZY |
538 | if ((iwl_queue_space(q) < q->high_mark)) |
539 | goto drop; | |
540 | ||
b481de9c ZY |
541 | spin_lock_irqsave(&priv->lock, flags); |
542 | ||
fc4b6853 | 543 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 544 | |
6440adb5 | 545 | /* Set up driver data for this TFD */ |
dbb6654c | 546 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); |
ff0d91c3 | 547 | txq->txb[q->write_ptr].skb = skb; |
c90cbbbd | 548 | txq->txb[q->write_ptr].ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
6440adb5 BC |
549 | |
550 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
188cf6c7 | 551 | out_cmd = txq->cmd[idx]; |
c2acea8e | 552 | out_meta = &txq->meta[idx]; |
9744c91f | 553 | tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload; |
b481de9c | 554 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); |
9744c91f | 555 | memset(tx_cmd, 0, sizeof(*tx_cmd)); |
6440adb5 BC |
556 | |
557 | /* | |
558 | * Set up the Tx-command (not MAC!) header. | |
559 | * Store the chosen Tx queue and TFD index within the sequence field; | |
560 | * after Tx, uCode's Tx response will return this value so driver can | |
561 | * locate the frame within the tx queue and do post-tx processing. | |
562 | */ | |
b481de9c ZY |
563 | out_cmd->hdr.cmd = REPLY_TX; |
564 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 565 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 BC |
566 | |
567 | /* Copy MAC header from skb into command buffer */ | |
9744c91f | 568 | memcpy(tx_cmd->hdr, hdr, hdr_len); |
b481de9c | 569 | |
df833b1d RC |
570 | |
571 | if (info->control.hw_key) | |
572 | iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id); | |
573 | ||
574 | /* TODO need this for burst mode later on */ | |
575 | iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id); | |
576 | ||
577 | /* set is_hcca to 0; it probably will never be implemented */ | |
578 | iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0); | |
579 | ||
580 | /* Total # bytes to be transmitted */ | |
581 | len = (u16)skb->len; | |
9744c91f | 582 | tx_cmd->len = cpu_to_le16(len); |
df833b1d | 583 | |
20594eb0 | 584 | iwl_dbg_log_tx_data_frame(priv, len, hdr); |
22fdf3c9 | 585 | iwl_update_stats(priv, true, fc, len); |
9744c91f AK |
586 | tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; |
587 | tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
df833b1d RC |
588 | |
589 | if (!ieee80211_has_morefrags(hdr->frame_control)) { | |
590 | txq->need_update = 1; | |
df833b1d RC |
591 | } else { |
592 | wait_write_ptr = 1; | |
593 | txq->need_update = 0; | |
594 | } | |
595 | ||
91dd6c27 | 596 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n", |
df833b1d | 597 | le16_to_cpu(out_cmd->hdr.sequence)); |
91dd6c27 | 598 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
9744c91f AK |
599 | iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd)); |
600 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, | |
df833b1d RC |
601 | ieee80211_hdrlen(fc)); |
602 | ||
6440adb5 BC |
603 | /* |
604 | * Use the first empty entry in this queue's command buffer array | |
605 | * to contain the Tx command and MAC header concatenated together | |
606 | * (payload data will be in another buffer). | |
607 | * Size of this varies, due to varying MAC header length. | |
608 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
609 | * of the MAC header (device reads on dword boundaries). | |
610 | * We'll tell device about this padding later. | |
611 | */ | |
3832ec9d | 612 | len = sizeof(struct iwl3945_tx_cmd) + |
4c897253 | 613 | sizeof(struct iwl_cmd_header) + hdr_len; |
b481de9c ZY |
614 | |
615 | len_org = len; | |
616 | len = (len + 3) & ~3; | |
617 | ||
618 | if (len_org != len) | |
619 | len_org = 1; | |
620 | else | |
621 | len_org = 0; | |
622 | ||
6440adb5 BC |
623 | /* Physical address of this Tx command's header (not MAC header!), |
624 | * within command buffer array. */ | |
df833b1d RC |
625 | txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
626 | len, PCI_DMA_TODEVICE); | |
627 | /* we do not map meta data ... so we can safely access address to | |
628 | * provide to unmap command*/ | |
2e724443 FT |
629 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); |
630 | dma_unmap_len_set(out_meta, len, len); | |
b481de9c | 631 | |
6440adb5 BC |
632 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
633 | * first entry */ | |
7aaa1d79 SO |
634 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
635 | txcmd_phys, len, 1, 0); | |
b481de9c | 636 | |
b481de9c | 637 | |
6440adb5 BC |
638 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
639 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
640 | len = skb->len - hdr_len; |
641 | if (len) { | |
642 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
643 | len, PCI_DMA_TODEVICE); | |
7aaa1d79 SO |
644 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
645 | phys_addr, len, | |
646 | 0, U32_PAD(len)); | |
b481de9c ZY |
647 | } |
648 | ||
b481de9c | 649 | |
6440adb5 | 650 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 651 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
7bfedc59 | 652 | iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
653 | spin_unlock_irqrestore(&priv->lock, flags); |
654 | ||
d20b3c65 | 655 | if ((iwl_queue_space(q) < q->high_mark) |
b481de9c ZY |
656 | && priv->mac80211_registered) { |
657 | if (wait_write_ptr) { | |
658 | spin_lock_irqsave(&priv->lock, flags); | |
659 | txq->need_update = 1; | |
4f3602c8 | 660 | iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
661 | spin_unlock_irqrestore(&priv->lock, flags); |
662 | } | |
663 | ||
e4e72fb4 | 664 | iwl_stop_queue(priv, skb_get_queue_mapping(skb)); |
b481de9c ZY |
665 | } |
666 | ||
667 | return 0; | |
668 | ||
669 | drop_unlock: | |
670 | spin_unlock_irqrestore(&priv->lock, flags); | |
671 | drop: | |
672 | return -1; | |
673 | } | |
674 | ||
4a8a4322 | 675 | static int iwl3945_get_measurement(struct iwl_priv *priv, |
b481de9c ZY |
676 | struct ieee80211_measurement_params *params, |
677 | u8 type) | |
678 | { | |
600c0e11 | 679 | struct iwl_spectrum_cmd spectrum; |
2f301227 | 680 | struct iwl_rx_packet *pkt; |
c2d79b48 | 681 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
682 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
683 | .data = (void *)&spectrum, | |
c2acea8e | 684 | .flags = CMD_WANT_SKB, |
b481de9c ZY |
685 | }; |
686 | u32 add_time = le64_to_cpu(params->start_time); | |
687 | int rc; | |
688 | int spectrum_resp_status; | |
689 | int duration = le16_to_cpu(params->duration); | |
246ed355 | 690 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c | 691 | |
246ed355 | 692 | if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) |
a0ee74cf | 693 | add_time = iwl_usecs_to_beacons(priv, |
e99f168c | 694 | le64_to_cpu(params->start_time) - priv->_3945.last_tsf, |
246ed355 | 695 | le16_to_cpu(ctx->timing.beacon_interval)); |
b481de9c ZY |
696 | |
697 | memset(&spectrum, 0, sizeof(spectrum)); | |
698 | ||
699 | spectrum.channel_count = cpu_to_le16(1); | |
700 | spectrum.flags = | |
701 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
702 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
703 | cmd.len = sizeof(spectrum); | |
704 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
705 | ||
246ed355 | 706 | if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) |
b481de9c | 707 | spectrum.start_time = |
a0ee74cf WYG |
708 | iwl_add_beacon_time(priv, |
709 | priv->_3945.last_beacon_time, add_time, | |
246ed355 | 710 | le16_to_cpu(ctx->timing.beacon_interval)); |
b481de9c ZY |
711 | else |
712 | spectrum.start_time = 0; | |
713 | ||
714 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
715 | spectrum.channels[0].channel = params->channel; | |
716 | spectrum.channels[0].type = type; | |
246ed355 | 717 | if (ctx->active.flags & RXON_FLG_BAND_24G_MSK) |
b481de9c ZY |
718 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | |
719 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
720 | ||
518099a8 | 721 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
722 | if (rc) |
723 | return rc; | |
724 | ||
2f301227 ZY |
725 | pkt = (struct iwl_rx_packet *)cmd.reply_page; |
726 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
15b1687c | 727 | IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n"); |
b481de9c ZY |
728 | rc = -EIO; |
729 | } | |
730 | ||
2f301227 | 731 | spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status); |
b481de9c ZY |
732 | switch (spectrum_resp_status) { |
733 | case 0: /* Command will be handled */ | |
2f301227 | 734 | if (pkt->u.spectrum.id != 0xff) { |
e1623446 | 735 | IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n", |
2f301227 | 736 | pkt->u.spectrum.id); |
b481de9c ZY |
737 | priv->measurement_status &= ~MEASUREMENT_READY; |
738 | } | |
739 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
740 | rc = 0; | |
741 | break; | |
742 | ||
743 | case 1: /* Command will not be handled */ | |
744 | rc = -EAGAIN; | |
745 | break; | |
746 | } | |
747 | ||
64a76b50 | 748 | iwl_free_pages(priv, cmd.reply_page); |
b481de9c ZY |
749 | |
750 | return rc; | |
751 | } | |
b481de9c | 752 | |
4a8a4322 | 753 | static void iwl3945_rx_reply_alive(struct iwl_priv *priv, |
6100b588 | 754 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 755 | { |
2f301227 | 756 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
3d24a9f7 | 757 | struct iwl_alive_resp *palive; |
b481de9c ZY |
758 | struct delayed_work *pwork; |
759 | ||
760 | palive = &pkt->u.alive_frame; | |
761 | ||
e1623446 | 762 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
763 | "0x%01X 0x%01X\n", |
764 | palive->is_valid, palive->ver_type, | |
765 | palive->ver_subtype); | |
766 | ||
767 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 768 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
3d24a9f7 TW |
769 | memcpy(&priv->card_alive_init, &pkt->u.alive_frame, |
770 | sizeof(struct iwl_alive_resp)); | |
b481de9c ZY |
771 | pwork = &priv->init_alive_start; |
772 | } else { | |
e1623446 | 773 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 774 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
3d24a9f7 | 775 | sizeof(struct iwl_alive_resp)); |
b481de9c | 776 | pwork = &priv->alive_start; |
bb8c093b | 777 | iwl3945_disable_events(priv); |
b481de9c ZY |
778 | } |
779 | ||
780 | /* We delay the ALIVE response by 5ms to | |
781 | * give the HW RF Kill time to activate... */ | |
782 | if (palive->is_valid == UCODE_VALID_OK) | |
783 | queue_delayed_work(priv->workqueue, pwork, | |
784 | msecs_to_jiffies(5)); | |
785 | else | |
39aadf8c | 786 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
787 | } |
788 | ||
4a8a4322 | 789 | static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv, |
6100b588 | 790 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 791 | { |
c7e035a9 | 792 | #ifdef CONFIG_IWLWIFI_DEBUG |
2f301227 | 793 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
c7e035a9 | 794 | #endif |
b481de9c | 795 | |
e1623446 | 796 | IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); |
b481de9c ZY |
797 | } |
798 | ||
bb8c093b | 799 | static void iwl3945_bg_beacon_update(struct work_struct *work) |
b481de9c | 800 | { |
4a8a4322 AK |
801 | struct iwl_priv *priv = |
802 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
803 | struct sk_buff *beacon; |
804 | ||
805 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
8bd413e6 JB |
806 | beacon = ieee80211_beacon_get(priv->hw, |
807 | priv->contexts[IWL_RXON_CTX_BSS].vif); | |
b481de9c ZY |
808 | |
809 | if (!beacon) { | |
15b1687c | 810 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
811 | return; |
812 | } | |
813 | ||
814 | mutex_lock(&priv->mutex); | |
815 | /* new beacon skb is allocated every time; dispose previous.*/ | |
816 | if (priv->ibss_beacon) | |
817 | dev_kfree_skb(priv->ibss_beacon); | |
818 | ||
819 | priv->ibss_beacon = beacon; | |
820 | mutex_unlock(&priv->mutex); | |
821 | ||
bb8c093b | 822 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
823 | } |
824 | ||
4a8a4322 | 825 | static void iwl3945_rx_beacon_notif(struct iwl_priv *priv, |
6100b588 | 826 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 827 | { |
2f301227 | 828 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
bb8c093b | 829 | struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status); |
a85d7cca | 830 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
831 | u8 rate = beacon->beacon_notify_hdr.rate; |
832 | ||
e1623446 | 833 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c ZY |
834 | "tsf %d %d rate %d\n", |
835 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
836 | beacon->beacon_notify_hdr.failure_frame, | |
837 | le32_to_cpu(beacon->ibss_mgr_status), | |
838 | le32_to_cpu(beacon->high_tsf), | |
839 | le32_to_cpu(beacon->low_tsf), rate); | |
840 | #endif | |
841 | ||
a85d7cca JB |
842 | priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status); |
843 | ||
05c914fe | 844 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
845 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
846 | queue_work(priv->workqueue, &priv->beacon_update); | |
847 | } | |
848 | ||
b481de9c ZY |
849 | /* Handle notification from uCode that card's power state is changing |
850 | * due to software, hardware, or critical temperature RFKILL */ | |
4a8a4322 | 851 | static void iwl3945_rx_card_state_notif(struct iwl_priv *priv, |
6100b588 | 852 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 853 | { |
2f301227 | 854 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
b481de9c ZY |
855 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
856 | unsigned long status = priv->status; | |
857 | ||
4c423a2b | 858 | IWL_WARN(priv, "Card state received: HW:%s SW:%s\n", |
b481de9c ZY |
859 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
860 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
861 | ||
5d49f498 | 862 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
863 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
864 | ||
865 | if (flags & HW_CARD_DISABLED) | |
866 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
867 | else | |
868 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
869 | ||
870 | ||
af0053d6 | 871 | iwl_scan_cancel(priv); |
b481de9c ZY |
872 | |
873 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
874 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
875 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
876 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
877 | else |
878 | wake_up_interruptible(&priv->wait_command_queue); | |
879 | } | |
880 | ||
881 | /** | |
bb8c093b | 882 | * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
883 | * |
884 | * Setup the RX handlers for each of the reply types sent from the uCode | |
885 | * to the host. | |
886 | * | |
887 | * This function chains into the hardware specific files for them to setup | |
888 | * any hardware specific handlers as well. | |
889 | */ | |
4a8a4322 | 890 | static void iwl3945_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 891 | { |
bb8c093b CH |
892 | priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive; |
893 | priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta; | |
261b9c33 | 894 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
8ccde88a | 895 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; |
81963d68 RC |
896 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
897 | iwl_rx_spectrum_measure_notif; | |
030f05ed | 898 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 899 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
030f05ed | 900 | iwl_rx_pm_debug_statistics_notif; |
bb8c093b | 901 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif; |
b481de9c | 902 | |
9fbab516 BC |
903 | /* |
904 | * The same handler is used for both the REPLY to a discrete | |
905 | * statistics request from the host as well as for the periodic | |
906 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 907 | */ |
17f36fc6 | 908 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_reply_statistics; |
bb8c093b | 909 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics; |
b481de9c | 910 | |
cade0eb2 | 911 | iwl_setup_rx_scan_handlers(priv); |
bb8c093b | 912 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif; |
b481de9c | 913 | |
9fbab516 | 914 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 915 | iwl3945_hw_rx_handler_setup(priv); |
b481de9c ZY |
916 | } |
917 | ||
b481de9c ZY |
918 | /************************** RX-FUNCTIONS ****************************/ |
919 | /* | |
920 | * Rx theory of operation | |
921 | * | |
922 | * The host allocates 32 DMA target addresses and passes the host address | |
923 | * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is | |
924 | * 0 to 31 | |
925 | * | |
926 | * Rx Queue Indexes | |
927 | * The host/firmware share two index registers for managing the Rx buffers. | |
928 | * | |
929 | * The READ index maps to the first position that the firmware may be writing | |
930 | * to -- the driver can read up to (but not including) this position and get | |
931 | * good data. | |
932 | * The READ index is managed by the firmware once the card is enabled. | |
933 | * | |
934 | * The WRITE index maps to the last position the driver has read from -- the | |
935 | * position preceding WRITE is the last slot the firmware can place a packet. | |
936 | * | |
937 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
938 | * WRITE = READ. | |
939 | * | |
9fbab516 | 940 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
941 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
942 | * | |
9fbab516 | 943 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
944 | * and fire the RX interrupt. The driver can then query the READ index and |
945 | * process as many packets as possible, moving the WRITE index forward as it | |
946 | * resets the Rx queue buffers with new memory. | |
947 | * | |
948 | * The management in the driver is as follows: | |
949 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
950 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 951 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 952 | * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
953 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
954 | * 'processed' and 'read' driver indexes as well) | |
955 | * + A received packet is processed and handed to the kernel network stack, | |
956 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
957 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
958 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
959 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
960 | * were enough free buffers and RX_STALLED is set it is cleared. | |
961 | * | |
962 | * | |
963 | * Driver sequence: | |
964 | * | |
9fbab516 | 965 | * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls |
bb8c093b | 966 | * iwl3945_rx_queue_restock |
9fbab516 | 967 | * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
968 | * queue, updates firmware pointers, and updates |
969 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 970 | * are available, schedules iwl3945_rx_replenish |
b481de9c ZY |
971 | * |
972 | * -- enable interrupts -- | |
6100b588 | 973 | * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the |
b481de9c ZY |
974 | * READ INDEX, detaching the SKB from the pool. |
975 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 976 | * Calls iwl3945_rx_queue_restock to refill any empty |
b481de9c ZY |
977 | * slots. |
978 | * ... | |
979 | * | |
980 | */ | |
981 | ||
b481de9c | 982 | /** |
9fbab516 | 983 | * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 984 | */ |
4a8a4322 | 985 | static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv, |
b481de9c ZY |
986 | dma_addr_t dma_addr) |
987 | { | |
988 | return cpu_to_le32((u32)dma_addr); | |
989 | } | |
990 | ||
991 | /** | |
bb8c093b | 992 | * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 993 | * |
9fbab516 | 994 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 995 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 996 | * as we can, pulling from rx_free. |
b481de9c ZY |
997 | * |
998 | * This moves the 'write' index forward to catch up with 'processed', and | |
999 | * also updates the memory address in the firmware to reference the new | |
1000 | * target buffer. | |
1001 | */ | |
7bfedc59 | 1002 | static void iwl3945_rx_queue_restock(struct iwl_priv *priv) |
b481de9c | 1003 | { |
cc2f362c | 1004 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1005 | struct list_head *element; |
6100b588 | 1006 | struct iwl_rx_mem_buffer *rxb; |
b481de9c | 1007 | unsigned long flags; |
7bfedc59 | 1008 | int write; |
b481de9c ZY |
1009 | |
1010 | spin_lock_irqsave(&rxq->lock, flags); | |
1011 | write = rxq->write & ~0x7; | |
37d68317 | 1012 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 1013 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 1014 | element = rxq->rx_free.next; |
6100b588 | 1015 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
b481de9c | 1016 | list_del(element); |
6440adb5 BC |
1017 | |
1018 | /* Point to Rx buffer via next RBD in circular buffer */ | |
2f301227 | 1019 | rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma); |
b481de9c ZY |
1020 | rxq->queue[rxq->write] = rxb; |
1021 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
1022 | rxq->free_count--; | |
1023 | } | |
1024 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1025 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
1026 | * refill it */ | |
1027 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
1028 | queue_work(priv->workqueue, &priv->rx_replenish); | |
1029 | ||
1030 | ||
6440adb5 BC |
1031 | /* If we've added more space for the firmware to place data, tell it. |
1032 | * Increment device's write pointer in multiples of 8. */ | |
d14d4440 | 1033 | if ((rxq->write_actual != (rxq->write & ~0x7)) |
b481de9c ZY |
1034 | || (abs(rxq->write - rxq->read) > 7)) { |
1035 | spin_lock_irqsave(&rxq->lock, flags); | |
1036 | rxq->need_update = 1; | |
1037 | spin_unlock_irqrestore(&rxq->lock, flags); | |
7bfedc59 | 1038 | iwl_rx_queue_update_write_ptr(priv, rxq); |
b481de9c | 1039 | } |
b481de9c ZY |
1040 | } |
1041 | ||
1042 | /** | |
bb8c093b | 1043 | * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
1044 | * |
1045 | * When moving to rx_free an SKB is allocated for the slot. | |
1046 | * | |
bb8c093b | 1047 | * Also restock the Rx queue via iwl3945_rx_queue_restock. |
01ebd063 | 1048 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 1049 | */ |
d14d4440 | 1050 | static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority) |
b481de9c | 1051 | { |
cc2f362c | 1052 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1053 | struct list_head *element; |
6100b588 | 1054 | struct iwl_rx_mem_buffer *rxb; |
2f301227 | 1055 | struct page *page; |
b481de9c | 1056 | unsigned long flags; |
29b1b268 | 1057 | gfp_t gfp_mask = priority; |
72240498 AK |
1058 | |
1059 | while (1) { | |
1060 | spin_lock_irqsave(&rxq->lock, flags); | |
1061 | ||
1062 | if (list_empty(&rxq->rx_used)) { | |
1063 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1064 | return; | |
1065 | } | |
72240498 | 1066 | spin_unlock_irqrestore(&rxq->lock, flags); |
6440adb5 | 1067 | |
f82a924c | 1068 | if (rxq->free_count > RX_LOW_WATERMARK) |
29b1b268 | 1069 | gfp_mask |= __GFP_NOWARN; |
2f301227 ZY |
1070 | |
1071 | if (priv->hw_params.rx_page_order > 0) | |
29b1b268 | 1072 | gfp_mask |= __GFP_COMP; |
2f301227 | 1073 | |
6440adb5 | 1074 | /* Alloc a new receive buffer */ |
29b1b268 | 1075 | page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order); |
2f301227 | 1076 | if (!page) { |
b481de9c | 1077 | if (net_ratelimit()) |
f82a924c RC |
1078 | IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n"); |
1079 | if ((rxq->free_count <= RX_LOW_WATERMARK) && | |
1080 | net_ratelimit()) | |
1081 | IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n", | |
1082 | priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", | |
1083 | rxq->free_count); | |
b481de9c ZY |
1084 | /* We don't reschedule replenish work here -- we will |
1085 | * call the restock method and if it still needs | |
1086 | * more buffers it will schedule replenish */ | |
1087 | break; | |
1088 | } | |
12342c47 | 1089 | |
de0bd508 RC |
1090 | spin_lock_irqsave(&rxq->lock, flags); |
1091 | if (list_empty(&rxq->rx_used)) { | |
1092 | spin_unlock_irqrestore(&rxq->lock, flags); | |
2f301227 | 1093 | __free_pages(page, priv->hw_params.rx_page_order); |
de0bd508 RC |
1094 | return; |
1095 | } | |
1096 | element = rxq->rx_used.next; | |
1097 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
1098 | list_del(element); | |
1099 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1100 | ||
2f301227 | 1101 | rxb->page = page; |
6440adb5 | 1102 | /* Get physical address of RB/SKB */ |
2f301227 ZY |
1103 | rxb->page_dma = pci_map_page(priv->pci_dev, page, 0, |
1104 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1105 | PCI_DMA_FROMDEVICE); | |
72240498 AK |
1106 | |
1107 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 1108 | |
b481de9c ZY |
1109 | list_add_tail(&rxb->list, &rxq->rx_free); |
1110 | rxq->free_count++; | |
2f301227 ZY |
1111 | priv->alloc_rxb_page++; |
1112 | ||
72240498 | 1113 | spin_unlock_irqrestore(&rxq->lock, flags); |
b481de9c | 1114 | } |
5c0eef96 MA |
1115 | } |
1116 | ||
df833b1d RC |
1117 | void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
1118 | { | |
1119 | unsigned long flags; | |
1120 | int i; | |
1121 | spin_lock_irqsave(&rxq->lock, flags); | |
1122 | INIT_LIST_HEAD(&rxq->rx_free); | |
1123 | INIT_LIST_HEAD(&rxq->rx_used); | |
1124 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
1125 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
1126 | /* In the reset function, these buffers may have been allocated | |
1127 | * to an SKB, so we need to unmap and free potential storage */ | |
2f301227 ZY |
1128 | if (rxq->pool[i].page != NULL) { |
1129 | pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, | |
1130 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1131 | PCI_DMA_FROMDEVICE); | |
64a76b50 | 1132 | __iwl_free_pages(priv, rxq->pool[i].page); |
2f301227 | 1133 | rxq->pool[i].page = NULL; |
df833b1d RC |
1134 | } |
1135 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
1136 | } | |
1137 | ||
1138 | /* Set us so that we have processed and used all buffers, but have | |
1139 | * not restocked the Rx queue with fresh buffers */ | |
1140 | rxq->read = rxq->write = 0; | |
d14d4440 | 1141 | rxq->write_actual = 0; |
2f301227 | 1142 | rxq->free_count = 0; |
df833b1d RC |
1143 | spin_unlock_irqrestore(&rxq->lock, flags); |
1144 | } | |
df833b1d | 1145 | |
5c0eef96 MA |
1146 | void iwl3945_rx_replenish(void *data) |
1147 | { | |
4a8a4322 | 1148 | struct iwl_priv *priv = data; |
5c0eef96 MA |
1149 | unsigned long flags; |
1150 | ||
d14d4440 | 1151 | iwl3945_rx_allocate(priv, GFP_KERNEL); |
b481de9c ZY |
1152 | |
1153 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 1154 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
1155 | spin_unlock_irqrestore(&priv->lock, flags); |
1156 | } | |
1157 | ||
d14d4440 AK |
1158 | static void iwl3945_rx_replenish_now(struct iwl_priv *priv) |
1159 | { | |
1160 | iwl3945_rx_allocate(priv, GFP_ATOMIC); | |
1161 | ||
1162 | iwl3945_rx_queue_restock(priv); | |
1163 | } | |
1164 | ||
1165 | ||
df833b1d RC |
1166 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. |
1167 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
1168 | * This free routine walks the list of POOL entries and if SKB is set to | |
1169 | * non NULL it is unmapped and freed | |
1170 | */ | |
1171 | static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
1172 | { | |
1173 | int i; | |
1174 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
2f301227 ZY |
1175 | if (rxq->pool[i].page != NULL) { |
1176 | pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, | |
1177 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1178 | PCI_DMA_FROMDEVICE); | |
64a76b50 | 1179 | __iwl_free_pages(priv, rxq->pool[i].page); |
2f301227 | 1180 | rxq->pool[i].page = NULL; |
df833b1d RC |
1181 | } |
1182 | } | |
1183 | ||
f36d04ab | 1184 | dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd, |
d5b25c90 | 1185 | rxq->bd_dma); |
f36d04ab SG |
1186 | dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status), |
1187 | rxq->rb_stts, rxq->rb_stts_dma); | |
df833b1d RC |
1188 | rxq->bd = NULL; |
1189 | rxq->rb_stts = NULL; | |
1190 | } | |
df833b1d RC |
1191 | |
1192 | ||
b481de9c ZY |
1193 | /* Convert linear signal-to-noise ratio into dB */ |
1194 | static u8 ratio2dB[100] = { | |
1195 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
1196 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
1197 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
1198 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
1199 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
1200 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
1201 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
1202 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
1203 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
1204 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
1205 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
1206 | }; | |
1207 | ||
1208 | /* Calculates a relative dB value from a ratio of linear | |
1209 | * (i.e. not dB) signal levels. | |
1210 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 1211 | int iwl3945_calc_db_from_ratio(int sig_ratio) |
b481de9c | 1212 | { |
221c80cf AB |
1213 | /* 1000:1 or higher just report as 60 dB */ |
1214 | if (sig_ratio >= 1000) | |
b481de9c ZY |
1215 | return 60; |
1216 | ||
221c80cf | 1217 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 1218 | * add 20 dB to make up for divide by 10 */ |
221c80cf | 1219 | if (sig_ratio >= 100) |
3ac7f146 | 1220 | return 20 + (int)ratio2dB[sig_ratio/10]; |
b481de9c ZY |
1221 | |
1222 | /* We shouldn't see this */ | |
1223 | if (sig_ratio < 1) | |
1224 | return 0; | |
1225 | ||
1226 | /* Use table for ratios 1:1 - 99:1 */ | |
1227 | return (int)ratio2dB[sig_ratio]; | |
1228 | } | |
1229 | ||
b481de9c | 1230 | /** |
9fbab516 | 1231 | * iwl3945_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
1232 | * |
1233 | * Uses the priv->rx_handlers callback function array to invoke | |
1234 | * the appropriate handlers, including command responses, | |
1235 | * frame-received notifications, and other notifications. | |
1236 | */ | |
4a8a4322 | 1237 | static void iwl3945_rx_handle(struct iwl_priv *priv) |
b481de9c | 1238 | { |
6100b588 | 1239 | struct iwl_rx_mem_buffer *rxb; |
3d24a9f7 | 1240 | struct iwl_rx_packet *pkt; |
cc2f362c | 1241 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
1242 | u32 r, i; |
1243 | int reclaim; | |
1244 | unsigned long flags; | |
5c0eef96 | 1245 | u8 fill_rx = 0; |
d68ab680 | 1246 | u32 count = 8; |
d14d4440 | 1247 | int total_empty = 0; |
b481de9c | 1248 | |
6440adb5 BC |
1249 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
1250 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8cd812bc | 1251 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
1252 | i = rxq->read; |
1253 | ||
d14d4440 | 1254 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 1255 | total_empty = r - rxq->write_actual; |
d14d4440 AK |
1256 | if (total_empty < 0) |
1257 | total_empty += RX_QUEUE_SIZE; | |
1258 | ||
1259 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 | 1260 | fill_rx = 1; |
b481de9c ZY |
1261 | /* Rx interrupt, but nothing sent from uCode */ |
1262 | if (i == r) | |
af472a95 | 1263 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c ZY |
1264 | |
1265 | while (i != r) { | |
f4989d9b JB |
1266 | int len; |
1267 | ||
b481de9c ZY |
1268 | rxb = rxq->queue[i]; |
1269 | ||
9fbab516 | 1270 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
1271 | * then a bug has been introduced in the queue refilling |
1272 | * routines -- catch it here */ | |
1273 | BUG_ON(rxb == NULL); | |
1274 | ||
1275 | rxq->queue[i] = NULL; | |
1276 | ||
2f301227 ZY |
1277 | pci_unmap_page(priv->pci_dev, rxb->page_dma, |
1278 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1279 | PCI_DMA_FROMDEVICE); | |
1280 | pkt = rxb_addr(rxb); | |
b481de9c | 1281 | |
f4989d9b JB |
1282 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
1283 | len += sizeof(u32); /* account for status word */ | |
1284 | trace_iwlwifi_dev_rx(priv, pkt, len); | |
be1a71a1 | 1285 | |
b481de9c ZY |
1286 | /* Reclaim a command buffer only if this packet is a response |
1287 | * to a (driver-originated) command. | |
1288 | * If the packet (e.g. Rx frame) originated from uCode, | |
1289 | * there is no command buffer to reclaim. | |
1290 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
1291 | * but apparently a few don't get set; catch them here. */ | |
1292 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
1293 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
1294 | (pkt->hdr.cmd != REPLY_TX); | |
1295 | ||
1296 | /* Based on type of command response or notification, | |
1297 | * handle those that need handling via function in | |
bb8c093b | 1298 | * rx_handlers table. See iwl3945_setup_rx_handlers() */ |
b481de9c | 1299 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
af472a95 | 1300 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i, |
b481de9c | 1301 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
86ddbf62 | 1302 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 1303 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
1304 | } else { |
1305 | /* No handling needed */ | |
2f301227 ZY |
1306 | IWL_DEBUG_RX(priv, |
1307 | "r %d i %d No handler needed for %s, 0x%02x\n", | |
b481de9c ZY |
1308 | r, i, get_cmd_string(pkt->hdr.cmd), |
1309 | pkt->hdr.cmd); | |
1310 | } | |
1311 | ||
29b1b268 ZY |
1312 | /* |
1313 | * XXX: After here, we should always check rxb->page | |
1314 | * against NULL before touching it or its virtual | |
1315 | * memory (pkt). Because some rx_handler might have | |
1316 | * already taken or freed the pages. | |
1317 | */ | |
1318 | ||
b481de9c | 1319 | if (reclaim) { |
2f301227 ZY |
1320 | /* Invoke any callbacks, transfer the buffer to caller, |
1321 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 1322 | * as we reclaim the driver command queue */ |
29b1b268 | 1323 | if (rxb->page) |
732587ab | 1324 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 1325 | else |
39aadf8c | 1326 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
1327 | } |
1328 | ||
7300515d ZY |
1329 | /* Reuse the page if possible. For notification packets and |
1330 | * SKBs that fail to Rx correctly, add them back into the | |
1331 | * rx_free list for reuse later. */ | |
1332 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 1333 | if (rxb->page != NULL) { |
7300515d ZY |
1334 | rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page, |
1335 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
1336 | PCI_DMA_FROMDEVICE); | |
1337 | list_add_tail(&rxb->list, &rxq->rx_free); | |
1338 | rxq->free_count++; | |
1339 | } else | |
1340 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 1341 | |
b481de9c | 1342 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 1343 | |
b481de9c | 1344 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
1345 | /* If there are a lot of unused frames, |
1346 | * restock the Rx queue so ucode won't assert. */ | |
1347 | if (fill_rx) { | |
1348 | count++; | |
1349 | if (count >= 8) { | |
7300515d | 1350 | rxq->read = i; |
d14d4440 | 1351 | iwl3945_rx_replenish_now(priv); |
5c0eef96 MA |
1352 | count = 0; |
1353 | } | |
1354 | } | |
b481de9c ZY |
1355 | } |
1356 | ||
1357 | /* Backtrack one entry */ | |
7300515d | 1358 | rxq->read = i; |
d14d4440 AK |
1359 | if (fill_rx) |
1360 | iwl3945_rx_replenish_now(priv); | |
1361 | else | |
1362 | iwl3945_rx_queue_restock(priv); | |
b481de9c ZY |
1363 | } |
1364 | ||
0359facc | 1365 | /* call this function to flush any scheduled tasklet */ |
4a8a4322 | 1366 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) |
0359facc | 1367 | { |
a96a27f9 | 1368 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1369 | synchronize_irq(priv->pci_dev->irq); |
1370 | tasklet_kill(&priv->irq_tasklet); | |
1371 | } | |
1372 | ||
b481de9c ZY |
1373 | static const char *desc_lookup(int i) |
1374 | { | |
1375 | switch (i) { | |
1376 | case 1: | |
1377 | return "FAIL"; | |
1378 | case 2: | |
1379 | return "BAD_PARAM"; | |
1380 | case 3: | |
1381 | return "BAD_CHECKSUM"; | |
1382 | case 4: | |
1383 | return "NMI_INTERRUPT"; | |
1384 | case 5: | |
1385 | return "SYSASSERT"; | |
1386 | case 6: | |
1387 | return "FATAL_ERROR"; | |
1388 | } | |
1389 | ||
1390 | return "UNKNOWN"; | |
1391 | } | |
1392 | ||
1393 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1394 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1395 | ||
b7a79404 | 1396 | void iwl3945_dump_nic_error_log(struct iwl_priv *priv) |
b481de9c ZY |
1397 | { |
1398 | u32 i; | |
1399 | u32 desc, time, count, base, data1; | |
1400 | u32 blink1, blink2, ilink1, ilink2; | |
b481de9c ZY |
1401 | |
1402 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
1403 | ||
bb8c093b | 1404 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1405 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); |
b481de9c ZY |
1406 | return; |
1407 | } | |
1408 | ||
b481de9c | 1409 | |
5d49f498 | 1410 | count = iwl_read_targ_mem(priv, base); |
b481de9c ZY |
1411 | |
1412 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
15b1687c WT |
1413 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); |
1414 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1415 | priv->status, count); | |
b481de9c ZY |
1416 | } |
1417 | ||
15b1687c | 1418 | IWL_ERR(priv, "Desc Time asrtPC blink2 " |
b481de9c ZY |
1419 | "ilink1 nmiPC Line\n"); |
1420 | for (i = ERROR_START_OFFSET; | |
1421 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
1422 | i += ERROR_ELEM_SIZE) { | |
5d49f498 | 1423 | desc = iwl_read_targ_mem(priv, base + i); |
b481de9c | 1424 | time = |
5d49f498 | 1425 | iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32)); |
b481de9c | 1426 | blink1 = |
5d49f498 | 1427 | iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32)); |
b481de9c | 1428 | blink2 = |
5d49f498 | 1429 | iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32)); |
b481de9c | 1430 | ilink1 = |
5d49f498 | 1431 | iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32)); |
b481de9c | 1432 | ilink2 = |
5d49f498 | 1433 | iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32)); |
b481de9c | 1434 | data1 = |
5d49f498 | 1435 | iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32)); |
b481de9c | 1436 | |
15b1687c | 1437 | IWL_ERR(priv, |
87563715 | 1438 | "%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", |
15b1687c WT |
1439 | desc_lookup(desc), desc, time, blink1, blink2, |
1440 | ilink1, ilink2, data1); | |
be1a71a1 JB |
1441 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0, |
1442 | 0, blink1, blink2, ilink1, ilink2); | |
b481de9c | 1443 | } |
b481de9c ZY |
1444 | } |
1445 | ||
f58177b9 | 1446 | #define EVENT_START_OFFSET (6 * sizeof(u32)) |
b481de9c ZY |
1447 | |
1448 | /** | |
bb8c093b | 1449 | * iwl3945_print_event_log - Dump error event log to syslog |
b481de9c | 1450 | * |
b481de9c | 1451 | */ |
b03d7d0f WYG |
1452 | static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx, |
1453 | u32 num_events, u32 mode, | |
1454 | int pos, char **buf, size_t bufsz) | |
b481de9c ZY |
1455 | { |
1456 | u32 i; | |
1457 | u32 base; /* SRAM byte address of event log header */ | |
1458 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1459 | u32 ptr; /* SRAM byte address of log data */ | |
1460 | u32 ev, time, data; /* event log data */ | |
e5854471 | 1461 | unsigned long reg_flags; |
b481de9c ZY |
1462 | |
1463 | if (num_events == 0) | |
b03d7d0f | 1464 | return pos; |
b481de9c ZY |
1465 | |
1466 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1467 | ||
1468 | if (mode == 0) | |
1469 | event_size = 2 * sizeof(u32); | |
1470 | else | |
1471 | event_size = 3 * sizeof(u32); | |
1472 | ||
1473 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1474 | ||
e5854471 BC |
1475 | /* Make sure device is powered up for SRAM reads */ |
1476 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
1477 | iwl_grab_nic_access(priv); | |
1478 | ||
1479 | /* Set starting address; reads will auto-increment */ | |
1480 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
1481 | rmb(); | |
1482 | ||
b481de9c ZY |
1483 | /* "time" is actually "data" for mode 0 (no timestamp). |
1484 | * place event id # at far right for easier visual parsing. */ | |
1485 | for (i = 0; i < num_events; i++) { | |
e5854471 BC |
1486 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
1487 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
15b1687c WT |
1488 | if (mode == 0) { |
1489 | /* data, ev */ | |
b03d7d0f WYG |
1490 | if (bufsz) { |
1491 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1492 | "0x%08x:%04u\n", | |
1493 | time, ev); | |
1494 | } else { | |
1495 | IWL_ERR(priv, "0x%08x\t%04u\n", time, ev); | |
1496 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
1497 | time, ev); | |
1498 | } | |
15b1687c | 1499 | } else { |
e5854471 | 1500 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
1501 | if (bufsz) { |
1502 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1503 | "%010u:0x%08x:%04u\n", | |
1504 | time, data, ev); | |
1505 | } else { | |
1506 | IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", | |
1507 | time, data, ev); | |
1508 | trace_iwlwifi_dev_ucode_event(priv, time, | |
1509 | data, ev); | |
1510 | } | |
b481de9c ZY |
1511 | } |
1512 | } | |
e5854471 BC |
1513 | |
1514 | /* Allow device to power down */ | |
1515 | iwl_release_nic_access(priv); | |
1516 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 1517 | return pos; |
b481de9c ZY |
1518 | } |
1519 | ||
c341ddb2 WYG |
1520 | /** |
1521 | * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog | |
1522 | */ | |
b03d7d0f | 1523 | static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
c341ddb2 | 1524 | u32 num_wraps, u32 next_entry, |
b03d7d0f WYG |
1525 | u32 size, u32 mode, |
1526 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
1527 | { |
1528 | /* | |
1529 | * display the newest DEFAULT_LOG_ENTRIES entries | |
1530 | * i.e the entries just before the next ont that uCode would fill. | |
1531 | */ | |
1532 | if (num_wraps) { | |
1533 | if (next_entry < size) { | |
b03d7d0f WYG |
1534 | pos = iwl3945_print_event_log(priv, |
1535 | capacity - (size - next_entry), | |
1536 | size - next_entry, mode, | |
1537 | pos, buf, bufsz); | |
1538 | pos = iwl3945_print_event_log(priv, 0, | |
1539 | next_entry, mode, | |
1540 | pos, buf, bufsz); | |
c341ddb2 | 1541 | } else |
b03d7d0f WYG |
1542 | pos = iwl3945_print_event_log(priv, next_entry - size, |
1543 | size, mode, | |
1544 | pos, buf, bufsz); | |
c341ddb2 WYG |
1545 | } else { |
1546 | if (next_entry < size) | |
b03d7d0f WYG |
1547 | pos = iwl3945_print_event_log(priv, 0, |
1548 | next_entry, mode, | |
1549 | pos, buf, bufsz); | |
c341ddb2 | 1550 | else |
b03d7d0f WYG |
1551 | pos = iwl3945_print_event_log(priv, next_entry - size, |
1552 | size, mode, | |
1553 | pos, buf, bufsz); | |
c341ddb2 | 1554 | } |
b03d7d0f | 1555 | return pos; |
c341ddb2 WYG |
1556 | } |
1557 | ||
c341ddb2 WYG |
1558 | #define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20) |
1559 | ||
b03d7d0f WYG |
1560 | int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
1561 | char **buf, bool display) | |
b481de9c | 1562 | { |
b481de9c ZY |
1563 | u32 base; /* SRAM byte address of event log header */ |
1564 | u32 capacity; /* event log capacity in # entries */ | |
1565 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1566 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1567 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1568 | u32 size; /* # entries that we'll print */ | |
b03d7d0f WYG |
1569 | int pos = 0; |
1570 | size_t bufsz = 0; | |
b481de9c ZY |
1571 | |
1572 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 1573 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1574 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); |
937c397e | 1575 | return -EINVAL; |
b481de9c ZY |
1576 | } |
1577 | ||
b481de9c | 1578 | /* event log header */ |
5d49f498 AK |
1579 | capacity = iwl_read_targ_mem(priv, base); |
1580 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1581 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1582 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c | 1583 | |
678b385d | 1584 | if (capacity > priv->cfg->max_event_log_size) { |
84c40692 | 1585 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", |
678b385d WYG |
1586 | capacity, priv->cfg->max_event_log_size); |
1587 | capacity = priv->cfg->max_event_log_size; | |
84c40692 BC |
1588 | } |
1589 | ||
678b385d | 1590 | if (next_entry > priv->cfg->max_event_log_size) { |
84c40692 | 1591 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", |
678b385d WYG |
1592 | next_entry, priv->cfg->max_event_log_size); |
1593 | next_entry = priv->cfg->max_event_log_size; | |
84c40692 BC |
1594 | } |
1595 | ||
b481de9c ZY |
1596 | size = num_wraps ? capacity : next_entry; |
1597 | ||
1598 | /* bail out if nothing in log */ | |
1599 | if (size == 0) { | |
15b1687c | 1600 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); |
b03d7d0f | 1601 | return pos; |
b481de9c ZY |
1602 | } |
1603 | ||
c341ddb2 | 1604 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 1605 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
1606 | size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES) |
1607 | ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size; | |
1608 | #else | |
1609 | size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES) | |
1610 | ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size; | |
1611 | #endif | |
1612 | ||
1613 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n", | |
1614 | size); | |
b481de9c | 1615 | |
c341ddb2 | 1616 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
1617 | if (display) { |
1618 | if (full_log) | |
1619 | bufsz = capacity * 48; | |
1620 | else | |
1621 | bufsz = size * 48; | |
1622 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
1623 | if (!*buf) | |
937c397e | 1624 | return -ENOMEM; |
b03d7d0f | 1625 | } |
c341ddb2 WYG |
1626 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
1627 | /* if uCode has wrapped back to top of log, | |
1628 | * start at the oldest entry, | |
1629 | * i.e the next one that uCode would fill. | |
1630 | */ | |
1631 | if (num_wraps) | |
b03d7d0f WYG |
1632 | pos = iwl3945_print_event_log(priv, next_entry, |
1633 | capacity - next_entry, mode, | |
1634 | pos, buf, bufsz); | |
c341ddb2 WYG |
1635 | |
1636 | /* (then/else) start at top of log */ | |
b03d7d0f WYG |
1637 | pos = iwl3945_print_event_log(priv, 0, next_entry, mode, |
1638 | pos, buf, bufsz); | |
c341ddb2 | 1639 | } else |
b03d7d0f WYG |
1640 | pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps, |
1641 | next_entry, size, mode, | |
1642 | pos, buf, bufsz); | |
b7a79404 | 1643 | #else |
b03d7d0f WYG |
1644 | pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps, |
1645 | next_entry, size, mode, | |
1646 | pos, buf, bufsz); | |
c341ddb2 | 1647 | #endif |
b03d7d0f | 1648 | return pos; |
b7a79404 RC |
1649 | } |
1650 | ||
4a8a4322 | 1651 | static void iwl3945_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
1652 | { |
1653 | u32 inta, handled = 0; | |
1654 | u32 inta_fh; | |
1655 | unsigned long flags; | |
d08853a3 | 1656 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1657 | u32 inta_mask; |
1658 | #endif | |
1659 | ||
1660 | spin_lock_irqsave(&priv->lock, flags); | |
1661 | ||
1662 | /* Ack/clear/reset pending uCode interrupts. | |
1663 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1664 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
5d49f498 AK |
1665 | inta = iwl_read32(priv, CSR_INT); |
1666 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1667 | |
1668 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1669 | * Any new interrupts that happen after this, either while we're | |
1670 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
5d49f498 AK |
1671 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1672 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1673 | |
d08853a3 | 1674 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1675 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 1676 | /* just for debug */ |
5d49f498 | 1677 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1678 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1679 | inta, inta_mask, inta_fh); |
1680 | } | |
1681 | #endif | |
1682 | ||
2f301227 ZY |
1683 | spin_unlock_irqrestore(&priv->lock, flags); |
1684 | ||
b481de9c ZY |
1685 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not |
1686 | * atomic, make sure that inta covers all the interrupts that | |
1687 | * we've discovered, even if FH interrupt came in just after | |
1688 | * reading CSR_INT. */ | |
6f83eaa1 | 1689 | if (inta_fh & CSR39_FH_INT_RX_MASK) |
b481de9c | 1690 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1691 | if (inta_fh & CSR39_FH_INT_TX_MASK) |
b481de9c ZY |
1692 | inta |= CSR_INT_BIT_FH_TX; |
1693 | ||
1694 | /* Now service all interrupt bits discovered above. */ | |
1695 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1696 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
1697 | |
1698 | /* Tell the device to stop sending interrupts */ | |
ed3b932e | 1699 | iwl_disable_interrupts(priv); |
b481de9c | 1700 | |
86ddbf62 | 1701 | priv->isr_stats.hw++; |
8ccde88a | 1702 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1703 | |
1704 | handled |= CSR_INT_BIT_HW_ERR; | |
1705 | ||
b481de9c ZY |
1706 | return; |
1707 | } | |
1708 | ||
d08853a3 | 1709 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1710 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 1711 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
86ddbf62 | 1712 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1713 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1714 | "the frame/frames.\n"); |
86ddbf62 AK |
1715 | priv->isr_stats.sch++; |
1716 | } | |
b481de9c ZY |
1717 | |
1718 | /* Alive notification via Rx interrupt will do the real work */ | |
86ddbf62 | 1719 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1720 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
86ddbf62 AK |
1721 | priv->isr_stats.alive++; |
1722 | } | |
b481de9c ZY |
1723 | } |
1724 | #endif | |
1725 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1726 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1727 | |
b481de9c ZY |
1728 | /* Error detected by uCode */ |
1729 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1730 | IWL_ERR(priv, "Microcode SW error detected. " |
1731 | "Restarting 0x%X.\n", inta); | |
86ddbf62 | 1732 | priv->isr_stats.sw++; |
8ccde88a | 1733 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1734 | handled |= CSR_INT_BIT_SW_ERR; |
1735 | } | |
1736 | ||
1737 | /* uCode wakes up after power-down sleep */ | |
1738 | if (inta & CSR_INT_BIT_WAKEUP) { | |
e1623446 | 1739 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
141c43a3 | 1740 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
4f3602c8 SO |
1741 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
1742 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1743 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1744 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1745 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1746 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c | 1747 | |
86ddbf62 | 1748 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1749 | handled |= CSR_INT_BIT_WAKEUP; |
1750 | } | |
1751 | ||
1752 | /* All uCode command responses, including Tx command responses, | |
1753 | * Rx "responses" (frame-received notification), and other | |
1754 | * notifications from uCode come through here*/ | |
1755 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 1756 | iwl3945_rx_handle(priv); |
86ddbf62 | 1757 | priv->isr_stats.rx++; |
b481de9c ZY |
1758 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1759 | } | |
1760 | ||
1761 | if (inta & CSR_INT_BIT_FH_TX) { | |
e1623446 | 1762 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); |
86ddbf62 | 1763 | priv->isr_stats.tx++; |
b481de9c | 1764 | |
5d49f498 | 1765 | iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); |
a8b50a0a MA |
1766 | iwl_write_direct32(priv, FH39_TCSR_CREDIT |
1767 | (FH39_SRVC_CHNL), 0x0); | |
b481de9c ZY |
1768 | handled |= CSR_INT_BIT_FH_TX; |
1769 | } | |
1770 | ||
86ddbf62 | 1771 | if (inta & ~handled) { |
15b1687c | 1772 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
86ddbf62 AK |
1773 | priv->isr_stats.unhandled++; |
1774 | } | |
b481de9c | 1775 | |
40cefda9 | 1776 | if (inta & ~priv->inta_mask) { |
39aadf8c | 1777 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1778 | inta & ~priv->inta_mask); |
39aadf8c | 1779 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1780 | } |
1781 | ||
1782 | /* Re-enable all interrupts */ | |
0359facc MA |
1783 | /* only Re-enable if disabled by irq */ |
1784 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
ed3b932e | 1785 | iwl_enable_interrupts(priv); |
b481de9c | 1786 | |
d08853a3 | 1787 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1788 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
5d49f498 AK |
1789 | inta = iwl_read32(priv, CSR_INT); |
1790 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1791 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1792 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1793 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1794 | } | |
1795 | #endif | |
b481de9c ZY |
1796 | } |
1797 | ||
14023641 AK |
1798 | static int iwl3945_get_single_channel_for_scan(struct iwl_priv *priv, |
1799 | struct ieee80211_vif *vif, | |
1800 | enum ieee80211_band band, | |
1801 | struct iwl3945_scan_channel *scan_ch) | |
1802 | { | |
1803 | const struct ieee80211_supported_band *sband; | |
1804 | u16 passive_dwell = 0; | |
1805 | u16 active_dwell = 0; | |
1806 | int added = 0; | |
1807 | u8 channel = 0; | |
1808 | ||
1809 | sband = iwl_get_hw_mode(priv, band); | |
1810 | if (!sband) { | |
1811 | IWL_ERR(priv, "invalid band\n"); | |
1812 | return added; | |
1813 | } | |
1814 | ||
1815 | active_dwell = iwl_get_active_dwell_time(priv, band, 0); | |
1816 | passive_dwell = iwl_get_passive_dwell_time(priv, band, vif); | |
1817 | ||
1818 | if (passive_dwell <= active_dwell) | |
1819 | passive_dwell = active_dwell + 1; | |
1820 | ||
1821 | ||
1822 | channel = iwl_get_single_channel_number(priv, band); | |
1823 | ||
1824 | if (channel) { | |
1825 | scan_ch->channel = channel; | |
1826 | scan_ch->type = 0; /* passive */ | |
1827 | scan_ch->active_dwell = cpu_to_le16(active_dwell); | |
1828 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
1829 | /* Set txpower levels to defaults */ | |
1830 | scan_ch->tpc.dsp_atten = 110; | |
1831 | if (band == IEEE80211_BAND_5GHZ) | |
1832 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; | |
1833 | else | |
1834 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
1835 | added++; | |
1836 | } else | |
1837 | IWL_ERR(priv, "no valid channel found\n"); | |
1838 | return added; | |
1839 | } | |
1840 | ||
4a8a4322 | 1841 | static int iwl3945_get_channels_for_scan(struct iwl_priv *priv, |
8318d78a | 1842 | enum ieee80211_band band, |
f9340520 | 1843 | u8 is_active, u8 n_probes, |
1dda6d28 JB |
1844 | struct iwl3945_scan_channel *scan_ch, |
1845 | struct ieee80211_vif *vif) | |
b481de9c | 1846 | { |
4e05c234 | 1847 | struct ieee80211_channel *chan; |
8318d78a | 1848 | const struct ieee80211_supported_band *sband; |
d20b3c65 | 1849 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
1850 | u16 passive_dwell = 0; |
1851 | u16 active_dwell = 0; | |
1852 | int added, i; | |
1853 | ||
cbba18c6 | 1854 | sband = iwl_get_hw_mode(priv, band); |
8318d78a | 1855 | if (!sband) |
b481de9c ZY |
1856 | return 0; |
1857 | ||
77fecfb8 | 1858 | active_dwell = iwl_get_active_dwell_time(priv, band, n_probes); |
1dda6d28 | 1859 | passive_dwell = iwl_get_passive_dwell_time(priv, band, vif); |
b481de9c | 1860 | |
8f4807a1 AK |
1861 | if (passive_dwell <= active_dwell) |
1862 | passive_dwell = active_dwell + 1; | |
1863 | ||
4e05c234 JB |
1864 | for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) { |
1865 | chan = priv->scan_request->channels[i]; | |
1866 | ||
1867 | if (chan->band != band) | |
182e2e66 JB |
1868 | continue; |
1869 | ||
4e05c234 | 1870 | scan_ch->channel = chan->hw_value; |
b481de9c | 1871 | |
e6148917 | 1872 | ch_info = iwl_get_channel_info(priv, band, scan_ch->channel); |
b481de9c | 1873 | if (!is_channel_valid(ch_info)) { |
e1623446 | 1874 | IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n", |
b481de9c ZY |
1875 | scan_ch->channel); |
1876 | continue; | |
1877 | } | |
1878 | ||
011a0330 AK |
1879 | scan_ch->active_dwell = cpu_to_le16(active_dwell); |
1880 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
1881 | /* If passive , set up for auto-switch | |
1882 | * and use long active_dwell time. | |
1883 | */ | |
b481de9c | 1884 | if (!is_active || is_channel_passive(ch_info) || |
4e05c234 | 1885 | (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) { |
b481de9c | 1886 | scan_ch->type = 0; /* passive */ |
011a0330 AK |
1887 | if (IWL_UCODE_API(priv->ucode_ver) == 1) |
1888 | scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1); | |
1889 | } else { | |
b481de9c | 1890 | scan_ch->type = 1; /* active */ |
011a0330 | 1891 | } |
b481de9c | 1892 | |
011a0330 AK |
1893 | /* Set direct probe bits. These may be used both for active |
1894 | * scan channels (probes gets sent right away), | |
1895 | * or for passive channels (probes get se sent only after | |
1896 | * hearing clear Rx packet).*/ | |
1897 | if (IWL_UCODE_API(priv->ucode_ver) >= 2) { | |
1898 | if (n_probes) | |
0d21044e | 1899 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 AK |
1900 | } else { |
1901 | /* uCode v1 does not allow setting direct probe bits on | |
1902 | * passive channel. */ | |
1903 | if ((scan_ch->type & 1) && n_probes) | |
0d21044e | 1904 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 | 1905 | } |
b481de9c | 1906 | |
9fbab516 | 1907 | /* Set txpower levels to defaults */ |
b481de9c ZY |
1908 | scan_ch->tpc.dsp_atten = 110; |
1909 | /* scan_pwr_info->tpc.dsp_atten; */ | |
1910 | ||
1911 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 1912 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
1913 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
1914 | else { | |
1915 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
1916 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 1917 | * power level: |
8a1b0245 | 1918 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
1919 | */ |
1920 | } | |
1921 | ||
e1623446 | 1922 | IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n", |
b481de9c ZY |
1923 | scan_ch->channel, |
1924 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
1925 | (scan_ch->type & 1) ? | |
1926 | active_dwell : passive_dwell); | |
1927 | ||
1928 | scan_ch++; | |
1929 | added++; | |
1930 | } | |
1931 | ||
91dd6c27 | 1932 | IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added); |
b481de9c ZY |
1933 | return added; |
1934 | } | |
1935 | ||
4a8a4322 | 1936 | static void iwl3945_init_hw_rates(struct iwl_priv *priv, |
b481de9c ZY |
1937 | struct ieee80211_rate *rates) |
1938 | { | |
1939 | int i; | |
1940 | ||
8e1a53c6 | 1941 | for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) { |
8318d78a JB |
1942 | rates[i].bitrate = iwl3945_rates[i].ieee * 5; |
1943 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
1944 | rates[i].hw_value_short = i; | |
1945 | rates[i].flags = 0; | |
d9829a67 | 1946 | if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { |
b481de9c | 1947 | /* |
8318d78a | 1948 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 1949 | */ |
bb8c093b | 1950 | rates[i].flags |= (iwl3945_rates[i].plcp == 10) ? |
8318d78a | 1951 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
b481de9c | 1952 | } |
b481de9c ZY |
1953 | } |
1954 | } | |
1955 | ||
b481de9c ZY |
1956 | /****************************************************************************** |
1957 | * | |
1958 | * uCode download functions | |
1959 | * | |
1960 | ******************************************************************************/ | |
1961 | ||
4a8a4322 | 1962 | static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1963 | { |
98c92211 TW |
1964 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1965 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1966 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1967 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1968 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1969 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1970 | } |
1971 | ||
1972 | /** | |
bb8c093b | 1973 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
1974 | * looking at all data. |
1975 | */ | |
4a8a4322 | 1976 | static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
1977 | { |
1978 | u32 val; | |
1979 | u32 save_len = len; | |
1980 | int rc = 0; | |
1981 | u32 errcnt; | |
1982 | ||
e1623446 | 1983 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 1984 | |
5d49f498 | 1985 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 1986 | IWL39_RTC_INST_LOWER_BOUND); |
b481de9c ZY |
1987 | |
1988 | errcnt = 0; | |
1989 | for (; len > 0; len -= sizeof(u32), image++) { | |
1990 | /* read data comes through single port, auto-incr addr */ | |
1991 | /* NOTE: Use the debugless read so we don't flood kernel log | |
1992 | * if IWL_DL_IO is set */ | |
5d49f498 | 1993 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c | 1994 | if (val != le32_to_cpu(*image)) { |
15b1687c | 1995 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
1996 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
1997 | save_len - len, val, le32_to_cpu(*image)); | |
1998 | rc = -EIO; | |
1999 | errcnt++; | |
2000 | if (errcnt >= 20) | |
2001 | break; | |
2002 | } | |
2003 | } | |
2004 | ||
b481de9c ZY |
2005 | |
2006 | if (!errcnt) | |
e1623446 TW |
2007 | IWL_DEBUG_INFO(priv, |
2008 | "ucode image in INSTRUCTION memory is good\n"); | |
b481de9c ZY |
2009 | |
2010 | return rc; | |
2011 | } | |
2012 | ||
2013 | ||
2014 | /** | |
bb8c093b | 2015 | * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
2016 | * using sample data 100 bytes apart. If these sample points are good, |
2017 | * it's a pretty good bet that everything between them is good, too. | |
2018 | */ | |
4a8a4322 | 2019 | static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
2020 | { |
2021 | u32 val; | |
2022 | int rc = 0; | |
2023 | u32 errcnt = 0; | |
2024 | u32 i; | |
2025 | ||
e1623446 | 2026 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 2027 | |
b481de9c ZY |
2028 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { |
2029 | /* read data comes through single port, auto-incr addr */ | |
2030 | /* NOTE: Use the debugless read so we don't flood kernel log | |
2031 | * if IWL_DL_IO is set */ | |
5d49f498 | 2032 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 2033 | i + IWL39_RTC_INST_LOWER_BOUND); |
5d49f498 | 2034 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
2035 | if (val != le32_to_cpu(*image)) { |
2036 | #if 0 /* Enable this if you want to see details */ | |
15b1687c | 2037 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
2038 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
2039 | i, val, *image); | |
2040 | #endif | |
2041 | rc = -EIO; | |
2042 | errcnt++; | |
2043 | if (errcnt >= 3) | |
2044 | break; | |
2045 | } | |
2046 | } | |
2047 | ||
b481de9c ZY |
2048 | return rc; |
2049 | } | |
2050 | ||
2051 | ||
2052 | /** | |
bb8c093b | 2053 | * iwl3945_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
2054 | * and verify its contents |
2055 | */ | |
4a8a4322 | 2056 | static int iwl3945_verify_ucode(struct iwl_priv *priv) |
b481de9c ZY |
2057 | { |
2058 | __le32 *image; | |
2059 | u32 len; | |
2060 | int rc = 0; | |
2061 | ||
2062 | /* Try bootstrap */ | |
2063 | image = (__le32 *)priv->ucode_boot.v_addr; | |
2064 | len = priv->ucode_boot.len; | |
bb8c093b | 2065 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2066 | if (rc == 0) { |
e1623446 | 2067 | IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n"); |
b481de9c ZY |
2068 | return 0; |
2069 | } | |
2070 | ||
2071 | /* Try initialize */ | |
2072 | image = (__le32 *)priv->ucode_init.v_addr; | |
2073 | len = priv->ucode_init.len; | |
bb8c093b | 2074 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2075 | if (rc == 0) { |
e1623446 | 2076 | IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n"); |
b481de9c ZY |
2077 | return 0; |
2078 | } | |
2079 | ||
2080 | /* Try runtime/protocol */ | |
2081 | image = (__le32 *)priv->ucode_code.v_addr; | |
2082 | len = priv->ucode_code.len; | |
bb8c093b | 2083 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2084 | if (rc == 0) { |
e1623446 | 2085 | IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n"); |
b481de9c ZY |
2086 | return 0; |
2087 | } | |
2088 | ||
15b1687c | 2089 | IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
b481de9c | 2090 | |
9fbab516 BC |
2091 | /* Since nothing seems to match, show first several data entries in |
2092 | * instruction SRAM, so maybe visual inspection will give a clue. | |
2093 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
2094 | image = (__le32 *)priv->ucode_boot.v_addr; |
2095 | len = priv->ucode_boot.len; | |
bb8c093b | 2096 | rc = iwl3945_verify_inst_full(priv, image, len); |
b481de9c ZY |
2097 | |
2098 | return rc; | |
2099 | } | |
2100 | ||
4a8a4322 | 2101 | static void iwl3945_nic_start(struct iwl_priv *priv) |
b481de9c ZY |
2102 | { |
2103 | /* Remove all resets to allow NIC to operate */ | |
5d49f498 | 2104 | iwl_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
2105 | } |
2106 | ||
93b1a2f9 JB |
2107 | #define IWL3945_UCODE_GET(item) \ |
2108 | static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode)\ | |
2109 | { \ | |
2110 | return le32_to_cpu(ucode->u.v1.item); \ | |
2111 | } | |
2112 | ||
2113 | static u32 iwl3945_ucode_get_header_size(u32 api_ver) | |
2114 | { | |
22adba2a | 2115 | return 24; |
93b1a2f9 JB |
2116 | } |
2117 | ||
2118 | static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode) | |
2119 | { | |
2120 | return (u8 *) ucode->u.v1.data; | |
2121 | } | |
2122 | ||
2123 | IWL3945_UCODE_GET(inst_size); | |
2124 | IWL3945_UCODE_GET(data_size); | |
2125 | IWL3945_UCODE_GET(init_size); | |
2126 | IWL3945_UCODE_GET(init_data_size); | |
2127 | IWL3945_UCODE_GET(boot_size); | |
2128 | ||
b481de9c | 2129 | /** |
bb8c093b | 2130 | * iwl3945_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
2131 | * |
2132 | * Copy into buffers for card to fetch via bus-mastering | |
2133 | */ | |
4a8a4322 | 2134 | static int iwl3945_read_ucode(struct iwl_priv *priv) |
b481de9c | 2135 | { |
cc0f555d | 2136 | const struct iwl_ucode_header *ucode; |
a0987a8d | 2137 | int ret = -EINVAL, index; |
b481de9c ZY |
2138 | const struct firmware *ucode_raw; |
2139 | /* firmware file name contains uCode/driver compatibility version */ | |
a0987a8d RC |
2140 | const char *name_pre = priv->cfg->fw_name_pre; |
2141 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
2142 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
2143 | char buf[25]; | |
b481de9c ZY |
2144 | u8 *src; |
2145 | size_t len; | |
a0987a8d | 2146 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; |
b481de9c ZY |
2147 | |
2148 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
2149 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
2150 | for (index = api_max; index >= api_min; index--) { |
2151 | sprintf(buf, "%s%u%s", name_pre, index, ".ucode"); | |
2152 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
2153 | if (ret < 0) { | |
15b1687c | 2154 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
2155 | buf, ret); |
2156 | if (ret == -ENOENT) | |
2157 | continue; | |
2158 | else | |
2159 | goto error; | |
2160 | } else { | |
2161 | if (index < api_max) | |
15b1687c WT |
2162 | IWL_ERR(priv, "Loaded firmware %s, " |
2163 | "which is deprecated. " | |
2164 | " Please use API v%u instead.\n", | |
a0987a8d | 2165 | buf, api_max); |
e1623446 TW |
2166 | IWL_DEBUG_INFO(priv, "Got firmware '%s' file " |
2167 | "(%zd bytes) from disk\n", | |
a0987a8d RC |
2168 | buf, ucode_raw->size); |
2169 | break; | |
2170 | } | |
b481de9c ZY |
2171 | } |
2172 | ||
a0987a8d RC |
2173 | if (ret < 0) |
2174 | goto error; | |
b481de9c ZY |
2175 | |
2176 | /* Make sure that we got at least our header! */ | |
93b1a2f9 | 2177 | if (ucode_raw->size < iwl3945_ucode_get_header_size(1)) { |
15b1687c | 2178 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 2179 | ret = -EINVAL; |
b481de9c ZY |
2180 | goto err_release; |
2181 | } | |
2182 | ||
2183 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 2184 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 2185 | |
c02b3acd | 2186 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 2187 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
93b1a2f9 JB |
2188 | inst_size = iwl3945_ucode_get_inst_size(ucode); |
2189 | data_size = iwl3945_ucode_get_data_size(ucode); | |
2190 | init_size = iwl3945_ucode_get_init_size(ucode); | |
2191 | init_data_size = iwl3945_ucode_get_init_data_size(ucode); | |
2192 | boot_size = iwl3945_ucode_get_boot_size(ucode); | |
2193 | src = iwl3945_ucode_get_data(ucode); | |
b481de9c | 2194 | |
a0987a8d RC |
2195 | /* api_ver should match the api version forming part of the |
2196 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 2197 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
2198 | |
2199 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 2200 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
2201 | "Driver supports v%u, firmware is v%u.\n", |
2202 | api_max, api_ver); | |
2203 | priv->ucode_ver = 0; | |
2204 | ret = -EINVAL; | |
2205 | goto err_release; | |
2206 | } | |
2207 | if (api_ver != api_max) | |
15b1687c | 2208 | IWL_ERR(priv, "Firmware has old API version. Expected %u, " |
a0987a8d RC |
2209 | "got %u. New firmware can be obtained " |
2210 | "from http://www.intellinuxwireless.org.\n", | |
2211 | api_max, api_ver); | |
2212 | ||
978785a3 TW |
2213 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
2214 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2215 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2216 | IWL_UCODE_API(priv->ucode_ver), | |
2217 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
2218 | ||
5ebeb5a6 RC |
2219 | snprintf(priv->hw->wiphy->fw_version, |
2220 | sizeof(priv->hw->wiphy->fw_version), | |
2221 | "%u.%u.%u.%u", | |
2222 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2223 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2224 | IWL_UCODE_API(priv->ucode_ver), | |
2225 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
2226 | ||
e1623446 | 2227 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 2228 | priv->ucode_ver); |
e1623446 TW |
2229 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
2230 | inst_size); | |
2231 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", | |
2232 | data_size); | |
2233 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", | |
2234 | init_size); | |
2235 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", | |
2236 | init_data_size); | |
2237 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", | |
2238 | boot_size); | |
b481de9c | 2239 | |
a0987a8d | 2240 | |
b481de9c | 2241 | /* Verify size of file vs. image size info in file's header */ |
93b1a2f9 | 2242 | if (ucode_raw->size != iwl3945_ucode_get_header_size(api_ver) + |
b481de9c ZY |
2243 | inst_size + data_size + init_size + |
2244 | init_data_size + boot_size) { | |
2245 | ||
cc0f555d JS |
2246 | IWL_DEBUG_INFO(priv, |
2247 | "uCode file size %zd does not match expected size\n", | |
2248 | ucode_raw->size); | |
90e759d1 | 2249 | ret = -EINVAL; |
b481de9c ZY |
2250 | goto err_release; |
2251 | } | |
2252 | ||
2253 | /* Verify that uCode images will fit in card's SRAM */ | |
250bdd21 | 2254 | if (inst_size > IWL39_MAX_INST_SIZE) { |
e1623446 | 2255 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 TW |
2256 | inst_size); |
2257 | ret = -EINVAL; | |
b481de9c ZY |
2258 | goto err_release; |
2259 | } | |
2260 | ||
250bdd21 | 2261 | if (data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 | 2262 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 TW |
2263 | data_size); |
2264 | ret = -EINVAL; | |
b481de9c ZY |
2265 | goto err_release; |
2266 | } | |
250bdd21 | 2267 | if (init_size > IWL39_MAX_INST_SIZE) { |
e1623446 TW |
2268 | IWL_DEBUG_INFO(priv, |
2269 | "uCode init instr len %d too large to fit in\n", | |
90e759d1 TW |
2270 | init_size); |
2271 | ret = -EINVAL; | |
b481de9c ZY |
2272 | goto err_release; |
2273 | } | |
250bdd21 | 2274 | if (init_data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 TW |
2275 | IWL_DEBUG_INFO(priv, |
2276 | "uCode init data len %d too large to fit in\n", | |
90e759d1 TW |
2277 | init_data_size); |
2278 | ret = -EINVAL; | |
b481de9c ZY |
2279 | goto err_release; |
2280 | } | |
250bdd21 | 2281 | if (boot_size > IWL39_MAX_BSM_SIZE) { |
e1623446 TW |
2282 | IWL_DEBUG_INFO(priv, |
2283 | "uCode boot instr len %d too large to fit in\n", | |
90e759d1 TW |
2284 | boot_size); |
2285 | ret = -EINVAL; | |
b481de9c ZY |
2286 | goto err_release; |
2287 | } | |
2288 | ||
2289 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
2290 | ||
2291 | /* Runtime instructions and 2 copies of data: | |
2292 | * 1) unmodified from disk | |
2293 | * 2) backup cache for save/restore during power-downs */ | |
2294 | priv->ucode_code.len = inst_size; | |
98c92211 | 2295 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
2296 | |
2297 | priv->ucode_data.len = data_size; | |
98c92211 | 2298 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
2299 | |
2300 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 2301 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 2302 | |
90e759d1 TW |
2303 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
2304 | !priv->ucode_data_backup.v_addr) | |
2305 | goto err_pci_alloc; | |
b481de9c ZY |
2306 | |
2307 | /* Initialization instructions and data */ | |
90e759d1 TW |
2308 | if (init_size && init_data_size) { |
2309 | priv->ucode_init.len = init_size; | |
98c92211 | 2310 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
2311 | |
2312 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 2313 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
2314 | |
2315 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
2316 | goto err_pci_alloc; | |
2317 | } | |
b481de9c ZY |
2318 | |
2319 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
2320 | if (boot_size) { |
2321 | priv->ucode_boot.len = boot_size; | |
98c92211 | 2322 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 2323 | |
90e759d1 TW |
2324 | if (!priv->ucode_boot.v_addr) |
2325 | goto err_pci_alloc; | |
2326 | } | |
b481de9c ZY |
2327 | |
2328 | /* Copy images into buffers for card's bus-master reads ... */ | |
2329 | ||
2330 | /* Runtime instructions (first block of data in file) */ | |
cc0f555d | 2331 | len = inst_size; |
e1623446 TW |
2332 | IWL_DEBUG_INFO(priv, |
2333 | "Copying (but not loading) uCode instr len %zd\n", len); | |
b481de9c | 2334 | memcpy(priv->ucode_code.v_addr, src, len); |
cc0f555d JS |
2335 | src += len; |
2336 | ||
e1623446 | 2337 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
2338 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
2339 | ||
2340 | /* Runtime data (2nd block) | |
bb8c093b | 2341 | * NOTE: Copy into backup buffer will be done in iwl3945_up() */ |
cc0f555d | 2342 | len = data_size; |
e1623446 TW |
2343 | IWL_DEBUG_INFO(priv, |
2344 | "Copying (but not loading) uCode data len %zd\n", len); | |
b481de9c ZY |
2345 | memcpy(priv->ucode_data.v_addr, src, len); |
2346 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
cc0f555d | 2347 | src += len; |
b481de9c ZY |
2348 | |
2349 | /* Initialization instructions (3rd block) */ | |
2350 | if (init_size) { | |
cc0f555d | 2351 | len = init_size; |
e1623446 TW |
2352 | IWL_DEBUG_INFO(priv, |
2353 | "Copying (but not loading) init instr len %zd\n", len); | |
b481de9c | 2354 | memcpy(priv->ucode_init.v_addr, src, len); |
cc0f555d | 2355 | src += len; |
b481de9c ZY |
2356 | } |
2357 | ||
2358 | /* Initialization data (4th block) */ | |
2359 | if (init_data_size) { | |
cc0f555d | 2360 | len = init_data_size; |
e1623446 TW |
2361 | IWL_DEBUG_INFO(priv, |
2362 | "Copying (but not loading) init data len %zd\n", len); | |
b481de9c | 2363 | memcpy(priv->ucode_init_data.v_addr, src, len); |
cc0f555d | 2364 | src += len; |
b481de9c ZY |
2365 | } |
2366 | ||
2367 | /* Bootstrap instructions (5th block) */ | |
cc0f555d | 2368 | len = boot_size; |
e1623446 TW |
2369 | IWL_DEBUG_INFO(priv, |
2370 | "Copying (but not loading) boot instr len %zd\n", len); | |
b481de9c ZY |
2371 | memcpy(priv->ucode_boot.v_addr, src, len); |
2372 | ||
2373 | /* We have our copies now, allow OS release its copies */ | |
2374 | release_firmware(ucode_raw); | |
2375 | return 0; | |
2376 | ||
2377 | err_pci_alloc: | |
15b1687c | 2378 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 2379 | ret = -ENOMEM; |
bb8c093b | 2380 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
2381 | |
2382 | err_release: | |
2383 | release_firmware(ucode_raw); | |
2384 | ||
2385 | error: | |
90e759d1 | 2386 | return ret; |
b481de9c ZY |
2387 | } |
2388 | ||
2389 | ||
2390 | /** | |
bb8c093b | 2391 | * iwl3945_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
2392 | * |
2393 | * Tell initialization uCode where to find runtime uCode. | |
2394 | * | |
2395 | * BSM registers initially contain pointers to initialization uCode. | |
2396 | * We need to replace them to load runtime uCode inst and data, | |
2397 | * and to save runtime data when powering down. | |
2398 | */ | |
4a8a4322 | 2399 | static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv) |
b481de9c ZY |
2400 | { |
2401 | dma_addr_t pinst; | |
2402 | dma_addr_t pdata; | |
b481de9c ZY |
2403 | |
2404 | /* bits 31:0 for 3945 */ | |
2405 | pinst = priv->ucode_code.p_addr; | |
2406 | pdata = priv->ucode_data_backup.p_addr; | |
2407 | ||
b481de9c | 2408 | /* Tell bootstrap uCode where to find image to load */ |
5d49f498 AK |
2409 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
2410 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
2411 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
2412 | priv->ucode_data.len); |
2413 | ||
a96a27f9 | 2414 | /* Inst byte count must be last to set up, bit 31 signals uCode |
b481de9c | 2415 | * that all new ptr/size info is in place */ |
5d49f498 | 2416 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
2417 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
2418 | ||
e1623446 | 2419 | IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n"); |
b481de9c | 2420 | |
a8b50a0a | 2421 | return 0; |
b481de9c ZY |
2422 | } |
2423 | ||
2424 | /** | |
bb8c093b | 2425 | * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
2426 | * |
2427 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
2428 | * | |
b481de9c | 2429 | * Tell "initialize" uCode to go ahead and load the runtime uCode. |
9fbab516 | 2430 | */ |
4a8a4322 | 2431 | static void iwl3945_init_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
2432 | { |
2433 | /* Check alive response for "valid" sign from uCode */ | |
2434 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
2435 | /* We had an error bringing up the hardware, so take it | |
2436 | * all the way back down so we can try again */ | |
e1623446 | 2437 | IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); |
b481de9c ZY |
2438 | goto restart; |
2439 | } | |
2440 | ||
2441 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
2442 | * This is a paranoid check, because we would not have gotten the | |
2443 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 2444 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2445 | /* Runtime instruction load was bad; |
2446 | * take it all the way back down so we can try again */ | |
e1623446 | 2447 | IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); |
b481de9c ZY |
2448 | goto restart; |
2449 | } | |
2450 | ||
2451 | /* Send pointers to protocol/runtime uCode image ... init code will | |
2452 | * load and launch runtime uCode, which will send us another "Alive" | |
2453 | * notification. */ | |
e1623446 | 2454 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
bb8c093b | 2455 | if (iwl3945_set_ucode_ptrs(priv)) { |
b481de9c ZY |
2456 | /* Runtime instruction load won't happen; |
2457 | * take it all the way back down so we can try again */ | |
e1623446 | 2458 | IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n"); |
b481de9c ZY |
2459 | goto restart; |
2460 | } | |
2461 | return; | |
2462 | ||
2463 | restart: | |
2464 | queue_work(priv->workqueue, &priv->restart); | |
2465 | } | |
2466 | ||
b481de9c | 2467 | /** |
bb8c093b | 2468 | * iwl3945_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2469 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 2470 | * Alive gets handled by iwl3945_init_alive_start()). |
b481de9c | 2471 | */ |
4a8a4322 | 2472 | static void iwl3945_alive_start(struct iwl_priv *priv) |
b481de9c | 2473 | { |
b481de9c ZY |
2474 | int thermal_spin = 0; |
2475 | u32 rfkill; | |
246ed355 | 2476 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c | 2477 | |
e1623446 | 2478 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
2479 | |
2480 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
2481 | /* We had an error bringing up the hardware, so take it | |
2482 | * all the way back down so we can try again */ | |
e1623446 | 2483 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
2484 | goto restart; |
2485 | } | |
2486 | ||
2487 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2488 | * This is a paranoid check, because we would not have gotten the | |
2489 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 2490 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2491 | /* Runtime instruction load was bad; |
2492 | * take it all the way back down so we can try again */ | |
e1623446 | 2493 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2494 | goto restart; |
2495 | } | |
2496 | ||
5d49f498 | 2497 | rfkill = iwl_read_prph(priv, APMG_RFKILL_REG); |
e1623446 | 2498 | IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill); |
b481de9c ZY |
2499 | |
2500 | if (rfkill & 0x1) { | |
2501 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a96a27f9 | 2502 | /* if RFKILL is not on, then wait for thermal |
b481de9c | 2503 | * sensor in adapter to kick in */ |
bb8c093b | 2504 | while (iwl3945_hw_get_temperature(priv) == 0) { |
b481de9c ZY |
2505 | thermal_spin++; |
2506 | udelay(10); | |
2507 | } | |
2508 | ||
2509 | if (thermal_spin) | |
e1623446 | 2510 | IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n", |
b481de9c ZY |
2511 | thermal_spin * 10); |
2512 | } else | |
2513 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2514 | ||
9fbab516 | 2515 | /* After the ALIVE response, we can send commands to 3945 uCode */ |
b481de9c ZY |
2516 | set_bit(STATUS_ALIVE, &priv->status); |
2517 | ||
b74e31a9 WYG |
2518 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
2519 | /* Enable timer to monitor the driver queues */ | |
2520 | mod_timer(&priv->monitor_recover, | |
2521 | jiffies + | |
2522 | msecs_to_jiffies(priv->cfg->monitor_recover_period)); | |
2523 | } | |
2524 | ||
775a6e27 | 2525 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2526 | return; |
2527 | ||
36d6825b | 2528 | ieee80211_wake_queues(priv->hw); |
b481de9c | 2529 | |
470ab2dd | 2530 | priv->active_rate = IWL_RATES_MASK; |
b481de9c | 2531 | |
4d6ccbf5 | 2532 | iwl_power_update_mode(priv, true); |
b481de9c | 2533 | |
246ed355 | 2534 | if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) { |
bb8c093b | 2535 | struct iwl3945_rxon_cmd *active_rxon = |
246ed355 | 2536 | (struct iwl3945_rxon_cmd *)(&ctx->active); |
b481de9c | 2537 | |
246ed355 | 2538 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c ZY |
2539 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2540 | } else { | |
2541 | /* Initialize our rx_config data */ | |
d0fe478c | 2542 | iwl_connection_init_rx_config(priv, ctx); |
b481de9c ZY |
2543 | } |
2544 | ||
9fbab516 | 2545 | /* Configure Bluetooth device coexistence support */ |
65b52bde | 2546 | priv->cfg->ops->hcmd->send_bt_config(priv); |
b481de9c ZY |
2547 | |
2548 | /* Configure the adapter for unassociated operation */ | |
246ed355 | 2549 | iwlcore_commit_rxon(priv, ctx); |
b481de9c | 2550 | |
b481de9c ZY |
2551 | iwl3945_reg_txpower_periodic(priv); |
2552 | ||
e932a609 | 2553 | iwl_leds_init(priv); |
fe00b5a5 | 2554 | |
e1623446 | 2555 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 2556 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 2557 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2558 | |
b481de9c ZY |
2559 | return; |
2560 | ||
2561 | restart: | |
2562 | queue_work(priv->workqueue, &priv->restart); | |
2563 | } | |
2564 | ||
4a8a4322 | 2565 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2566 | |
4a8a4322 | 2567 | static void __iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2568 | { |
2569 | unsigned long flags; | |
d745d472 | 2570 | int exit_pending; |
b481de9c | 2571 | |
e1623446 | 2572 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 2573 | |
d745d472 SG |
2574 | iwl_scan_cancel_timeout(priv, 200); |
2575 | ||
2576 | exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 2577 | |
b62177a0 SG |
2578 | /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set |
2579 | * to prevent rearm timer */ | |
2580 | if (priv->cfg->ops->lib->recover_from_tx_stall) | |
2581 | del_timer_sync(&priv->monitor_recover); | |
2582 | ||
7e246191 | 2583 | /* Station information will now be cleared in device */ |
dcef732c | 2584 | iwl_clear_ucode_stations(priv, NULL); |
a194e324 | 2585 | iwl_dealloc_bcast_stations(priv); |
db125c78 | 2586 | iwl_clear_driver_stations(priv); |
b481de9c ZY |
2587 | |
2588 | /* Unblock any waiting calls */ | |
2589 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2590 | ||
b481de9c ZY |
2591 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2592 | * exiting the module */ | |
2593 | if (!exit_pending) | |
2594 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2595 | ||
2596 | /* stop and reset the on-board processor */ | |
5d49f498 | 2597 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2598 | |
2599 | /* tell the device to stop sending interrupts */ | |
0359facc | 2600 | spin_lock_irqsave(&priv->lock, flags); |
ed3b932e | 2601 | iwl_disable_interrupts(priv); |
0359facc MA |
2602 | spin_unlock_irqrestore(&priv->lock, flags); |
2603 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2604 | |
2605 | if (priv->mac80211_registered) | |
2606 | ieee80211_stop_queues(priv->hw); | |
2607 | ||
bb8c093b | 2608 | /* If we have not previously called iwl3945_init() then |
6da3a13e | 2609 | * clear all bits but the RF Kill bits and return */ |
775a6e27 | 2610 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2611 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2612 | STATUS_RF_KILL_HW | | |
9788864e RC |
2613 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2614 | STATUS_GEO_CONFIGURED | | |
ebef2008 AK |
2615 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2616 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2617 | goto exit; |
2618 | } | |
2619 | ||
6da3a13e | 2620 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2621 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2622 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2623 | STATUS_RF_KILL_HW | | |
9788864e RC |
2624 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2625 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2626 | test_bit(STATUS_FW_ERROR, &priv->status) << |
ebef2008 AK |
2627 | STATUS_FW_ERROR | |
2628 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2629 | STATUS_EXIT_PENDING; | |
b481de9c | 2630 | |
bb8c093b CH |
2631 | iwl3945_hw_txq_ctx_stop(priv); |
2632 | iwl3945_hw_rxq_stop(priv); | |
b481de9c | 2633 | |
309e731a BC |
2634 | /* Power-down device's busmaster DMA clocks */ |
2635 | iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2636 | udelay(5); |
2637 | ||
4d2ccdb9 BC |
2638 | /* Stop the device, and put it in low power state */ |
2639 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
e9414b6b | 2640 | |
b481de9c | 2641 | exit: |
3d24a9f7 | 2642 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
2643 | |
2644 | if (priv->ibss_beacon) | |
2645 | dev_kfree_skb(priv->ibss_beacon); | |
2646 | priv->ibss_beacon = NULL; | |
2647 | ||
2648 | /* clear out any free frames */ | |
bb8c093b | 2649 | iwl3945_clear_free_frames(priv); |
b481de9c ZY |
2650 | } |
2651 | ||
4a8a4322 | 2652 | static void iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2653 | { |
2654 | mutex_lock(&priv->mutex); | |
bb8c093b | 2655 | __iwl3945_down(priv); |
b481de9c | 2656 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2657 | |
bb8c093b | 2658 | iwl3945_cancel_deferred_work(priv); |
b481de9c ZY |
2659 | } |
2660 | ||
2661 | #define MAX_HW_RESTARTS 5 | |
2662 | ||
4a8a4322 | 2663 | static int __iwl3945_up(struct iwl_priv *priv) |
b481de9c ZY |
2664 | { |
2665 | int rc, i; | |
2666 | ||
a194e324 JB |
2667 | rc = iwl_alloc_bcast_station(priv, &priv->contexts[IWL_RXON_CTX_BSS], |
2668 | false); | |
2c810ccd JB |
2669 | if (rc) |
2670 | return rc; | |
2671 | ||
b481de9c | 2672 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { |
39aadf8c | 2673 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2674 | return -EIO; |
2675 | } | |
2676 | ||
e903fbd4 | 2677 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2678 | IWL_ERR(priv, "ucode not available for device bring up\n"); |
e903fbd4 RC |
2679 | return -EIO; |
2680 | } | |
2681 | ||
e655b9f0 | 2682 | /* If platform's RF_KILL switch is NOT set to KILL */ |
5d49f498 | 2683 | if (iwl_read32(priv, CSR_GP_CNTRL) & |
e655b9f0 ZY |
2684 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
2685 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2686 | else { | |
2687 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6da3a13e WYG |
2688 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
2689 | return -ENODEV; | |
b481de9c | 2690 | } |
80fcc9e2 | 2691 | |
5d49f498 | 2692 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2693 | |
bb8c093b | 2694 | rc = iwl3945_hw_nic_init(priv); |
b481de9c | 2695 | if (rc) { |
15b1687c | 2696 | IWL_ERR(priv, "Unable to int nic\n"); |
b481de9c ZY |
2697 | return rc; |
2698 | } | |
2699 | ||
2700 | /* make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2701 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2702 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2703 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2704 | ||
2705 | /* clear (again), then enable host interrupts */ | |
5d49f498 | 2706 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
ed3b932e | 2707 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2708 | |
2709 | /* really make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2710 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2711 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2712 | |
2713 | /* Copy original ucode data image from disk into backup cache. | |
2714 | * This will be used to initialize the on-board processor's | |
2715 | * data SRAM for a clean start when the runtime program first loads. */ | |
2716 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2717 | priv->ucode_data.len); |
b481de9c | 2718 | |
e655b9f0 ZY |
2719 | /* We return success when we resume from suspend and rf_kill is on. */ |
2720 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
2721 | return 0; | |
2722 | ||
b481de9c ZY |
2723 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2724 | ||
b481de9c ZY |
2725 | /* load bootstrap state machine, |
2726 | * load bootstrap program into processor's memory, | |
2727 | * prepare to load the "initialize" uCode */ | |
75a9a926 | 2728 | rc = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c ZY |
2729 | |
2730 | if (rc) { | |
15b1687c WT |
2731 | IWL_ERR(priv, |
2732 | "Unable to set up bootstrap uCode: %d\n", rc); | |
b481de9c ZY |
2733 | continue; |
2734 | } | |
2735 | ||
2736 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 2737 | iwl3945_nic_start(priv); |
b481de9c | 2738 | |
e1623446 | 2739 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2740 | |
2741 | return 0; | |
2742 | } | |
2743 | ||
2744 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 2745 | __iwl3945_down(priv); |
ebef2008 | 2746 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2747 | |
2748 | /* tried to restart and config the device for as long as our | |
2749 | * patience could withstand */ | |
15b1687c | 2750 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2751 | return -EIO; |
2752 | } | |
2753 | ||
2754 | ||
2755 | /***************************************************************************** | |
2756 | * | |
2757 | * Workqueue callbacks | |
2758 | * | |
2759 | *****************************************************************************/ | |
2760 | ||
bb8c093b | 2761 | static void iwl3945_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2762 | { |
4a8a4322 AK |
2763 | struct iwl_priv *priv = |
2764 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2765 | |
2766 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2767 | return; | |
2768 | ||
2769 | mutex_lock(&priv->mutex); | |
bb8c093b | 2770 | iwl3945_init_alive_start(priv); |
b481de9c ZY |
2771 | mutex_unlock(&priv->mutex); |
2772 | } | |
2773 | ||
bb8c093b | 2774 | static void iwl3945_bg_alive_start(struct work_struct *data) |
b481de9c | 2775 | { |
4a8a4322 AK |
2776 | struct iwl_priv *priv = |
2777 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2778 | |
2779 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2780 | return; | |
2781 | ||
2782 | mutex_lock(&priv->mutex); | |
bb8c093b | 2783 | iwl3945_alive_start(priv); |
b481de9c ZY |
2784 | mutex_unlock(&priv->mutex); |
2785 | } | |
2786 | ||
743cdf1b BC |
2787 | /* |
2788 | * 3945 cannot interrupt driver when hardware rf kill switch toggles; | |
2789 | * driver must poll CSR_GP_CNTRL_REG register for change. This register | |
2790 | * *is* readable even when device has been SW_RESET into low power mode | |
2791 | * (e.g. during RF KILL). | |
2792 | */ | |
2663516d HS |
2793 | static void iwl3945_rfkill_poll(struct work_struct *data) |
2794 | { | |
2795 | struct iwl_priv *priv = | |
ee525d13 | 2796 | container_of(data, struct iwl_priv, _3945.rfkill_poll.work); |
743cdf1b BC |
2797 | bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status); |
2798 | bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL) | |
2799 | & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | |
2663516d | 2800 | |
743cdf1b BC |
2801 | if (new_rfkill != old_rfkill) { |
2802 | if (new_rfkill) | |
2803 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2804 | else | |
2805 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2663516d | 2806 | |
743cdf1b BC |
2807 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill); |
2808 | ||
2809 | IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n", | |
2810 | new_rfkill ? "disable radio" : "enable radio"); | |
2811 | } | |
2663516d | 2812 | |
743cdf1b BC |
2813 | /* Keep this running, even if radio now enabled. This will be |
2814 | * cancelled in mac_start() if system decides to start again */ | |
ee525d13 | 2815 | queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll, |
2663516d HS |
2816 | round_jiffies_relative(2 * HZ)); |
2817 | ||
2818 | } | |
2819 | ||
3eecce52 | 2820 | int iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c | 2821 | { |
c2d79b48 | 2822 | struct iwl_host_cmd cmd = { |
b481de9c | 2823 | .id = REPLY_SCAN_CMD, |
bb8c093b | 2824 | .len = sizeof(struct iwl3945_scan_cmd), |
c2acea8e | 2825 | .flags = CMD_SIZE_HUGE, |
b481de9c | 2826 | }; |
bb8c093b | 2827 | struct iwl3945_scan_cmd *scan; |
1ecf9fc1 | 2828 | u8 n_probes = 0; |
8318d78a | 2829 | enum ieee80211_band band; |
1ecf9fc1 | 2830 | bool is_active = false; |
3eecce52 | 2831 | int ret; |
b481de9c | 2832 | |
3eecce52 | 2833 | lockdep_assert_held(&priv->mutex); |
b481de9c | 2834 | |
811ecc99 JB |
2835 | if (!priv->scan_cmd) { |
2836 | priv->scan_cmd = kmalloc(sizeof(struct iwl3945_scan_cmd) + | |
2837 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); | |
2838 | if (!priv->scan_cmd) { | |
4f4d4088 | 2839 | IWL_DEBUG_SCAN(priv, "Fail to allocate scan memory\n"); |
3eecce52 | 2840 | return -ENOMEM; |
b481de9c ZY |
2841 | } |
2842 | } | |
811ecc99 | 2843 | scan = priv->scan_cmd; |
bb8c093b | 2844 | memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
2845 | |
2846 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
2847 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
2848 | ||
246ed355 | 2849 | if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) { |
b481de9c ZY |
2850 | u16 interval = 0; |
2851 | u32 extra; | |
2852 | u32 suspend_time = 100; | |
2853 | u32 scan_suspend_time = 100; | |
2854 | unsigned long flags; | |
2855 | ||
e1623446 | 2856 | IWL_DEBUG_INFO(priv, "Scanning while associated...\n"); |
b481de9c ZY |
2857 | |
2858 | spin_lock_irqsave(&priv->lock, flags); | |
a6e492b9 JL |
2859 | if (priv->is_internal_short_scan) |
2860 | interval = 0; | |
2861 | else | |
2862 | interval = vif->bss_conf.beacon_int; | |
b481de9c ZY |
2863 | spin_unlock_irqrestore(&priv->lock, flags); |
2864 | ||
2865 | scan->suspend_time = 0; | |
15e869d8 | 2866 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
2867 | if (!interval) |
2868 | interval = suspend_time; | |
2869 | /* | |
2870 | * suspend time format: | |
2871 | * 0-19: beacon interval in usec (time before exec.) | |
2872 | * 20-23: 0 | |
2873 | * 24-31: number of beacons (suspend between channels) | |
2874 | */ | |
2875 | ||
2876 | extra = (suspend_time / interval) << 24; | |
2877 | scan_suspend_time = 0xFF0FFFFF & | |
2878 | (extra | ((suspend_time % interval) * 1024)); | |
2879 | ||
2880 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
e1623446 | 2881 | IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n", |
b481de9c ZY |
2882 | scan_suspend_time, interval); |
2883 | } | |
2884 | ||
4f4d4088 WYG |
2885 | if (priv->is_internal_short_scan) { |
2886 | IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n"); | |
2887 | } else if (priv->scan_request->n_ssids) { | |
1ecf9fc1 JB |
2888 | int i, p = 0; |
2889 | IWL_DEBUG_SCAN(priv, "Kicking off active scan\n"); | |
2890 | for (i = 0; i < priv->scan_request->n_ssids; i++) { | |
2891 | /* always does wildcard anyway */ | |
2892 | if (!priv->scan_request->ssids[i].ssid_len) | |
2893 | continue; | |
2894 | scan->direct_scan[p].id = WLAN_EID_SSID; | |
2895 | scan->direct_scan[p].len = | |
2896 | priv->scan_request->ssids[i].ssid_len; | |
2897 | memcpy(scan->direct_scan[p].ssid, | |
2898 | priv->scan_request->ssids[i].ssid, | |
2899 | priv->scan_request->ssids[i].ssid_len); | |
2900 | n_probes++; | |
2901 | p++; | |
2902 | } | |
2903 | is_active = true; | |
f9340520 | 2904 | } else |
1ecf9fc1 | 2905 | IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n"); |
b481de9c ZY |
2906 | |
2907 | /* We don't build a direct scan probe request; the uCode will do | |
2908 | * that based on the direct_mask added to each channel entry */ | |
b481de9c | 2909 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
a194e324 | 2910 | scan->tx_cmd.sta_id = priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id; |
b481de9c ZY |
2911 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
2912 | ||
2913 | /* flags + rate selection */ | |
2914 | ||
00700ee0 JB |
2915 | switch (priv->scan_band) { |
2916 | case IEEE80211_BAND_2GHZ: | |
b481de9c ZY |
2917 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; |
2918 | scan->tx_cmd.rate = IWL_RATE_1M_PLCP; | |
2919 | scan->good_CRC_th = 0; | |
8318d78a | 2920 | band = IEEE80211_BAND_2GHZ; |
00700ee0 JB |
2921 | break; |
2922 | case IEEE80211_BAND_5GHZ: | |
b481de9c | 2923 | scan->tx_cmd.rate = IWL_RATE_6M_PLCP; |
b097ad29 JB |
2924 | /* |
2925 | * If active scaning is requested but a certain channel | |
2926 | * is marked passive, we can do active scanning if we | |
2927 | * detect transmissions. | |
2928 | */ | |
96ff5641 JB |
2929 | scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT : |
2930 | IWL_GOOD_CRC_TH_DISABLED; | |
8318d78a | 2931 | band = IEEE80211_BAND_5GHZ; |
00700ee0 JB |
2932 | break; |
2933 | default: | |
2934 | IWL_WARN(priv, "Invalid scan band\n"); | |
3eecce52 | 2935 | return -EIO; |
b481de9c ZY |
2936 | } |
2937 | ||
4f4d4088 WYG |
2938 | if (!priv->is_internal_short_scan) { |
2939 | scan->tx_cmd.len = cpu_to_le16( | |
1ecf9fc1 JB |
2940 | iwl_fill_probe_req(priv, |
2941 | (struct ieee80211_mgmt *)scan->data, | |
3a0b9aad | 2942 | vif->addr, |
1ecf9fc1 JB |
2943 | priv->scan_request->ie, |
2944 | priv->scan_request->ie_len, | |
2945 | IWL_MAX_SCAN_SIZE - sizeof(*scan))); | |
4f4d4088 | 2946 | } else { |
3a0b9aad | 2947 | /* use bcast addr, will not be transmitted but must be valid */ |
4f4d4088 WYG |
2948 | scan->tx_cmd.len = cpu_to_le16( |
2949 | iwl_fill_probe_req(priv, | |
2950 | (struct ieee80211_mgmt *)scan->data, | |
3a0b9aad | 2951 | iwl_bcast_addr, NULL, 0, |
4f4d4088 WYG |
2952 | IWL_MAX_SCAN_SIZE - sizeof(*scan))); |
2953 | } | |
b481de9c ZY |
2954 | /* select Rx antennas */ |
2955 | scan->flags |= iwl3945_get_antenna_flags(priv); | |
2956 | ||
14023641 AK |
2957 | if (priv->is_internal_short_scan) { |
2958 | scan->channel_count = | |
2959 | iwl3945_get_single_channel_for_scan(priv, vif, band, | |
2960 | (void *)&scan->data[le16_to_cpu( | |
2961 | scan->tx_cmd.len)]); | |
2962 | } else { | |
2963 | scan->channel_count = | |
2964 | iwl3945_get_channels_for_scan(priv, band, is_active, n_probes, | |
2965 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)], vif); | |
2966 | } | |
b481de9c | 2967 | |
14b54336 | 2968 | if (scan->channel_count == 0) { |
e1623446 | 2969 | IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count); |
3eecce52 | 2970 | return -EIO; |
14b54336 RC |
2971 | } |
2972 | ||
b481de9c | 2973 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + |
bb8c093b | 2974 | scan->channel_count * sizeof(struct iwl3945_scan_channel); |
b481de9c ZY |
2975 | cmd.data = scan; |
2976 | scan->len = cpu_to_le16(cmd.len); | |
2977 | ||
2978 | set_bit(STATUS_SCAN_HW, &priv->status); | |
3eecce52 JB |
2979 | ret = iwl_send_cmd_sync(priv, &cmd); |
2980 | if (ret) | |
2981 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
2982 | return ret; | |
b481de9c ZY |
2983 | } |
2984 | ||
bb8c093b | 2985 | static void iwl3945_bg_restart(struct work_struct *data) |
b481de9c | 2986 | { |
4a8a4322 | 2987 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2988 | |
2989 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2990 | return; | |
2991 | ||
19cc1087 | 2992 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
8bd413e6 | 2993 | struct iwl_rxon_context *ctx; |
19cc1087 | 2994 | mutex_lock(&priv->mutex); |
8bd413e6 JB |
2995 | for_each_context(priv, ctx) |
2996 | ctx->vif = NULL; | |
19cc1087 JB |
2997 | priv->is_open = 0; |
2998 | mutex_unlock(&priv->mutex); | |
2999 | iwl3945_down(priv); | |
3000 | ieee80211_restart_hw(priv->hw); | |
3001 | } else { | |
3002 | iwl3945_down(priv); | |
80676518 JB |
3003 | |
3004 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3005 | return; | |
3006 | ||
3007 | mutex_lock(&priv->mutex); | |
3008 | __iwl3945_up(priv); | |
3009 | mutex_unlock(&priv->mutex); | |
19cc1087 | 3010 | } |
b481de9c ZY |
3011 | } |
3012 | ||
bb8c093b | 3013 | static void iwl3945_bg_rx_replenish(struct work_struct *data) |
b481de9c | 3014 | { |
4a8a4322 AK |
3015 | struct iwl_priv *priv = |
3016 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
3017 | |
3018 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3019 | return; | |
3020 | ||
3021 | mutex_lock(&priv->mutex); | |
bb8c093b | 3022 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
3023 | mutex_unlock(&priv->mutex); |
3024 | } | |
3025 | ||
1dda6d28 | 3026 | void iwl3945_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c | 3027 | { |
b481de9c ZY |
3028 | int rc = 0; |
3029 | struct ieee80211_conf *conf = NULL; | |
246ed355 | 3030 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c | 3031 | |
1dda6d28 JB |
3032 | if (!vif || !priv->is_open) |
3033 | return; | |
3034 | ||
3035 | if (vif->type == NL80211_IFTYPE_AP) { | |
15b1687c | 3036 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
3037 | return; |
3038 | } | |
3039 | ||
e1623446 | 3040 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
246ed355 | 3041 | vif->bss_conf.aid, ctx->active.bssid_addr); |
b481de9c ZY |
3042 | |
3043 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3044 | return; | |
3045 | ||
af0053d6 | 3046 | iwl_scan_cancel_timeout(priv, 200); |
15e869d8 | 3047 | |
b481de9c ZY |
3048 | conf = ieee80211_get_hw_conf(priv->hw); |
3049 | ||
246ed355 JB |
3050 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
3051 | iwlcore_commit_rxon(priv, ctx); | |
b481de9c | 3052 | |
47313e34 | 3053 | rc = iwl_send_rxon_timing(priv, ctx); |
b481de9c | 3054 | if (rc) |
39aadf8c | 3055 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3056 | "Attempting to continue.\n"); |
3057 | ||
246ed355 | 3058 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c | 3059 | |
246ed355 | 3060 | ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid); |
b481de9c | 3061 | |
e1623446 | 3062 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
1dda6d28 | 3063 | vif->bss_conf.aid, vif->bss_conf.beacon_int); |
b481de9c | 3064 | |
c213d745 | 3065 | if (vif->bss_conf.use_short_preamble) |
246ed355 | 3066 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3067 | else |
246ed355 | 3068 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3069 | |
246ed355 | 3070 | if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) { |
c213d745 | 3071 | if (vif->bss_conf.use_short_slot) |
246ed355 | 3072 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3073 | else |
246ed355 | 3074 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
3075 | } |
3076 | ||
246ed355 | 3077 | iwlcore_commit_rxon(priv, ctx); |
b481de9c | 3078 | |
1dda6d28 | 3079 | switch (vif->type) { |
05c914fe | 3080 | case NL80211_IFTYPE_STATION: |
bb8c093b | 3081 | iwl3945_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c | 3082 | break; |
05c914fe | 3083 | case NL80211_IFTYPE_ADHOC: |
bb8c093b | 3084 | iwl3945_send_beacon_cmd(priv); |
b481de9c | 3085 | break; |
b481de9c | 3086 | default: |
1dda6d28 JB |
3087 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3088 | __func__, vif->type); | |
b481de9c ZY |
3089 | break; |
3090 | } | |
cd56d331 AK |
3091 | } |
3092 | ||
b481de9c ZY |
3093 | /***************************************************************************** |
3094 | * | |
3095 | * mac80211 entry point functions | |
3096 | * | |
3097 | *****************************************************************************/ | |
3098 | ||
5a66926a ZY |
3099 | #define UCODE_READY_TIMEOUT (2 * HZ) |
3100 | ||
bb8c093b | 3101 | static int iwl3945_mac_start(struct ieee80211_hw *hw) |
b481de9c | 3102 | { |
4a8a4322 | 3103 | struct iwl_priv *priv = hw->priv; |
5a66926a | 3104 | int ret; |
b481de9c | 3105 | |
e1623446 | 3106 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
3107 | |
3108 | /* we should be verifying the device is ready to be opened */ | |
3109 | mutex_lock(&priv->mutex); | |
3110 | ||
5a66926a ZY |
3111 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
3112 | * ucode filename and max sizes are card-specific. */ | |
3113 | ||
3114 | if (!priv->ucode_code.len) { | |
3115 | ret = iwl3945_read_ucode(priv); | |
3116 | if (ret) { | |
15b1687c | 3117 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a ZY |
3118 | mutex_unlock(&priv->mutex); |
3119 | goto out_release_irq; | |
3120 | } | |
3121 | } | |
b481de9c | 3122 | |
e655b9f0 | 3123 | ret = __iwl3945_up(priv); |
b481de9c ZY |
3124 | |
3125 | mutex_unlock(&priv->mutex); | |
5a66926a | 3126 | |
e655b9f0 ZY |
3127 | if (ret) |
3128 | goto out_release_irq; | |
3129 | ||
e1623446 | 3130 | IWL_DEBUG_INFO(priv, "Start UP work.\n"); |
e655b9f0 | 3131 | |
5a66926a ZY |
3132 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
3133 | * mac80211 will not be run successfully. */ | |
3134 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
3135 | test_bit(STATUS_READY, &priv->status), | |
3136 | UCODE_READY_TIMEOUT); | |
3137 | if (!ret) { | |
3138 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c WT |
3139 | IWL_ERR(priv, |
3140 | "Wait for START_ALIVE timeout after %dms.\n", | |
3141 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
5a66926a ZY |
3142 | ret = -ETIMEDOUT; |
3143 | goto out_release_irq; | |
3144 | } | |
3145 | } | |
3146 | ||
2663516d HS |
3147 | /* ucode is running and will send rfkill notifications, |
3148 | * no need to poll the killswitch state anymore */ | |
ee525d13 | 3149 | cancel_delayed_work(&priv->_3945.rfkill_poll); |
2663516d | 3150 | |
e932a609 JB |
3151 | iwl_led_start(priv); |
3152 | ||
e655b9f0 | 3153 | priv->is_open = 1; |
e1623446 | 3154 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3155 | return 0; |
5a66926a ZY |
3156 | |
3157 | out_release_irq: | |
e655b9f0 | 3158 | priv->is_open = 0; |
e1623446 | 3159 | IWL_DEBUG_MAC80211(priv, "leave - failed\n"); |
5a66926a | 3160 | return ret; |
b481de9c ZY |
3161 | } |
3162 | ||
bb8c093b | 3163 | static void iwl3945_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 3164 | { |
4a8a4322 | 3165 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3166 | |
e1623446 | 3167 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
6ef89d0a | 3168 | |
e655b9f0 | 3169 | if (!priv->is_open) { |
e1623446 | 3170 | IWL_DEBUG_MAC80211(priv, "leave - skip\n"); |
e655b9f0 ZY |
3171 | return; |
3172 | } | |
3173 | ||
b481de9c | 3174 | priv->is_open = 0; |
5a66926a | 3175 | |
5a66926a ZY |
3176 | iwl3945_down(priv); |
3177 | ||
3178 | flush_workqueue(priv->workqueue); | |
2663516d HS |
3179 | |
3180 | /* start polling the killswitch state again */ | |
ee525d13 | 3181 | queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll, |
2663516d | 3182 | round_jiffies_relative(2 * HZ)); |
6ef89d0a | 3183 | |
e1623446 | 3184 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3185 | } |
3186 | ||
e039fa4a | 3187 | static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 3188 | { |
4a8a4322 | 3189 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3190 | |
e1623446 | 3191 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3192 | |
e1623446 | 3193 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 3194 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 3195 | |
e039fa4a | 3196 | if (iwl3945_tx_skb(priv, skb)) |
b481de9c ZY |
3197 | dev_kfree_skb_any(skb); |
3198 | ||
e1623446 | 3199 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
637f8837 | 3200 | return NETDEV_TX_OK; |
b481de9c ZY |
3201 | } |
3202 | ||
1dda6d28 | 3203 | void iwl3945_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c | 3204 | { |
246ed355 | 3205 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c ZY |
3206 | int rc = 0; |
3207 | ||
d986bcd1 | 3208 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
3209 | return; |
3210 | ||
3211 | /* The following should be done only at AP bring up */ | |
246ed355 | 3212 | if (!(iwl_is_associated(priv, IWL_RXON_CTX_BSS))) { |
b481de9c ZY |
3213 | |
3214 | /* RXON - unassoc (to set timing command) */ | |
246ed355 JB |
3215 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
3216 | iwlcore_commit_rxon(priv, ctx); | |
b481de9c ZY |
3217 | |
3218 | /* RXON Timing */ | |
47313e34 | 3219 | rc = iwl_send_rxon_timing(priv, ctx); |
b481de9c | 3220 | if (rc) |
39aadf8c | 3221 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3222 | "Attempting to continue.\n"); |
3223 | ||
246ed355 | 3224 | ctx->staging.assoc_id = 0; |
1dda6d28 | 3225 | |
c213d745 | 3226 | if (vif->bss_conf.use_short_preamble) |
246ed355 | 3227 | ctx->staging.flags |= |
b481de9c ZY |
3228 | RXON_FLG_SHORT_PREAMBLE_MSK; |
3229 | else | |
246ed355 | 3230 | ctx->staging.flags &= |
b481de9c ZY |
3231 | ~RXON_FLG_SHORT_PREAMBLE_MSK; |
3232 | ||
246ed355 | 3233 | if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) { |
c213d745 | 3234 | if (vif->bss_conf.use_short_slot) |
246ed355 | 3235 | ctx->staging.flags |= |
b481de9c ZY |
3236 | RXON_FLG_SHORT_SLOT_MSK; |
3237 | else | |
246ed355 | 3238 | ctx->staging.flags &= |
b481de9c | 3239 | ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
3240 | } |
3241 | /* restore RXON assoc */ | |
246ed355 JB |
3242 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
3243 | iwlcore_commit_rxon(priv, ctx); | |
556f8db7 | 3244 | } |
bb8c093b | 3245 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
3246 | |
3247 | /* FIXME - we need to add code here to detect a totally new | |
3248 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
3249 | * clear sta table, add BCAST sta... */ | |
3250 | } | |
3251 | ||
bb8c093b | 3252 | static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
3253 | struct ieee80211_vif *vif, |
3254 | struct ieee80211_sta *sta, | |
3255 | struct ieee80211_key_conf *key) | |
b481de9c | 3256 | { |
4a8a4322 | 3257 | struct iwl_priv *priv = hw->priv; |
6e21f15c AK |
3258 | int ret = 0; |
3259 | u8 sta_id = IWL_INVALID_STATION; | |
3260 | u8 static_key; | |
b481de9c | 3261 | |
e1623446 | 3262 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3263 | |
df878d8f | 3264 | if (iwl3945_mod_params.sw_crypto) { |
e1623446 | 3265 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
3266 | return -EOPNOTSUPP; |
3267 | } | |
3268 | ||
246ed355 | 3269 | static_key = !iwl_is_associated(priv, IWL_RXON_CTX_BSS); |
6e21f15c AK |
3270 | |
3271 | if (!static_key) { | |
a194e324 JB |
3272 | sta_id = iwl_sta_id_or_broadcast( |
3273 | priv, &priv->contexts[IWL_RXON_CTX_BSS], sta); | |
0af8bcae JB |
3274 | if (sta_id == IWL_INVALID_STATION) |
3275 | return -EINVAL; | |
b481de9c ZY |
3276 | } |
3277 | ||
3278 | mutex_lock(&priv->mutex); | |
af0053d6 | 3279 | iwl_scan_cancel_timeout(priv, 100); |
15e869d8 | 3280 | |
b481de9c | 3281 | switch (cmd) { |
6e21f15c AK |
3282 | case SET_KEY: |
3283 | if (static_key) | |
3284 | ret = iwl3945_set_static_key(priv, key); | |
3285 | else | |
3286 | ret = iwl3945_set_dynamic_key(priv, key, sta_id); | |
3287 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); | |
b481de9c ZY |
3288 | break; |
3289 | case DISABLE_KEY: | |
6e21f15c AK |
3290 | if (static_key) |
3291 | ret = iwl3945_remove_static_key(priv); | |
3292 | else | |
3293 | ret = iwl3945_clear_sta_key_info(priv, sta_id); | |
3294 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); | |
b481de9c ZY |
3295 | break; |
3296 | default: | |
42986796 | 3297 | ret = -EINVAL; |
b481de9c ZY |
3298 | } |
3299 | ||
72e15d71 | 3300 | mutex_unlock(&priv->mutex); |
e1623446 | 3301 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3302 | |
42986796 | 3303 | return ret; |
b481de9c ZY |
3304 | } |
3305 | ||
fe6b23dd RC |
3306 | static int iwl3945_mac_sta_add(struct ieee80211_hw *hw, |
3307 | struct ieee80211_vif *vif, | |
3308 | struct ieee80211_sta *sta) | |
3309 | { | |
3310 | struct iwl_priv *priv = hw->priv; | |
fd1af15d | 3311 | struct iwl3945_sta_priv *sta_priv = (void *)sta->drv_priv; |
fe6b23dd | 3312 | int ret; |
fd1af15d | 3313 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; |
fe6b23dd RC |
3314 | u8 sta_id; |
3315 | ||
3316 | IWL_DEBUG_INFO(priv, "received request to add station %pM\n", | |
3317 | sta->addr); | |
da5ae1cf RC |
3318 | mutex_lock(&priv->mutex); |
3319 | IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n", | |
3320 | sta->addr); | |
3321 | sta_priv->common.sta_id = IWL_INVALID_STATION; | |
3322 | ||
fe6b23dd | 3323 | |
a194e324 | 3324 | ret = iwl_add_station_common(priv, &priv->contexts[IWL_RXON_CTX_BSS], |
238d781d | 3325 | sta->addr, is_ap, sta, &sta_id); |
fe6b23dd RC |
3326 | if (ret) { |
3327 | IWL_ERR(priv, "Unable to add station %pM (%d)\n", | |
3328 | sta->addr, ret); | |
3329 | /* Should we return success if return code is EEXIST ? */ | |
da5ae1cf | 3330 | mutex_unlock(&priv->mutex); |
fe6b23dd RC |
3331 | return ret; |
3332 | } | |
3333 | ||
fd1af15d JB |
3334 | sta_priv->common.sta_id = sta_id; |
3335 | ||
fe6b23dd | 3336 | /* Initialize rate scaling */ |
91dd6c27 | 3337 | IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n", |
fe6b23dd RC |
3338 | sta->addr); |
3339 | iwl3945_rs_rate_init(priv, sta, sta_id); | |
da5ae1cf | 3340 | mutex_unlock(&priv->mutex); |
fe6b23dd RC |
3341 | |
3342 | return 0; | |
fe6b23dd | 3343 | } |
8b8ab9d5 JB |
3344 | |
3345 | static void iwl3945_configure_filter(struct ieee80211_hw *hw, | |
3346 | unsigned int changed_flags, | |
3347 | unsigned int *total_flags, | |
3348 | u64 multicast) | |
3349 | { | |
3350 | struct iwl_priv *priv = hw->priv; | |
3351 | __le32 filter_or = 0, filter_nand = 0; | |
246ed355 | 3352 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
8b8ab9d5 JB |
3353 | |
3354 | #define CHK(test, flag) do { \ | |
3355 | if (*total_flags & (test)) \ | |
3356 | filter_or |= (flag); \ | |
3357 | else \ | |
3358 | filter_nand |= (flag); \ | |
3359 | } while (0) | |
3360 | ||
3361 | IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n", | |
3362 | changed_flags, *total_flags); | |
3363 | ||
3364 | CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK); | |
3365 | CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK); | |
3366 | CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); | |
3367 | ||
3368 | #undef CHK | |
3369 | ||
3370 | mutex_lock(&priv->mutex); | |
3371 | ||
246ed355 JB |
3372 | ctx->staging.filter_flags &= ~filter_nand; |
3373 | ctx->staging.filter_flags |= filter_or; | |
8b8ab9d5 JB |
3374 | |
3375 | /* | |
3376 | * Committing directly here breaks for some reason, | |
3377 | * but we'll eventually commit the filter flags | |
3378 | * change anyway. | |
3379 | */ | |
3380 | ||
3381 | mutex_unlock(&priv->mutex); | |
3382 | ||
3383 | /* | |
3384 | * Receiving all multicast frames is always enabled by the | |
3385 | * default flags setup in iwl_connection_init_rx_config() | |
3386 | * since we currently do not support programming multicast | |
3387 | * filters into the device. | |
3388 | */ | |
3389 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
3390 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
3391 | } | |
3392 | ||
3393 | ||
b481de9c ZY |
3394 | /***************************************************************************** |
3395 | * | |
3396 | * sysfs attributes | |
3397 | * | |
3398 | *****************************************************************************/ | |
3399 | ||
d08853a3 | 3400 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3401 | |
3402 | /* | |
3403 | * The following adds a new attribute to the sysfs representation | |
3404 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
3405 | * used for controlling the debug level. | |
3406 | * | |
3407 | * See the level definitions in iwl for details. | |
a562a9dd | 3408 | * |
3d816c77 RC |
3409 | * The debug_level being managed using sysfs below is a per device debug |
3410 | * level that is used instead of the global debug level if it (the per | |
3411 | * device debug level) is set. | |
b481de9c | 3412 | */ |
40b8ec0b SO |
3413 | static ssize_t show_debug_level(struct device *d, |
3414 | struct device_attribute *attr, char *buf) | |
b481de9c | 3415 | { |
3d816c77 RC |
3416 | struct iwl_priv *priv = dev_get_drvdata(d); |
3417 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
b481de9c | 3418 | } |
40b8ec0b SO |
3419 | static ssize_t store_debug_level(struct device *d, |
3420 | struct device_attribute *attr, | |
b481de9c ZY |
3421 | const char *buf, size_t count) |
3422 | { | |
928841b1 | 3423 | struct iwl_priv *priv = dev_get_drvdata(d); |
40b8ec0b SO |
3424 | unsigned long val; |
3425 | int ret; | |
b481de9c | 3426 | |
40b8ec0b SO |
3427 | ret = strict_strtoul(buf, 0, &val); |
3428 | if (ret) | |
978785a3 | 3429 | IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf); |
20594eb0 | 3430 | else { |
3d816c77 | 3431 | priv->debug_level = val; |
20594eb0 WYG |
3432 | if (iwl_alloc_traffic_mem(priv)) |
3433 | IWL_ERR(priv, | |
3434 | "Not enough memory to generate traffic log\n"); | |
3435 | } | |
b481de9c ZY |
3436 | return strnlen(buf, count); |
3437 | } | |
3438 | ||
40b8ec0b SO |
3439 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
3440 | show_debug_level, store_debug_level); | |
b481de9c | 3441 | |
d08853a3 | 3442 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 3443 | |
b481de9c ZY |
3444 | static ssize_t show_temperature(struct device *d, |
3445 | struct device_attribute *attr, char *buf) | |
3446 | { | |
928841b1 | 3447 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3448 | |
775a6e27 | 3449 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3450 | return -EAGAIN; |
3451 | ||
bb8c093b | 3452 | return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv)); |
b481de9c ZY |
3453 | } |
3454 | ||
3455 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
3456 | ||
b481de9c ZY |
3457 | static ssize_t show_tx_power(struct device *d, |
3458 | struct device_attribute *attr, char *buf) | |
3459 | { | |
928841b1 | 3460 | struct iwl_priv *priv = dev_get_drvdata(d); |
62ea9c5b | 3461 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); |
b481de9c ZY |
3462 | } |
3463 | ||
3464 | static ssize_t store_tx_power(struct device *d, | |
3465 | struct device_attribute *attr, | |
3466 | const char *buf, size_t count) | |
3467 | { | |
928841b1 | 3468 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3469 | char *p = (char *)buf; |
3470 | u32 val; | |
3471 | ||
3472 | val = simple_strtoul(p, &p, 10); | |
3473 | if (p == buf) | |
978785a3 | 3474 | IWL_INFO(priv, ": %s is not in decimal form.\n", buf); |
b481de9c | 3475 | else |
bb8c093b | 3476 | iwl3945_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
3477 | |
3478 | return count; | |
3479 | } | |
3480 | ||
3481 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
3482 | ||
3483 | static ssize_t show_flags(struct device *d, | |
3484 | struct device_attribute *attr, char *buf) | |
3485 | { | |
928841b1 | 3486 | struct iwl_priv *priv = dev_get_drvdata(d); |
246ed355 | 3487 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c | 3488 | |
246ed355 | 3489 | return sprintf(buf, "0x%04X\n", ctx->active.flags); |
b481de9c ZY |
3490 | } |
3491 | ||
3492 | static ssize_t store_flags(struct device *d, | |
3493 | struct device_attribute *attr, | |
3494 | const char *buf, size_t count) | |
3495 | { | |
928841b1 | 3496 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3497 | u32 flags = simple_strtoul(buf, NULL, 0); |
246ed355 | 3498 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c ZY |
3499 | |
3500 | mutex_lock(&priv->mutex); | |
246ed355 | 3501 | if (le32_to_cpu(ctx->staging.flags) != flags) { |
b481de9c | 3502 | /* Cancel any currently running scans... */ |
af0053d6 | 3503 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3504 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3505 | else { |
e1623446 | 3506 | IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n", |
b481de9c | 3507 | flags); |
246ed355 JB |
3508 | ctx->staging.flags = cpu_to_le32(flags); |
3509 | iwlcore_commit_rxon(priv, ctx); | |
b481de9c ZY |
3510 | } |
3511 | } | |
3512 | mutex_unlock(&priv->mutex); | |
3513 | ||
3514 | return count; | |
3515 | } | |
3516 | ||
3517 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
3518 | ||
3519 | static ssize_t show_filter_flags(struct device *d, | |
3520 | struct device_attribute *attr, char *buf) | |
3521 | { | |
928841b1 | 3522 | struct iwl_priv *priv = dev_get_drvdata(d); |
246ed355 | 3523 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c ZY |
3524 | |
3525 | return sprintf(buf, "0x%04X\n", | |
246ed355 | 3526 | le32_to_cpu(ctx->active.filter_flags)); |
b481de9c ZY |
3527 | } |
3528 | ||
3529 | static ssize_t store_filter_flags(struct device *d, | |
3530 | struct device_attribute *attr, | |
3531 | const char *buf, size_t count) | |
3532 | { | |
928841b1 | 3533 | struct iwl_priv *priv = dev_get_drvdata(d); |
246ed355 | 3534 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c ZY |
3535 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
3536 | ||
3537 | mutex_lock(&priv->mutex); | |
246ed355 | 3538 | if (le32_to_cpu(ctx->staging.filter_flags) != filter_flags) { |
b481de9c | 3539 | /* Cancel any currently running scans... */ |
af0053d6 | 3540 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3541 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3542 | else { |
e1623446 | 3543 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c | 3544 | "0x%04X\n", filter_flags); |
246ed355 | 3545 | ctx->staging.filter_flags = |
b481de9c | 3546 | cpu_to_le32(filter_flags); |
246ed355 | 3547 | iwlcore_commit_rxon(priv, ctx); |
b481de9c ZY |
3548 | } |
3549 | } | |
3550 | mutex_unlock(&priv->mutex); | |
3551 | ||
3552 | return count; | |
3553 | } | |
3554 | ||
3555 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
3556 | store_filter_flags); | |
3557 | ||
b481de9c ZY |
3558 | static ssize_t show_measurement(struct device *d, |
3559 | struct device_attribute *attr, char *buf) | |
3560 | { | |
4a8a4322 | 3561 | struct iwl_priv *priv = dev_get_drvdata(d); |
600c0e11 | 3562 | struct iwl_spectrum_notification measure_report; |
b481de9c | 3563 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
3ac7f146 | 3564 | u8 *data = (u8 *)&measure_report; |
b481de9c ZY |
3565 | unsigned long flags; |
3566 | ||
3567 | spin_lock_irqsave(&priv->lock, flags); | |
3568 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
3569 | spin_unlock_irqrestore(&priv->lock, flags); | |
3570 | return 0; | |
3571 | } | |
3572 | memcpy(&measure_report, &priv->measure_report, size); | |
3573 | priv->measurement_status = 0; | |
3574 | spin_unlock_irqrestore(&priv->lock, flags); | |
3575 | ||
3576 | while (size && (PAGE_SIZE - len)) { | |
3577 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3578 | PAGE_SIZE - len, 1); | |
3579 | len = strlen(buf); | |
3580 | if (PAGE_SIZE - len) | |
3581 | buf[len++] = '\n'; | |
3582 | ||
3583 | ofs += 16; | |
3584 | size -= min(size, 16U); | |
3585 | } | |
3586 | ||
3587 | return len; | |
3588 | } | |
3589 | ||
3590 | static ssize_t store_measurement(struct device *d, | |
3591 | struct device_attribute *attr, | |
3592 | const char *buf, size_t count) | |
3593 | { | |
4a8a4322 | 3594 | struct iwl_priv *priv = dev_get_drvdata(d); |
246ed355 | 3595 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c | 3596 | struct ieee80211_measurement_params params = { |
246ed355 | 3597 | .channel = le16_to_cpu(ctx->active.channel), |
e99f168c | 3598 | .start_time = cpu_to_le64(priv->_3945.last_tsf), |
b481de9c ZY |
3599 | .duration = cpu_to_le16(1), |
3600 | }; | |
3601 | u8 type = IWL_MEASURE_BASIC; | |
3602 | u8 buffer[32]; | |
3603 | u8 channel; | |
3604 | ||
3605 | if (count) { | |
3606 | char *p = buffer; | |
3607 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
3608 | channel = simple_strtoul(p, NULL, 0); | |
3609 | if (channel) | |
3610 | params.channel = channel; | |
3611 | ||
3612 | p = buffer; | |
3613 | while (*p && *p != ' ') | |
3614 | p++; | |
3615 | if (*p) | |
3616 | type = simple_strtoul(p + 1, NULL, 0); | |
3617 | } | |
3618 | ||
e1623446 | 3619 | IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on " |
b481de9c | 3620 | "channel %d (for '%s')\n", type, params.channel, buf); |
bb8c093b | 3621 | iwl3945_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
3622 | |
3623 | return count; | |
3624 | } | |
3625 | ||
3626 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
3627 | show_measurement, store_measurement); | |
b481de9c | 3628 | |
b481de9c ZY |
3629 | static ssize_t store_retry_rate(struct device *d, |
3630 | struct device_attribute *attr, | |
3631 | const char *buf, size_t count) | |
3632 | { | |
4a8a4322 | 3633 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3634 | |
3635 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
3636 | if (priv->retry_rate <= 0) | |
3637 | priv->retry_rate = 1; | |
3638 | ||
3639 | return count; | |
3640 | } | |
3641 | ||
3642 | static ssize_t show_retry_rate(struct device *d, | |
3643 | struct device_attribute *attr, char *buf) | |
3644 | { | |
4a8a4322 | 3645 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3646 | return sprintf(buf, "%d", priv->retry_rate); |
3647 | } | |
3648 | ||
3649 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
3650 | store_retry_rate); | |
3651 | ||
d25aabb0 | 3652 | |
b481de9c ZY |
3653 | static ssize_t show_channels(struct device *d, |
3654 | struct device_attribute *attr, char *buf) | |
3655 | { | |
8318d78a JB |
3656 | /* all this shit doesn't belong into sysfs anyway */ |
3657 | return 0; | |
b481de9c ZY |
3658 | } |
3659 | ||
3660 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
3661 | ||
b481de9c ZY |
3662 | static ssize_t show_antenna(struct device *d, |
3663 | struct device_attribute *attr, char *buf) | |
3664 | { | |
4a8a4322 | 3665 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3666 | |
775a6e27 | 3667 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3668 | return -EAGAIN; |
3669 | ||
7e4bca5e | 3670 | return sprintf(buf, "%d\n", iwl3945_mod_params.antenna); |
b481de9c ZY |
3671 | } |
3672 | ||
3673 | static ssize_t store_antenna(struct device *d, | |
3674 | struct device_attribute *attr, | |
3675 | const char *buf, size_t count) | |
3676 | { | |
7530f85f | 3677 | struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d); |
b481de9c | 3678 | int ant; |
b481de9c ZY |
3679 | |
3680 | if (count == 0) | |
3681 | return 0; | |
3682 | ||
3683 | if (sscanf(buf, "%1i", &ant) != 1) { | |
e1623446 | 3684 | IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n"); |
b481de9c ZY |
3685 | return count; |
3686 | } | |
3687 | ||
3688 | if ((ant >= 0) && (ant <= 2)) { | |
e1623446 | 3689 | IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant); |
7e4bca5e | 3690 | iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant; |
b481de9c | 3691 | } else |
e1623446 | 3692 | IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant); |
b481de9c ZY |
3693 | |
3694 | ||
3695 | return count; | |
3696 | } | |
3697 | ||
3698 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
3699 | ||
3700 | static ssize_t show_status(struct device *d, | |
3701 | struct device_attribute *attr, char *buf) | |
3702 | { | |
928841b1 | 3703 | struct iwl_priv *priv = dev_get_drvdata(d); |
775a6e27 | 3704 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3705 | return -EAGAIN; |
3706 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
3707 | } | |
3708 | ||
3709 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
3710 | ||
3711 | static ssize_t dump_error_log(struct device *d, | |
3712 | struct device_attribute *attr, | |
3713 | const char *buf, size_t count) | |
3714 | { | |
928841b1 | 3715 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3716 | char *p = (char *)buf; |
3717 | ||
3718 | if (p[0] == '1') | |
928841b1 | 3719 | iwl3945_dump_nic_error_log(priv); |
b481de9c ZY |
3720 | |
3721 | return strnlen(buf, count); | |
3722 | } | |
3723 | ||
3724 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
3725 | ||
b481de9c ZY |
3726 | /***************************************************************************** |
3727 | * | |
a96a27f9 | 3728 | * driver setup and tear down |
b481de9c ZY |
3729 | * |
3730 | *****************************************************************************/ | |
3731 | ||
4a8a4322 | 3732 | static void iwl3945_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3733 | { |
d21050c7 | 3734 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3735 | |
3736 | init_waitqueue_head(&priv->wait_command_queue); | |
3737 | ||
bb8c093b CH |
3738 | INIT_WORK(&priv->restart, iwl3945_bg_restart); |
3739 | INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish); | |
bb8c093b | 3740 | INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); |
bb8c093b CH |
3741 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); |
3742 | INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); | |
ee525d13 | 3743 | INIT_DELAYED_WORK(&priv->_3945.rfkill_poll, iwl3945_rfkill_poll); |
c240879f SG |
3744 | |
3745 | iwl_setup_scan_deferred_work(priv); | |
bb8c093b CH |
3746 | |
3747 | iwl3945_hw_setup_deferred_work(priv); | |
b481de9c | 3748 | |
b74e31a9 WYG |
3749 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
3750 | init_timer(&priv->monitor_recover); | |
3751 | priv->monitor_recover.data = (unsigned long)priv; | |
3752 | priv->monitor_recover.function = | |
3753 | priv->cfg->ops->lib->recover_from_tx_stall; | |
3754 | } | |
3755 | ||
b481de9c | 3756 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) |
bb8c093b | 3757 | iwl3945_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
3758 | } |
3759 | ||
4a8a4322 | 3760 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3761 | { |
bb8c093b | 3762 | iwl3945_hw_cancel_deferred_work(priv); |
b481de9c | 3763 | |
e47eb6ad | 3764 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c | 3765 | cancel_delayed_work(&priv->alive_start); |
b481de9c | 3766 | cancel_work_sync(&priv->beacon_update); |
e7e16b90 SG |
3767 | |
3768 | iwl_cancel_scan_deferred_work(priv); | |
b481de9c ZY |
3769 | } |
3770 | ||
bb8c093b | 3771 | static struct attribute *iwl3945_sysfs_entries[] = { |
b481de9c ZY |
3772 | &dev_attr_antenna.attr, |
3773 | &dev_attr_channels.attr, | |
3774 | &dev_attr_dump_errors.attr, | |
b481de9c ZY |
3775 | &dev_attr_flags.attr, |
3776 | &dev_attr_filter_flags.attr, | |
b481de9c | 3777 | &dev_attr_measurement.attr, |
b481de9c | 3778 | &dev_attr_retry_rate.attr, |
b481de9c ZY |
3779 | &dev_attr_status.attr, |
3780 | &dev_attr_temperature.attr, | |
b481de9c | 3781 | &dev_attr_tx_power.attr, |
d08853a3 | 3782 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b SO |
3783 | &dev_attr_debug_level.attr, |
3784 | #endif | |
b481de9c ZY |
3785 | NULL |
3786 | }; | |
3787 | ||
bb8c093b | 3788 | static struct attribute_group iwl3945_attribute_group = { |
b481de9c | 3789 | .name = NULL, /* put in device directory */ |
bb8c093b | 3790 | .attrs = iwl3945_sysfs_entries, |
b481de9c ZY |
3791 | }; |
3792 | ||
bb8c093b CH |
3793 | static struct ieee80211_ops iwl3945_hw_ops = { |
3794 | .tx = iwl3945_mac_tx, | |
3795 | .start = iwl3945_mac_start, | |
3796 | .stop = iwl3945_mac_stop, | |
cbb6ab94 | 3797 | .add_interface = iwl_mac_add_interface, |
d8052319 | 3798 | .remove_interface = iwl_mac_remove_interface, |
4808368d | 3799 | .config = iwl_mac_config, |
8b8ab9d5 | 3800 | .configure_filter = iwl3945_configure_filter, |
bb8c093b | 3801 | .set_key = iwl3945_mac_set_key, |
488829f1 | 3802 | .conf_tx = iwl_mac_conf_tx, |
bd564261 | 3803 | .reset_tsf = iwl_mac_reset_tsf, |
5bbe233b | 3804 | .bss_info_changed = iwl_bss_info_changed, |
fe6b23dd RC |
3805 | .hw_scan = iwl_mac_hw_scan, |
3806 | .sta_add = iwl3945_mac_sta_add, | |
3807 | .sta_remove = iwl_mac_sta_remove, | |
a85d7cca | 3808 | .tx_last_beacon = iwl_mac_tx_last_beacon, |
b481de9c ZY |
3809 | }; |
3810 | ||
e52119c5 | 3811 | static int iwl3945_init_drv(struct iwl_priv *priv) |
90a30a02 KA |
3812 | { |
3813 | int ret; | |
e6148917 | 3814 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
90a30a02 KA |
3815 | |
3816 | priv->retry_rate = 1; | |
3817 | priv->ibss_beacon = NULL; | |
3818 | ||
90a30a02 KA |
3819 | spin_lock_init(&priv->sta_lock); |
3820 | spin_lock_init(&priv->hcmd_lock); | |
3821 | ||
3822 | INIT_LIST_HEAD(&priv->free_frames); | |
3823 | ||
3824 | mutex_init(&priv->mutex); | |
d2dfe6df | 3825 | mutex_init(&priv->sync_cmd_mutex); |
90a30a02 | 3826 | |
90a30a02 KA |
3827 | priv->ieee_channels = NULL; |
3828 | priv->ieee_rates = NULL; | |
3829 | priv->band = IEEE80211_BAND_2GHZ; | |
3830 | ||
3831 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
a13d276f | 3832 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
90a30a02 | 3833 | |
62ea9c5b | 3834 | priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER; |
90a30a02 | 3835 | |
e6148917 SO |
3836 | if (eeprom->version < EEPROM_3945_EEPROM_VERSION) { |
3837 | IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n", | |
3838 | eeprom->version); | |
3839 | ret = -EINVAL; | |
3840 | goto err; | |
3841 | } | |
3842 | ret = iwl_init_channel_map(priv); | |
90a30a02 KA |
3843 | if (ret) { |
3844 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3845 | goto err; | |
3846 | } | |
3847 | ||
e6148917 SO |
3848 | /* Set up txpower settings in driver for all channels */ |
3849 | if (iwl3945_txpower_set_from_eeprom(priv)) { | |
3850 | ret = -EIO; | |
3851 | goto err_free_channel_map; | |
3852 | } | |
3853 | ||
534166de | 3854 | ret = iwlcore_init_geos(priv); |
90a30a02 KA |
3855 | if (ret) { |
3856 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3857 | goto err_free_channel_map; | |
3858 | } | |
534166de SO |
3859 | iwl3945_init_hw_rates(priv, priv->ieee_rates); |
3860 | ||
2a4ddaab AK |
3861 | return 0; |
3862 | ||
3863 | err_free_channel_map: | |
3864 | iwl_free_channel_map(priv); | |
3865 | err: | |
3866 | return ret; | |
3867 | } | |
3868 | ||
dd7a2509 JB |
3869 | #define IWL3945_MAX_PROBE_REQUEST 200 |
3870 | ||
2a4ddaab AK |
3871 | static int iwl3945_setup_mac(struct iwl_priv *priv) |
3872 | { | |
3873 | int ret; | |
3874 | struct ieee80211_hw *hw = priv->hw; | |
3875 | ||
3876 | hw->rate_control_algorithm = "iwl-3945-rs"; | |
3877 | hw->sta_data_size = sizeof(struct iwl3945_sta_priv); | |
fd1af15d | 3878 | hw->vif_data_size = sizeof(struct iwl_vif_priv); |
2a4ddaab AK |
3879 | |
3880 | /* Tell mac80211 our characteristics */ | |
3881 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
bc45a670 RC |
3882 | IEEE80211_HW_SPECTRUM_MGMT; |
3883 | ||
3884 | if (!priv->cfg->broken_powersave) | |
3885 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | | |
3886 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
2a4ddaab AK |
3887 | |
3888 | hw->wiphy->interface_modes = | |
d0fe478c | 3889 | priv->contexts[IWL_RXON_CTX_BSS].interface_modes; |
2a4ddaab | 3890 | |
f6c8f152 | 3891 | hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | |
5be83de5 | 3892 | WIPHY_FLAG_DISABLE_BEACON_HINTS; |
37184244 | 3893 | |
1ecf9fc1 JB |
3894 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945; |
3895 | /* we create the 802.11 header and a zero-length SSID element */ | |
dd7a2509 | 3896 | hw->wiphy->max_scan_ie_len = IWL3945_MAX_PROBE_REQUEST - 24 - 2; |
d60cc91a | 3897 | |
2a4ddaab AK |
3898 | /* Default value; 4 EDCA QOS priorities */ |
3899 | hw->queues = 4; | |
3900 | ||
534166de SO |
3901 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
3902 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
3903 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2a4ddaab | 3904 | |
534166de SO |
3905 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) |
3906 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
3907 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
90a30a02 | 3908 | |
2a4ddaab AK |
3909 | ret = ieee80211_register_hw(priv->hw); |
3910 | if (ret) { | |
3911 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
3912 | return ret; | |
3913 | } | |
3914 | priv->mac80211_registered = 1; | |
90a30a02 | 3915 | |
2a4ddaab | 3916 | return 0; |
90a30a02 KA |
3917 | } |
3918 | ||
bb8c093b | 3919 | static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c | 3920 | { |
246ed355 | 3921 | int err = 0, i; |
4a8a4322 | 3922 | struct iwl_priv *priv; |
b481de9c | 3923 | struct ieee80211_hw *hw; |
c0f20d91 | 3924 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
e6148917 | 3925 | struct iwl3945_eeprom *eeprom; |
0359facc | 3926 | unsigned long flags; |
b481de9c | 3927 | |
cee53ddb KA |
3928 | /*********************** |
3929 | * 1. Allocating HW data | |
3930 | * ********************/ | |
3931 | ||
b481de9c ZY |
3932 | /* mac80211 allocates memory for this device instance, including |
3933 | * space for this driver's private structure */ | |
90a30a02 | 3934 | hw = iwl_alloc_all(cfg, &iwl3945_hw_ops); |
b481de9c | 3935 | if (hw == NULL) { |
c96c31e4 | 3936 | pr_err("Can not allocate network device\n"); |
b481de9c ZY |
3937 | err = -ENOMEM; |
3938 | goto out; | |
3939 | } | |
b481de9c | 3940 | priv = hw->priv; |
90a30a02 | 3941 | SET_IEEE80211_DEV(hw, &pdev->dev); |
6440adb5 | 3942 | |
13bb9483 JB |
3943 | priv->cmd_queue = IWL39_CMD_QUEUE_NUM; |
3944 | ||
246ed355 JB |
3945 | /* 3945 has only one valid context */ |
3946 | priv->valid_contexts = BIT(IWL_RXON_CTX_BSS); | |
3947 | ||
3948 | for (i = 0; i < NUM_IWL_RXON_CTX; i++) | |
3949 | priv->contexts[i].ctxid = i; | |
3950 | ||
8f2d3d2a JB |
3951 | priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON; |
3952 | priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING; | |
3953 | priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC; | |
8dfdb9d5 | 3954 | priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM; |
2995bafa | 3955 | priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID; |
c10afb6e | 3956 | priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY; |
d0fe478c JB |
3957 | priv->contexts[IWL_RXON_CTX_BSS].interface_modes = |
3958 | BIT(NL80211_IFTYPE_STATION) | | |
3959 | BIT(NL80211_IFTYPE_ADHOC); | |
3960 | priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS; | |
3961 | priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS; | |
3962 | priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS; | |
8f2d3d2a | 3963 | |
90a30a02 KA |
3964 | /* |
3965 | * Disabling hardware scan means that mac80211 will perform scans | |
3966 | * "the hard way", rather than using device's scan. | |
3967 | */ | |
df878d8f | 3968 | if (iwl3945_mod_params.disable_hw_scan) { |
e1623446 | 3969 | IWL_DEBUG_INFO(priv, "Disabling hw_scan\n"); |
40b8ec0b SO |
3970 | iwl3945_hw_ops.hw_scan = NULL; |
3971 | } | |
3972 | ||
90a30a02 | 3973 | |
e1623446 | 3974 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
90a30a02 KA |
3975 | priv->cfg = cfg; |
3976 | priv->pci_dev = pdev; | |
40cefda9 | 3977 | priv->inta_mask = CSR_INI_SET_MASK; |
cee53ddb | 3978 | |
20594eb0 WYG |
3979 | if (iwl_alloc_traffic_mem(priv)) |
3980 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 3981 | |
cee53ddb KA |
3982 | /*************************** |
3983 | * 2. Initializing PCI bus | |
3984 | * *************************/ | |
1a7123cd JL |
3985 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | |
3986 | PCIE_LINK_STATE_CLKPM); | |
3987 | ||
b481de9c ZY |
3988 | if (pci_enable_device(pdev)) { |
3989 | err = -ENODEV; | |
3990 | goto out_ieee80211_free_hw; | |
3991 | } | |
3992 | ||
3993 | pci_set_master(pdev); | |
3994 | ||
284901a9 | 3995 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 3996 | if (!err) |
284901a9 | 3997 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 3998 | if (err) { |
978785a3 | 3999 | IWL_WARN(priv, "No suitable DMA available.\n"); |
b481de9c ZY |
4000 | goto out_pci_disable_device; |
4001 | } | |
4002 | ||
4003 | pci_set_drvdata(pdev, priv); | |
4004 | err = pci_request_regions(pdev, DRV_NAME); | |
4005 | if (err) | |
4006 | goto out_pci_disable_device; | |
6440adb5 | 4007 | |
cee53ddb KA |
4008 | /*********************** |
4009 | * 3. Read REV Register | |
4010 | * ********************/ | |
b481de9c ZY |
4011 | priv->hw_base = pci_iomap(pdev, 0, 0); |
4012 | if (!priv->hw_base) { | |
4013 | err = -ENODEV; | |
4014 | goto out_pci_release_regions; | |
4015 | } | |
4016 | ||
e1623446 | 4017 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
b481de9c | 4018 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 4019 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
b481de9c | 4020 | |
cee53ddb KA |
4021 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
4022 | * PCI Tx retries from interfering with C3 CPU state */ | |
4023 | pci_write_config_byte(pdev, 0x41, 0x00); | |
b481de9c | 4024 | |
731a29b7 | 4025 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
4026 | * we should init now |
4027 | */ | |
4028 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 4029 | spin_lock_init(&priv->lock); |
a8b50a0a | 4030 | |
4843b5a7 RC |
4031 | /* |
4032 | * stop and reset the on-board processor just in case it is in a | |
4033 | * strange state ... like being left stranded by a primary kernel | |
4034 | * and this is now the kdump kernel trying to start up | |
4035 | */ | |
4036 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
4037 | ||
cee53ddb KA |
4038 | /*********************** |
4039 | * 4. Read EEPROM | |
4040 | * ********************/ | |
90a30a02 | 4041 | |
cee53ddb | 4042 | /* Read the EEPROM */ |
e6148917 | 4043 | err = iwl_eeprom_init(priv); |
cee53ddb | 4044 | if (err) { |
15b1687c | 4045 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
c8f16138 | 4046 | goto out_iounmap; |
cee53ddb KA |
4047 | } |
4048 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
e6148917 | 4049 | eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
30eabc17 JB |
4050 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", eeprom->mac_address); |
4051 | SET_IEEE80211_PERM_ADDR(priv->hw, eeprom->mac_address); | |
b481de9c | 4052 | |
cee53ddb KA |
4053 | /*********************** |
4054 | * 5. Setup HW Constants | |
4055 | * ********************/ | |
b481de9c | 4056 | /* Device-specific setup */ |
3832ec9d | 4057 | if (iwl3945_hw_set_hw_params(priv)) { |
15b1687c | 4058 | IWL_ERR(priv, "failed to set hw settings\n"); |
c8f16138 | 4059 | goto out_eeprom_free; |
b481de9c ZY |
4060 | } |
4061 | ||
cee53ddb KA |
4062 | /*********************** |
4063 | * 6. Setup priv | |
4064 | * ********************/ | |
cee53ddb | 4065 | |
90a30a02 | 4066 | err = iwl3945_init_drv(priv); |
b481de9c | 4067 | if (err) { |
90a30a02 | 4068 | IWL_ERR(priv, "initializing driver failed\n"); |
c8f16138 | 4069 | goto out_unset_hw_params; |
b481de9c ZY |
4070 | } |
4071 | ||
978785a3 TW |
4072 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n", |
4073 | priv->cfg->name); | |
cee53ddb | 4074 | |
cee53ddb | 4075 | /*********************** |
09f9bf79 | 4076 | * 7. Setup Services |
cee53ddb KA |
4077 | * ********************/ |
4078 | ||
4079 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4080 | iwl_disable_interrupts(priv); |
cee53ddb KA |
4081 | spin_unlock_irqrestore(&priv->lock, flags); |
4082 | ||
2663516d HS |
4083 | pci_enable_msi(priv->pci_dev); |
4084 | ||
ef850d7c MA |
4085 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, |
4086 | IRQF_SHARED, DRV_NAME, priv); | |
2663516d HS |
4087 | if (err) { |
4088 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
4089 | goto out_disable_msi; | |
4090 | } | |
4091 | ||
cee53ddb | 4092 | err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
849e0dce | 4093 | if (err) { |
15b1687c | 4094 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
90a30a02 | 4095 | goto out_release_irq; |
849e0dce | 4096 | } |
849e0dce | 4097 | |
8ccde88a | 4098 | iwl_set_rxon_channel(priv, |
246ed355 JB |
4099 | &priv->bands[IEEE80211_BAND_2GHZ].channels[5], |
4100 | &priv->contexts[IWL_RXON_CTX_BSS]); | |
cee53ddb KA |
4101 | iwl3945_setup_deferred_work(priv); |
4102 | iwl3945_setup_rx_handlers(priv); | |
008a9e3e | 4103 | iwl_power_initialize(priv); |
cee53ddb | 4104 | |
cee53ddb | 4105 | /********************************* |
09f9bf79 | 4106 | * 8. Setup and Register mac80211 |
cee53ddb KA |
4107 | * *******************************/ |
4108 | ||
2a4ddaab | 4109 | iwl_enable_interrupts(priv); |
b481de9c | 4110 | |
2a4ddaab AK |
4111 | err = iwl3945_setup_mac(priv); |
4112 | if (err) | |
4113 | goto out_remove_sysfs; | |
cee53ddb | 4114 | |
a75fbe8d AK |
4115 | err = iwl_dbgfs_register(priv, DRV_NAME); |
4116 | if (err) | |
4117 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
4118 | ||
2663516d | 4119 | /* Start monitoring the killswitch */ |
ee525d13 | 4120 | queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll, |
2663516d HS |
4121 | 2 * HZ); |
4122 | ||
b481de9c ZY |
4123 | return 0; |
4124 | ||
cee53ddb | 4125 | out_remove_sysfs: |
c8f16138 RC |
4126 | destroy_workqueue(priv->workqueue); |
4127 | priv->workqueue = NULL; | |
cee53ddb | 4128 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4129 | out_release_irq: |
2663516d | 4130 | free_irq(priv->pci_dev->irq, priv); |
2663516d HS |
4131 | out_disable_msi: |
4132 | pci_disable_msi(priv->pci_dev); | |
c8f16138 RC |
4133 | iwlcore_free_geos(priv); |
4134 | iwl_free_channel_map(priv); | |
4135 | out_unset_hw_params: | |
4136 | iwl3945_unset_hw_params(priv); | |
4137 | out_eeprom_free: | |
4138 | iwl_eeprom_free(priv); | |
b481de9c ZY |
4139 | out_iounmap: |
4140 | pci_iounmap(pdev, priv->hw_base); | |
4141 | out_pci_release_regions: | |
4142 | pci_release_regions(pdev); | |
4143 | out_pci_disable_device: | |
b481de9c | 4144 | pci_set_drvdata(pdev, NULL); |
623d563e | 4145 | pci_disable_device(pdev); |
b481de9c | 4146 | out_ieee80211_free_hw: |
20594eb0 | 4147 | iwl_free_traffic_mem(priv); |
d7c76f4c | 4148 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
4149 | out: |
4150 | return err; | |
4151 | } | |
4152 | ||
c83dbf68 | 4153 | static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) |
b481de9c | 4154 | { |
4a8a4322 | 4155 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 4156 | unsigned long flags; |
b481de9c ZY |
4157 | |
4158 | if (!priv) | |
4159 | return; | |
4160 | ||
e1623446 | 4161 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 4162 | |
a75fbe8d AK |
4163 | iwl_dbgfs_unregister(priv); |
4164 | ||
b481de9c | 4165 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 4166 | |
d552bfb6 KA |
4167 | if (priv->mac80211_registered) { |
4168 | ieee80211_unregister_hw(priv->hw); | |
4169 | priv->mac80211_registered = 0; | |
4170 | } else { | |
4171 | iwl3945_down(priv); | |
4172 | } | |
b481de9c | 4173 | |
c166b25a BC |
4174 | /* |
4175 | * Make sure device is reset to low power before unloading driver. | |
4176 | * This may be redundant with iwl_down(), but there are paths to | |
4177 | * run iwl_down() without calling apm_ops.stop(), and there are | |
4178 | * paths to avoid running iwl_down() at all before leaving driver. | |
4179 | * This (inexpensive) call *makes sure* device is reset. | |
4180 | */ | |
4181 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
4182 | ||
0359facc MA |
4183 | /* make sure we flush any pending irq or |
4184 | * tasklet for the driver | |
4185 | */ | |
4186 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4187 | iwl_disable_interrupts(priv); |
0359facc MA |
4188 | spin_unlock_irqrestore(&priv->lock, flags); |
4189 | ||
4190 | iwl_synchronize_irq(priv); | |
4191 | ||
bb8c093b | 4192 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4193 | |
ee525d13 | 4194 | cancel_delayed_work_sync(&priv->_3945.rfkill_poll); |
2663516d | 4195 | |
bb8c093b | 4196 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
4197 | |
4198 | if (priv->rxq.bd) | |
df833b1d | 4199 | iwl3945_rx_queue_free(priv, &priv->rxq); |
bb8c093b | 4200 | iwl3945_hw_txq_ctx_free(priv); |
b481de9c | 4201 | |
3832ec9d | 4202 | iwl3945_unset_hw_params(priv); |
b481de9c | 4203 | |
6ef89d0a MA |
4204 | /*netif_stop_queue(dev); */ |
4205 | flush_workqueue(priv->workqueue); | |
4206 | ||
bb8c093b | 4207 | /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes |
b481de9c ZY |
4208 | * priv->workqueue... so we can't take down the workqueue |
4209 | * until now... */ | |
4210 | destroy_workqueue(priv->workqueue); | |
4211 | priv->workqueue = NULL; | |
20594eb0 | 4212 | iwl_free_traffic_mem(priv); |
b481de9c | 4213 | |
2663516d HS |
4214 | free_irq(pdev->irq, priv); |
4215 | pci_disable_msi(pdev); | |
4216 | ||
b481de9c ZY |
4217 | pci_iounmap(pdev, priv->hw_base); |
4218 | pci_release_regions(pdev); | |
4219 | pci_disable_device(pdev); | |
4220 | pci_set_drvdata(pdev, NULL); | |
4221 | ||
e6148917 | 4222 | iwl_free_channel_map(priv); |
534166de | 4223 | iwlcore_free_geos(priv); |
811ecc99 | 4224 | kfree(priv->scan_cmd); |
b481de9c ZY |
4225 | if (priv->ibss_beacon) |
4226 | dev_kfree_skb(priv->ibss_beacon); | |
4227 | ||
4228 | ieee80211_free_hw(priv->hw); | |
4229 | } | |
4230 | ||
b481de9c ZY |
4231 | |
4232 | /***************************************************************************** | |
4233 | * | |
4234 | * driver and module entry point | |
4235 | * | |
4236 | *****************************************************************************/ | |
4237 | ||
bb8c093b | 4238 | static struct pci_driver iwl3945_driver = { |
b481de9c | 4239 | .name = DRV_NAME, |
bb8c093b CH |
4240 | .id_table = iwl3945_hw_card_ids, |
4241 | .probe = iwl3945_pci_probe, | |
4242 | .remove = __devexit_p(iwl3945_pci_remove), | |
b481de9c | 4243 | #ifdef CONFIG_PM |
6da3a13e WYG |
4244 | .suspend = iwl_pci_suspend, |
4245 | .resume = iwl_pci_resume, | |
b481de9c ZY |
4246 | #endif |
4247 | }; | |
4248 | ||
bb8c093b | 4249 | static int __init iwl3945_init(void) |
b481de9c ZY |
4250 | { |
4251 | ||
4252 | int ret; | |
c96c31e4 JP |
4253 | pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); |
4254 | pr_info(DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
4255 | |
4256 | ret = iwl3945_rate_control_register(); | |
4257 | if (ret) { | |
c96c31e4 | 4258 | pr_err("Unable to register rate control algorithm: %d\n", ret); |
897e1cf2 RC |
4259 | return ret; |
4260 | } | |
4261 | ||
bb8c093b | 4262 | ret = pci_register_driver(&iwl3945_driver); |
b481de9c | 4263 | if (ret) { |
c96c31e4 | 4264 | pr_err("Unable to initialize PCI module\n"); |
897e1cf2 | 4265 | goto error_register; |
b481de9c | 4266 | } |
b481de9c ZY |
4267 | |
4268 | return ret; | |
897e1cf2 | 4269 | |
897e1cf2 RC |
4270 | error_register: |
4271 | iwl3945_rate_control_unregister(); | |
4272 | return ret; | |
b481de9c ZY |
4273 | } |
4274 | ||
bb8c093b | 4275 | static void __exit iwl3945_exit(void) |
b481de9c | 4276 | { |
bb8c093b | 4277 | pci_unregister_driver(&iwl3945_driver); |
897e1cf2 | 4278 | iwl3945_rate_control_unregister(); |
b481de9c ZY |
4279 | } |
4280 | ||
a0987a8d | 4281 | MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX)); |
25cb6cad | 4282 | |
4e30cb69 | 4283 | module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO); |
b481de9c | 4284 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
4e30cb69 | 4285 | module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO); |
9c74d9fb SO |
4286 | MODULE_PARM_DESC(swcrypto, |
4287 | "using software crypto (default 1 [software])\n"); | |
a562a9dd | 4288 | #ifdef CONFIG_IWLWIFI_DEBUG |
4e30cb69 | 4289 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
b481de9c | 4290 | MODULE_PARM_DESC(debug, "debug output mask"); |
a562a9dd | 4291 | #endif |
4e30cb69 WYG |
4292 | module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, |
4293 | int, S_IRUGO); | |
b481de9c | 4294 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |
4e30cb69 | 4295 | module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO); |
af48d048 SO |
4296 | MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error"); |
4297 | ||
bb8c093b CH |
4298 | module_exit(iwl3945_exit); |
4299 | module_init(iwl3945_init); |