]>
Commit | Line | Data |
---|---|---|
b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
d43c36dc | 36 | #include <linux/sched.h> |
b481de9c ZY |
37 | #include <linux/skbuff.h> |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/wireless.h> | |
40 | #include <linux/firmware.h> | |
b481de9c ZY |
41 | #include <linux/etherdevice.h> |
42 | #include <linux/if_arp.h> | |
43 | ||
44 | #include <net/ieee80211_radiotap.h> | |
7e272fcf | 45 | #include <net/lib80211.h> |
b481de9c ZY |
46 | #include <net/mac80211.h> |
47 | ||
48 | #include <asm/div64.h> | |
49 | ||
a3139c59 SO |
50 | #define DRV_NAME "iwl3945" |
51 | ||
dbb6654c WT |
52 | #include "iwl-fh.h" |
53 | #include "iwl-3945-fh.h" | |
600c0e11 | 54 | #include "iwl-commands.h" |
17f841cd | 55 | #include "iwl-sta.h" |
b481de9c ZY |
56 | #include "iwl-3945.h" |
57 | #include "iwl-helpers.h" | |
5747d47f | 58 | #include "iwl-core.h" |
d20b3c65 | 59 | #include "iwl-dev.h" |
b481de9c | 60 | |
b481de9c ZY |
61 | /* |
62 | * module name, copyright, version, etc. | |
b481de9c ZY |
63 | */ |
64 | ||
65 | #define DRV_DESCRIPTION \ | |
66 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
67 | ||
d08853a3 | 68 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
69 | #define VD "d" |
70 | #else | |
71 | #define VD | |
72 | #endif | |
73 | ||
c8b0e6e1 | 74 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
75 | #define VS "s" |
76 | #else | |
77 | #define VS | |
78 | #endif | |
79 | ||
eaa686c3 | 80 | #define IWL39_VERSION "1.2.26k" VD VS |
01f8162a | 81 | #define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation" |
a7b75207 | 82 | #define DRV_AUTHOR "<ilw@linux.intel.com>" |
eaa686c3 | 83 | #define DRV_VERSION IWL39_VERSION |
b481de9c | 84 | |
b481de9c ZY |
85 | |
86 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
87 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 88 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c ZY |
89 | MODULE_LICENSE("GPL"); |
90 | ||
df878d8f KA |
91 | /* module parameters */ |
92 | struct iwl_mod_params iwl3945_mod_params = { | |
5905a1aa | 93 | .num_of_queues = IWL39_NUM_QUEUES, /* Not used */ |
9c74d9fb | 94 | .sw_crypto = 1, |
af48d048 | 95 | .restart_fw = 1, |
df878d8f KA |
96 | /* the rest are 0 by default */ |
97 | }; | |
98 | ||
7e4bca5e SO |
99 | /** |
100 | * iwl3945_get_antenna_flags - Get antenna flags for RXON command | |
101 | * @priv: eeprom and antenna fields are used to determine antenna flags | |
102 | * | |
103 | * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed | |
104 | * iwl3945_mod_params.antenna specifies the antenna diversity mode: | |
105 | * | |
106 | * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself | |
107 | * IWL_ANTENNA_MAIN - Force MAIN antenna | |
108 | * IWL_ANTENNA_AUX - Force AUX antenna | |
109 | */ | |
110 | __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv) | |
111 | { | |
112 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; | |
113 | ||
114 | switch (iwl3945_mod_params.antenna) { | |
115 | case IWL_ANTENNA_DIVERSITY: | |
116 | return 0; | |
117 | ||
118 | case IWL_ANTENNA_MAIN: | |
119 | if (eeprom->antenna_switch_type) | |
120 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
121 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
122 | ||
123 | case IWL_ANTENNA_AUX: | |
124 | if (eeprom->antenna_switch_type) | |
125 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
126 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
127 | } | |
128 | ||
129 | /* bad antenna selector value */ | |
130 | IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", | |
131 | iwl3945_mod_params.antenna); | |
132 | ||
133 | return 0; /* "diversity" is default if error */ | |
134 | } | |
135 | ||
6e21f15c | 136 | static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv, |
b481de9c ZY |
137 | struct ieee80211_key_conf *keyconf, |
138 | u8 sta_id) | |
139 | { | |
140 | unsigned long flags; | |
141 | __le16 key_flags = 0; | |
6e21f15c AK |
142 | int ret; |
143 | ||
144 | key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); | |
145 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
146 | ||
147 | if (sta_id == priv->hw_params.bcast_sta_id) | |
148 | key_flags |= STA_KEY_MULTICAST_MSK; | |
149 | ||
150 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
151 | keyconf->hw_key_idx = keyconf->keyidx; | |
152 | key_flags &= ~STA_KEY_FLG_INVALID; | |
b481de9c | 153 | |
b481de9c | 154 | spin_lock_irqsave(&priv->sta_lock, flags); |
c587de0b TW |
155 | priv->stations[sta_id].keyinfo.alg = keyconf->alg; |
156 | priv->stations[sta_id].keyinfo.keylen = keyconf->keylen; | |
157 | memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, | |
b481de9c ZY |
158 | keyconf->keylen); |
159 | ||
c587de0b | 160 | memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, |
b481de9c | 161 | keyconf->keylen); |
6e21f15c | 162 | |
c587de0b | 163 | if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK) |
6e21f15c | 164 | == STA_KEY_FLG_NO_ENC) |
c587de0b | 165 | priv->stations[sta_id].sta.key.key_offset = |
6e21f15c AK |
166 | iwl_get_free_ucode_key_index(priv); |
167 | /* else, we are overriding an existing key => no need to allocated room | |
168 | * in uCode. */ | |
169 | ||
c587de0b | 170 | WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, |
6e21f15c AK |
171 | "no space for a new key"); |
172 | ||
c587de0b TW |
173 | priv->stations[sta_id].sta.key.key_flags = key_flags; |
174 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
175 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c | 176 | |
6e21f15c AK |
177 | IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n"); |
178 | ||
c587de0b | 179 | ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC); |
6e21f15c | 180 | |
b481de9c ZY |
181 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
182 | ||
6e21f15c AK |
183 | return ret; |
184 | } | |
185 | ||
186 | static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv, | |
187 | struct ieee80211_key_conf *keyconf, | |
188 | u8 sta_id) | |
189 | { | |
190 | return -EOPNOTSUPP; | |
191 | } | |
192 | ||
193 | static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv, | |
194 | struct ieee80211_key_conf *keyconf, | |
195 | u8 sta_id) | |
196 | { | |
197 | return -EOPNOTSUPP; | |
b481de9c ZY |
198 | } |
199 | ||
4a8a4322 | 200 | static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id) |
b481de9c ZY |
201 | { |
202 | unsigned long flags; | |
203 | ||
204 | spin_lock_irqsave(&priv->sta_lock, flags); | |
c587de0b TW |
205 | memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key)); |
206 | memset(&priv->stations[sta_id].sta.key, 0, | |
4c897253 | 207 | sizeof(struct iwl4965_keyinfo)); |
c587de0b TW |
208 | priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
209 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
210 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c ZY |
211 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
212 | ||
e1623446 | 213 | IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n"); |
c587de0b | 214 | iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0); |
b481de9c ZY |
215 | return 0; |
216 | } | |
217 | ||
fa11d525 | 218 | static int iwl3945_set_dynamic_key(struct iwl_priv *priv, |
6e21f15c AK |
219 | struct ieee80211_key_conf *keyconf, u8 sta_id) |
220 | { | |
221 | int ret = 0; | |
222 | ||
223 | keyconf->hw_key_idx = HW_KEY_DYNAMIC; | |
224 | ||
225 | switch (keyconf->alg) { | |
226 | case ALG_CCMP: | |
227 | ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id); | |
228 | break; | |
229 | case ALG_TKIP: | |
230 | ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id); | |
231 | break; | |
232 | case ALG_WEP: | |
233 | ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id); | |
234 | break; | |
235 | default: | |
1e680233 | 236 | IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg); |
6e21f15c AK |
237 | ret = -EINVAL; |
238 | } | |
239 | ||
240 | IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n", | |
241 | keyconf->alg, keyconf->keylen, keyconf->keyidx, | |
242 | sta_id, ret); | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
247 | static int iwl3945_remove_static_key(struct iwl_priv *priv) | |
248 | { | |
249 | int ret = -EOPNOTSUPP; | |
250 | ||
251 | return ret; | |
252 | } | |
253 | ||
254 | static int iwl3945_set_static_key(struct iwl_priv *priv, | |
255 | struct ieee80211_key_conf *key) | |
256 | { | |
257 | if (key->alg == ALG_WEP) | |
258 | return -EOPNOTSUPP; | |
259 | ||
260 | IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg); | |
261 | return -EINVAL; | |
262 | } | |
263 | ||
4a8a4322 | 264 | static void iwl3945_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
265 | { |
266 | struct list_head *element; | |
267 | ||
e1623446 | 268 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
269 | priv->frames_count); |
270 | ||
271 | while (!list_empty(&priv->free_frames)) { | |
272 | element = priv->free_frames.next; | |
273 | list_del(element); | |
bb8c093b | 274 | kfree(list_entry(element, struct iwl3945_frame, list)); |
b481de9c ZY |
275 | priv->frames_count--; |
276 | } | |
277 | ||
278 | if (priv->frames_count) { | |
39aadf8c | 279 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
280 | priv->frames_count); |
281 | priv->frames_count = 0; | |
282 | } | |
283 | } | |
284 | ||
4a8a4322 | 285 | static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv) |
b481de9c | 286 | { |
bb8c093b | 287 | struct iwl3945_frame *frame; |
b481de9c ZY |
288 | struct list_head *element; |
289 | if (list_empty(&priv->free_frames)) { | |
290 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
291 | if (!frame) { | |
15b1687c | 292 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
293 | return NULL; |
294 | } | |
295 | ||
296 | priv->frames_count++; | |
297 | return frame; | |
298 | } | |
299 | ||
300 | element = priv->free_frames.next; | |
301 | list_del(element); | |
bb8c093b | 302 | return list_entry(element, struct iwl3945_frame, list); |
b481de9c ZY |
303 | } |
304 | ||
4a8a4322 | 305 | static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame) |
b481de9c ZY |
306 | { |
307 | memset(frame, 0, sizeof(*frame)); | |
308 | list_add(&frame->list, &priv->free_frames); | |
309 | } | |
310 | ||
4a8a4322 | 311 | unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv, |
b481de9c | 312 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 313 | int left) |
b481de9c ZY |
314 | { |
315 | ||
8ccde88a | 316 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
317 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
318 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
319 | return 0; |
320 | ||
321 | if (priv->ibss_beacon->len > left) | |
322 | return 0; | |
323 | ||
324 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
325 | ||
326 | return priv->ibss_beacon->len; | |
327 | } | |
328 | ||
4a8a4322 | 329 | static int iwl3945_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 330 | { |
bb8c093b | 331 | struct iwl3945_frame *frame; |
b481de9c ZY |
332 | unsigned int frame_size; |
333 | int rc; | |
334 | u8 rate; | |
335 | ||
bb8c093b | 336 | frame = iwl3945_get_free_frame(priv); |
b481de9c ZY |
337 | |
338 | if (!frame) { | |
15b1687c | 339 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
340 | "command.\n"); |
341 | return -ENOMEM; | |
342 | } | |
343 | ||
8ccde88a | 344 | rate = iwl_rate_get_lowest_plcp(priv); |
b481de9c | 345 | |
bb8c093b | 346 | frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 347 | |
518099a8 | 348 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
349 | &frame->u.cmd[0]); |
350 | ||
bb8c093b | 351 | iwl3945_free_frame(priv, frame); |
b481de9c ZY |
352 | |
353 | return rc; | |
354 | } | |
355 | ||
4a8a4322 | 356 | static void iwl3945_unset_hw_params(struct iwl_priv *priv) |
b481de9c | 357 | { |
3832ec9d | 358 | if (priv->shared_virt) |
b481de9c | 359 | pci_free_consistent(priv->pci_dev, |
bb8c093b | 360 | sizeof(struct iwl3945_shared), |
3832ec9d AK |
361 | priv->shared_virt, |
362 | priv->shared_phys); | |
b481de9c ZY |
363 | } |
364 | ||
4a8a4322 | 365 | static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv, |
e039fa4a | 366 | struct ieee80211_tx_info *info, |
c2acea8e | 367 | struct iwl_device_cmd *cmd, |
b481de9c | 368 | struct sk_buff *skb_frag, |
6e21f15c | 369 | int sta_id) |
b481de9c | 370 | { |
e52119c5 | 371 | struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
c587de0b | 372 | struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo; |
b481de9c ZY |
373 | |
374 | switch (keyinfo->alg) { | |
375 | case ALG_CCMP: | |
e52119c5 WT |
376 | tx->sec_ctl = TX_CMD_SEC_CCM; |
377 | memcpy(tx->key, keyinfo->key, keyinfo->keylen); | |
e1623446 | 378 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); |
b481de9c ZY |
379 | break; |
380 | ||
381 | case ALG_TKIP: | |
b481de9c ZY |
382 | break; |
383 | ||
384 | case ALG_WEP: | |
e52119c5 | 385 | tx->sec_ctl = TX_CMD_SEC_WEP | |
e039fa4a | 386 | (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; |
b481de9c ZY |
387 | |
388 | if (keyinfo->keylen == 13) | |
e52119c5 | 389 | tx->sec_ctl |= TX_CMD_SEC_KEY128; |
b481de9c | 390 | |
e52119c5 | 391 | memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen); |
b481de9c | 392 | |
e1623446 | 393 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " |
e039fa4a | 394 | "with key %d\n", info->control.hw_key->hw_key_idx); |
b481de9c ZY |
395 | break; |
396 | ||
b481de9c | 397 | default: |
978785a3 | 398 | IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg); |
b481de9c ZY |
399 | break; |
400 | } | |
401 | } | |
402 | ||
403 | /* | |
404 | * handle build REPLY_TX command notification. | |
405 | */ | |
4a8a4322 | 406 | static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv, |
c2acea8e | 407 | struct iwl_device_cmd *cmd, |
e039fa4a | 408 | struct ieee80211_tx_info *info, |
e52119c5 | 409 | struct ieee80211_hdr *hdr, u8 std_id) |
b481de9c | 410 | { |
e52119c5 WT |
411 | struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
412 | __le32 tx_flags = tx->tx_flags; | |
fd7c8a40 | 413 | __le16 fc = hdr->frame_control; |
e6a9854b | 414 | u8 rc_flags = info->control.rates[0].flags; |
b481de9c | 415 | |
e52119c5 | 416 | tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
e039fa4a | 417 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
b481de9c | 418 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 419 | if (ieee80211_is_mgmt(fc)) |
b481de9c | 420 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 421 | if (ieee80211_is_probe_resp(fc) && |
b481de9c ZY |
422 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
423 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
424 | } else { | |
425 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
426 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
427 | } | |
428 | ||
e52119c5 | 429 | tx->sta_id = std_id; |
8b7b1e05 | 430 | if (ieee80211_has_morefrags(fc)) |
b481de9c ZY |
431 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
432 | ||
fd7c8a40 HH |
433 | if (ieee80211_is_data_qos(fc)) { |
434 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
e52119c5 | 435 | tx->tid_tspec = qc[0] & 0xf; |
b481de9c | 436 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 437 | } else { |
b481de9c | 438 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 439 | } |
b481de9c | 440 | |
e6a9854b | 441 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { |
b481de9c ZY |
442 | tx_flags |= TX_CMD_FLG_RTS_MSK; |
443 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
e6a9854b | 444 | } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
b481de9c ZY |
445 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
446 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
447 | } | |
448 | ||
449 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
450 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
451 | ||
452 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
453 | if (ieee80211_is_mgmt(fc)) { |
454 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
e52119c5 | 455 | tx->timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 456 | else |
e52119c5 | 457 | tx->timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 458 | } else { |
e52119c5 | 459 | tx->timeout.pm_frame_timeout = 0; |
5c8df2d5 | 460 | #ifdef CONFIG_IWLWIFI_LEDS |
ab53d8af MA |
461 | priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len); |
462 | #endif | |
463 | } | |
b481de9c | 464 | |
e52119c5 WT |
465 | tx->driver_txop = 0; |
466 | tx->tx_flags = tx_flags; | |
467 | tx->next_frame_len = 0; | |
b481de9c ZY |
468 | } |
469 | ||
b481de9c ZY |
470 | /* |
471 | * start REPLY_TX command process | |
472 | */ | |
4a8a4322 | 473 | static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
b481de9c ZY |
474 | { |
475 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 476 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
e52119c5 | 477 | struct iwl3945_tx_cmd *tx; |
188cf6c7 | 478 | struct iwl_tx_queue *txq = NULL; |
d20b3c65 | 479 | struct iwl_queue *q = NULL; |
c2acea8e JB |
480 | struct iwl_device_cmd *out_cmd; |
481 | struct iwl_cmd_meta *out_meta; | |
b481de9c ZY |
482 | dma_addr_t phys_addr; |
483 | dma_addr_t txcmd_phys; | |
e52119c5 | 484 | int txq_id = skb_get_queue_mapping(skb); |
df833b1d | 485 | u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */ |
54dbb525 TW |
486 | u8 id; |
487 | u8 unicast; | |
b481de9c | 488 | u8 sta_id; |
54dbb525 | 489 | u8 tid = 0; |
b481de9c | 490 | u16 seq_number = 0; |
fd7c8a40 | 491 | __le16 fc; |
b481de9c | 492 | u8 wait_write_ptr = 0; |
54dbb525 | 493 | u8 *qc = NULL; |
b481de9c ZY |
494 | unsigned long flags; |
495 | int rc; | |
496 | ||
497 | spin_lock_irqsave(&priv->lock, flags); | |
775a6e27 | 498 | if (iwl_is_rfkill(priv)) { |
e1623446 | 499 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); |
b481de9c ZY |
500 | goto drop_unlock; |
501 | } | |
502 | ||
e039fa4a | 503 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) { |
15b1687c | 504 | IWL_ERR(priv, "ERROR: No TX rate available.\n"); |
b481de9c ZY |
505 | goto drop_unlock; |
506 | } | |
507 | ||
508 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
509 | id = 0; | |
510 | ||
fd7c8a40 | 511 | fc = hdr->frame_control; |
b481de9c | 512 | |
d08853a3 | 513 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c | 514 | if (ieee80211_is_auth(fc)) |
e1623446 | 515 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); |
fd7c8a40 | 516 | else if (ieee80211_is_assoc_req(fc)) |
e1623446 | 517 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); |
fd7c8a40 | 518 | else if (ieee80211_is_reassoc_req(fc)) |
e1623446 | 519 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); |
b481de9c ZY |
520 | #endif |
521 | ||
aa065263 | 522 | /* drop all non-injected data frame if we are not associated */ |
914233d6 | 523 | if (ieee80211_is_data(fc) && |
aa065263 | 524 | !(info->flags & IEEE80211_TX_CTL_INJECTED) && |
8ccde88a | 525 | (!iwl_is_associated(priv) || |
05c914fe | 526 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) { |
e1623446 | 527 | IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n"); |
b481de9c ZY |
528 | goto drop_unlock; |
529 | } | |
530 | ||
531 | spin_unlock_irqrestore(&priv->lock, flags); | |
532 | ||
7294ec95 | 533 | hdr_len = ieee80211_hdrlen(fc); |
6440adb5 BC |
534 | |
535 | /* Find (or create) index into station table for destination station */ | |
aa065263 GS |
536 | if (info->flags & IEEE80211_TX_CTL_INJECTED) |
537 | sta_id = priv->hw_params.bcast_sta_id; | |
538 | else | |
539 | sta_id = iwl_get_sta_id(priv, hdr); | |
b481de9c | 540 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 541 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", |
e174961c | 542 | hdr->addr1); |
b481de9c ZY |
543 | goto drop; |
544 | } | |
545 | ||
e1623446 | 546 | IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id); |
b481de9c | 547 | |
fd7c8a40 HH |
548 | if (ieee80211_is_data_qos(fc)) { |
549 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 550 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
e6a6cf4c RC |
551 | if (unlikely(tid >= MAX_TID_COUNT)) |
552 | goto drop; | |
c587de0b | 553 | seq_number = priv->stations[sta_id].tid[tid].seq_number & |
b481de9c ZY |
554 | IEEE80211_SCTL_SEQ; |
555 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
556 | (hdr->seq_ctrl & | |
c1b4aa3f | 557 | cpu_to_le16(IEEE80211_SCTL_FRAG)); |
b481de9c ZY |
558 | seq_number += 0x10; |
559 | } | |
6440adb5 BC |
560 | |
561 | /* Descriptor for chosen Tx queue */ | |
188cf6c7 | 562 | txq = &priv->txq[txq_id]; |
b481de9c ZY |
563 | q = &txq->q; |
564 | ||
565 | spin_lock_irqsave(&priv->lock, flags); | |
566 | ||
fc4b6853 | 567 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 568 | |
6440adb5 | 569 | /* Set up driver data for this TFD */ |
dbb6654c | 570 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); |
fc4b6853 | 571 | txq->txb[q->write_ptr].skb[0] = skb; |
6440adb5 BC |
572 | |
573 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
188cf6c7 | 574 | out_cmd = txq->cmd[idx]; |
c2acea8e | 575 | out_meta = &txq->meta[idx]; |
e52119c5 | 576 | tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload; |
b481de9c | 577 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); |
e52119c5 | 578 | memset(tx, 0, sizeof(*tx)); |
6440adb5 BC |
579 | |
580 | /* | |
581 | * Set up the Tx-command (not MAC!) header. | |
582 | * Store the chosen Tx queue and TFD index within the sequence field; | |
583 | * after Tx, uCode's Tx response will return this value so driver can | |
584 | * locate the frame within the tx queue and do post-tx processing. | |
585 | */ | |
b481de9c ZY |
586 | out_cmd->hdr.cmd = REPLY_TX; |
587 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 588 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 BC |
589 | |
590 | /* Copy MAC header from skb into command buffer */ | |
e52119c5 | 591 | memcpy(tx->hdr, hdr, hdr_len); |
b481de9c | 592 | |
df833b1d RC |
593 | |
594 | if (info->control.hw_key) | |
595 | iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id); | |
596 | ||
597 | /* TODO need this for burst mode later on */ | |
598 | iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id); | |
599 | ||
600 | /* set is_hcca to 0; it probably will never be implemented */ | |
601 | iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0); | |
602 | ||
603 | /* Total # bytes to be transmitted */ | |
604 | len = (u16)skb->len; | |
605 | tx->len = cpu_to_le16(len); | |
606 | ||
20594eb0 | 607 | iwl_dbg_log_tx_data_frame(priv, len, hdr); |
22fdf3c9 | 608 | iwl_update_stats(priv, true, fc, len); |
df833b1d RC |
609 | tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; |
610 | tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
611 | ||
612 | if (!ieee80211_has_morefrags(hdr->frame_control)) { | |
613 | txq->need_update = 1; | |
614 | if (qc) | |
c587de0b | 615 | priv->stations[sta_id].tid[tid].seq_number = seq_number; |
df833b1d RC |
616 | } else { |
617 | wait_write_ptr = 1; | |
618 | txq->need_update = 0; | |
619 | } | |
620 | ||
621 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n", | |
622 | le16_to_cpu(out_cmd->hdr.sequence)); | |
623 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx->tx_flags)); | |
3d816c77 RC |
624 | iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx)); |
625 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr, | |
df833b1d RC |
626 | ieee80211_hdrlen(fc)); |
627 | ||
6440adb5 BC |
628 | /* |
629 | * Use the first empty entry in this queue's command buffer array | |
630 | * to contain the Tx command and MAC header concatenated together | |
631 | * (payload data will be in another buffer). | |
632 | * Size of this varies, due to varying MAC header length. | |
633 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
634 | * of the MAC header (device reads on dword boundaries). | |
635 | * We'll tell device about this padding later. | |
636 | */ | |
3832ec9d | 637 | len = sizeof(struct iwl3945_tx_cmd) + |
4c897253 | 638 | sizeof(struct iwl_cmd_header) + hdr_len; |
b481de9c ZY |
639 | |
640 | len_org = len; | |
641 | len = (len + 3) & ~3; | |
642 | ||
643 | if (len_org != len) | |
644 | len_org = 1; | |
645 | else | |
646 | len_org = 0; | |
647 | ||
6440adb5 BC |
648 | /* Physical address of this Tx command's header (not MAC header!), |
649 | * within command buffer array. */ | |
df833b1d RC |
650 | txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
651 | len, PCI_DMA_TODEVICE); | |
652 | /* we do not map meta data ... so we can safely access address to | |
653 | * provide to unmap command*/ | |
c2acea8e JB |
654 | pci_unmap_addr_set(out_meta, mapping, txcmd_phys); |
655 | pci_unmap_len_set(out_meta, len, len); | |
b481de9c | 656 | |
6440adb5 BC |
657 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
658 | * first entry */ | |
7aaa1d79 SO |
659 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
660 | txcmd_phys, len, 1, 0); | |
b481de9c | 661 | |
b481de9c | 662 | |
6440adb5 BC |
663 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
664 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
665 | len = skb->len - hdr_len; |
666 | if (len) { | |
667 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
668 | len, PCI_DMA_TODEVICE); | |
7aaa1d79 SO |
669 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
670 | phys_addr, len, | |
671 | 0, U32_PAD(len)); | |
b481de9c ZY |
672 | } |
673 | ||
b481de9c | 674 | |
6440adb5 | 675 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 676 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
4f3602c8 | 677 | rc = iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
678 | spin_unlock_irqrestore(&priv->lock, flags); |
679 | ||
680 | if (rc) | |
681 | return rc; | |
682 | ||
d20b3c65 | 683 | if ((iwl_queue_space(q) < q->high_mark) |
b481de9c ZY |
684 | && priv->mac80211_registered) { |
685 | if (wait_write_ptr) { | |
686 | spin_lock_irqsave(&priv->lock, flags); | |
687 | txq->need_update = 1; | |
4f3602c8 | 688 | iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
689 | spin_unlock_irqrestore(&priv->lock, flags); |
690 | } | |
691 | ||
e4e72fb4 | 692 | iwl_stop_queue(priv, skb_get_queue_mapping(skb)); |
b481de9c ZY |
693 | } |
694 | ||
695 | return 0; | |
696 | ||
697 | drop_unlock: | |
698 | spin_unlock_irqrestore(&priv->lock, flags); | |
699 | drop: | |
700 | return -1; | |
701 | } | |
702 | ||
c8b0e6e1 | 703 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
704 | |
705 | #include "iwl-spectrum.h" | |
706 | ||
707 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
708 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
709 | #define TIME_UNIT 1024 | |
710 | ||
711 | /* | |
712 | * extended beacon time format | |
713 | * time in usec will be changed into a 32-bit value in 8:24 format | |
714 | * the high 1 byte is the beacon counts | |
715 | * the lower 3 bytes is the time in usec within one beacon interval | |
716 | */ | |
717 | ||
bb8c093b | 718 | static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
719 | { |
720 | u32 quot; | |
721 | u32 rem; | |
722 | u32 interval = beacon_interval * 1024; | |
723 | ||
724 | if (!interval || !usec) | |
725 | return 0; | |
726 | ||
727 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
728 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
729 | ||
730 | return (quot << 24) + rem; | |
731 | } | |
732 | ||
733 | /* base is usually what we get from ucode with each received frame, | |
734 | * the same as HW timer counter counting down | |
735 | */ | |
736 | ||
bb8c093b | 737 | static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
738 | { |
739 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
740 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
741 | u32 interval = beacon_interval * TIME_UNIT; | |
742 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
743 | (addon & BEACON_TIME_MASK_HIGH); | |
744 | ||
745 | if (base_low > addon_low) | |
746 | res += base_low - addon_low; | |
747 | else if (base_low < addon_low) { | |
748 | res += interval + base_low - addon_low; | |
749 | res += (1 << 24); | |
750 | } else | |
751 | res += (1 << 24); | |
752 | ||
753 | return cpu_to_le32(res); | |
754 | } | |
755 | ||
4a8a4322 | 756 | static int iwl3945_get_measurement(struct iwl_priv *priv, |
b481de9c ZY |
757 | struct ieee80211_measurement_params *params, |
758 | u8 type) | |
759 | { | |
600c0e11 | 760 | struct iwl_spectrum_cmd spectrum; |
3d24a9f7 | 761 | struct iwl_rx_packet *res; |
c2d79b48 | 762 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
763 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
764 | .data = (void *)&spectrum, | |
c2acea8e | 765 | .flags = CMD_WANT_SKB, |
b481de9c ZY |
766 | }; |
767 | u32 add_time = le64_to_cpu(params->start_time); | |
768 | int rc; | |
769 | int spectrum_resp_status; | |
770 | int duration = le16_to_cpu(params->duration); | |
771 | ||
8ccde88a | 772 | if (iwl_is_associated(priv)) |
b481de9c | 773 | add_time = |
bb8c093b | 774 | iwl3945_usecs_to_beacons( |
b481de9c ZY |
775 | le64_to_cpu(params->start_time) - priv->last_tsf, |
776 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
777 | ||
778 | memset(&spectrum, 0, sizeof(spectrum)); | |
779 | ||
780 | spectrum.channel_count = cpu_to_le16(1); | |
781 | spectrum.flags = | |
782 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
783 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
784 | cmd.len = sizeof(spectrum); | |
785 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
786 | ||
8ccde88a | 787 | if (iwl_is_associated(priv)) |
b481de9c | 788 | spectrum.start_time = |
bb8c093b | 789 | iwl3945_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
790 | add_time, |
791 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
792 | else | |
793 | spectrum.start_time = 0; | |
794 | ||
795 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
796 | spectrum.channels[0].channel = params->channel; | |
797 | spectrum.channels[0].type = type; | |
8ccde88a | 798 | if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK) |
b481de9c ZY |
799 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | |
800 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
801 | ||
518099a8 | 802 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
803 | if (rc) |
804 | return rc; | |
805 | ||
c2acea8e | 806 | res = (struct iwl_rx_packet *)cmd.reply_skb->data; |
b481de9c | 807 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
15b1687c | 808 | IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n"); |
b481de9c ZY |
809 | rc = -EIO; |
810 | } | |
811 | ||
812 | spectrum_resp_status = le16_to_cpu(res->u.spectrum.status); | |
813 | switch (spectrum_resp_status) { | |
814 | case 0: /* Command will be handled */ | |
815 | if (res->u.spectrum.id != 0xff) { | |
e1623446 | 816 | IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n", |
bc434dd2 | 817 | res->u.spectrum.id); |
b481de9c ZY |
818 | priv->measurement_status &= ~MEASUREMENT_READY; |
819 | } | |
820 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
821 | rc = 0; | |
822 | break; | |
823 | ||
824 | case 1: /* Command will not be handled */ | |
825 | rc = -EAGAIN; | |
826 | break; | |
827 | } | |
828 | ||
c2acea8e | 829 | dev_kfree_skb_any(cmd.reply_skb); |
b481de9c ZY |
830 | |
831 | return rc; | |
832 | } | |
833 | #endif | |
834 | ||
4a8a4322 | 835 | static void iwl3945_rx_reply_alive(struct iwl_priv *priv, |
6100b588 | 836 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 837 | { |
3d24a9f7 TW |
838 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
839 | struct iwl_alive_resp *palive; | |
b481de9c ZY |
840 | struct delayed_work *pwork; |
841 | ||
842 | palive = &pkt->u.alive_frame; | |
843 | ||
e1623446 | 844 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
845 | "0x%01X 0x%01X\n", |
846 | palive->is_valid, palive->ver_type, | |
847 | palive->ver_subtype); | |
848 | ||
849 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 850 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
3d24a9f7 TW |
851 | memcpy(&priv->card_alive_init, &pkt->u.alive_frame, |
852 | sizeof(struct iwl_alive_resp)); | |
b481de9c ZY |
853 | pwork = &priv->init_alive_start; |
854 | } else { | |
e1623446 | 855 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 856 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
3d24a9f7 | 857 | sizeof(struct iwl_alive_resp)); |
b481de9c | 858 | pwork = &priv->alive_start; |
bb8c093b | 859 | iwl3945_disable_events(priv); |
b481de9c ZY |
860 | } |
861 | ||
862 | /* We delay the ALIVE response by 5ms to | |
863 | * give the HW RF Kill time to activate... */ | |
864 | if (palive->is_valid == UCODE_VALID_OK) | |
865 | queue_delayed_work(priv->workqueue, pwork, | |
866 | msecs_to_jiffies(5)); | |
867 | else | |
39aadf8c | 868 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
869 | } |
870 | ||
4a8a4322 | 871 | static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv, |
6100b588 | 872 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 873 | { |
c7e035a9 | 874 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d24a9f7 | 875 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
c7e035a9 | 876 | #endif |
b481de9c | 877 | |
e1623446 | 878 | IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); |
b481de9c ZY |
879 | return; |
880 | } | |
881 | ||
bb8c093b | 882 | static void iwl3945_bg_beacon_update(struct work_struct *work) |
b481de9c | 883 | { |
4a8a4322 AK |
884 | struct iwl_priv *priv = |
885 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
886 | struct sk_buff *beacon; |
887 | ||
888 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 889 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
890 | |
891 | if (!beacon) { | |
15b1687c | 892 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
893 | return; |
894 | } | |
895 | ||
896 | mutex_lock(&priv->mutex); | |
897 | /* new beacon skb is allocated every time; dispose previous.*/ | |
898 | if (priv->ibss_beacon) | |
899 | dev_kfree_skb(priv->ibss_beacon); | |
900 | ||
901 | priv->ibss_beacon = beacon; | |
902 | mutex_unlock(&priv->mutex); | |
903 | ||
bb8c093b | 904 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
905 | } |
906 | ||
4a8a4322 | 907 | static void iwl3945_rx_beacon_notif(struct iwl_priv *priv, |
6100b588 | 908 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 909 | { |
d08853a3 | 910 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d24a9f7 | 911 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
bb8c093b | 912 | struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status); |
b481de9c ZY |
913 | u8 rate = beacon->beacon_notify_hdr.rate; |
914 | ||
e1623446 | 915 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c ZY |
916 | "tsf %d %d rate %d\n", |
917 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
918 | beacon->beacon_notify_hdr.failure_frame, | |
919 | le32_to_cpu(beacon->ibss_mgr_status), | |
920 | le32_to_cpu(beacon->high_tsf), | |
921 | le32_to_cpu(beacon->low_tsf), rate); | |
922 | #endif | |
923 | ||
05c914fe | 924 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
925 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
926 | queue_work(priv->workqueue, &priv->beacon_update); | |
927 | } | |
928 | ||
b481de9c ZY |
929 | /* Handle notification from uCode that card's power state is changing |
930 | * due to software, hardware, or critical temperature RFKILL */ | |
4a8a4322 | 931 | static void iwl3945_rx_card_state_notif(struct iwl_priv *priv, |
6100b588 | 932 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 933 | { |
3d24a9f7 | 934 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
935 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
936 | unsigned long status = priv->status; | |
937 | ||
4c423a2b | 938 | IWL_WARN(priv, "Card state received: HW:%s SW:%s\n", |
b481de9c ZY |
939 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
940 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
941 | ||
5d49f498 | 942 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
943 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
944 | ||
945 | if (flags & HW_CARD_DISABLED) | |
946 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
947 | else | |
948 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
949 | ||
950 | ||
af0053d6 | 951 | iwl_scan_cancel(priv); |
b481de9c ZY |
952 | |
953 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
954 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
955 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
956 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
957 | else |
958 | wake_up_interruptible(&priv->wait_command_queue); | |
959 | } | |
960 | ||
961 | /** | |
bb8c093b | 962 | * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
963 | * |
964 | * Setup the RX handlers for each of the reply types sent from the uCode | |
965 | * to the host. | |
966 | * | |
967 | * This function chains into the hardware specific files for them to setup | |
968 | * any hardware specific handlers as well. | |
969 | */ | |
4a8a4322 | 970 | static void iwl3945_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 971 | { |
bb8c093b CH |
972 | priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive; |
973 | priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta; | |
261b9c33 | 974 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
8ccde88a | 975 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; |
030f05ed | 976 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 977 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
030f05ed | 978 | iwl_rx_pm_debug_statistics_notif; |
bb8c093b | 979 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif; |
b481de9c | 980 | |
9fbab516 BC |
981 | /* |
982 | * The same handler is used for both the REPLY to a discrete | |
983 | * statistics request from the host as well as for the periodic | |
984 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 985 | */ |
bb8c093b CH |
986 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics; |
987 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics; | |
b481de9c | 988 | |
261b9c33 | 989 | iwl_setup_spectrum_handlers(priv); |
cade0eb2 | 990 | iwl_setup_rx_scan_handlers(priv); |
bb8c093b | 991 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif; |
b481de9c | 992 | |
9fbab516 | 993 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 994 | iwl3945_hw_rx_handler_setup(priv); |
b481de9c ZY |
995 | } |
996 | ||
b481de9c ZY |
997 | /************************** RX-FUNCTIONS ****************************/ |
998 | /* | |
999 | * Rx theory of operation | |
1000 | * | |
1001 | * The host allocates 32 DMA target addresses and passes the host address | |
1002 | * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is | |
1003 | * 0 to 31 | |
1004 | * | |
1005 | * Rx Queue Indexes | |
1006 | * The host/firmware share two index registers for managing the Rx buffers. | |
1007 | * | |
1008 | * The READ index maps to the first position that the firmware may be writing | |
1009 | * to -- the driver can read up to (but not including) this position and get | |
1010 | * good data. | |
1011 | * The READ index is managed by the firmware once the card is enabled. | |
1012 | * | |
1013 | * The WRITE index maps to the last position the driver has read from -- the | |
1014 | * position preceding WRITE is the last slot the firmware can place a packet. | |
1015 | * | |
1016 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
1017 | * WRITE = READ. | |
1018 | * | |
9fbab516 | 1019 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
1020 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
1021 | * | |
9fbab516 | 1022 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
1023 | * and fire the RX interrupt. The driver can then query the READ index and |
1024 | * process as many packets as possible, moving the WRITE index forward as it | |
1025 | * resets the Rx queue buffers with new memory. | |
1026 | * | |
1027 | * The management in the driver is as follows: | |
1028 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
1029 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 1030 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 1031 | * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
1032 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
1033 | * 'processed' and 'read' driver indexes as well) | |
1034 | * + A received packet is processed and handed to the kernel network stack, | |
1035 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
1036 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
1037 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
1038 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
1039 | * were enough free buffers and RX_STALLED is set it is cleared. | |
1040 | * | |
1041 | * | |
1042 | * Driver sequence: | |
1043 | * | |
9fbab516 | 1044 | * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls |
bb8c093b | 1045 | * iwl3945_rx_queue_restock |
9fbab516 | 1046 | * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
1047 | * queue, updates firmware pointers, and updates |
1048 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 1049 | * are available, schedules iwl3945_rx_replenish |
b481de9c ZY |
1050 | * |
1051 | * -- enable interrupts -- | |
6100b588 | 1052 | * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the |
b481de9c ZY |
1053 | * READ INDEX, detaching the SKB from the pool. |
1054 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 1055 | * Calls iwl3945_rx_queue_restock to refill any empty |
b481de9c ZY |
1056 | * slots. |
1057 | * ... | |
1058 | * | |
1059 | */ | |
1060 | ||
b481de9c | 1061 | /** |
9fbab516 | 1062 | * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 1063 | */ |
4a8a4322 | 1064 | static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv, |
b481de9c ZY |
1065 | dma_addr_t dma_addr) |
1066 | { | |
1067 | return cpu_to_le32((u32)dma_addr); | |
1068 | } | |
1069 | ||
1070 | /** | |
bb8c093b | 1071 | * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 1072 | * |
9fbab516 | 1073 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 1074 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 1075 | * as we can, pulling from rx_free. |
b481de9c ZY |
1076 | * |
1077 | * This moves the 'write' index forward to catch up with 'processed', and | |
1078 | * also updates the memory address in the firmware to reference the new | |
1079 | * target buffer. | |
1080 | */ | |
4a8a4322 | 1081 | static int iwl3945_rx_queue_restock(struct iwl_priv *priv) |
b481de9c | 1082 | { |
cc2f362c | 1083 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1084 | struct list_head *element; |
6100b588 | 1085 | struct iwl_rx_mem_buffer *rxb; |
b481de9c ZY |
1086 | unsigned long flags; |
1087 | int write, rc; | |
1088 | ||
1089 | spin_lock_irqsave(&rxq->lock, flags); | |
1090 | write = rxq->write & ~0x7; | |
37d68317 | 1091 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 1092 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 1093 | element = rxq->rx_free.next; |
6100b588 | 1094 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
b481de9c | 1095 | list_del(element); |
6440adb5 BC |
1096 | |
1097 | /* Point to Rx buffer via next RBD in circular buffer */ | |
6100b588 | 1098 | rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr); |
b481de9c ZY |
1099 | rxq->queue[rxq->write] = rxb; |
1100 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
1101 | rxq->free_count--; | |
1102 | } | |
1103 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1104 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
1105 | * refill it */ | |
1106 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
1107 | queue_work(priv->workqueue, &priv->rx_replenish); | |
1108 | ||
1109 | ||
6440adb5 BC |
1110 | /* If we've added more space for the firmware to place data, tell it. |
1111 | * Increment device's write pointer in multiples of 8. */ | |
d14d4440 | 1112 | if ((rxq->write_actual != (rxq->write & ~0x7)) |
b481de9c ZY |
1113 | || (abs(rxq->write - rxq->read) > 7)) { |
1114 | spin_lock_irqsave(&rxq->lock, flags); | |
1115 | rxq->need_update = 1; | |
1116 | spin_unlock_irqrestore(&rxq->lock, flags); | |
141c43a3 | 1117 | rc = iwl_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
1118 | if (rc) |
1119 | return rc; | |
1120 | } | |
1121 | ||
1122 | return 0; | |
1123 | } | |
1124 | ||
1125 | /** | |
bb8c093b | 1126 | * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
1127 | * |
1128 | * When moving to rx_free an SKB is allocated for the slot. | |
1129 | * | |
bb8c093b | 1130 | * Also restock the Rx queue via iwl3945_rx_queue_restock. |
01ebd063 | 1131 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 1132 | */ |
d14d4440 | 1133 | static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority) |
b481de9c | 1134 | { |
cc2f362c | 1135 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1136 | struct list_head *element; |
6100b588 | 1137 | struct iwl_rx_mem_buffer *rxb; |
de0bd508 | 1138 | struct sk_buff *skb; |
b481de9c | 1139 | unsigned long flags; |
72240498 AK |
1140 | |
1141 | while (1) { | |
1142 | spin_lock_irqsave(&rxq->lock, flags); | |
1143 | ||
1144 | if (list_empty(&rxq->rx_used)) { | |
1145 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1146 | return; | |
1147 | } | |
72240498 | 1148 | spin_unlock_irqrestore(&rxq->lock, flags); |
6440adb5 | 1149 | |
f82a924c RC |
1150 | if (rxq->free_count > RX_LOW_WATERMARK) |
1151 | priority |= __GFP_NOWARN; | |
6440adb5 | 1152 | /* Alloc a new receive buffer */ |
de0bd508 RC |
1153 | skb = alloc_skb(priv->hw_params.rx_buf_size, priority); |
1154 | if (!skb) { | |
b481de9c | 1155 | if (net_ratelimit()) |
f82a924c RC |
1156 | IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n"); |
1157 | if ((rxq->free_count <= RX_LOW_WATERMARK) && | |
1158 | net_ratelimit()) | |
1159 | IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n", | |
1160 | priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", | |
1161 | rxq->free_count); | |
b481de9c ZY |
1162 | /* We don't reschedule replenish work here -- we will |
1163 | * call the restock method and if it still needs | |
1164 | * more buffers it will schedule replenish */ | |
1165 | break; | |
1166 | } | |
12342c47 | 1167 | |
de0bd508 RC |
1168 | spin_lock_irqsave(&rxq->lock, flags); |
1169 | if (list_empty(&rxq->rx_used)) { | |
1170 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1171 | dev_kfree_skb_any(skb); | |
1172 | return; | |
1173 | } | |
1174 | element = rxq->rx_used.next; | |
1175 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
1176 | list_del(element); | |
1177 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1178 | ||
1179 | rxb->skb = skb; | |
1180 | ||
12342c47 ZY |
1181 | /* If radiotap head is required, reserve some headroom here. |
1182 | * The physical head count is a variable rx_stats->phy_count. | |
1183 | * We reserve 4 bytes here. Plus these extra bytes, the | |
1184 | * headroom of the physical head should be enough for the | |
1185 | * radiotap head that iwl3945 supported. See iwl3945_rt. | |
1186 | */ | |
1187 | skb_reserve(rxb->skb, 4); | |
1188 | ||
6440adb5 | 1189 | /* Get physical address of RB/SKB */ |
1e33dc64 WT |
1190 | rxb->real_dma_addr = pci_map_single(priv->pci_dev, |
1191 | rxb->skb->data, | |
1192 | priv->hw_params.rx_buf_size, | |
1193 | PCI_DMA_FROMDEVICE); | |
72240498 AK |
1194 | |
1195 | spin_lock_irqsave(&rxq->lock, flags); | |
b481de9c | 1196 | list_add_tail(&rxb->list, &rxq->rx_free); |
72240498 | 1197 | priv->alloc_rxb_skb++; |
b481de9c | 1198 | rxq->free_count++; |
72240498 | 1199 | spin_unlock_irqrestore(&rxq->lock, flags); |
b481de9c | 1200 | } |
5c0eef96 MA |
1201 | } |
1202 | ||
df833b1d RC |
1203 | void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
1204 | { | |
1205 | unsigned long flags; | |
1206 | int i; | |
1207 | spin_lock_irqsave(&rxq->lock, flags); | |
1208 | INIT_LIST_HEAD(&rxq->rx_free); | |
1209 | INIT_LIST_HEAD(&rxq->rx_used); | |
1210 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
1211 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
1212 | /* In the reset function, these buffers may have been allocated | |
1213 | * to an SKB, so we need to unmap and free potential storage */ | |
1214 | if (rxq->pool[i].skb != NULL) { | |
1215 | pci_unmap_single(priv->pci_dev, | |
1216 | rxq->pool[i].real_dma_addr, | |
1217 | priv->hw_params.rx_buf_size, | |
1218 | PCI_DMA_FROMDEVICE); | |
1219 | priv->alloc_rxb_skb--; | |
1220 | dev_kfree_skb(rxq->pool[i].skb); | |
1221 | rxq->pool[i].skb = NULL; | |
1222 | } | |
1223 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
1224 | } | |
1225 | ||
1226 | /* Set us so that we have processed and used all buffers, but have | |
1227 | * not restocked the Rx queue with fresh buffers */ | |
1228 | rxq->read = rxq->write = 0; | |
1229 | rxq->free_count = 0; | |
d14d4440 | 1230 | rxq->write_actual = 0; |
df833b1d RC |
1231 | spin_unlock_irqrestore(&rxq->lock, flags); |
1232 | } | |
df833b1d | 1233 | |
5c0eef96 MA |
1234 | void iwl3945_rx_replenish(void *data) |
1235 | { | |
4a8a4322 | 1236 | struct iwl_priv *priv = data; |
5c0eef96 MA |
1237 | unsigned long flags; |
1238 | ||
d14d4440 | 1239 | iwl3945_rx_allocate(priv, GFP_KERNEL); |
b481de9c ZY |
1240 | |
1241 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 1242 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
1243 | spin_unlock_irqrestore(&priv->lock, flags); |
1244 | } | |
1245 | ||
d14d4440 AK |
1246 | static void iwl3945_rx_replenish_now(struct iwl_priv *priv) |
1247 | { | |
1248 | iwl3945_rx_allocate(priv, GFP_ATOMIC); | |
1249 | ||
1250 | iwl3945_rx_queue_restock(priv); | |
1251 | } | |
1252 | ||
1253 | ||
df833b1d RC |
1254 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. |
1255 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
1256 | * This free routine walks the list of POOL entries and if SKB is set to | |
1257 | * non NULL it is unmapped and freed | |
1258 | */ | |
1259 | static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
1260 | { | |
1261 | int i; | |
1262 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
1263 | if (rxq->pool[i].skb != NULL) { | |
1264 | pci_unmap_single(priv->pci_dev, | |
1265 | rxq->pool[i].real_dma_addr, | |
1266 | priv->hw_params.rx_buf_size, | |
1267 | PCI_DMA_FROMDEVICE); | |
1268 | dev_kfree_skb(rxq->pool[i].skb); | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
1273 | rxq->dma_addr); | |
1274 | pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status), | |
1275 | rxq->rb_stts, rxq->rb_stts_dma); | |
1276 | rxq->bd = NULL; | |
1277 | rxq->rb_stts = NULL; | |
1278 | } | |
df833b1d RC |
1279 | |
1280 | ||
b481de9c ZY |
1281 | /* Convert linear signal-to-noise ratio into dB */ |
1282 | static u8 ratio2dB[100] = { | |
1283 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
1284 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
1285 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
1286 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
1287 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
1288 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
1289 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
1290 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
1291 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
1292 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
1293 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
1294 | }; | |
1295 | ||
1296 | /* Calculates a relative dB value from a ratio of linear | |
1297 | * (i.e. not dB) signal levels. | |
1298 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 1299 | int iwl3945_calc_db_from_ratio(int sig_ratio) |
b481de9c | 1300 | { |
221c80cf AB |
1301 | /* 1000:1 or higher just report as 60 dB */ |
1302 | if (sig_ratio >= 1000) | |
b481de9c ZY |
1303 | return 60; |
1304 | ||
221c80cf | 1305 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 1306 | * add 20 dB to make up for divide by 10 */ |
221c80cf | 1307 | if (sig_ratio >= 100) |
3ac7f146 | 1308 | return 20 + (int)ratio2dB[sig_ratio/10]; |
b481de9c ZY |
1309 | |
1310 | /* We shouldn't see this */ | |
1311 | if (sig_ratio < 1) | |
1312 | return 0; | |
1313 | ||
1314 | /* Use table for ratios 1:1 - 99:1 */ | |
1315 | return (int)ratio2dB[sig_ratio]; | |
1316 | } | |
1317 | ||
1318 | #define PERFECT_RSSI (-20) /* dBm */ | |
1319 | #define WORST_RSSI (-95) /* dBm */ | |
1320 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
1321 | ||
1322 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
1323 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
1324 | * about formulas used below. */ | |
bb8c093b | 1325 | int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm) |
b481de9c ZY |
1326 | { |
1327 | int sig_qual; | |
1328 | int degradation = PERFECT_RSSI - rssi_dbm; | |
1329 | ||
1330 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
1331 | * as indicator; formula is (signal dbm - noise dbm). | |
1332 | * SNR at or above 40 is a great signal (100%). | |
1333 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
1334 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
1335 | if (noise_dbm) { | |
1336 | if (rssi_dbm - noise_dbm >= 40) | |
1337 | return 100; | |
1338 | else if (rssi_dbm < noise_dbm) | |
1339 | return 0; | |
1340 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
1341 | ||
1342 | /* Else use just the signal level. | |
1343 | * This formula is a least squares fit of data points collected and | |
1344 | * compared with a reference system that had a percentage (%) display | |
1345 | * for signal quality. */ | |
1346 | } else | |
1347 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
1348 | (15 * RSSI_RANGE + 62 * degradation)) / | |
1349 | (RSSI_RANGE * RSSI_RANGE); | |
1350 | ||
1351 | if (sig_qual > 100) | |
1352 | sig_qual = 100; | |
1353 | else if (sig_qual < 1) | |
1354 | sig_qual = 0; | |
1355 | ||
1356 | return sig_qual; | |
1357 | } | |
1358 | ||
1359 | /** | |
9fbab516 | 1360 | * iwl3945_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
1361 | * |
1362 | * Uses the priv->rx_handlers callback function array to invoke | |
1363 | * the appropriate handlers, including command responses, | |
1364 | * frame-received notifications, and other notifications. | |
1365 | */ | |
4a8a4322 | 1366 | static void iwl3945_rx_handle(struct iwl_priv *priv) |
b481de9c | 1367 | { |
6100b588 | 1368 | struct iwl_rx_mem_buffer *rxb; |
3d24a9f7 | 1369 | struct iwl_rx_packet *pkt; |
cc2f362c | 1370 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
1371 | u32 r, i; |
1372 | int reclaim; | |
1373 | unsigned long flags; | |
5c0eef96 | 1374 | u8 fill_rx = 0; |
d68ab680 | 1375 | u32 count = 8; |
d14d4440 | 1376 | int total_empty = 0; |
b481de9c | 1377 | |
6440adb5 BC |
1378 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
1379 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8cd812bc | 1380 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
1381 | i = rxq->read; |
1382 | ||
d14d4440 AK |
1383 | /* calculate total frames need to be restock after handling RX */ |
1384 | total_empty = r - priv->rxq.write_actual; | |
1385 | if (total_empty < 0) | |
1386 | total_empty += RX_QUEUE_SIZE; | |
1387 | ||
1388 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 | 1389 | fill_rx = 1; |
b481de9c ZY |
1390 | /* Rx interrupt, but nothing sent from uCode */ |
1391 | if (i == r) | |
af472a95 | 1392 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c ZY |
1393 | |
1394 | while (i != r) { | |
1395 | rxb = rxq->queue[i]; | |
1396 | ||
9fbab516 | 1397 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
1398 | * then a bug has been introduced in the queue refilling |
1399 | * routines -- catch it here */ | |
1400 | BUG_ON(rxb == NULL); | |
1401 | ||
1402 | rxq->queue[i] = NULL; | |
1403 | ||
df833b1d RC |
1404 | pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, |
1405 | priv->hw_params.rx_buf_size, | |
1406 | PCI_DMA_FROMDEVICE); | |
3d24a9f7 | 1407 | pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
1408 | |
1409 | /* Reclaim a command buffer only if this packet is a response | |
1410 | * to a (driver-originated) command. | |
1411 | * If the packet (e.g. Rx frame) originated from uCode, | |
1412 | * there is no command buffer to reclaim. | |
1413 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
1414 | * but apparently a few don't get set; catch them here. */ | |
1415 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
1416 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
1417 | (pkt->hdr.cmd != REPLY_TX); | |
1418 | ||
1419 | /* Based on type of command response or notification, | |
1420 | * handle those that need handling via function in | |
bb8c093b | 1421 | * rx_handlers table. See iwl3945_setup_rx_handlers() */ |
b481de9c | 1422 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
af472a95 | 1423 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i, |
b481de9c ZY |
1424 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
1425 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); | |
86ddbf62 | 1426 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
b481de9c ZY |
1427 | } else { |
1428 | /* No handling needed */ | |
af472a95 | 1429 | IWL_DEBUG_RX(priv, "r %d i %d No handler needed for %s, 0x%02x\n", |
b481de9c ZY |
1430 | r, i, get_cmd_string(pkt->hdr.cmd), |
1431 | pkt->hdr.cmd); | |
1432 | } | |
1433 | ||
1434 | if (reclaim) { | |
9fbab516 | 1435 | /* Invoke any callbacks, transfer the skb to caller, and |
518099a8 | 1436 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
1437 | * as we reclaim the driver command queue */ |
1438 | if (rxb && rxb->skb) | |
732587ab | 1439 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 1440 | else |
39aadf8c | 1441 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
1442 | } |
1443 | ||
1444 | /* For now we just don't re-use anything. We can tweak this | |
1445 | * later to try and re-use notification packets and SKBs that | |
1446 | * fail to Rx correctly */ | |
1447 | if (rxb->skb != NULL) { | |
1448 | priv->alloc_rxb_skb--; | |
1449 | dev_kfree_skb_any(rxb->skb); | |
1450 | rxb->skb = NULL; | |
1451 | } | |
1452 | ||
b481de9c ZY |
1453 | spin_lock_irqsave(&rxq->lock, flags); |
1454 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
1455 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1456 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
1457 | /* If there are a lot of unused frames, |
1458 | * restock the Rx queue so ucode won't assert. */ | |
1459 | if (fill_rx) { | |
1460 | count++; | |
1461 | if (count >= 8) { | |
1462 | priv->rxq.read = i; | |
d14d4440 | 1463 | iwl3945_rx_replenish_now(priv); |
5c0eef96 MA |
1464 | count = 0; |
1465 | } | |
1466 | } | |
b481de9c ZY |
1467 | } |
1468 | ||
1469 | /* Backtrack one entry */ | |
1470 | priv->rxq.read = i; | |
d14d4440 AK |
1471 | if (fill_rx) |
1472 | iwl3945_rx_replenish_now(priv); | |
1473 | else | |
1474 | iwl3945_rx_queue_restock(priv); | |
b481de9c ZY |
1475 | } |
1476 | ||
0359facc | 1477 | /* call this function to flush any scheduled tasklet */ |
4a8a4322 | 1478 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) |
0359facc | 1479 | { |
a96a27f9 | 1480 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1481 | synchronize_irq(priv->pci_dev->irq); |
1482 | tasklet_kill(&priv->irq_tasklet); | |
1483 | } | |
1484 | ||
b7a79404 | 1485 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1486 | static const char *desc_lookup(int i) |
1487 | { | |
1488 | switch (i) { | |
1489 | case 1: | |
1490 | return "FAIL"; | |
1491 | case 2: | |
1492 | return "BAD_PARAM"; | |
1493 | case 3: | |
1494 | return "BAD_CHECKSUM"; | |
1495 | case 4: | |
1496 | return "NMI_INTERRUPT"; | |
1497 | case 5: | |
1498 | return "SYSASSERT"; | |
1499 | case 6: | |
1500 | return "FATAL_ERROR"; | |
1501 | } | |
1502 | ||
1503 | return "UNKNOWN"; | |
1504 | } | |
1505 | ||
1506 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1507 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1508 | ||
b7a79404 | 1509 | void iwl3945_dump_nic_error_log(struct iwl_priv *priv) |
b481de9c ZY |
1510 | { |
1511 | u32 i; | |
1512 | u32 desc, time, count, base, data1; | |
1513 | u32 blink1, blink2, ilink1, ilink2; | |
b481de9c ZY |
1514 | |
1515 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
1516 | ||
bb8c093b | 1517 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1518 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); |
b481de9c ZY |
1519 | return; |
1520 | } | |
1521 | ||
b481de9c | 1522 | |
5d49f498 | 1523 | count = iwl_read_targ_mem(priv, base); |
b481de9c ZY |
1524 | |
1525 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
15b1687c WT |
1526 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); |
1527 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1528 | priv->status, count); | |
b481de9c ZY |
1529 | } |
1530 | ||
15b1687c | 1531 | IWL_ERR(priv, "Desc Time asrtPC blink2 " |
b481de9c ZY |
1532 | "ilink1 nmiPC Line\n"); |
1533 | for (i = ERROR_START_OFFSET; | |
1534 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
1535 | i += ERROR_ELEM_SIZE) { | |
5d49f498 | 1536 | desc = iwl_read_targ_mem(priv, base + i); |
b481de9c | 1537 | time = |
5d49f498 | 1538 | iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32)); |
b481de9c | 1539 | blink1 = |
5d49f498 | 1540 | iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32)); |
b481de9c | 1541 | blink2 = |
5d49f498 | 1542 | iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32)); |
b481de9c | 1543 | ilink1 = |
5d49f498 | 1544 | iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32)); |
b481de9c | 1545 | ilink2 = |
5d49f498 | 1546 | iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32)); |
b481de9c | 1547 | data1 = |
5d49f498 | 1548 | iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32)); |
b481de9c | 1549 | |
15b1687c WT |
1550 | IWL_ERR(priv, |
1551 | "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", | |
1552 | desc_lookup(desc), desc, time, blink1, blink2, | |
1553 | ilink1, ilink2, data1); | |
b481de9c ZY |
1554 | } |
1555 | ||
b481de9c ZY |
1556 | } |
1557 | ||
f58177b9 | 1558 | #define EVENT_START_OFFSET (6 * sizeof(u32)) |
b481de9c ZY |
1559 | |
1560 | /** | |
bb8c093b | 1561 | * iwl3945_print_event_log - Dump error event log to syslog |
b481de9c | 1562 | * |
b481de9c | 1563 | */ |
4a8a4322 | 1564 | static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx, |
b481de9c ZY |
1565 | u32 num_events, u32 mode) |
1566 | { | |
1567 | u32 i; | |
1568 | u32 base; /* SRAM byte address of event log header */ | |
1569 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1570 | u32 ptr; /* SRAM byte address of log data */ | |
1571 | u32 ev, time, data; /* event log data */ | |
1572 | ||
1573 | if (num_events == 0) | |
1574 | return; | |
1575 | ||
1576 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1577 | ||
1578 | if (mode == 0) | |
1579 | event_size = 2 * sizeof(u32); | |
1580 | else | |
1581 | event_size = 3 * sizeof(u32); | |
1582 | ||
1583 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1584 | ||
1585 | /* "time" is actually "data" for mode 0 (no timestamp). | |
1586 | * place event id # at far right for easier visual parsing. */ | |
1587 | for (i = 0; i < num_events; i++) { | |
5d49f498 | 1588 | ev = iwl_read_targ_mem(priv, ptr); |
b481de9c | 1589 | ptr += sizeof(u32); |
5d49f498 | 1590 | time = iwl_read_targ_mem(priv, ptr); |
b481de9c | 1591 | ptr += sizeof(u32); |
15b1687c WT |
1592 | if (mode == 0) { |
1593 | /* data, ev */ | |
1594 | IWL_ERR(priv, "0x%08x\t%04u\n", time, ev); | |
1595 | } else { | |
5d49f498 | 1596 | data = iwl_read_targ_mem(priv, ptr); |
b481de9c | 1597 | ptr += sizeof(u32); |
15b1687c | 1598 | IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev); |
b481de9c ZY |
1599 | } |
1600 | } | |
1601 | } | |
1602 | ||
b7a79404 | 1603 | void iwl3945_dump_nic_event_log(struct iwl_priv *priv) |
b481de9c | 1604 | { |
b481de9c ZY |
1605 | u32 base; /* SRAM byte address of event log header */ |
1606 | u32 capacity; /* event log capacity in # entries */ | |
1607 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1608 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1609 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1610 | u32 size; /* # entries that we'll print */ | |
1611 | ||
1612 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 1613 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1614 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); |
b481de9c ZY |
1615 | return; |
1616 | } | |
1617 | ||
b481de9c | 1618 | /* event log header */ |
5d49f498 AK |
1619 | capacity = iwl_read_targ_mem(priv, base); |
1620 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1621 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1622 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c ZY |
1623 | |
1624 | size = num_wraps ? capacity : next_entry; | |
1625 | ||
1626 | /* bail out if nothing in log */ | |
1627 | if (size == 0) { | |
15b1687c | 1628 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); |
b481de9c ZY |
1629 | return; |
1630 | } | |
1631 | ||
15b1687c | 1632 | IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n", |
b481de9c ZY |
1633 | size, num_wraps); |
1634 | ||
1635 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
1636 | * i.e the next one that uCode would fill. */ | |
1637 | if (num_wraps) | |
bb8c093b | 1638 | iwl3945_print_event_log(priv, next_entry, |
b481de9c ZY |
1639 | capacity - next_entry, mode); |
1640 | ||
1641 | /* (then/else) start at top of log */ | |
bb8c093b | 1642 | iwl3945_print_event_log(priv, 0, next_entry, mode); |
b481de9c | 1643 | |
b481de9c | 1644 | } |
b7a79404 RC |
1645 | #else |
1646 | void iwl3945_dump_nic_event_log(struct iwl_priv *priv) | |
1647 | { | |
1648 | } | |
1649 | ||
1650 | void iwl3945_dump_nic_error_log(struct iwl_priv *priv) | |
1651 | { | |
1652 | } | |
1653 | ||
1654 | #endif | |
b481de9c | 1655 | |
4a8a4322 | 1656 | static void iwl3945_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
1657 | { |
1658 | u32 inta, handled = 0; | |
1659 | u32 inta_fh; | |
1660 | unsigned long flags; | |
d08853a3 | 1661 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1662 | u32 inta_mask; |
1663 | #endif | |
1664 | ||
1665 | spin_lock_irqsave(&priv->lock, flags); | |
1666 | ||
1667 | /* Ack/clear/reset pending uCode interrupts. | |
1668 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1669 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
5d49f498 AK |
1670 | inta = iwl_read32(priv, CSR_INT); |
1671 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1672 | |
1673 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1674 | * Any new interrupts that happen after this, either while we're | |
1675 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
5d49f498 AK |
1676 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1677 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1678 | |
d08853a3 | 1679 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1680 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 1681 | /* just for debug */ |
5d49f498 | 1682 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1683 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1684 | inta, inta_mask, inta_fh); |
1685 | } | |
1686 | #endif | |
1687 | ||
1688 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
1689 | * atomic, make sure that inta covers all the interrupts that | |
1690 | * we've discovered, even if FH interrupt came in just after | |
1691 | * reading CSR_INT. */ | |
6f83eaa1 | 1692 | if (inta_fh & CSR39_FH_INT_RX_MASK) |
b481de9c | 1693 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1694 | if (inta_fh & CSR39_FH_INT_TX_MASK) |
b481de9c ZY |
1695 | inta |= CSR_INT_BIT_FH_TX; |
1696 | ||
1697 | /* Now service all interrupt bits discovered above. */ | |
1698 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1699 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
1700 | |
1701 | /* Tell the device to stop sending interrupts */ | |
ed3b932e | 1702 | iwl_disable_interrupts(priv); |
b481de9c | 1703 | |
86ddbf62 | 1704 | priv->isr_stats.hw++; |
8ccde88a | 1705 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1706 | |
1707 | handled |= CSR_INT_BIT_HW_ERR; | |
1708 | ||
1709 | spin_unlock_irqrestore(&priv->lock, flags); | |
1710 | ||
1711 | return; | |
1712 | } | |
1713 | ||
d08853a3 | 1714 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1715 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 1716 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
86ddbf62 | 1717 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1718 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1719 | "the frame/frames.\n"); |
86ddbf62 AK |
1720 | priv->isr_stats.sch++; |
1721 | } | |
b481de9c ZY |
1722 | |
1723 | /* Alive notification via Rx interrupt will do the real work */ | |
86ddbf62 | 1724 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1725 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
86ddbf62 AK |
1726 | priv->isr_stats.alive++; |
1727 | } | |
b481de9c ZY |
1728 | } |
1729 | #endif | |
1730 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1731 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1732 | |
b481de9c ZY |
1733 | /* Error detected by uCode */ |
1734 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1735 | IWL_ERR(priv, "Microcode SW error detected. " |
1736 | "Restarting 0x%X.\n", inta); | |
86ddbf62 AK |
1737 | priv->isr_stats.sw++; |
1738 | priv->isr_stats.sw_err = inta; | |
8ccde88a | 1739 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1740 | handled |= CSR_INT_BIT_SW_ERR; |
1741 | } | |
1742 | ||
1743 | /* uCode wakes up after power-down sleep */ | |
1744 | if (inta & CSR_INT_BIT_WAKEUP) { | |
e1623446 | 1745 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
141c43a3 | 1746 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
4f3602c8 SO |
1747 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
1748 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1749 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1750 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1751 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1752 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c | 1753 | |
86ddbf62 | 1754 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1755 | handled |= CSR_INT_BIT_WAKEUP; |
1756 | } | |
1757 | ||
1758 | /* All uCode command responses, including Tx command responses, | |
1759 | * Rx "responses" (frame-received notification), and other | |
1760 | * notifications from uCode come through here*/ | |
1761 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 1762 | iwl3945_rx_handle(priv); |
86ddbf62 | 1763 | priv->isr_stats.rx++; |
b481de9c ZY |
1764 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1765 | } | |
1766 | ||
1767 | if (inta & CSR_INT_BIT_FH_TX) { | |
e1623446 | 1768 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); |
86ddbf62 | 1769 | priv->isr_stats.tx++; |
b481de9c | 1770 | |
5d49f498 | 1771 | iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); |
a8b50a0a MA |
1772 | iwl_write_direct32(priv, FH39_TCSR_CREDIT |
1773 | (FH39_SRVC_CHNL), 0x0); | |
b481de9c ZY |
1774 | handled |= CSR_INT_BIT_FH_TX; |
1775 | } | |
1776 | ||
86ddbf62 | 1777 | if (inta & ~handled) { |
15b1687c | 1778 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
86ddbf62 AK |
1779 | priv->isr_stats.unhandled++; |
1780 | } | |
b481de9c | 1781 | |
40cefda9 | 1782 | if (inta & ~priv->inta_mask) { |
39aadf8c | 1783 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1784 | inta & ~priv->inta_mask); |
39aadf8c | 1785 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1786 | } |
1787 | ||
1788 | /* Re-enable all interrupts */ | |
0359facc MA |
1789 | /* only Re-enable if disabled by irq */ |
1790 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
ed3b932e | 1791 | iwl_enable_interrupts(priv); |
b481de9c | 1792 | |
d08853a3 | 1793 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1794 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
5d49f498 AK |
1795 | inta = iwl_read32(priv, CSR_INT); |
1796 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1797 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1798 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1799 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1800 | } | |
1801 | #endif | |
1802 | spin_unlock_irqrestore(&priv->lock, flags); | |
1803 | } | |
1804 | ||
4a8a4322 | 1805 | static int iwl3945_get_channels_for_scan(struct iwl_priv *priv, |
8318d78a | 1806 | enum ieee80211_band band, |
f9340520 | 1807 | u8 is_active, u8 n_probes, |
bb8c093b | 1808 | struct iwl3945_scan_channel *scan_ch) |
b481de9c | 1809 | { |
4e05c234 | 1810 | struct ieee80211_channel *chan; |
8318d78a | 1811 | const struct ieee80211_supported_band *sband; |
d20b3c65 | 1812 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
1813 | u16 passive_dwell = 0; |
1814 | u16 active_dwell = 0; | |
1815 | int added, i; | |
1816 | ||
cbba18c6 | 1817 | sband = iwl_get_hw_mode(priv, band); |
8318d78a | 1818 | if (!sband) |
b481de9c ZY |
1819 | return 0; |
1820 | ||
77fecfb8 SO |
1821 | active_dwell = iwl_get_active_dwell_time(priv, band, n_probes); |
1822 | passive_dwell = iwl_get_passive_dwell_time(priv, band); | |
b481de9c | 1823 | |
8f4807a1 AK |
1824 | if (passive_dwell <= active_dwell) |
1825 | passive_dwell = active_dwell + 1; | |
1826 | ||
4e05c234 JB |
1827 | for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) { |
1828 | chan = priv->scan_request->channels[i]; | |
1829 | ||
1830 | if (chan->band != band) | |
182e2e66 JB |
1831 | continue; |
1832 | ||
4e05c234 | 1833 | scan_ch->channel = chan->hw_value; |
b481de9c | 1834 | |
e6148917 | 1835 | ch_info = iwl_get_channel_info(priv, band, scan_ch->channel); |
b481de9c | 1836 | if (!is_channel_valid(ch_info)) { |
e1623446 | 1837 | IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n", |
b481de9c ZY |
1838 | scan_ch->channel); |
1839 | continue; | |
1840 | } | |
1841 | ||
011a0330 AK |
1842 | scan_ch->active_dwell = cpu_to_le16(active_dwell); |
1843 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
1844 | /* If passive , set up for auto-switch | |
1845 | * and use long active_dwell time. | |
1846 | */ | |
b481de9c | 1847 | if (!is_active || is_channel_passive(ch_info) || |
4e05c234 | 1848 | (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) { |
b481de9c | 1849 | scan_ch->type = 0; /* passive */ |
011a0330 AK |
1850 | if (IWL_UCODE_API(priv->ucode_ver) == 1) |
1851 | scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1); | |
1852 | } else { | |
b481de9c | 1853 | scan_ch->type = 1; /* active */ |
011a0330 | 1854 | } |
b481de9c | 1855 | |
011a0330 AK |
1856 | /* Set direct probe bits. These may be used both for active |
1857 | * scan channels (probes gets sent right away), | |
1858 | * or for passive channels (probes get se sent only after | |
1859 | * hearing clear Rx packet).*/ | |
1860 | if (IWL_UCODE_API(priv->ucode_ver) >= 2) { | |
1861 | if (n_probes) | |
0d21044e | 1862 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 AK |
1863 | } else { |
1864 | /* uCode v1 does not allow setting direct probe bits on | |
1865 | * passive channel. */ | |
1866 | if ((scan_ch->type & 1) && n_probes) | |
0d21044e | 1867 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 | 1868 | } |
b481de9c | 1869 | |
9fbab516 | 1870 | /* Set txpower levels to defaults */ |
b481de9c ZY |
1871 | scan_ch->tpc.dsp_atten = 110; |
1872 | /* scan_pwr_info->tpc.dsp_atten; */ | |
1873 | ||
1874 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 1875 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
1876 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
1877 | else { | |
1878 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
1879 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 1880 | * power level: |
8a1b0245 | 1881 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
1882 | */ |
1883 | } | |
1884 | ||
e1623446 | 1885 | IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n", |
b481de9c ZY |
1886 | scan_ch->channel, |
1887 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
1888 | (scan_ch->type & 1) ? | |
1889 | active_dwell : passive_dwell); | |
1890 | ||
1891 | scan_ch++; | |
1892 | added++; | |
1893 | } | |
1894 | ||
e1623446 | 1895 | IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added); |
b481de9c ZY |
1896 | return added; |
1897 | } | |
1898 | ||
4a8a4322 | 1899 | static void iwl3945_init_hw_rates(struct iwl_priv *priv, |
b481de9c ZY |
1900 | struct ieee80211_rate *rates) |
1901 | { | |
1902 | int i; | |
1903 | ||
1904 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
1905 | rates[i].bitrate = iwl3945_rates[i].ieee * 5; |
1906 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
1907 | rates[i].hw_value_short = i; | |
1908 | rates[i].flags = 0; | |
d9829a67 | 1909 | if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { |
b481de9c | 1910 | /* |
8318d78a | 1911 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 1912 | */ |
bb8c093b | 1913 | rates[i].flags |= (iwl3945_rates[i].plcp == 10) ? |
8318d78a | 1914 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
b481de9c | 1915 | } |
b481de9c ZY |
1916 | } |
1917 | } | |
1918 | ||
b481de9c ZY |
1919 | /****************************************************************************** |
1920 | * | |
1921 | * uCode download functions | |
1922 | * | |
1923 | ******************************************************************************/ | |
1924 | ||
4a8a4322 | 1925 | static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1926 | { |
98c92211 TW |
1927 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1928 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1929 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1930 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1931 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1932 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1933 | } |
1934 | ||
1935 | /** | |
bb8c093b | 1936 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
1937 | * looking at all data. |
1938 | */ | |
4a8a4322 | 1939 | static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
1940 | { |
1941 | u32 val; | |
1942 | u32 save_len = len; | |
1943 | int rc = 0; | |
1944 | u32 errcnt; | |
1945 | ||
e1623446 | 1946 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 1947 | |
5d49f498 | 1948 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 1949 | IWL39_RTC_INST_LOWER_BOUND); |
b481de9c ZY |
1950 | |
1951 | errcnt = 0; | |
1952 | for (; len > 0; len -= sizeof(u32), image++) { | |
1953 | /* read data comes through single port, auto-incr addr */ | |
1954 | /* NOTE: Use the debugless read so we don't flood kernel log | |
1955 | * if IWL_DL_IO is set */ | |
5d49f498 | 1956 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c | 1957 | if (val != le32_to_cpu(*image)) { |
15b1687c | 1958 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
1959 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
1960 | save_len - len, val, le32_to_cpu(*image)); | |
1961 | rc = -EIO; | |
1962 | errcnt++; | |
1963 | if (errcnt >= 20) | |
1964 | break; | |
1965 | } | |
1966 | } | |
1967 | ||
b481de9c ZY |
1968 | |
1969 | if (!errcnt) | |
e1623446 TW |
1970 | IWL_DEBUG_INFO(priv, |
1971 | "ucode image in INSTRUCTION memory is good\n"); | |
b481de9c ZY |
1972 | |
1973 | return rc; | |
1974 | } | |
1975 | ||
1976 | ||
1977 | /** | |
bb8c093b | 1978 | * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
1979 | * using sample data 100 bytes apart. If these sample points are good, |
1980 | * it's a pretty good bet that everything between them is good, too. | |
1981 | */ | |
4a8a4322 | 1982 | static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
1983 | { |
1984 | u32 val; | |
1985 | int rc = 0; | |
1986 | u32 errcnt = 0; | |
1987 | u32 i; | |
1988 | ||
e1623446 | 1989 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 1990 | |
b481de9c ZY |
1991 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { |
1992 | /* read data comes through single port, auto-incr addr */ | |
1993 | /* NOTE: Use the debugless read so we don't flood kernel log | |
1994 | * if IWL_DL_IO is set */ | |
5d49f498 | 1995 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 1996 | i + IWL39_RTC_INST_LOWER_BOUND); |
5d49f498 | 1997 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
1998 | if (val != le32_to_cpu(*image)) { |
1999 | #if 0 /* Enable this if you want to see details */ | |
15b1687c | 2000 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
2001 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
2002 | i, val, *image); | |
2003 | #endif | |
2004 | rc = -EIO; | |
2005 | errcnt++; | |
2006 | if (errcnt >= 3) | |
2007 | break; | |
2008 | } | |
2009 | } | |
2010 | ||
b481de9c ZY |
2011 | return rc; |
2012 | } | |
2013 | ||
2014 | ||
2015 | /** | |
bb8c093b | 2016 | * iwl3945_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
2017 | * and verify its contents |
2018 | */ | |
4a8a4322 | 2019 | static int iwl3945_verify_ucode(struct iwl_priv *priv) |
b481de9c ZY |
2020 | { |
2021 | __le32 *image; | |
2022 | u32 len; | |
2023 | int rc = 0; | |
2024 | ||
2025 | /* Try bootstrap */ | |
2026 | image = (__le32 *)priv->ucode_boot.v_addr; | |
2027 | len = priv->ucode_boot.len; | |
bb8c093b | 2028 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2029 | if (rc == 0) { |
e1623446 | 2030 | IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n"); |
b481de9c ZY |
2031 | return 0; |
2032 | } | |
2033 | ||
2034 | /* Try initialize */ | |
2035 | image = (__le32 *)priv->ucode_init.v_addr; | |
2036 | len = priv->ucode_init.len; | |
bb8c093b | 2037 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2038 | if (rc == 0) { |
e1623446 | 2039 | IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n"); |
b481de9c ZY |
2040 | return 0; |
2041 | } | |
2042 | ||
2043 | /* Try runtime/protocol */ | |
2044 | image = (__le32 *)priv->ucode_code.v_addr; | |
2045 | len = priv->ucode_code.len; | |
bb8c093b | 2046 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2047 | if (rc == 0) { |
e1623446 | 2048 | IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n"); |
b481de9c ZY |
2049 | return 0; |
2050 | } | |
2051 | ||
15b1687c | 2052 | IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
b481de9c | 2053 | |
9fbab516 BC |
2054 | /* Since nothing seems to match, show first several data entries in |
2055 | * instruction SRAM, so maybe visual inspection will give a clue. | |
2056 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
2057 | image = (__le32 *)priv->ucode_boot.v_addr; |
2058 | len = priv->ucode_boot.len; | |
bb8c093b | 2059 | rc = iwl3945_verify_inst_full(priv, image, len); |
b481de9c ZY |
2060 | |
2061 | return rc; | |
2062 | } | |
2063 | ||
4a8a4322 | 2064 | static void iwl3945_nic_start(struct iwl_priv *priv) |
b481de9c ZY |
2065 | { |
2066 | /* Remove all resets to allow NIC to operate */ | |
5d49f498 | 2067 | iwl_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
2068 | } |
2069 | ||
2070 | /** | |
bb8c093b | 2071 | * iwl3945_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
2072 | * |
2073 | * Copy into buffers for card to fetch via bus-mastering | |
2074 | */ | |
4a8a4322 | 2075 | static int iwl3945_read_ucode(struct iwl_priv *priv) |
b481de9c | 2076 | { |
cc0f555d | 2077 | const struct iwl_ucode_header *ucode; |
a0987a8d | 2078 | int ret = -EINVAL, index; |
b481de9c ZY |
2079 | const struct firmware *ucode_raw; |
2080 | /* firmware file name contains uCode/driver compatibility version */ | |
a0987a8d RC |
2081 | const char *name_pre = priv->cfg->fw_name_pre; |
2082 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
2083 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
2084 | char buf[25]; | |
b481de9c ZY |
2085 | u8 *src; |
2086 | size_t len; | |
a0987a8d | 2087 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; |
b481de9c ZY |
2088 | |
2089 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
2090 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
2091 | for (index = api_max; index >= api_min; index--) { |
2092 | sprintf(buf, "%s%u%s", name_pre, index, ".ucode"); | |
2093 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
2094 | if (ret < 0) { | |
15b1687c | 2095 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
2096 | buf, ret); |
2097 | if (ret == -ENOENT) | |
2098 | continue; | |
2099 | else | |
2100 | goto error; | |
2101 | } else { | |
2102 | if (index < api_max) | |
15b1687c WT |
2103 | IWL_ERR(priv, "Loaded firmware %s, " |
2104 | "which is deprecated. " | |
2105 | " Please use API v%u instead.\n", | |
a0987a8d | 2106 | buf, api_max); |
e1623446 TW |
2107 | IWL_DEBUG_INFO(priv, "Got firmware '%s' file " |
2108 | "(%zd bytes) from disk\n", | |
a0987a8d RC |
2109 | buf, ucode_raw->size); |
2110 | break; | |
2111 | } | |
b481de9c ZY |
2112 | } |
2113 | ||
a0987a8d RC |
2114 | if (ret < 0) |
2115 | goto error; | |
b481de9c ZY |
2116 | |
2117 | /* Make sure that we got at least our header! */ | |
cc0f555d | 2118 | if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) { |
15b1687c | 2119 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 2120 | ret = -EINVAL; |
b481de9c ZY |
2121 | goto err_release; |
2122 | } | |
2123 | ||
2124 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 2125 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 2126 | |
c02b3acd | 2127 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 2128 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
cc0f555d JS |
2129 | inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver); |
2130 | data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver); | |
2131 | init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver); | |
2132 | init_data_size = | |
2133 | priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver); | |
2134 | boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver); | |
2135 | src = priv->cfg->ops->ucode->get_data(ucode, api_ver); | |
b481de9c | 2136 | |
a0987a8d RC |
2137 | /* api_ver should match the api version forming part of the |
2138 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 2139 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
2140 | |
2141 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 2142 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
2143 | "Driver supports v%u, firmware is v%u.\n", |
2144 | api_max, api_ver); | |
2145 | priv->ucode_ver = 0; | |
2146 | ret = -EINVAL; | |
2147 | goto err_release; | |
2148 | } | |
2149 | if (api_ver != api_max) | |
15b1687c | 2150 | IWL_ERR(priv, "Firmware has old API version. Expected %u, " |
a0987a8d RC |
2151 | "got %u. New firmware can be obtained " |
2152 | "from http://www.intellinuxwireless.org.\n", | |
2153 | api_max, api_ver); | |
2154 | ||
978785a3 TW |
2155 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
2156 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2157 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2158 | IWL_UCODE_API(priv->ucode_ver), | |
2159 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
2160 | ||
e1623446 | 2161 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 2162 | priv->ucode_ver); |
e1623446 TW |
2163 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
2164 | inst_size); | |
2165 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", | |
2166 | data_size); | |
2167 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", | |
2168 | init_size); | |
2169 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", | |
2170 | init_data_size); | |
2171 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", | |
2172 | boot_size); | |
b481de9c | 2173 | |
a0987a8d | 2174 | |
b481de9c | 2175 | /* Verify size of file vs. image size info in file's header */ |
cc0f555d | 2176 | if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) + |
b481de9c ZY |
2177 | inst_size + data_size + init_size + |
2178 | init_data_size + boot_size) { | |
2179 | ||
cc0f555d JS |
2180 | IWL_DEBUG_INFO(priv, |
2181 | "uCode file size %zd does not match expected size\n", | |
2182 | ucode_raw->size); | |
90e759d1 | 2183 | ret = -EINVAL; |
b481de9c ZY |
2184 | goto err_release; |
2185 | } | |
2186 | ||
2187 | /* Verify that uCode images will fit in card's SRAM */ | |
250bdd21 | 2188 | if (inst_size > IWL39_MAX_INST_SIZE) { |
e1623446 | 2189 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 TW |
2190 | inst_size); |
2191 | ret = -EINVAL; | |
b481de9c ZY |
2192 | goto err_release; |
2193 | } | |
2194 | ||
250bdd21 | 2195 | if (data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 | 2196 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 TW |
2197 | data_size); |
2198 | ret = -EINVAL; | |
b481de9c ZY |
2199 | goto err_release; |
2200 | } | |
250bdd21 | 2201 | if (init_size > IWL39_MAX_INST_SIZE) { |
e1623446 TW |
2202 | IWL_DEBUG_INFO(priv, |
2203 | "uCode init instr len %d too large to fit in\n", | |
90e759d1 TW |
2204 | init_size); |
2205 | ret = -EINVAL; | |
b481de9c ZY |
2206 | goto err_release; |
2207 | } | |
250bdd21 | 2208 | if (init_data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 TW |
2209 | IWL_DEBUG_INFO(priv, |
2210 | "uCode init data len %d too large to fit in\n", | |
90e759d1 TW |
2211 | init_data_size); |
2212 | ret = -EINVAL; | |
b481de9c ZY |
2213 | goto err_release; |
2214 | } | |
250bdd21 | 2215 | if (boot_size > IWL39_MAX_BSM_SIZE) { |
e1623446 TW |
2216 | IWL_DEBUG_INFO(priv, |
2217 | "uCode boot instr len %d too large to fit in\n", | |
90e759d1 TW |
2218 | boot_size); |
2219 | ret = -EINVAL; | |
b481de9c ZY |
2220 | goto err_release; |
2221 | } | |
2222 | ||
2223 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
2224 | ||
2225 | /* Runtime instructions and 2 copies of data: | |
2226 | * 1) unmodified from disk | |
2227 | * 2) backup cache for save/restore during power-downs */ | |
2228 | priv->ucode_code.len = inst_size; | |
98c92211 | 2229 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
2230 | |
2231 | priv->ucode_data.len = data_size; | |
98c92211 | 2232 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
2233 | |
2234 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 2235 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 2236 | |
90e759d1 TW |
2237 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
2238 | !priv->ucode_data_backup.v_addr) | |
2239 | goto err_pci_alloc; | |
b481de9c ZY |
2240 | |
2241 | /* Initialization instructions and data */ | |
90e759d1 TW |
2242 | if (init_size && init_data_size) { |
2243 | priv->ucode_init.len = init_size; | |
98c92211 | 2244 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
2245 | |
2246 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 2247 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
2248 | |
2249 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
2250 | goto err_pci_alloc; | |
2251 | } | |
b481de9c ZY |
2252 | |
2253 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
2254 | if (boot_size) { |
2255 | priv->ucode_boot.len = boot_size; | |
98c92211 | 2256 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 2257 | |
90e759d1 TW |
2258 | if (!priv->ucode_boot.v_addr) |
2259 | goto err_pci_alloc; | |
2260 | } | |
b481de9c ZY |
2261 | |
2262 | /* Copy images into buffers for card's bus-master reads ... */ | |
2263 | ||
2264 | /* Runtime instructions (first block of data in file) */ | |
cc0f555d | 2265 | len = inst_size; |
e1623446 TW |
2266 | IWL_DEBUG_INFO(priv, |
2267 | "Copying (but not loading) uCode instr len %zd\n", len); | |
b481de9c | 2268 | memcpy(priv->ucode_code.v_addr, src, len); |
cc0f555d JS |
2269 | src += len; |
2270 | ||
e1623446 | 2271 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
2272 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
2273 | ||
2274 | /* Runtime data (2nd block) | |
bb8c093b | 2275 | * NOTE: Copy into backup buffer will be done in iwl3945_up() */ |
cc0f555d | 2276 | len = data_size; |
e1623446 TW |
2277 | IWL_DEBUG_INFO(priv, |
2278 | "Copying (but not loading) uCode data len %zd\n", len); | |
b481de9c ZY |
2279 | memcpy(priv->ucode_data.v_addr, src, len); |
2280 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
cc0f555d | 2281 | src += len; |
b481de9c ZY |
2282 | |
2283 | /* Initialization instructions (3rd block) */ | |
2284 | if (init_size) { | |
cc0f555d | 2285 | len = init_size; |
e1623446 TW |
2286 | IWL_DEBUG_INFO(priv, |
2287 | "Copying (but not loading) init instr len %zd\n", len); | |
b481de9c | 2288 | memcpy(priv->ucode_init.v_addr, src, len); |
cc0f555d | 2289 | src += len; |
b481de9c ZY |
2290 | } |
2291 | ||
2292 | /* Initialization data (4th block) */ | |
2293 | if (init_data_size) { | |
cc0f555d | 2294 | len = init_data_size; |
e1623446 TW |
2295 | IWL_DEBUG_INFO(priv, |
2296 | "Copying (but not loading) init data len %zd\n", len); | |
b481de9c | 2297 | memcpy(priv->ucode_init_data.v_addr, src, len); |
cc0f555d | 2298 | src += len; |
b481de9c ZY |
2299 | } |
2300 | ||
2301 | /* Bootstrap instructions (5th block) */ | |
cc0f555d | 2302 | len = boot_size; |
e1623446 TW |
2303 | IWL_DEBUG_INFO(priv, |
2304 | "Copying (but not loading) boot instr len %zd\n", len); | |
b481de9c ZY |
2305 | memcpy(priv->ucode_boot.v_addr, src, len); |
2306 | ||
2307 | /* We have our copies now, allow OS release its copies */ | |
2308 | release_firmware(ucode_raw); | |
2309 | return 0; | |
2310 | ||
2311 | err_pci_alloc: | |
15b1687c | 2312 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 2313 | ret = -ENOMEM; |
bb8c093b | 2314 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
2315 | |
2316 | err_release: | |
2317 | release_firmware(ucode_raw); | |
2318 | ||
2319 | error: | |
90e759d1 | 2320 | return ret; |
b481de9c ZY |
2321 | } |
2322 | ||
2323 | ||
2324 | /** | |
bb8c093b | 2325 | * iwl3945_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
2326 | * |
2327 | * Tell initialization uCode where to find runtime uCode. | |
2328 | * | |
2329 | * BSM registers initially contain pointers to initialization uCode. | |
2330 | * We need to replace them to load runtime uCode inst and data, | |
2331 | * and to save runtime data when powering down. | |
2332 | */ | |
4a8a4322 | 2333 | static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv) |
b481de9c ZY |
2334 | { |
2335 | dma_addr_t pinst; | |
2336 | dma_addr_t pdata; | |
b481de9c ZY |
2337 | |
2338 | /* bits 31:0 for 3945 */ | |
2339 | pinst = priv->ucode_code.p_addr; | |
2340 | pdata = priv->ucode_data_backup.p_addr; | |
2341 | ||
b481de9c | 2342 | /* Tell bootstrap uCode where to find image to load */ |
5d49f498 AK |
2343 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
2344 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
2345 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
2346 | priv->ucode_data.len); |
2347 | ||
a96a27f9 | 2348 | /* Inst byte count must be last to set up, bit 31 signals uCode |
b481de9c | 2349 | * that all new ptr/size info is in place */ |
5d49f498 | 2350 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
2351 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
2352 | ||
e1623446 | 2353 | IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n"); |
b481de9c | 2354 | |
a8b50a0a | 2355 | return 0; |
b481de9c ZY |
2356 | } |
2357 | ||
2358 | /** | |
bb8c093b | 2359 | * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
2360 | * |
2361 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
2362 | * | |
b481de9c | 2363 | * Tell "initialize" uCode to go ahead and load the runtime uCode. |
9fbab516 | 2364 | */ |
4a8a4322 | 2365 | static void iwl3945_init_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
2366 | { |
2367 | /* Check alive response for "valid" sign from uCode */ | |
2368 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
2369 | /* We had an error bringing up the hardware, so take it | |
2370 | * all the way back down so we can try again */ | |
e1623446 | 2371 | IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); |
b481de9c ZY |
2372 | goto restart; |
2373 | } | |
2374 | ||
2375 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
2376 | * This is a paranoid check, because we would not have gotten the | |
2377 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 2378 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2379 | /* Runtime instruction load was bad; |
2380 | * take it all the way back down so we can try again */ | |
e1623446 | 2381 | IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); |
b481de9c ZY |
2382 | goto restart; |
2383 | } | |
2384 | ||
2385 | /* Send pointers to protocol/runtime uCode image ... init code will | |
2386 | * load and launch runtime uCode, which will send us another "Alive" | |
2387 | * notification. */ | |
e1623446 | 2388 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
bb8c093b | 2389 | if (iwl3945_set_ucode_ptrs(priv)) { |
b481de9c ZY |
2390 | /* Runtime instruction load won't happen; |
2391 | * take it all the way back down so we can try again */ | |
e1623446 | 2392 | IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n"); |
b481de9c ZY |
2393 | goto restart; |
2394 | } | |
2395 | return; | |
2396 | ||
2397 | restart: | |
2398 | queue_work(priv->workqueue, &priv->restart); | |
2399 | } | |
2400 | ||
b481de9c | 2401 | /** |
bb8c093b | 2402 | * iwl3945_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2403 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 2404 | * Alive gets handled by iwl3945_init_alive_start()). |
b481de9c | 2405 | */ |
4a8a4322 | 2406 | static void iwl3945_alive_start(struct iwl_priv *priv) |
b481de9c | 2407 | { |
b481de9c ZY |
2408 | int thermal_spin = 0; |
2409 | u32 rfkill; | |
2410 | ||
e1623446 | 2411 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
2412 | |
2413 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
2414 | /* We had an error bringing up the hardware, so take it | |
2415 | * all the way back down so we can try again */ | |
e1623446 | 2416 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
2417 | goto restart; |
2418 | } | |
2419 | ||
2420 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2421 | * This is a paranoid check, because we would not have gotten the | |
2422 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 2423 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2424 | /* Runtime instruction load was bad; |
2425 | * take it all the way back down so we can try again */ | |
e1623446 | 2426 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2427 | goto restart; |
2428 | } | |
2429 | ||
c587de0b | 2430 | iwl_clear_stations_table(priv); |
b481de9c | 2431 | |
5d49f498 | 2432 | rfkill = iwl_read_prph(priv, APMG_RFKILL_REG); |
e1623446 | 2433 | IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill); |
b481de9c ZY |
2434 | |
2435 | if (rfkill & 0x1) { | |
2436 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a96a27f9 | 2437 | /* if RFKILL is not on, then wait for thermal |
b481de9c | 2438 | * sensor in adapter to kick in */ |
bb8c093b | 2439 | while (iwl3945_hw_get_temperature(priv) == 0) { |
b481de9c ZY |
2440 | thermal_spin++; |
2441 | udelay(10); | |
2442 | } | |
2443 | ||
2444 | if (thermal_spin) | |
e1623446 | 2445 | IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n", |
b481de9c ZY |
2446 | thermal_spin * 10); |
2447 | } else | |
2448 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2449 | ||
9fbab516 | 2450 | /* After the ALIVE response, we can send commands to 3945 uCode */ |
b481de9c ZY |
2451 | set_bit(STATUS_ALIVE, &priv->status); |
2452 | ||
775a6e27 | 2453 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2454 | return; |
2455 | ||
36d6825b | 2456 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
2457 | |
2458 | priv->active_rate = priv->rates_mask; | |
2459 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
2460 | ||
d25aabb0 | 2461 | iwl_power_update_mode(priv, false); |
b481de9c | 2462 | |
8ccde88a | 2463 | if (iwl_is_associated(priv)) { |
bb8c093b | 2464 | struct iwl3945_rxon_cmd *active_rxon = |
8ccde88a | 2465 | (struct iwl3945_rxon_cmd *)(&priv->active_rxon); |
b481de9c | 2466 | |
8a9b9926 | 2467 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c ZY |
2468 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2469 | } else { | |
2470 | /* Initialize our rx_config data */ | |
8ccde88a | 2471 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
b481de9c ZY |
2472 | } |
2473 | ||
9fbab516 | 2474 | /* Configure Bluetooth device coexistence support */ |
17f841cd | 2475 | iwl_send_bt_config(priv); |
b481de9c ZY |
2476 | |
2477 | /* Configure the adapter for unassociated operation */ | |
e0158e61 | 2478 | iwlcore_commit_rxon(priv); |
b481de9c | 2479 | |
b481de9c ZY |
2480 | iwl3945_reg_txpower_periodic(priv); |
2481 | ||
fe00b5a5 RC |
2482 | iwl3945_led_register(priv); |
2483 | ||
e1623446 | 2484 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 2485 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 2486 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2487 | |
9bdf5eca MA |
2488 | /* reassociate for ADHOC mode */ |
2489 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
2490 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
2491 | priv->vif); | |
2492 | if (beacon) | |
9944b938 | 2493 | iwl_mac_beacon_update(priv->hw, beacon); |
9bdf5eca MA |
2494 | } |
2495 | ||
f45c2714 | 2496 | if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) |
727882d6 | 2497 | iwl_set_mode(priv, priv->iw_mode); |
f45c2714 | 2498 | |
b481de9c ZY |
2499 | return; |
2500 | ||
2501 | restart: | |
2502 | queue_work(priv->workqueue, &priv->restart); | |
2503 | } | |
2504 | ||
4a8a4322 | 2505 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2506 | |
4a8a4322 | 2507 | static void __iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2508 | { |
2509 | unsigned long flags; | |
2510 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
2511 | struct ieee80211_conf *conf = NULL; | |
2512 | ||
e1623446 | 2513 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c ZY |
2514 | |
2515 | conf = ieee80211_get_hw_conf(priv->hw); | |
2516 | ||
2517 | if (!exit_pending) | |
2518 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
2519 | ||
ab53d8af | 2520 | iwl3945_led_unregister(priv); |
c587de0b | 2521 | iwl_clear_stations_table(priv); |
b481de9c ZY |
2522 | |
2523 | /* Unblock any waiting calls */ | |
2524 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2525 | ||
b481de9c ZY |
2526 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2527 | * exiting the module */ | |
2528 | if (!exit_pending) | |
2529 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2530 | ||
2531 | /* stop and reset the on-board processor */ | |
5d49f498 | 2532 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2533 | |
2534 | /* tell the device to stop sending interrupts */ | |
0359facc | 2535 | spin_lock_irqsave(&priv->lock, flags); |
ed3b932e | 2536 | iwl_disable_interrupts(priv); |
0359facc MA |
2537 | spin_unlock_irqrestore(&priv->lock, flags); |
2538 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2539 | |
2540 | if (priv->mac80211_registered) | |
2541 | ieee80211_stop_queues(priv->hw); | |
2542 | ||
bb8c093b | 2543 | /* If we have not previously called iwl3945_init() then |
6da3a13e | 2544 | * clear all bits but the RF Kill bits and return */ |
775a6e27 | 2545 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2546 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2547 | STATUS_RF_KILL_HW | | |
9788864e RC |
2548 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2549 | STATUS_GEO_CONFIGURED | | |
ebef2008 AK |
2550 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2551 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2552 | goto exit; |
2553 | } | |
2554 | ||
6da3a13e | 2555 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2556 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2557 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2558 | STATUS_RF_KILL_HW | | |
9788864e RC |
2559 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2560 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2561 | test_bit(STATUS_FW_ERROR, &priv->status) << |
ebef2008 AK |
2562 | STATUS_FW_ERROR | |
2563 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2564 | STATUS_EXIT_PENDING; | |
b481de9c | 2565 | |
e9414b6b | 2566 | priv->cfg->ops->lib->apm_ops.reset(priv); |
b481de9c | 2567 | spin_lock_irqsave(&priv->lock, flags); |
5d49f498 | 2568 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
2569 | spin_unlock_irqrestore(&priv->lock, flags); |
2570 | ||
bb8c093b CH |
2571 | iwl3945_hw_txq_ctx_stop(priv); |
2572 | iwl3945_hw_rxq_stop(priv); | |
b481de9c | 2573 | |
a8b50a0a MA |
2574 | iwl_write_prph(priv, APMG_CLK_DIS_REG, |
2575 | APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2576 | |
2577 | udelay(5); | |
2578 | ||
6da3a13e | 2579 | if (exit_pending) |
e9414b6b AM |
2580 | priv->cfg->ops->lib->apm_ops.stop(priv); |
2581 | else | |
2582 | priv->cfg->ops->lib->apm_ops.reset(priv); | |
2583 | ||
b481de9c | 2584 | exit: |
3d24a9f7 | 2585 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
2586 | |
2587 | if (priv->ibss_beacon) | |
2588 | dev_kfree_skb(priv->ibss_beacon); | |
2589 | priv->ibss_beacon = NULL; | |
2590 | ||
2591 | /* clear out any free frames */ | |
bb8c093b | 2592 | iwl3945_clear_free_frames(priv); |
b481de9c ZY |
2593 | } |
2594 | ||
4a8a4322 | 2595 | static void iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2596 | { |
2597 | mutex_lock(&priv->mutex); | |
bb8c093b | 2598 | __iwl3945_down(priv); |
b481de9c | 2599 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2600 | |
bb8c093b | 2601 | iwl3945_cancel_deferred_work(priv); |
b481de9c ZY |
2602 | } |
2603 | ||
2604 | #define MAX_HW_RESTARTS 5 | |
2605 | ||
4a8a4322 | 2606 | static int __iwl3945_up(struct iwl_priv *priv) |
b481de9c ZY |
2607 | { |
2608 | int rc, i; | |
2609 | ||
2610 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 2611 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2612 | return -EIO; |
2613 | } | |
2614 | ||
e903fbd4 | 2615 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2616 | IWL_ERR(priv, "ucode not available for device bring up\n"); |
e903fbd4 RC |
2617 | return -EIO; |
2618 | } | |
2619 | ||
e655b9f0 | 2620 | /* If platform's RF_KILL switch is NOT set to KILL */ |
5d49f498 | 2621 | if (iwl_read32(priv, CSR_GP_CNTRL) & |
e655b9f0 ZY |
2622 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
2623 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2624 | else { | |
2625 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6da3a13e WYG |
2626 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
2627 | return -ENODEV; | |
b481de9c | 2628 | } |
80fcc9e2 | 2629 | |
5d49f498 | 2630 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2631 | |
bb8c093b | 2632 | rc = iwl3945_hw_nic_init(priv); |
b481de9c | 2633 | if (rc) { |
15b1687c | 2634 | IWL_ERR(priv, "Unable to int nic\n"); |
b481de9c ZY |
2635 | return rc; |
2636 | } | |
2637 | ||
2638 | /* make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2639 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2640 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2641 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2642 | ||
2643 | /* clear (again), then enable host interrupts */ | |
5d49f498 | 2644 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
ed3b932e | 2645 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2646 | |
2647 | /* really make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2648 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2649 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2650 | |
2651 | /* Copy original ucode data image from disk into backup cache. | |
2652 | * This will be used to initialize the on-board processor's | |
2653 | * data SRAM for a clean start when the runtime program first loads. */ | |
2654 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2655 | priv->ucode_data.len); |
b481de9c | 2656 | |
e655b9f0 ZY |
2657 | /* We return success when we resume from suspend and rf_kill is on. */ |
2658 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
2659 | return 0; | |
2660 | ||
b481de9c ZY |
2661 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2662 | ||
c587de0b | 2663 | iwl_clear_stations_table(priv); |
b481de9c ZY |
2664 | |
2665 | /* load bootstrap state machine, | |
2666 | * load bootstrap program into processor's memory, | |
2667 | * prepare to load the "initialize" uCode */ | |
0164b9b4 | 2668 | priv->cfg->ops->lib->load_ucode(priv); |
b481de9c ZY |
2669 | |
2670 | if (rc) { | |
15b1687c WT |
2671 | IWL_ERR(priv, |
2672 | "Unable to set up bootstrap uCode: %d\n", rc); | |
b481de9c ZY |
2673 | continue; |
2674 | } | |
2675 | ||
2676 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 2677 | iwl3945_nic_start(priv); |
b481de9c | 2678 | |
e1623446 | 2679 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2680 | |
2681 | return 0; | |
2682 | } | |
2683 | ||
2684 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 2685 | __iwl3945_down(priv); |
ebef2008 | 2686 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2687 | |
2688 | /* tried to restart and config the device for as long as our | |
2689 | * patience could withstand */ | |
15b1687c | 2690 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2691 | return -EIO; |
2692 | } | |
2693 | ||
2694 | ||
2695 | /***************************************************************************** | |
2696 | * | |
2697 | * Workqueue callbacks | |
2698 | * | |
2699 | *****************************************************************************/ | |
2700 | ||
bb8c093b | 2701 | static void iwl3945_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2702 | { |
4a8a4322 AK |
2703 | struct iwl_priv *priv = |
2704 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2705 | |
2706 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2707 | return; | |
2708 | ||
2709 | mutex_lock(&priv->mutex); | |
bb8c093b | 2710 | iwl3945_init_alive_start(priv); |
b481de9c ZY |
2711 | mutex_unlock(&priv->mutex); |
2712 | } | |
2713 | ||
bb8c093b | 2714 | static void iwl3945_bg_alive_start(struct work_struct *data) |
b481de9c | 2715 | { |
4a8a4322 AK |
2716 | struct iwl_priv *priv = |
2717 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2718 | |
2719 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2720 | return; | |
2721 | ||
2722 | mutex_lock(&priv->mutex); | |
bb8c093b | 2723 | iwl3945_alive_start(priv); |
b481de9c ZY |
2724 | mutex_unlock(&priv->mutex); |
2725 | } | |
2726 | ||
2663516d HS |
2727 | static void iwl3945_rfkill_poll(struct work_struct *data) |
2728 | { | |
2729 | struct iwl_priv *priv = | |
2730 | container_of(data, struct iwl_priv, rfkill_poll.work); | |
2663516d HS |
2731 | |
2732 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
2733 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2734 | else | |
2735 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2736 | ||
a60e77e5 JB |
2737 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
2738 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
2663516d HS |
2739 | |
2740 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
2741 | round_jiffies_relative(2 * HZ)); | |
2742 | ||
2743 | } | |
2744 | ||
b481de9c | 2745 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) |
bb8c093b | 2746 | static void iwl3945_bg_request_scan(struct work_struct *data) |
b481de9c | 2747 | { |
4a8a4322 AK |
2748 | struct iwl_priv *priv = |
2749 | container_of(data, struct iwl_priv, request_scan); | |
c2d79b48 | 2750 | struct iwl_host_cmd cmd = { |
b481de9c | 2751 | .id = REPLY_SCAN_CMD, |
bb8c093b | 2752 | .len = sizeof(struct iwl3945_scan_cmd), |
c2acea8e | 2753 | .flags = CMD_SIZE_HUGE, |
b481de9c ZY |
2754 | }; |
2755 | int rc = 0; | |
bb8c093b | 2756 | struct iwl3945_scan_cmd *scan; |
b481de9c | 2757 | struct ieee80211_conf *conf = NULL; |
1ecf9fc1 | 2758 | u8 n_probes = 0; |
8318d78a | 2759 | enum ieee80211_band band; |
1ecf9fc1 | 2760 | bool is_active = false; |
b481de9c ZY |
2761 | |
2762 | conf = ieee80211_get_hw_conf(priv->hw); | |
2763 | ||
2764 | mutex_lock(&priv->mutex); | |
2765 | ||
fbc9f97b RC |
2766 | cancel_delayed_work(&priv->scan_check); |
2767 | ||
775a6e27 | 2768 | if (!iwl_is_ready(priv)) { |
39aadf8c | 2769 | IWL_WARN(priv, "request scan called when driver not ready.\n"); |
b481de9c ZY |
2770 | goto done; |
2771 | } | |
2772 | ||
a96a27f9 | 2773 | /* Make sure the scan wasn't canceled before this queued work |
b481de9c ZY |
2774 | * was given the chance to run... */ |
2775 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
2776 | goto done; | |
2777 | ||
2778 | /* This should never be called or scheduled if there is currently | |
2779 | * a scan active in the hardware. */ | |
2780 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
e1623446 TW |
2781 | IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests " |
2782 | "Ignoring second request.\n"); | |
b481de9c ZY |
2783 | rc = -EIO; |
2784 | goto done; | |
2785 | } | |
2786 | ||
2787 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
e1623446 | 2788 | IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n"); |
b481de9c ZY |
2789 | goto done; |
2790 | } | |
2791 | ||
2792 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
e1623446 TW |
2793 | IWL_DEBUG_HC(priv, |
2794 | "Scan request while abort pending. Queuing.\n"); | |
b481de9c ZY |
2795 | goto done; |
2796 | } | |
2797 | ||
775a6e27 | 2798 | if (iwl_is_rfkill(priv)) { |
e1623446 | 2799 | IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n"); |
b481de9c ZY |
2800 | goto done; |
2801 | } | |
2802 | ||
2803 | if (!test_bit(STATUS_READY, &priv->status)) { | |
e1623446 TW |
2804 | IWL_DEBUG_HC(priv, |
2805 | "Scan request while uninitialized. Queuing.\n"); | |
b481de9c ZY |
2806 | goto done; |
2807 | } | |
2808 | ||
2809 | if (!priv->scan_bands) { | |
e1623446 | 2810 | IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n"); |
b481de9c ZY |
2811 | goto done; |
2812 | } | |
2813 | ||
805cee5b WT |
2814 | if (!priv->scan) { |
2815 | priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) + | |
b481de9c | 2816 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
805cee5b | 2817 | if (!priv->scan) { |
b481de9c ZY |
2818 | rc = -ENOMEM; |
2819 | goto done; | |
2820 | } | |
2821 | } | |
805cee5b | 2822 | scan = priv->scan; |
bb8c093b | 2823 | memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
2824 | |
2825 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
2826 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
2827 | ||
8ccde88a | 2828 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
2829 | u16 interval = 0; |
2830 | u32 extra; | |
2831 | u32 suspend_time = 100; | |
2832 | u32 scan_suspend_time = 100; | |
2833 | unsigned long flags; | |
2834 | ||
e1623446 | 2835 | IWL_DEBUG_INFO(priv, "Scanning while associated...\n"); |
b481de9c ZY |
2836 | |
2837 | spin_lock_irqsave(&priv->lock, flags); | |
2838 | interval = priv->beacon_int; | |
2839 | spin_unlock_irqrestore(&priv->lock, flags); | |
2840 | ||
2841 | scan->suspend_time = 0; | |
15e869d8 | 2842 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
2843 | if (!interval) |
2844 | interval = suspend_time; | |
2845 | /* | |
2846 | * suspend time format: | |
2847 | * 0-19: beacon interval in usec (time before exec.) | |
2848 | * 20-23: 0 | |
2849 | * 24-31: number of beacons (suspend between channels) | |
2850 | */ | |
2851 | ||
2852 | extra = (suspend_time / interval) << 24; | |
2853 | scan_suspend_time = 0xFF0FFFFF & | |
2854 | (extra | ((suspend_time % interval) * 1024)); | |
2855 | ||
2856 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
e1623446 | 2857 | IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n", |
b481de9c ZY |
2858 | scan_suspend_time, interval); |
2859 | } | |
2860 | ||
1ecf9fc1 JB |
2861 | if (priv->scan_request->n_ssids) { |
2862 | int i, p = 0; | |
2863 | IWL_DEBUG_SCAN(priv, "Kicking off active scan\n"); | |
2864 | for (i = 0; i < priv->scan_request->n_ssids; i++) { | |
2865 | /* always does wildcard anyway */ | |
2866 | if (!priv->scan_request->ssids[i].ssid_len) | |
2867 | continue; | |
2868 | scan->direct_scan[p].id = WLAN_EID_SSID; | |
2869 | scan->direct_scan[p].len = | |
2870 | priv->scan_request->ssids[i].ssid_len; | |
2871 | memcpy(scan->direct_scan[p].ssid, | |
2872 | priv->scan_request->ssids[i].ssid, | |
2873 | priv->scan_request->ssids[i].ssid_len); | |
2874 | n_probes++; | |
2875 | p++; | |
2876 | } | |
2877 | is_active = true; | |
f9340520 | 2878 | } else |
1ecf9fc1 | 2879 | IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n"); |
b481de9c ZY |
2880 | |
2881 | /* We don't build a direct scan probe request; the uCode will do | |
2882 | * that based on the direct_mask added to each channel entry */ | |
b481de9c | 2883 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
3832ec9d | 2884 | scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id; |
b481de9c ZY |
2885 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
2886 | ||
2887 | /* flags + rate selection */ | |
2888 | ||
66b5004d | 2889 | if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) { |
b481de9c ZY |
2890 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; |
2891 | scan->tx_cmd.rate = IWL_RATE_1M_PLCP; | |
2892 | scan->good_CRC_th = 0; | |
8318d78a | 2893 | band = IEEE80211_BAND_2GHZ; |
66b5004d | 2894 | } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) { |
b481de9c | 2895 | scan->tx_cmd.rate = IWL_RATE_6M_PLCP; |
b097ad29 JB |
2896 | /* |
2897 | * If active scaning is requested but a certain channel | |
2898 | * is marked passive, we can do active scanning if we | |
2899 | * detect transmissions. | |
2900 | */ | |
2901 | scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0; | |
8318d78a | 2902 | band = IEEE80211_BAND_5GHZ; |
66b5004d | 2903 | } else { |
39aadf8c | 2904 | IWL_WARN(priv, "Invalid scan band count\n"); |
b481de9c ZY |
2905 | goto done; |
2906 | } | |
2907 | ||
77fecfb8 | 2908 | scan->tx_cmd.len = cpu_to_le16( |
1ecf9fc1 JB |
2909 | iwl_fill_probe_req(priv, |
2910 | (struct ieee80211_mgmt *)scan->data, | |
2911 | priv->scan_request->ie, | |
2912 | priv->scan_request->ie_len, | |
2913 | IWL_MAX_SCAN_SIZE - sizeof(*scan))); | |
77fecfb8 | 2914 | |
b481de9c ZY |
2915 | /* select Rx antennas */ |
2916 | scan->flags |= iwl3945_get_antenna_flags(priv); | |
2917 | ||
279b05d4 | 2918 | if (iwl_is_monitor_mode(priv)) |
b481de9c ZY |
2919 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; |
2920 | ||
f9340520 | 2921 | scan->channel_count = |
1ecf9fc1 | 2922 | iwl3945_get_channels_for_scan(priv, band, is_active, n_probes, |
f9340520 | 2923 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); |
b481de9c | 2924 | |
14b54336 | 2925 | if (scan->channel_count == 0) { |
e1623446 | 2926 | IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count); |
14b54336 RC |
2927 | goto done; |
2928 | } | |
2929 | ||
b481de9c | 2930 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + |
bb8c093b | 2931 | scan->channel_count * sizeof(struct iwl3945_scan_channel); |
b481de9c ZY |
2932 | cmd.data = scan; |
2933 | scan->len = cpu_to_le16(cmd.len); | |
2934 | ||
2935 | set_bit(STATUS_SCAN_HW, &priv->status); | |
518099a8 | 2936 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
2937 | if (rc) |
2938 | goto done; | |
2939 | ||
2940 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
2941 | IWL_SCAN_CHECK_WATCHDOG); | |
2942 | ||
2943 | mutex_unlock(&priv->mutex); | |
2944 | return; | |
2945 | ||
2946 | done: | |
2420ebc1 MA |
2947 | /* can not perform scan make sure we clear scanning |
2948 | * bits from status so next scan request can be performed. | |
2949 | * if we dont clear scanning status bit here all next scan | |
2950 | * will fail | |
2951 | */ | |
2952 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
2953 | clear_bit(STATUS_SCANNING, &priv->status); | |
2954 | ||
01ebd063 | 2955 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
2956 | queue_work(priv->workqueue, &priv->scan_completed); |
2957 | mutex_unlock(&priv->mutex); | |
2958 | } | |
2959 | ||
bb8c093b | 2960 | static void iwl3945_bg_up(struct work_struct *data) |
b481de9c | 2961 | { |
4a8a4322 | 2962 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
2963 | |
2964 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2965 | return; | |
2966 | ||
2967 | mutex_lock(&priv->mutex); | |
bb8c093b | 2968 | __iwl3945_up(priv); |
b481de9c ZY |
2969 | mutex_unlock(&priv->mutex); |
2970 | } | |
2971 | ||
bb8c093b | 2972 | static void iwl3945_bg_restart(struct work_struct *data) |
b481de9c | 2973 | { |
4a8a4322 | 2974 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2975 | |
2976 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2977 | return; | |
2978 | ||
19cc1087 JB |
2979 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
2980 | mutex_lock(&priv->mutex); | |
2981 | priv->vif = NULL; | |
2982 | priv->is_open = 0; | |
2983 | mutex_unlock(&priv->mutex); | |
2984 | iwl3945_down(priv); | |
2985 | ieee80211_restart_hw(priv->hw); | |
2986 | } else { | |
2987 | iwl3945_down(priv); | |
2988 | queue_work(priv->workqueue, &priv->up); | |
2989 | } | |
b481de9c ZY |
2990 | } |
2991 | ||
bb8c093b | 2992 | static void iwl3945_bg_rx_replenish(struct work_struct *data) |
b481de9c | 2993 | { |
4a8a4322 AK |
2994 | struct iwl_priv *priv = |
2995 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
2996 | |
2997 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2998 | return; | |
2999 | ||
3000 | mutex_lock(&priv->mutex); | |
bb8c093b | 3001 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
3002 | mutex_unlock(&priv->mutex); |
3003 | } | |
3004 | ||
7878a5a4 MA |
3005 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
3006 | ||
5bbe233b | 3007 | void iwl3945_post_associate(struct iwl_priv *priv) |
b481de9c | 3008 | { |
b481de9c ZY |
3009 | int rc = 0; |
3010 | struct ieee80211_conf *conf = NULL; | |
3011 | ||
05c914fe | 3012 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 3013 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
3014 | return; |
3015 | } | |
3016 | ||
3017 | ||
e1623446 | 3018 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
8ccde88a | 3019 | priv->assoc_id, priv->active_rxon.bssid_addr); |
b481de9c ZY |
3020 | |
3021 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3022 | return; | |
3023 | ||
322a9811 | 3024 | if (!priv->vif || !priv->is_open) |
6ef89d0a | 3025 | return; |
322a9811 | 3026 | |
af0053d6 | 3027 | iwl_scan_cancel_timeout(priv, 200); |
15e869d8 | 3028 | |
b481de9c ZY |
3029 | conf = ieee80211_get_hw_conf(priv->hw); |
3030 | ||
8ccde88a | 3031 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3032 | iwlcore_commit_rxon(priv); |
b481de9c | 3033 | |
28afaf91 | 3034 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
2c2f3b33 | 3035 | iwl_setup_rxon_timing(priv); |
518099a8 | 3036 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c ZY |
3037 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
3038 | if (rc) | |
39aadf8c | 3039 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3040 | "Attempting to continue.\n"); |
3041 | ||
8ccde88a | 3042 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c | 3043 | |
8ccde88a | 3044 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c | 3045 | |
e1623446 | 3046 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
b481de9c ZY |
3047 | priv->assoc_id, priv->beacon_int); |
3048 | ||
3049 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
8ccde88a | 3050 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3051 | else |
8ccde88a | 3052 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3053 | |
8ccde88a | 3054 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c | 3055 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
8ccde88a | 3056 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3057 | else |
8ccde88a | 3058 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3059 | |
05c914fe | 3060 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
8ccde88a | 3061 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
3062 | |
3063 | } | |
3064 | ||
e0158e61 | 3065 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3066 | |
3067 | switch (priv->iw_mode) { | |
05c914fe | 3068 | case NL80211_IFTYPE_STATION: |
bb8c093b | 3069 | iwl3945_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
3070 | break; |
3071 | ||
05c914fe | 3072 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 3073 | |
ce546fd2 | 3074 | priv->assoc_id = 1; |
c587de0b | 3075 | iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL); |
b481de9c | 3076 | iwl3945_sync_sta(priv, IWL_STA_ID, |
8318d78a | 3077 | (priv->band == IEEE80211_BAND_5GHZ) ? |
b481de9c ZY |
3078 | IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP, |
3079 | CMD_ASYNC); | |
bb8c093b CH |
3080 | iwl3945_rate_scale_init(priv->hw, IWL_STA_ID); |
3081 | iwl3945_send_beacon_cmd(priv); | |
b481de9c ZY |
3082 | |
3083 | break; | |
3084 | ||
3085 | default: | |
15b1687c | 3086 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 3087 | __func__, priv->iw_mode); |
b481de9c ZY |
3088 | break; |
3089 | } | |
3090 | ||
14d2aac5 | 3091 | iwl_activate_qos(priv, 0); |
292ae174 | 3092 | |
7878a5a4 MA |
3093 | /* we have just associated, don't start scan too early */ |
3094 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
cd56d331 AK |
3095 | } |
3096 | ||
b481de9c ZY |
3097 | /***************************************************************************** |
3098 | * | |
3099 | * mac80211 entry point functions | |
3100 | * | |
3101 | *****************************************************************************/ | |
3102 | ||
5a66926a ZY |
3103 | #define UCODE_READY_TIMEOUT (2 * HZ) |
3104 | ||
bb8c093b | 3105 | static int iwl3945_mac_start(struct ieee80211_hw *hw) |
b481de9c | 3106 | { |
4a8a4322 | 3107 | struct iwl_priv *priv = hw->priv; |
5a66926a | 3108 | int ret; |
b481de9c | 3109 | |
e1623446 | 3110 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
3111 | |
3112 | /* we should be verifying the device is ready to be opened */ | |
3113 | mutex_lock(&priv->mutex); | |
3114 | ||
5a66926a ZY |
3115 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
3116 | * ucode filename and max sizes are card-specific. */ | |
3117 | ||
3118 | if (!priv->ucode_code.len) { | |
3119 | ret = iwl3945_read_ucode(priv); | |
3120 | if (ret) { | |
15b1687c | 3121 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a ZY |
3122 | mutex_unlock(&priv->mutex); |
3123 | goto out_release_irq; | |
3124 | } | |
3125 | } | |
b481de9c | 3126 | |
e655b9f0 | 3127 | ret = __iwl3945_up(priv); |
b481de9c ZY |
3128 | |
3129 | mutex_unlock(&priv->mutex); | |
5a66926a | 3130 | |
e655b9f0 ZY |
3131 | if (ret) |
3132 | goto out_release_irq; | |
3133 | ||
e1623446 | 3134 | IWL_DEBUG_INFO(priv, "Start UP work.\n"); |
e655b9f0 | 3135 | |
5a66926a ZY |
3136 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
3137 | * mac80211 will not be run successfully. */ | |
3138 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
3139 | test_bit(STATUS_READY, &priv->status), | |
3140 | UCODE_READY_TIMEOUT); | |
3141 | if (!ret) { | |
3142 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c WT |
3143 | IWL_ERR(priv, |
3144 | "Wait for START_ALIVE timeout after %dms.\n", | |
3145 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
5a66926a ZY |
3146 | ret = -ETIMEDOUT; |
3147 | goto out_release_irq; | |
3148 | } | |
3149 | } | |
3150 | ||
2663516d HS |
3151 | /* ucode is running and will send rfkill notifications, |
3152 | * no need to poll the killswitch state anymore */ | |
3153 | cancel_delayed_work(&priv->rfkill_poll); | |
3154 | ||
e655b9f0 | 3155 | priv->is_open = 1; |
e1623446 | 3156 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3157 | return 0; |
5a66926a ZY |
3158 | |
3159 | out_release_irq: | |
e655b9f0 | 3160 | priv->is_open = 0; |
e1623446 | 3161 | IWL_DEBUG_MAC80211(priv, "leave - failed\n"); |
5a66926a | 3162 | return ret; |
b481de9c ZY |
3163 | } |
3164 | ||
bb8c093b | 3165 | static void iwl3945_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 3166 | { |
4a8a4322 | 3167 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3168 | |
e1623446 | 3169 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
6ef89d0a | 3170 | |
e655b9f0 | 3171 | if (!priv->is_open) { |
e1623446 | 3172 | IWL_DEBUG_MAC80211(priv, "leave - skip\n"); |
e655b9f0 ZY |
3173 | return; |
3174 | } | |
3175 | ||
b481de9c | 3176 | priv->is_open = 0; |
5a66926a | 3177 | |
775a6e27 | 3178 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
3179 | /* stop mac, cancel any scan request and clear |
3180 | * RXON_FILTER_ASSOC_MSK BIT | |
3181 | */ | |
5a66926a | 3182 | mutex_lock(&priv->mutex); |
af0053d6 | 3183 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 3184 | mutex_unlock(&priv->mutex); |
fde3571f MA |
3185 | } |
3186 | ||
5a66926a ZY |
3187 | iwl3945_down(priv); |
3188 | ||
3189 | flush_workqueue(priv->workqueue); | |
2663516d HS |
3190 | |
3191 | /* start polling the killswitch state again */ | |
3192 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
3193 | round_jiffies_relative(2 * HZ)); | |
6ef89d0a | 3194 | |
e1623446 | 3195 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3196 | } |
3197 | ||
e039fa4a | 3198 | static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 3199 | { |
4a8a4322 | 3200 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3201 | |
e1623446 | 3202 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3203 | |
e1623446 | 3204 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 3205 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 3206 | |
e039fa4a | 3207 | if (iwl3945_tx_skb(priv, skb)) |
b481de9c ZY |
3208 | dev_kfree_skb_any(skb); |
3209 | ||
e1623446 | 3210 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
637f8837 | 3211 | return NETDEV_TX_OK; |
b481de9c ZY |
3212 | } |
3213 | ||
60690a6a | 3214 | void iwl3945_config_ap(struct iwl_priv *priv) |
b481de9c ZY |
3215 | { |
3216 | int rc = 0; | |
3217 | ||
d986bcd1 | 3218 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
3219 | return; |
3220 | ||
3221 | /* The following should be done only at AP bring up */ | |
8ccde88a | 3222 | if (!(iwl_is_associated(priv))) { |
b481de9c ZY |
3223 | |
3224 | /* RXON - unassoc (to set timing command) */ | |
8ccde88a | 3225 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3226 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3227 | |
3228 | /* RXON Timing */ | |
28afaf91 | 3229 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
2c2f3b33 | 3230 | iwl_setup_rxon_timing(priv); |
518099a8 SO |
3231 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
3232 | sizeof(priv->rxon_timing), | |
3233 | &priv->rxon_timing); | |
b481de9c | 3234 | if (rc) |
39aadf8c | 3235 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3236 | "Attempting to continue.\n"); |
3237 | ||
3238 | /* FIXME: what should be the assoc_id for AP? */ | |
8ccde88a | 3239 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c | 3240 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) |
8ccde88a | 3241 | priv->staging_rxon.flags |= |
b481de9c ZY |
3242 | RXON_FLG_SHORT_PREAMBLE_MSK; |
3243 | else | |
8ccde88a | 3244 | priv->staging_rxon.flags &= |
b481de9c ZY |
3245 | ~RXON_FLG_SHORT_PREAMBLE_MSK; |
3246 | ||
8ccde88a | 3247 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c ZY |
3248 | if (priv->assoc_capability & |
3249 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
8ccde88a | 3250 | priv->staging_rxon.flags |= |
b481de9c ZY |
3251 | RXON_FLG_SHORT_SLOT_MSK; |
3252 | else | |
8ccde88a | 3253 | priv->staging_rxon.flags &= |
b481de9c ZY |
3254 | ~RXON_FLG_SHORT_SLOT_MSK; |
3255 | ||
05c914fe | 3256 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
8ccde88a | 3257 | priv->staging_rxon.flags &= |
b481de9c ZY |
3258 | ~RXON_FLG_SHORT_SLOT_MSK; |
3259 | } | |
3260 | /* restore RXON assoc */ | |
8ccde88a | 3261 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3262 | iwlcore_commit_rxon(priv); |
c587de0b | 3263 | iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL); |
556f8db7 | 3264 | } |
bb8c093b | 3265 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
3266 | |
3267 | /* FIXME - we need to add code here to detect a totally new | |
3268 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
3269 | * clear sta table, add BCAST sta... */ | |
3270 | } | |
3271 | ||
bb8c093b | 3272 | static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
3273 | struct ieee80211_vif *vif, |
3274 | struct ieee80211_sta *sta, | |
3275 | struct ieee80211_key_conf *key) | |
b481de9c | 3276 | { |
4a8a4322 | 3277 | struct iwl_priv *priv = hw->priv; |
dc822b5d | 3278 | const u8 *addr; |
6e21f15c AK |
3279 | int ret = 0; |
3280 | u8 sta_id = IWL_INVALID_STATION; | |
3281 | u8 static_key; | |
b481de9c | 3282 | |
e1623446 | 3283 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3284 | |
df878d8f | 3285 | if (iwl3945_mod_params.sw_crypto) { |
e1623446 | 3286 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
3287 | return -EOPNOTSUPP; |
3288 | } | |
3289 | ||
42986796 | 3290 | addr = sta ? sta->addr : iwl_bcast_addr; |
6e21f15c AK |
3291 | static_key = !iwl_is_associated(priv); |
3292 | ||
3293 | if (!static_key) { | |
c587de0b | 3294 | sta_id = iwl_find_station(priv, addr); |
6e21f15c | 3295 | if (sta_id == IWL_INVALID_STATION) { |
12514396 | 3296 | IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n", |
6e21f15c AK |
3297 | addr); |
3298 | return -EINVAL; | |
3299 | } | |
b481de9c ZY |
3300 | } |
3301 | ||
3302 | mutex_lock(&priv->mutex); | |
af0053d6 | 3303 | iwl_scan_cancel_timeout(priv, 100); |
6e21f15c | 3304 | mutex_unlock(&priv->mutex); |
15e869d8 | 3305 | |
b481de9c | 3306 | switch (cmd) { |
6e21f15c AK |
3307 | case SET_KEY: |
3308 | if (static_key) | |
3309 | ret = iwl3945_set_static_key(priv, key); | |
3310 | else | |
3311 | ret = iwl3945_set_dynamic_key(priv, key, sta_id); | |
3312 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); | |
b481de9c ZY |
3313 | break; |
3314 | case DISABLE_KEY: | |
6e21f15c AK |
3315 | if (static_key) |
3316 | ret = iwl3945_remove_static_key(priv); | |
3317 | else | |
3318 | ret = iwl3945_clear_sta_key_info(priv, sta_id); | |
3319 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); | |
b481de9c ZY |
3320 | break; |
3321 | default: | |
42986796 | 3322 | ret = -EINVAL; |
b481de9c ZY |
3323 | } |
3324 | ||
e1623446 | 3325 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3326 | |
42986796 | 3327 | return ret; |
b481de9c ZY |
3328 | } |
3329 | ||
b481de9c ZY |
3330 | /***************************************************************************** |
3331 | * | |
3332 | * sysfs attributes | |
3333 | * | |
3334 | *****************************************************************************/ | |
3335 | ||
d08853a3 | 3336 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3337 | |
3338 | /* | |
3339 | * The following adds a new attribute to the sysfs representation | |
3340 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
3341 | * used for controlling the debug level. | |
3342 | * | |
3343 | * See the level definitions in iwl for details. | |
a562a9dd | 3344 | * |
3d816c77 RC |
3345 | * The debug_level being managed using sysfs below is a per device debug |
3346 | * level that is used instead of the global debug level if it (the per | |
3347 | * device debug level) is set. | |
b481de9c | 3348 | */ |
40b8ec0b SO |
3349 | static ssize_t show_debug_level(struct device *d, |
3350 | struct device_attribute *attr, char *buf) | |
b481de9c | 3351 | { |
3d816c77 RC |
3352 | struct iwl_priv *priv = dev_get_drvdata(d); |
3353 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
b481de9c | 3354 | } |
40b8ec0b SO |
3355 | static ssize_t store_debug_level(struct device *d, |
3356 | struct device_attribute *attr, | |
b481de9c ZY |
3357 | const char *buf, size_t count) |
3358 | { | |
928841b1 | 3359 | struct iwl_priv *priv = dev_get_drvdata(d); |
40b8ec0b SO |
3360 | unsigned long val; |
3361 | int ret; | |
b481de9c | 3362 | |
40b8ec0b SO |
3363 | ret = strict_strtoul(buf, 0, &val); |
3364 | if (ret) | |
978785a3 | 3365 | IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf); |
20594eb0 | 3366 | else { |
3d816c77 | 3367 | priv->debug_level = val; |
20594eb0 WYG |
3368 | if (iwl_alloc_traffic_mem(priv)) |
3369 | IWL_ERR(priv, | |
3370 | "Not enough memory to generate traffic log\n"); | |
3371 | } | |
b481de9c ZY |
3372 | return strnlen(buf, count); |
3373 | } | |
3374 | ||
40b8ec0b SO |
3375 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
3376 | show_debug_level, store_debug_level); | |
b481de9c | 3377 | |
d08853a3 | 3378 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 3379 | |
b481de9c ZY |
3380 | static ssize_t show_temperature(struct device *d, |
3381 | struct device_attribute *attr, char *buf) | |
3382 | { | |
928841b1 | 3383 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3384 | |
775a6e27 | 3385 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3386 | return -EAGAIN; |
3387 | ||
bb8c093b | 3388 | return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv)); |
b481de9c ZY |
3389 | } |
3390 | ||
3391 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
3392 | ||
b481de9c ZY |
3393 | static ssize_t show_tx_power(struct device *d, |
3394 | struct device_attribute *attr, char *buf) | |
3395 | { | |
928841b1 | 3396 | struct iwl_priv *priv = dev_get_drvdata(d); |
62ea9c5b | 3397 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); |
b481de9c ZY |
3398 | } |
3399 | ||
3400 | static ssize_t store_tx_power(struct device *d, | |
3401 | struct device_attribute *attr, | |
3402 | const char *buf, size_t count) | |
3403 | { | |
928841b1 | 3404 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3405 | char *p = (char *)buf; |
3406 | u32 val; | |
3407 | ||
3408 | val = simple_strtoul(p, &p, 10); | |
3409 | if (p == buf) | |
978785a3 | 3410 | IWL_INFO(priv, ": %s is not in decimal form.\n", buf); |
b481de9c | 3411 | else |
bb8c093b | 3412 | iwl3945_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
3413 | |
3414 | return count; | |
3415 | } | |
3416 | ||
3417 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
3418 | ||
3419 | static ssize_t show_flags(struct device *d, | |
3420 | struct device_attribute *attr, char *buf) | |
3421 | { | |
928841b1 | 3422 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3423 | |
8ccde88a | 3424 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); |
b481de9c ZY |
3425 | } |
3426 | ||
3427 | static ssize_t store_flags(struct device *d, | |
3428 | struct device_attribute *attr, | |
3429 | const char *buf, size_t count) | |
3430 | { | |
928841b1 | 3431 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3432 | u32 flags = simple_strtoul(buf, NULL, 0); |
3433 | ||
3434 | mutex_lock(&priv->mutex); | |
8ccde88a | 3435 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { |
b481de9c | 3436 | /* Cancel any currently running scans... */ |
af0053d6 | 3437 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3438 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3439 | else { |
e1623446 | 3440 | IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n", |
b481de9c | 3441 | flags); |
8ccde88a | 3442 | priv->staging_rxon.flags = cpu_to_le32(flags); |
e0158e61 | 3443 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3444 | } |
3445 | } | |
3446 | mutex_unlock(&priv->mutex); | |
3447 | ||
3448 | return count; | |
3449 | } | |
3450 | ||
3451 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
3452 | ||
3453 | static ssize_t show_filter_flags(struct device *d, | |
3454 | struct device_attribute *attr, char *buf) | |
3455 | { | |
928841b1 | 3456 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3457 | |
3458 | return sprintf(buf, "0x%04X\n", | |
8ccde88a | 3459 | le32_to_cpu(priv->active_rxon.filter_flags)); |
b481de9c ZY |
3460 | } |
3461 | ||
3462 | static ssize_t store_filter_flags(struct device *d, | |
3463 | struct device_attribute *attr, | |
3464 | const char *buf, size_t count) | |
3465 | { | |
928841b1 | 3466 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3467 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
3468 | ||
3469 | mutex_lock(&priv->mutex); | |
8ccde88a | 3470 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { |
b481de9c | 3471 | /* Cancel any currently running scans... */ |
af0053d6 | 3472 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3473 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3474 | else { |
e1623446 | 3475 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c | 3476 | "0x%04X\n", filter_flags); |
8ccde88a | 3477 | priv->staging_rxon.filter_flags = |
b481de9c | 3478 | cpu_to_le32(filter_flags); |
e0158e61 | 3479 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3480 | } |
3481 | } | |
3482 | mutex_unlock(&priv->mutex); | |
3483 | ||
3484 | return count; | |
3485 | } | |
3486 | ||
3487 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
3488 | store_filter_flags); | |
3489 | ||
c8b0e6e1 | 3490 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
3491 | |
3492 | static ssize_t show_measurement(struct device *d, | |
3493 | struct device_attribute *attr, char *buf) | |
3494 | { | |
4a8a4322 | 3495 | struct iwl_priv *priv = dev_get_drvdata(d); |
600c0e11 | 3496 | struct iwl_spectrum_notification measure_report; |
b481de9c | 3497 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
3ac7f146 | 3498 | u8 *data = (u8 *)&measure_report; |
b481de9c ZY |
3499 | unsigned long flags; |
3500 | ||
3501 | spin_lock_irqsave(&priv->lock, flags); | |
3502 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
3503 | spin_unlock_irqrestore(&priv->lock, flags); | |
3504 | return 0; | |
3505 | } | |
3506 | memcpy(&measure_report, &priv->measure_report, size); | |
3507 | priv->measurement_status = 0; | |
3508 | spin_unlock_irqrestore(&priv->lock, flags); | |
3509 | ||
3510 | while (size && (PAGE_SIZE - len)) { | |
3511 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3512 | PAGE_SIZE - len, 1); | |
3513 | len = strlen(buf); | |
3514 | if (PAGE_SIZE - len) | |
3515 | buf[len++] = '\n'; | |
3516 | ||
3517 | ofs += 16; | |
3518 | size -= min(size, 16U); | |
3519 | } | |
3520 | ||
3521 | return len; | |
3522 | } | |
3523 | ||
3524 | static ssize_t store_measurement(struct device *d, | |
3525 | struct device_attribute *attr, | |
3526 | const char *buf, size_t count) | |
3527 | { | |
4a8a4322 | 3528 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3529 | struct ieee80211_measurement_params params = { |
8ccde88a | 3530 | .channel = le16_to_cpu(priv->active_rxon.channel), |
b481de9c ZY |
3531 | .start_time = cpu_to_le64(priv->last_tsf), |
3532 | .duration = cpu_to_le16(1), | |
3533 | }; | |
3534 | u8 type = IWL_MEASURE_BASIC; | |
3535 | u8 buffer[32]; | |
3536 | u8 channel; | |
3537 | ||
3538 | if (count) { | |
3539 | char *p = buffer; | |
3540 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
3541 | channel = simple_strtoul(p, NULL, 0); | |
3542 | if (channel) | |
3543 | params.channel = channel; | |
3544 | ||
3545 | p = buffer; | |
3546 | while (*p && *p != ' ') | |
3547 | p++; | |
3548 | if (*p) | |
3549 | type = simple_strtoul(p + 1, NULL, 0); | |
3550 | } | |
3551 | ||
e1623446 | 3552 | IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on " |
b481de9c | 3553 | "channel %d (for '%s')\n", type, params.channel, buf); |
bb8c093b | 3554 | iwl3945_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
3555 | |
3556 | return count; | |
3557 | } | |
3558 | ||
3559 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
3560 | show_measurement, store_measurement); | |
c8b0e6e1 | 3561 | #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */ |
b481de9c | 3562 | |
b481de9c ZY |
3563 | static ssize_t store_retry_rate(struct device *d, |
3564 | struct device_attribute *attr, | |
3565 | const char *buf, size_t count) | |
3566 | { | |
4a8a4322 | 3567 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3568 | |
3569 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
3570 | if (priv->retry_rate <= 0) | |
3571 | priv->retry_rate = 1; | |
3572 | ||
3573 | return count; | |
3574 | } | |
3575 | ||
3576 | static ssize_t show_retry_rate(struct device *d, | |
3577 | struct device_attribute *attr, char *buf) | |
3578 | { | |
4a8a4322 | 3579 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3580 | return sprintf(buf, "%d", priv->retry_rate); |
3581 | } | |
3582 | ||
3583 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
3584 | store_retry_rate); | |
3585 | ||
d25aabb0 | 3586 | |
b481de9c ZY |
3587 | static ssize_t show_channels(struct device *d, |
3588 | struct device_attribute *attr, char *buf) | |
3589 | { | |
8318d78a JB |
3590 | /* all this shit doesn't belong into sysfs anyway */ |
3591 | return 0; | |
b481de9c ZY |
3592 | } |
3593 | ||
3594 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
3595 | ||
3596 | static ssize_t show_statistics(struct device *d, | |
3597 | struct device_attribute *attr, char *buf) | |
3598 | { | |
4a8a4322 | 3599 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 3600 | u32 size = sizeof(struct iwl3945_notif_statistics); |
b481de9c | 3601 | u32 len = 0, ofs = 0; |
f2c7e521 | 3602 | u8 *data = (u8 *)&priv->statistics_39; |
b481de9c ZY |
3603 | int rc = 0; |
3604 | ||
775a6e27 | 3605 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3606 | return -EAGAIN; |
3607 | ||
3608 | mutex_lock(&priv->mutex); | |
17f841cd | 3609 | rc = iwl_send_statistics_request(priv, 0); |
b481de9c ZY |
3610 | mutex_unlock(&priv->mutex); |
3611 | ||
3612 | if (rc) { | |
3613 | len = sprintf(buf, | |
3614 | "Error sending statistics request: 0x%08X\n", rc); | |
3615 | return len; | |
3616 | } | |
3617 | ||
3618 | while (size && (PAGE_SIZE - len)) { | |
3619 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3620 | PAGE_SIZE - len, 1); | |
3621 | len = strlen(buf); | |
3622 | if (PAGE_SIZE - len) | |
3623 | buf[len++] = '\n'; | |
3624 | ||
3625 | ofs += 16; | |
3626 | size -= min(size, 16U); | |
3627 | } | |
3628 | ||
3629 | return len; | |
3630 | } | |
3631 | ||
3632 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
3633 | ||
3634 | static ssize_t show_antenna(struct device *d, | |
3635 | struct device_attribute *attr, char *buf) | |
3636 | { | |
4a8a4322 | 3637 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3638 | |
775a6e27 | 3639 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3640 | return -EAGAIN; |
3641 | ||
7e4bca5e | 3642 | return sprintf(buf, "%d\n", iwl3945_mod_params.antenna); |
b481de9c ZY |
3643 | } |
3644 | ||
3645 | static ssize_t store_antenna(struct device *d, | |
3646 | struct device_attribute *attr, | |
3647 | const char *buf, size_t count) | |
3648 | { | |
7530f85f | 3649 | struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d); |
b481de9c | 3650 | int ant; |
b481de9c ZY |
3651 | |
3652 | if (count == 0) | |
3653 | return 0; | |
3654 | ||
3655 | if (sscanf(buf, "%1i", &ant) != 1) { | |
e1623446 | 3656 | IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n"); |
b481de9c ZY |
3657 | return count; |
3658 | } | |
3659 | ||
3660 | if ((ant >= 0) && (ant <= 2)) { | |
e1623446 | 3661 | IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant); |
7e4bca5e | 3662 | iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant; |
b481de9c | 3663 | } else |
e1623446 | 3664 | IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant); |
b481de9c ZY |
3665 | |
3666 | ||
3667 | return count; | |
3668 | } | |
3669 | ||
3670 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
3671 | ||
3672 | static ssize_t show_status(struct device *d, | |
3673 | struct device_attribute *attr, char *buf) | |
3674 | { | |
928841b1 | 3675 | struct iwl_priv *priv = dev_get_drvdata(d); |
775a6e27 | 3676 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3677 | return -EAGAIN; |
3678 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
3679 | } | |
3680 | ||
3681 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
3682 | ||
3683 | static ssize_t dump_error_log(struct device *d, | |
3684 | struct device_attribute *attr, | |
3685 | const char *buf, size_t count) | |
3686 | { | |
928841b1 | 3687 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3688 | char *p = (char *)buf; |
3689 | ||
3690 | if (p[0] == '1') | |
928841b1 | 3691 | iwl3945_dump_nic_error_log(priv); |
b481de9c ZY |
3692 | |
3693 | return strnlen(buf, count); | |
3694 | } | |
3695 | ||
3696 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
3697 | ||
b481de9c ZY |
3698 | /***************************************************************************** |
3699 | * | |
a96a27f9 | 3700 | * driver setup and tear down |
b481de9c ZY |
3701 | * |
3702 | *****************************************************************************/ | |
3703 | ||
4a8a4322 | 3704 | static void iwl3945_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3705 | { |
d21050c7 | 3706 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3707 | |
3708 | init_waitqueue_head(&priv->wait_command_queue); | |
3709 | ||
bb8c093b CH |
3710 | INIT_WORK(&priv->up, iwl3945_bg_up); |
3711 | INIT_WORK(&priv->restart, iwl3945_bg_restart); | |
3712 | INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish); | |
bb8c093b | 3713 | INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); |
bb8c093b CH |
3714 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); |
3715 | INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); | |
2663516d | 3716 | INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll); |
77fecfb8 SO |
3717 | INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed); |
3718 | INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan); | |
3719 | INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan); | |
3720 | INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check); | |
bb8c093b CH |
3721 | |
3722 | iwl3945_hw_setup_deferred_work(priv); | |
b481de9c ZY |
3723 | |
3724 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 3725 | iwl3945_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
3726 | } |
3727 | ||
4a8a4322 | 3728 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3729 | { |
bb8c093b | 3730 | iwl3945_hw_cancel_deferred_work(priv); |
b481de9c | 3731 | |
e47eb6ad | 3732 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
3733 | cancel_delayed_work(&priv->scan_check); |
3734 | cancel_delayed_work(&priv->alive_start); | |
b481de9c ZY |
3735 | cancel_work_sync(&priv->beacon_update); |
3736 | } | |
3737 | ||
bb8c093b | 3738 | static struct attribute *iwl3945_sysfs_entries[] = { |
b481de9c ZY |
3739 | &dev_attr_antenna.attr, |
3740 | &dev_attr_channels.attr, | |
3741 | &dev_attr_dump_errors.attr, | |
b481de9c ZY |
3742 | &dev_attr_flags.attr, |
3743 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 3744 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
3745 | &dev_attr_measurement.attr, |
3746 | #endif | |
b481de9c | 3747 | &dev_attr_retry_rate.attr, |
b481de9c ZY |
3748 | &dev_attr_statistics.attr, |
3749 | &dev_attr_status.attr, | |
3750 | &dev_attr_temperature.attr, | |
b481de9c | 3751 | &dev_attr_tx_power.attr, |
d08853a3 | 3752 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b SO |
3753 | &dev_attr_debug_level.attr, |
3754 | #endif | |
b481de9c ZY |
3755 | NULL |
3756 | }; | |
3757 | ||
bb8c093b | 3758 | static struct attribute_group iwl3945_attribute_group = { |
b481de9c | 3759 | .name = NULL, /* put in device directory */ |
bb8c093b | 3760 | .attrs = iwl3945_sysfs_entries, |
b481de9c ZY |
3761 | }; |
3762 | ||
bb8c093b CH |
3763 | static struct ieee80211_ops iwl3945_hw_ops = { |
3764 | .tx = iwl3945_mac_tx, | |
3765 | .start = iwl3945_mac_start, | |
3766 | .stop = iwl3945_mac_stop, | |
cbb6ab94 | 3767 | .add_interface = iwl_mac_add_interface, |
d8052319 | 3768 | .remove_interface = iwl_mac_remove_interface, |
4808368d | 3769 | .config = iwl_mac_config, |
8ccde88a | 3770 | .configure_filter = iwl_configure_filter, |
bb8c093b | 3771 | .set_key = iwl3945_mac_set_key, |
aa89f31e | 3772 | .get_tx_stats = iwl_mac_get_tx_stats, |
488829f1 | 3773 | .conf_tx = iwl_mac_conf_tx, |
bd564261 | 3774 | .reset_tsf = iwl_mac_reset_tsf, |
5bbe233b | 3775 | .bss_info_changed = iwl_bss_info_changed, |
e9dde6f6 | 3776 | .hw_scan = iwl_mac_hw_scan |
b481de9c ZY |
3777 | }; |
3778 | ||
e52119c5 | 3779 | static int iwl3945_init_drv(struct iwl_priv *priv) |
90a30a02 KA |
3780 | { |
3781 | int ret; | |
e6148917 | 3782 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
90a30a02 KA |
3783 | |
3784 | priv->retry_rate = 1; | |
3785 | priv->ibss_beacon = NULL; | |
3786 | ||
3787 | spin_lock_init(&priv->lock); | |
90a30a02 KA |
3788 | spin_lock_init(&priv->sta_lock); |
3789 | spin_lock_init(&priv->hcmd_lock); | |
3790 | ||
3791 | INIT_LIST_HEAD(&priv->free_frames); | |
3792 | ||
3793 | mutex_init(&priv->mutex); | |
3794 | ||
3795 | /* Clear the driver's (not device's) station table */ | |
c587de0b | 3796 | iwl_clear_stations_table(priv); |
90a30a02 KA |
3797 | |
3798 | priv->data_retry_limit = -1; | |
3799 | priv->ieee_channels = NULL; | |
3800 | priv->ieee_rates = NULL; | |
3801 | priv->band = IEEE80211_BAND_2GHZ; | |
3802 | ||
3803 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
3804 | ||
3805 | iwl_reset_qos(priv); | |
3806 | ||
3807 | priv->qos_data.qos_active = 0; | |
3808 | priv->qos_data.qos_cap.val = 0; | |
3809 | ||
3810 | priv->rates_mask = IWL_RATES_MASK; | |
62ea9c5b | 3811 | priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER; |
90a30a02 | 3812 | |
e6148917 SO |
3813 | if (eeprom->version < EEPROM_3945_EEPROM_VERSION) { |
3814 | IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n", | |
3815 | eeprom->version); | |
3816 | ret = -EINVAL; | |
3817 | goto err; | |
3818 | } | |
3819 | ret = iwl_init_channel_map(priv); | |
90a30a02 KA |
3820 | if (ret) { |
3821 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3822 | goto err; | |
3823 | } | |
3824 | ||
e6148917 SO |
3825 | /* Set up txpower settings in driver for all channels */ |
3826 | if (iwl3945_txpower_set_from_eeprom(priv)) { | |
3827 | ret = -EIO; | |
3828 | goto err_free_channel_map; | |
3829 | } | |
3830 | ||
534166de | 3831 | ret = iwlcore_init_geos(priv); |
90a30a02 KA |
3832 | if (ret) { |
3833 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3834 | goto err_free_channel_map; | |
3835 | } | |
534166de SO |
3836 | iwl3945_init_hw_rates(priv, priv->ieee_rates); |
3837 | ||
2a4ddaab AK |
3838 | return 0; |
3839 | ||
3840 | err_free_channel_map: | |
3841 | iwl_free_channel_map(priv); | |
3842 | err: | |
3843 | return ret; | |
3844 | } | |
3845 | ||
3846 | static int iwl3945_setup_mac(struct iwl_priv *priv) | |
3847 | { | |
3848 | int ret; | |
3849 | struct ieee80211_hw *hw = priv->hw; | |
3850 | ||
3851 | hw->rate_control_algorithm = "iwl-3945-rs"; | |
3852 | hw->sta_data_size = sizeof(struct iwl3945_sta_priv); | |
3853 | ||
3854 | /* Tell mac80211 our characteristics */ | |
3855 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
b1c6019b | 3856 | IEEE80211_HW_NOISE_DBM | |
e312c24c JB |
3857 | IEEE80211_HW_SPECTRUM_MGMT | |
3858 | IEEE80211_HW_SUPPORTS_PS | | |
3859 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
2a4ddaab AK |
3860 | |
3861 | hw->wiphy->interface_modes = | |
3862 | BIT(NL80211_IFTYPE_STATION) | | |
3863 | BIT(NL80211_IFTYPE_ADHOC); | |
3864 | ||
3865 | hw->wiphy->custom_regulatory = true; | |
3866 | ||
37184244 LR |
3867 | /* Firmware does not support this */ |
3868 | hw->wiphy->disable_beacon_hints = true; | |
3869 | ||
1ecf9fc1 JB |
3870 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945; |
3871 | /* we create the 802.11 header and a zero-length SSID element */ | |
3872 | hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2; | |
d60cc91a | 3873 | |
2a4ddaab AK |
3874 | /* Default value; 4 EDCA QOS priorities */ |
3875 | hw->queues = 4; | |
3876 | ||
534166de SO |
3877 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
3878 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
3879 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2a4ddaab | 3880 | |
534166de SO |
3881 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) |
3882 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
3883 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
90a30a02 | 3884 | |
2a4ddaab AK |
3885 | ret = ieee80211_register_hw(priv->hw); |
3886 | if (ret) { | |
3887 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
3888 | return ret; | |
3889 | } | |
3890 | priv->mac80211_registered = 1; | |
90a30a02 | 3891 | |
2a4ddaab | 3892 | return 0; |
90a30a02 KA |
3893 | } |
3894 | ||
bb8c093b | 3895 | static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
3896 | { |
3897 | int err = 0; | |
4a8a4322 | 3898 | struct iwl_priv *priv; |
b481de9c | 3899 | struct ieee80211_hw *hw; |
c0f20d91 | 3900 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
e6148917 | 3901 | struct iwl3945_eeprom *eeprom; |
0359facc | 3902 | unsigned long flags; |
b481de9c | 3903 | |
cee53ddb KA |
3904 | /*********************** |
3905 | * 1. Allocating HW data | |
3906 | * ********************/ | |
3907 | ||
b481de9c ZY |
3908 | /* mac80211 allocates memory for this device instance, including |
3909 | * space for this driver's private structure */ | |
90a30a02 | 3910 | hw = iwl_alloc_all(cfg, &iwl3945_hw_ops); |
b481de9c | 3911 | if (hw == NULL) { |
a3139c59 | 3912 | printk(KERN_ERR DRV_NAME "Can not allocate network device\n"); |
b481de9c ZY |
3913 | err = -ENOMEM; |
3914 | goto out; | |
3915 | } | |
b481de9c | 3916 | priv = hw->priv; |
90a30a02 | 3917 | SET_IEEE80211_DEV(hw, &pdev->dev); |
6440adb5 | 3918 | |
90a30a02 KA |
3919 | /* |
3920 | * Disabling hardware scan means that mac80211 will perform scans | |
3921 | * "the hard way", rather than using device's scan. | |
3922 | */ | |
df878d8f | 3923 | if (iwl3945_mod_params.disable_hw_scan) { |
e1623446 | 3924 | IWL_DEBUG_INFO(priv, "Disabling hw_scan\n"); |
40b8ec0b SO |
3925 | iwl3945_hw_ops.hw_scan = NULL; |
3926 | } | |
3927 | ||
90a30a02 | 3928 | |
e1623446 | 3929 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
90a30a02 KA |
3930 | priv->cfg = cfg; |
3931 | priv->pci_dev = pdev; | |
40cefda9 | 3932 | priv->inta_mask = CSR_INI_SET_MASK; |
cee53ddb | 3933 | |
d08853a3 | 3934 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3935 | atomic_set(&priv->restrict_refcnt, 0); |
3936 | #endif | |
20594eb0 WYG |
3937 | if (iwl_alloc_traffic_mem(priv)) |
3938 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 3939 | |
cee53ddb KA |
3940 | /*************************** |
3941 | * 2. Initializing PCI bus | |
3942 | * *************************/ | |
b481de9c ZY |
3943 | if (pci_enable_device(pdev)) { |
3944 | err = -ENODEV; | |
3945 | goto out_ieee80211_free_hw; | |
3946 | } | |
3947 | ||
3948 | pci_set_master(pdev); | |
3949 | ||
284901a9 | 3950 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 3951 | if (!err) |
284901a9 | 3952 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 3953 | if (err) { |
978785a3 | 3954 | IWL_WARN(priv, "No suitable DMA available.\n"); |
b481de9c ZY |
3955 | goto out_pci_disable_device; |
3956 | } | |
3957 | ||
3958 | pci_set_drvdata(pdev, priv); | |
3959 | err = pci_request_regions(pdev, DRV_NAME); | |
3960 | if (err) | |
3961 | goto out_pci_disable_device; | |
6440adb5 | 3962 | |
cee53ddb KA |
3963 | /*********************** |
3964 | * 3. Read REV Register | |
3965 | * ********************/ | |
b481de9c ZY |
3966 | priv->hw_base = pci_iomap(pdev, 0, 0); |
3967 | if (!priv->hw_base) { | |
3968 | err = -ENODEV; | |
3969 | goto out_pci_release_regions; | |
3970 | } | |
3971 | ||
e1623446 | 3972 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
b481de9c | 3973 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 3974 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
b481de9c | 3975 | |
cee53ddb KA |
3976 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
3977 | * PCI Tx retries from interfering with C3 CPU state */ | |
3978 | pci_write_config_byte(pdev, 0x41, 0x00); | |
b481de9c | 3979 | |
a8b50a0a MA |
3980 | /* this spin lock will be used in apm_ops.init and EEPROM access |
3981 | * we should init now | |
3982 | */ | |
3983 | spin_lock_init(&priv->reg_lock); | |
3984 | ||
90a30a02 KA |
3985 | /* amp init */ |
3986 | err = priv->cfg->ops->lib->apm_ops.init(priv); | |
cee53ddb | 3987 | if (err < 0) { |
d5df2a16 | 3988 | IWL_DEBUG_INFO(priv, "Failed to init the card\n"); |
90a30a02 | 3989 | goto out_iounmap; |
cee53ddb | 3990 | } |
b481de9c | 3991 | |
cee53ddb KA |
3992 | /*********************** |
3993 | * 4. Read EEPROM | |
3994 | * ********************/ | |
90a30a02 | 3995 | |
cee53ddb | 3996 | /* Read the EEPROM */ |
e6148917 | 3997 | err = iwl_eeprom_init(priv); |
cee53ddb | 3998 | if (err) { |
15b1687c | 3999 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
c8f16138 | 4000 | goto out_iounmap; |
cee53ddb KA |
4001 | } |
4002 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
e6148917 SO |
4003 | eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
4004 | memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN); | |
e1623446 | 4005 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
cee53ddb | 4006 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
b481de9c | 4007 | |
cee53ddb KA |
4008 | /*********************** |
4009 | * 5. Setup HW Constants | |
4010 | * ********************/ | |
b481de9c | 4011 | /* Device-specific setup */ |
3832ec9d | 4012 | if (iwl3945_hw_set_hw_params(priv)) { |
15b1687c | 4013 | IWL_ERR(priv, "failed to set hw settings\n"); |
c8f16138 | 4014 | goto out_eeprom_free; |
b481de9c ZY |
4015 | } |
4016 | ||
cee53ddb KA |
4017 | /*********************** |
4018 | * 6. Setup priv | |
4019 | * ********************/ | |
cee53ddb | 4020 | |
90a30a02 | 4021 | err = iwl3945_init_drv(priv); |
b481de9c | 4022 | if (err) { |
90a30a02 | 4023 | IWL_ERR(priv, "initializing driver failed\n"); |
c8f16138 | 4024 | goto out_unset_hw_params; |
b481de9c ZY |
4025 | } |
4026 | ||
978785a3 TW |
4027 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n", |
4028 | priv->cfg->name); | |
cee53ddb | 4029 | |
cee53ddb | 4030 | /*********************** |
09f9bf79 | 4031 | * 7. Setup Services |
cee53ddb KA |
4032 | * ********************/ |
4033 | ||
4034 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4035 | iwl_disable_interrupts(priv); |
cee53ddb KA |
4036 | spin_unlock_irqrestore(&priv->lock, flags); |
4037 | ||
2663516d HS |
4038 | pci_enable_msi(priv->pci_dev); |
4039 | ||
ef850d7c MA |
4040 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, |
4041 | IRQF_SHARED, DRV_NAME, priv); | |
2663516d HS |
4042 | if (err) { |
4043 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
4044 | goto out_disable_msi; | |
4045 | } | |
4046 | ||
cee53ddb | 4047 | err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
849e0dce | 4048 | if (err) { |
15b1687c | 4049 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
90a30a02 | 4050 | goto out_release_irq; |
849e0dce | 4051 | } |
849e0dce | 4052 | |
8ccde88a SO |
4053 | iwl_set_rxon_channel(priv, |
4054 | &priv->bands[IEEE80211_BAND_2GHZ].channels[5]); | |
cee53ddb KA |
4055 | iwl3945_setup_deferred_work(priv); |
4056 | iwl3945_setup_rx_handlers(priv); | |
4057 | ||
cee53ddb | 4058 | /********************************* |
09f9bf79 | 4059 | * 8. Setup and Register mac80211 |
cee53ddb KA |
4060 | * *******************************/ |
4061 | ||
2a4ddaab | 4062 | iwl_enable_interrupts(priv); |
b481de9c | 4063 | |
2a4ddaab AK |
4064 | err = iwl3945_setup_mac(priv); |
4065 | if (err) | |
4066 | goto out_remove_sysfs; | |
cee53ddb | 4067 | |
a75fbe8d AK |
4068 | err = iwl_dbgfs_register(priv, DRV_NAME); |
4069 | if (err) | |
4070 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
4071 | ||
2663516d HS |
4072 | /* Start monitoring the killswitch */ |
4073 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
4074 | 2 * HZ); | |
4075 | ||
b481de9c ZY |
4076 | return 0; |
4077 | ||
cee53ddb | 4078 | out_remove_sysfs: |
c8f16138 RC |
4079 | destroy_workqueue(priv->workqueue); |
4080 | priv->workqueue = NULL; | |
cee53ddb | 4081 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4082 | out_release_irq: |
2663516d | 4083 | free_irq(priv->pci_dev->irq, priv); |
2663516d HS |
4084 | out_disable_msi: |
4085 | pci_disable_msi(priv->pci_dev); | |
c8f16138 RC |
4086 | iwlcore_free_geos(priv); |
4087 | iwl_free_channel_map(priv); | |
4088 | out_unset_hw_params: | |
4089 | iwl3945_unset_hw_params(priv); | |
4090 | out_eeprom_free: | |
4091 | iwl_eeprom_free(priv); | |
b481de9c ZY |
4092 | out_iounmap: |
4093 | pci_iounmap(pdev, priv->hw_base); | |
4094 | out_pci_release_regions: | |
4095 | pci_release_regions(pdev); | |
4096 | out_pci_disable_device: | |
b481de9c | 4097 | pci_set_drvdata(pdev, NULL); |
623d563e | 4098 | pci_disable_device(pdev); |
b481de9c ZY |
4099 | out_ieee80211_free_hw: |
4100 | ieee80211_free_hw(priv->hw); | |
20594eb0 | 4101 | iwl_free_traffic_mem(priv); |
b481de9c ZY |
4102 | out: |
4103 | return err; | |
4104 | } | |
4105 | ||
c83dbf68 | 4106 | static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) |
b481de9c | 4107 | { |
4a8a4322 | 4108 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 4109 | unsigned long flags; |
b481de9c ZY |
4110 | |
4111 | if (!priv) | |
4112 | return; | |
4113 | ||
e1623446 | 4114 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 4115 | |
a75fbe8d AK |
4116 | iwl_dbgfs_unregister(priv); |
4117 | ||
b481de9c | 4118 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 4119 | |
d552bfb6 KA |
4120 | if (priv->mac80211_registered) { |
4121 | ieee80211_unregister_hw(priv->hw); | |
4122 | priv->mac80211_registered = 0; | |
4123 | } else { | |
4124 | iwl3945_down(priv); | |
4125 | } | |
b481de9c | 4126 | |
0359facc MA |
4127 | /* make sure we flush any pending irq or |
4128 | * tasklet for the driver | |
4129 | */ | |
4130 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4131 | iwl_disable_interrupts(priv); |
0359facc MA |
4132 | spin_unlock_irqrestore(&priv->lock, flags); |
4133 | ||
4134 | iwl_synchronize_irq(priv); | |
4135 | ||
bb8c093b | 4136 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4137 | |
71d449b5 | 4138 | cancel_delayed_work_sync(&priv->rfkill_poll); |
2663516d | 4139 | |
bb8c093b | 4140 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
4141 | |
4142 | if (priv->rxq.bd) | |
df833b1d | 4143 | iwl3945_rx_queue_free(priv, &priv->rxq); |
bb8c093b | 4144 | iwl3945_hw_txq_ctx_free(priv); |
b481de9c | 4145 | |
3832ec9d | 4146 | iwl3945_unset_hw_params(priv); |
c587de0b | 4147 | iwl_clear_stations_table(priv); |
b481de9c | 4148 | |
6ef89d0a MA |
4149 | /*netif_stop_queue(dev); */ |
4150 | flush_workqueue(priv->workqueue); | |
4151 | ||
bb8c093b | 4152 | /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes |
b481de9c ZY |
4153 | * priv->workqueue... so we can't take down the workqueue |
4154 | * until now... */ | |
4155 | destroy_workqueue(priv->workqueue); | |
4156 | priv->workqueue = NULL; | |
20594eb0 | 4157 | iwl_free_traffic_mem(priv); |
b481de9c | 4158 | |
2663516d HS |
4159 | free_irq(pdev->irq, priv); |
4160 | pci_disable_msi(pdev); | |
4161 | ||
b481de9c ZY |
4162 | pci_iounmap(pdev, priv->hw_base); |
4163 | pci_release_regions(pdev); | |
4164 | pci_disable_device(pdev); | |
4165 | pci_set_drvdata(pdev, NULL); | |
4166 | ||
e6148917 | 4167 | iwl_free_channel_map(priv); |
534166de | 4168 | iwlcore_free_geos(priv); |
805cee5b | 4169 | kfree(priv->scan); |
b481de9c ZY |
4170 | if (priv->ibss_beacon) |
4171 | dev_kfree_skb(priv->ibss_beacon); | |
4172 | ||
4173 | ieee80211_free_hw(priv->hw); | |
4174 | } | |
4175 | ||
b481de9c ZY |
4176 | |
4177 | /***************************************************************************** | |
4178 | * | |
4179 | * driver and module entry point | |
4180 | * | |
4181 | *****************************************************************************/ | |
4182 | ||
bb8c093b | 4183 | static struct pci_driver iwl3945_driver = { |
b481de9c | 4184 | .name = DRV_NAME, |
bb8c093b CH |
4185 | .id_table = iwl3945_hw_card_ids, |
4186 | .probe = iwl3945_pci_probe, | |
4187 | .remove = __devexit_p(iwl3945_pci_remove), | |
b481de9c | 4188 | #ifdef CONFIG_PM |
6da3a13e WYG |
4189 | .suspend = iwl_pci_suspend, |
4190 | .resume = iwl_pci_resume, | |
b481de9c ZY |
4191 | #endif |
4192 | }; | |
4193 | ||
bb8c093b | 4194 | static int __init iwl3945_init(void) |
b481de9c ZY |
4195 | { |
4196 | ||
4197 | int ret; | |
4198 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
4199 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
4200 | |
4201 | ret = iwl3945_rate_control_register(); | |
4202 | if (ret) { | |
a3139c59 SO |
4203 | printk(KERN_ERR DRV_NAME |
4204 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
4205 | return ret; |
4206 | } | |
4207 | ||
bb8c093b | 4208 | ret = pci_register_driver(&iwl3945_driver); |
b481de9c | 4209 | if (ret) { |
a3139c59 | 4210 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 4211 | goto error_register; |
b481de9c | 4212 | } |
b481de9c ZY |
4213 | |
4214 | return ret; | |
897e1cf2 | 4215 | |
897e1cf2 RC |
4216 | error_register: |
4217 | iwl3945_rate_control_unregister(); | |
4218 | return ret; | |
b481de9c ZY |
4219 | } |
4220 | ||
bb8c093b | 4221 | static void __exit iwl3945_exit(void) |
b481de9c | 4222 | { |
bb8c093b | 4223 | pci_unregister_driver(&iwl3945_driver); |
897e1cf2 | 4224 | iwl3945_rate_control_unregister(); |
b481de9c ZY |
4225 | } |
4226 | ||
a0987a8d | 4227 | MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX)); |
25cb6cad | 4228 | |
df878d8f | 4229 | module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444); |
b481de9c | 4230 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
9c74d9fb SO |
4231 | module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444); |
4232 | MODULE_PARM_DESC(swcrypto, | |
4233 | "using software crypto (default 1 [software])\n"); | |
a562a9dd RC |
4234 | #ifdef CONFIG_IWLWIFI_DEBUG |
4235 | module_param_named(debug, iwl_debug_level, uint, 0644); | |
b481de9c | 4236 | MODULE_PARM_DESC(debug, "debug output mask"); |
a562a9dd | 4237 | #endif |
df878d8f | 4238 | module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444); |
b481de9c | 4239 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |
af48d048 SO |
4240 | module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, 0444); |
4241 | MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error"); | |
4242 | ||
bb8c093b CH |
4243 | module_exit(iwl3945_exit); |
4244 | module_init(iwl3945_init); |