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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
759ef89f | 22 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
24 | * | |
25 | *****************************************************************************/ | |
fcd427bb | 26 | /* |
3e0d4cb1 | 27 | * Please use this file (iwl-dev.h) for driver implementation definitions. |
5a36ba0e | 28 | * Please use iwl-commands.h for uCode API definitions. |
fcd427bb BC |
29 | * Please use iwl-4965-hw.h for hardware-related definitions. |
30 | */ | |
31 | ||
be1f3ab6 EG |
32 | #ifndef __iwl_dev_h__ |
33 | #define __iwl_dev_h__ | |
b481de9c | 34 | |
5d08cd1d CH |
35 | #include <linux/pci.h> /* for struct pci_device_id */ |
36 | #include <linux/kernel.h> | |
37 | #include <net/ieee80211_radiotap.h> | |
38 | ||
6bc913bd | 39 | #include "iwl-eeprom.h" |
6f83eaa1 | 40 | #include "iwl-csr.h" |
5d08cd1d | 41 | #include "iwl-prph.h" |
dbb6654c | 42 | #include "iwl-fh.h" |
0a6857e7 | 43 | #include "iwl-debug.h" |
dbb6654c WT |
44 | #include "iwl-4965-hw.h" |
45 | #include "iwl-3945-hw.h" | |
ab53d8af | 46 | #include "iwl-led.h" |
5da4b55f | 47 | #include "iwl-power.h" |
e227ceac | 48 | #include "iwl-agn-rs.h" |
5d08cd1d | 49 | |
fed9017e RR |
50 | /* configuration for the iwl4965 */ |
51 | extern struct iwl_cfg iwl4965_agn_cfg; | |
5a6a256e TW |
52 | extern struct iwl_cfg iwl5300_agn_cfg; |
53 | extern struct iwl_cfg iwl5100_agn_cfg; | |
54 | extern struct iwl_cfg iwl5350_agn_cfg; | |
ac592574 | 55 | extern struct iwl_cfg iwl5100_bgn_cfg; |
47408639 | 56 | extern struct iwl_cfg iwl5100_abg_cfg; |
7100e924 | 57 | extern struct iwl_cfg iwl5150_agn_cfg; |
ac592574 | 58 | extern struct iwl_cfg iwl5150_abg_cfg; |
65b7998a | 59 | extern struct iwl_cfg iwl6000i_2agn_cfg; |
0b5af201 | 60 | extern struct iwl_cfg iwl6000i_g2_2agn_cfg; |
5953a62e WYG |
61 | extern struct iwl_cfg iwl6000i_2abg_cfg; |
62 | extern struct iwl_cfg iwl6000i_2bg_cfg; | |
e1228374 JS |
63 | extern struct iwl_cfg iwl6000_3agn_cfg; |
64 | extern struct iwl_cfg iwl6050_2agn_cfg; | |
5953a62e | 65 | extern struct iwl_cfg iwl6050_2abg_cfg; |
77dcb6a9 | 66 | extern struct iwl_cfg iwl1000_bgn_cfg; |
4bd0914f | 67 | extern struct iwl_cfg iwl1000_bg_cfg; |
fed9017e | 68 | |
672639de WYG |
69 | struct iwl_tx_queue; |
70 | ||
099b40b7 | 71 | /* CT-KILL constants */ |
672639de WYG |
72 | #define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */ |
73 | #define CT_KILL_THRESHOLD 114 /* in Celsius */ | |
74 | #define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ | |
4bf775cd | 75 | |
5d08cd1d CH |
76 | /* Default noise level to report when noise measurement is not available. |
77 | * This may be because we're: | |
78 | * 1) Not associated (4965, no beacon statistics being sent to driver) | |
79 | * 2) Scanning (noise measurement does not apply to associated channel) | |
80 | * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) | |
81 | * Use default noise value of -127 ... this is below the range of measurable | |
82 | * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. | |
83 | * Also, -127 works better than 0 when averaging frames with/without | |
84 | * noise info (e.g. averaging might be done in app); measured dBm values are | |
85 | * always negative ... using a negative value as the default keeps all | |
86 | * averages within an s8's (used in some apps) range of negative values. */ | |
87 | #define IWL_NOISE_MEAS_NOT_AVAILABLE (-127) | |
88 | ||
5d08cd1d CH |
89 | /* |
90 | * RTS threshold here is total size [2347] minus 4 FCS bytes | |
91 | * Per spec: | |
92 | * a value of 0 means RTS on all data/management packets | |
93 | * a value > max MSDU size means no RTS | |
94 | * else RTS for data/management frames where MPDU is larger | |
95 | * than RTS value. | |
96 | */ | |
97 | #define DEFAULT_RTS_THRESHOLD 2347U | |
98 | #define MIN_RTS_THRESHOLD 0U | |
99 | #define MAX_RTS_THRESHOLD 2347U | |
100 | #define MAX_MSDU_SIZE 2304U | |
101 | #define MAX_MPDU_SIZE 2346U | |
102 | #define DEFAULT_BEACON_INTERVAL 100U | |
103 | #define DEFAULT_SHORT_RETRY_LIMIT 7U | |
104 | #define DEFAULT_LONG_RETRY_LIMIT 4U | |
105 | ||
a55360e4 | 106 | struct iwl_rx_mem_buffer { |
2f301227 ZY |
107 | dma_addr_t page_dma; |
108 | struct page *page; | |
5d08cd1d CH |
109 | struct list_head list; |
110 | }; | |
111 | ||
2f301227 ZY |
112 | #define rxb_addr(r) page_address(r->page) |
113 | ||
c2acea8e JB |
114 | /* defined below */ |
115 | struct iwl_device_cmd; | |
116 | ||
117 | struct iwl_cmd_meta { | |
118 | /* only for SYNC commands, iff the reply skb is wanted */ | |
119 | struct iwl_host_cmd *source; | |
120 | /* | |
121 | * only for ASYNC commands | |
122 | * (which is somewhat stupid -- look at iwl-sta.c for instance | |
123 | * which duplicates a bunch of code because the callback isn't | |
124 | * invoked for SYNC commands, if it were and its result passed | |
125 | * through it would be simpler...) | |
126 | */ | |
5696aea6 JB |
127 | void (*callback)(struct iwl_priv *priv, |
128 | struct iwl_device_cmd *cmd, | |
2f301227 | 129 | struct iwl_rx_packet *pkt); |
c2acea8e JB |
130 | |
131 | /* The CMD_SIZE_HUGE flag bit indicates that the command | |
132 | * structure is stored at the end of the shared queue memory. */ | |
133 | u32 flags; | |
134 | ||
135 | DECLARE_PCI_UNMAP_ADDR(mapping) | |
136 | DECLARE_PCI_UNMAP_LEN(len) | |
137 | }; | |
138 | ||
5d08cd1d CH |
139 | /* |
140 | * Generic queue structure | |
141 | * | |
142 | * Contains common data for Rx and Tx queues | |
143 | */ | |
443cfd45 | 144 | struct iwl_queue { |
5d08cd1d CH |
145 | int n_bd; /* number of BDs in this queue */ |
146 | int write_ptr; /* 1-st empty entry (index) host_w*/ | |
147 | int read_ptr; /* last used entry (index) host_r*/ | |
b74e31a9 WYG |
148 | /* use for monitoring and recovering the stuck queue */ |
149 | int last_read_ptr; /* storing the last read_ptr */ | |
150 | /* number of time read_ptr and last_read_ptr are the same */ | |
151 | u8 repeat_same_read_ptr; | |
5d08cd1d CH |
152 | dma_addr_t dma_addr; /* physical addr for BD's */ |
153 | int n_window; /* safe queue window */ | |
154 | u32 id; | |
155 | int low_mark; /* low watermark, resume queue if free | |
156 | * space more than this */ | |
157 | int high_mark; /* high watermark, stop queue if free | |
158 | * space less than this */ | |
159 | } __attribute__ ((packed)); | |
160 | ||
bc47279f | 161 | /* One for each TFD */ |
8567c63e | 162 | struct iwl_tx_info { |
499b1883 | 163 | struct sk_buff *skb[IWL_NUM_OF_TBS - 1]; |
5d08cd1d CH |
164 | }; |
165 | ||
166 | /** | |
16466903 | 167 | * struct iwl_tx_queue - Tx Queue for DMA |
bc47279f BC |
168 | * @q: generic Rx/Tx queue descriptor |
169 | * @bd: base of circular buffer of TFDs | |
c2acea8e JB |
170 | * @cmd: array of command/TX buffer pointers |
171 | * @meta: array of meta data for each command/tx buffer | |
bc47279f BC |
172 | * @dma_addr_cmd: physical address of cmd/tx buffer array |
173 | * @txb: array of per-TFD driver data | |
174 | * @need_update: indicates need to update read/write index | |
175 | * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled | |
5d08cd1d | 176 | * |
bc47279f BC |
177 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame |
178 | * descriptors) and required locking structures. | |
5d08cd1d | 179 | */ |
188cf6c7 SO |
180 | #define TFD_TX_CMD_SLOTS 256 |
181 | #define TFD_CMD_SLOTS 32 | |
182 | ||
16466903 | 183 | struct iwl_tx_queue { |
443cfd45 | 184 | struct iwl_queue q; |
59606ffa | 185 | void *tfds; |
c2acea8e JB |
186 | struct iwl_device_cmd **cmd; |
187 | struct iwl_cmd_meta *meta; | |
8567c63e | 188 | struct iwl_tx_info *txb; |
3fd07a1e TW |
189 | u8 need_update; |
190 | u8 sched_retry; | |
191 | u8 active; | |
192 | u8 swq_id; | |
5d08cd1d CH |
193 | }; |
194 | ||
195 | #define IWL_NUM_SCAN_RATES (2) | |
196 | ||
bb8c093b | 197 | struct iwl4965_channel_tgd_info { |
5d08cd1d CH |
198 | u8 type; |
199 | s8 max_power; | |
200 | }; | |
201 | ||
bb8c093b | 202 | struct iwl4965_channel_tgh_info { |
5d08cd1d CH |
203 | s64 last_radar_time; |
204 | }; | |
205 | ||
d20b3c65 SO |
206 | #define IWL4965_MAX_RATE (33) |
207 | ||
85d41495 KA |
208 | struct iwl3945_clip_group { |
209 | /* maximum power level to prevent clipping for each rate, derived by | |
210 | * us from this band's saturation power in EEPROM */ | |
211 | const s8 clip_powers[IWL_MAX_RATES]; | |
212 | }; | |
213 | ||
d20b3c65 SO |
214 | /* current Tx power values to use, one for each rate for each channel. |
215 | * requested power is limited by: | |
216 | * -- regulatory EEPROM limits for this channel | |
217 | * -- hardware capabilities (clip-powers) | |
218 | * -- spectrum management | |
219 | * -- user preference (e.g. iwconfig) | |
220 | * when requested power is set, base power index must also be set. */ | |
221 | struct iwl3945_channel_power_info { | |
222 | struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
223 | s8 power_table_index; /* actual (compenst'd) index into gain table */ | |
224 | s8 base_power_index; /* gain index for power at factory temp. */ | |
225 | s8 requested_power; /* power (dBm) requested for this chnl/rate */ | |
226 | }; | |
227 | ||
228 | /* current scan Tx power values to use, one for each scan rate for each | |
229 | * channel. */ | |
230 | struct iwl3945_scan_power_info { | |
231 | struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
232 | s8 power_table_index; /* actual (compenst'd) index into gain table */ | |
233 | s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */ | |
234 | }; | |
235 | ||
5d08cd1d CH |
236 | /* |
237 | * One for each channel, holds all channel setup data | |
238 | * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant | |
239 | * with one another! | |
240 | */ | |
bf85ea4f | 241 | struct iwl_channel_info { |
bb8c093b CH |
242 | struct iwl4965_channel_tgd_info tgd; |
243 | struct iwl4965_channel_tgh_info tgh; | |
073d3f5f | 244 | struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */ |
7aafef1c WYG |
245 | struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for |
246 | * HT40 channel */ | |
5d08cd1d CH |
247 | |
248 | u8 channel; /* channel number */ | |
249 | u8 flags; /* flags copied from EEPROM */ | |
250 | s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
fcd427bb | 251 | s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */ |
5d08cd1d CH |
252 | s8 min_power; /* always 0 */ |
253 | s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */ | |
254 | ||
255 | u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */ | |
256 | u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */ | |
8318d78a | 257 | enum ieee80211_band band; |
5d08cd1d | 258 | |
7aafef1c WYG |
259 | /* HT40 channel info */ |
260 | s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
7aafef1c WYG |
261 | u8 ht40_flags; /* flags copied from EEPROM */ |
262 | u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */ | |
d20b3c65 SO |
263 | |
264 | /* Radio/DSP gain settings for each "normal" data Tx rate. | |
265 | * These include, in addition to RF and DSP gain, a few fields for | |
266 | * remembering/modifying gain settings (indexes). */ | |
267 | struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE]; | |
268 | ||
269 | /* Radio/DSP gain settings for each scan rate, for directed scans. */ | |
270 | struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES]; | |
5d08cd1d CH |
271 | }; |
272 | ||
edc1a3a0 JB |
273 | #define IWL_TX_FIFO_BK 0 |
274 | #define IWL_TX_FIFO_BE 1 | |
275 | #define IWL_TX_FIFO_VI 2 | |
276 | #define IWL_TX_FIFO_VO 3 | |
277 | #define IWL_TX_FIFO_UNUSED -1 | |
5d08cd1d | 278 | |
01a7e084 RC |
279 | /* Minimum number of queues. MAX_NUM is defined in hw specific files. |
280 | * Set the minimum to accommodate the 4 standard TX queues, 1 command | |
281 | * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */ | |
282 | #define IWL_MIN_NUM_QUEUES 10 | |
5d08cd1d | 283 | |
bd35f150 | 284 | /* |
1a716557 JB |
285 | * Queue #4 is the command queue for 3945/4965/5x00/1000/6x00, |
286 | * the driver maps it into the appropriate device FIFO for the | |
287 | * uCode. | |
bd35f150 WYG |
288 | */ |
289 | #define IWL_CMD_QUEUE_NUM 4 | |
290 | ||
5d08cd1d CH |
291 | /* Power management (not Tx power) structures */ |
292 | ||
6f4083aa TW |
293 | enum iwl_pwr_src { |
294 | IWL_PWR_SRC_VMAIN, | |
295 | IWL_PWR_SRC_VAUX, | |
296 | }; | |
297 | ||
5d08cd1d CH |
298 | #define IEEE80211_DATA_LEN 2304 |
299 | #define IEEE80211_4ADDR_LEN 30 | |
300 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) | |
301 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) | |
302 | ||
fcab423d | 303 | struct iwl_frame { |
5d08cd1d CH |
304 | union { |
305 | struct ieee80211_hdr frame; | |
4bf64efd | 306 | struct iwl_tx_beacon_cmd beacon; |
5d08cd1d CH |
307 | u8 raw[IEEE80211_FRAME_LEN]; |
308 | u8 cmd[360]; | |
309 | } u; | |
310 | struct list_head list; | |
311 | }; | |
312 | ||
5d08cd1d CH |
313 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) |
314 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | |
315 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | |
316 | ||
317 | enum { | |
c587de0b TW |
318 | CMD_SYNC = 0, |
319 | CMD_SIZE_NORMAL = 0, | |
320 | CMD_NO_SKB = 0, | |
5d08cd1d | 321 | CMD_SIZE_HUGE = (1 << 0), |
5d08cd1d | 322 | CMD_ASYNC = (1 << 1), |
5d08cd1d CH |
323 | CMD_WANT_SKB = (1 << 2), |
324 | }; | |
325 | ||
c8c24872 | 326 | #define DEF_CMD_PAYLOAD_SIZE 320 |
bd68fb6f | 327 | |
2f301227 ZY |
328 | /* |
329 | * IWL_LINK_HDR_MAX should include ieee80211_hdr, radiotap header, | |
330 | * SNAP header and alignment. It should also be big enough for 802.11 | |
331 | * control frames. | |
332 | */ | |
333 | #define IWL_LINK_HDR_MAX 64 | |
334 | ||
bc47279f | 335 | /** |
c2acea8e | 336 | * struct iwl_device_cmd |
bc47279f BC |
337 | * |
338 | * For allocation of the command and tx queues, this establishes the overall | |
339 | * size of the largest command we send to uCode, except for a scan command | |
340 | * (which is relatively huge; space is allocated separately). | |
341 | */ | |
c2acea8e | 342 | struct iwl_device_cmd { |
857485c0 | 343 | struct iwl_cmd_header hdr; /* uCode API */ |
5d08cd1d | 344 | union { |
5d08cd1d CH |
345 | u32 flags; |
346 | u8 val8; | |
347 | u16 val16; | |
348 | u32 val32; | |
83d527d9 | 349 | struct iwl_tx_cmd tx; |
c8c24872 WYG |
350 | struct iwl6000_channel_switch_cmd chswitch; |
351 | u8 payload[DEF_CMD_PAYLOAD_SIZE]; | |
5d08cd1d CH |
352 | } __attribute__ ((packed)) cmd; |
353 | } __attribute__ ((packed)); | |
354 | ||
c2acea8e JB |
355 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) |
356 | ||
3257e5d4 | 357 | |
857485c0 | 358 | struct iwl_host_cmd { |
5d08cd1d | 359 | const void *data; |
2f301227 | 360 | unsigned long reply_page; |
5696aea6 JB |
361 | void (*callback)(struct iwl_priv *priv, |
362 | struct iwl_device_cmd *cmd, | |
2f301227 | 363 | struct iwl_rx_packet *pkt); |
c2acea8e JB |
364 | u32 flags; |
365 | u16 len; | |
366 | u8 id; | |
5d08cd1d CH |
367 | }; |
368 | ||
5d08cd1d CH |
369 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 |
370 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | |
371 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | |
372 | ||
373 | /** | |
a55360e4 | 374 | * struct iwl_rx_queue - Rx queue |
df833b1d RC |
375 | * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) |
376 | * @dma_addr: bus address of buffer of receive buffer descriptors (rbd) | |
5d08cd1d CH |
377 | * @read: Shared index to newest available Rx buffer |
378 | * @write: Shared index to oldest written Rx packet | |
379 | * @free_count: Number of pre-allocated buffers in rx_free | |
380 | * @rx_free: list of free SKBs for use | |
381 | * @rx_used: List of Rx buffers with no SKB | |
382 | * @need_update: flag to indicate we need to update read/write index | |
df833b1d RC |
383 | * @rb_stts: driver's pointer to receive buffer status |
384 | * @rb_stts_dma: bus address of receive buffer status | |
5d08cd1d | 385 | * |
a55360e4 | 386 | * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers |
5d08cd1d | 387 | */ |
a55360e4 | 388 | struct iwl_rx_queue { |
5d08cd1d CH |
389 | __le32 *bd; |
390 | dma_addr_t dma_addr; | |
a55360e4 TW |
391 | struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; |
392 | struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; | |
5d08cd1d CH |
393 | u32 read; |
394 | u32 write; | |
395 | u32 free_count; | |
4752c93c | 396 | u32 write_actual; |
5d08cd1d CH |
397 | struct list_head rx_free; |
398 | struct list_head rx_used; | |
399 | int need_update; | |
8d86422a WT |
400 | struct iwl_rb_status *rb_stts; |
401 | dma_addr_t rb_stts_dma; | |
5d08cd1d CH |
402 | spinlock_t lock; |
403 | }; | |
404 | ||
405 | #define IWL_SUPPORTED_RATES_IE_LEN 8 | |
406 | ||
5d08cd1d CH |
407 | #define MAX_TID_COUNT 9 |
408 | ||
409 | #define IWL_INVALID_RATE 0xFF | |
410 | #define IWL_INVALID_VALUE -1 | |
411 | ||
bc47279f | 412 | /** |
6def9761 | 413 | * struct iwl_ht_agg -- aggregation status while waiting for block-ack |
bc47279f BC |
414 | * @txq_id: Tx queue used for Tx attempt |
415 | * @frame_count: # frames attempted by Tx command | |
416 | * @wait_for_ba: Expect block-ack before next Tx reply | |
417 | * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window | |
418 | * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window | |
419 | * @bitmap1: High order, one bit for each frame pending ACK in Tx window | |
420 | * @rate_n_flags: Rate at which Tx was attempted | |
421 | * | |
422 | * If REPLY_TX indicates that aggregation was attempted, driver must wait | |
423 | * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info | |
424 | * until block ack arrives. | |
425 | */ | |
6def9761 | 426 | struct iwl_ht_agg { |
5d08cd1d CH |
427 | u16 txq_id; |
428 | u16 frame_count; | |
429 | u16 wait_for_ba; | |
430 | u16 start_idx; | |
fe01b477 | 431 | u64 bitmap; |
5d08cd1d | 432 | u32 rate_n_flags; |
fe01b477 RR |
433 | #define IWL_AGG_OFF 0 |
434 | #define IWL_AGG_ON 1 | |
435 | #define IWL_EMPTYING_HW_QUEUE_ADDBA 2 | |
436 | #define IWL_EMPTYING_HW_QUEUE_DELBA 3 | |
437 | u8 state; | |
5d08cd1d | 438 | }; |
fe01b477 | 439 | |
5d08cd1d | 440 | |
6def9761 | 441 | struct iwl_tid_data { |
5d08cd1d | 442 | u16 seq_number; |
fe01b477 | 443 | u16 tfds_in_queue; |
6def9761 | 444 | struct iwl_ht_agg agg; |
5d08cd1d CH |
445 | }; |
446 | ||
6def9761 | 447 | struct iwl_hw_key { |
5d08cd1d CH |
448 | enum ieee80211_key_alg alg; |
449 | int keylen; | |
0211ddda | 450 | u8 keyidx; |
5d08cd1d CH |
451 | u8 key[32]; |
452 | }; | |
453 | ||
a78fe754 | 454 | union iwl_ht_rate_supp { |
5d08cd1d CH |
455 | u16 rates; |
456 | struct { | |
457 | u8 siso_rate; | |
458 | u8 mimo_rate; | |
459 | }; | |
460 | }; | |
461 | ||
5d08cd1d | 462 | #define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3) |
bcc693a1 WYG |
463 | |
464 | /* | |
465 | * Maximal MPDU density for TX aggregation | |
466 | * 4 - 2us density | |
467 | * 5 - 4us density | |
468 | * 6 - 8us density | |
469 | * 7 - 16us density | |
470 | */ | |
471 | #define CFG_HT_MPDU_DENSITY_4USEC (0x5) | |
472 | #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC | |
5d08cd1d | 473 | |
fad95bf5 | 474 | struct iwl_ht_config { |
9e0cc6de | 475 | /* self configuration data */ |
c812ee24 JB |
476 | bool is_ht; |
477 | bool is_40mhz; | |
02bb1bea | 478 | bool single_chain_sufficient; |
ba37a3d0 | 479 | enum ieee80211_smps_mode smps; /* current smps mode */ |
9e0cc6de | 480 | /* BSS related data */ |
5d08cd1d | 481 | u8 extension_chan_offset; |
9e0cc6de RR |
482 | u8 ht_protection; |
483 | u8 non_GF_STA_present; | |
5d08cd1d | 484 | }; |
5d08cd1d | 485 | |
1ff50bda | 486 | union iwl_qos_capabity { |
5d08cd1d CH |
487 | struct { |
488 | u8 edca_count:4; /* bit 0-3 */ | |
489 | u8 q_ack:1; /* bit 4 */ | |
490 | u8 queue_request:1; /* bit 5 */ | |
491 | u8 txop_request:1; /* bit 6 */ | |
492 | u8 reserved:1; /* bit 7 */ | |
493 | } q_AP; | |
494 | struct { | |
495 | u8 acvo_APSD:1; /* bit 0 */ | |
496 | u8 acvi_APSD:1; /* bit 1 */ | |
497 | u8 ac_bk_APSD:1; /* bit 2 */ | |
498 | u8 ac_be_APSD:1; /* bit 3 */ | |
499 | u8 q_ack:1; /* bit 4 */ | |
500 | u8 max_len:2; /* bit 5-6 */ | |
501 | u8 more_data_ack:1; /* bit 7 */ | |
502 | } q_STA; | |
503 | u8 val; | |
504 | }; | |
505 | ||
506 | /* QoS structures */ | |
1ff50bda | 507 | struct iwl_qos_info { |
5d08cd1d | 508 | int qos_active; |
1ff50bda EG |
509 | union iwl_qos_capabity qos_cap; |
510 | struct iwl_qosparam_cmd def_qos_parm; | |
5d08cd1d | 511 | }; |
5d08cd1d | 512 | |
fe6b23dd RC |
513 | /* |
514 | * Structure should be accessed with sta_lock held. When station addition | |
515 | * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only | |
516 | * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock | |
517 | * held. | |
518 | */ | |
6def9761 | 519 | struct iwl_station_entry { |
133636de | 520 | struct iwl_addsta_cmd sta; |
6def9761 | 521 | struct iwl_tid_data tid[MAX_TID_COUNT]; |
5d08cd1d | 522 | u8 used; |
6def9761 | 523 | struct iwl_hw_key keyinfo; |
fe6b23dd | 524 | struct iwl_link_quality_cmd *lq; |
5d08cd1d CH |
525 | }; |
526 | ||
8d9698b3 RC |
527 | /* |
528 | * iwl_station_priv: Driver's private station information | |
529 | * | |
530 | * When mac80211 creates a station it reserves some space (hw->sta_data_size) | |
531 | * in the structure for use by driver. This structure is places in that | |
532 | * space. | |
8d9698b3 RC |
533 | */ |
534 | struct iwl_station_priv { | |
535 | struct iwl_lq_sta lq_sta; | |
6ab10ff8 JB |
536 | atomic_t pending_frames; |
537 | bool client; | |
538 | bool asleep; | |
8d9698b3 RC |
539 | }; |
540 | ||
5d08cd1d CH |
541 | /* one for each uCode image (inst/data, boot/init/runtime) */ |
542 | struct fw_desc { | |
543 | void *v_addr; /* access by driver */ | |
544 | dma_addr_t p_addr; /* access by card's busmaster DMA */ | |
545 | u32 len; /* bytes */ | |
546 | }; | |
547 | ||
548 | /* uCode file layout */ | |
cc0f555d JS |
549 | struct iwl_ucode_header { |
550 | __le32 ver; /* major/minor/API/serial */ | |
551 | union { | |
552 | struct { | |
553 | __le32 inst_size; /* bytes of runtime code */ | |
554 | __le32 data_size; /* bytes of runtime data */ | |
555 | __le32 init_size; /* bytes of init code */ | |
556 | __le32 init_data_size; /* bytes of init data */ | |
557 | __le32 boot_size; /* bytes of bootstrap code */ | |
558 | u8 data[0]; /* in same order as sizes */ | |
559 | } v1; | |
560 | struct { | |
561 | __le32 build; /* build number */ | |
562 | __le32 inst_size; /* bytes of runtime code */ | |
563 | __le32 data_size; /* bytes of runtime data */ | |
564 | __le32 init_size; /* bytes of init code */ | |
565 | __le32 init_data_size; /* bytes of init data */ | |
566 | __le32 boot_size; /* bytes of bootstrap code */ | |
567 | u8 data[0]; /* in same order as sizes */ | |
568 | } v2; | |
569 | } u; | |
5d08cd1d | 570 | }; |
cc0f555d | 571 | #define UCODE_HEADER_SIZE(ver) ((ver) == 1 ? 24 : 28) |
5d08cd1d | 572 | |
bb8c093b | 573 | struct iwl4965_ibss_seq { |
5d08cd1d CH |
574 | u8 mac[ETH_ALEN]; |
575 | u16 seq_num; | |
576 | u16 frag_num; | |
577 | unsigned long packet_time; | |
578 | struct list_head list; | |
579 | }; | |
580 | ||
f0832f13 EG |
581 | struct iwl_sensitivity_ranges { |
582 | u16 min_nrg_cck; | |
583 | u16 max_nrg_cck; | |
584 | ||
585 | u16 nrg_th_cck; | |
586 | u16 nrg_th_ofdm; | |
587 | ||
588 | u16 auto_corr_min_ofdm; | |
589 | u16 auto_corr_min_ofdm_mrc; | |
590 | u16 auto_corr_min_ofdm_x1; | |
591 | u16 auto_corr_min_ofdm_mrc_x1; | |
592 | ||
593 | u16 auto_corr_max_ofdm; | |
594 | u16 auto_corr_max_ofdm_mrc; | |
595 | u16 auto_corr_max_ofdm_x1; | |
596 | u16 auto_corr_max_ofdm_mrc_x1; | |
597 | ||
598 | u16 auto_corr_max_cck; | |
599 | u16 auto_corr_max_cck_mrc; | |
600 | u16 auto_corr_min_cck; | |
601 | u16 auto_corr_min_cck_mrc; | |
55036d66 WYG |
602 | |
603 | u16 barker_corr_th_min; | |
604 | u16 barker_corr_th_min_mrc; | |
605 | u16 nrg_th_cca; | |
f0832f13 EG |
606 | }; |
607 | ||
099b40b7 | 608 | |
b5047f78 TW |
609 | #define KELVIN_TO_CELSIUS(x) ((x)-273) |
610 | #define CELSIUS_TO_KELVIN(x) ((x)+273) | |
611 | ||
612 | ||
bc47279f | 613 | /** |
5425e490 | 614 | * struct iwl_hw_params |
bc47279f | 615 | * @max_txq_num: Max # Tx queues supported |
f3f911d1 | 616 | * @dma_chnl_num: Number of Tx DMA/FIFO channels |
4ddbb7d0 | 617 | * @scd_bc_tbls_size: size of scheduler byte count tables |
a8e74e27 | 618 | * @tfd_size: TFD size |
099b40b7 RR |
619 | * @tx/rx_chains_num: Number of TX/RX chains |
620 | * @valid_tx/rx_ant: usable antennas | |
bc47279f | 621 | * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2) |
bc47279f | 622 | * @max_rxq_log: Log-base-2 of max_rxq_size |
2f301227 | 623 | * @rx_page_order: Rx buffer page order |
141c43a3 | 624 | * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR |
bc47279f BC |
625 | * @max_stations: |
626 | * @bcast_sta_id: | |
7aafef1c | 627 | * @ht40_channel: is 40MHz width possible in band 2.4 |
099b40b7 RR |
628 | * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ) |
629 | * @sw_crypto: 0 for hw, 1 for sw | |
630 | * @max_xxx_size: for ucode uses | |
631 | * @ct_kill_threshold: temperature threshold | |
a96a27f9 | 632 | * @calib_init_cfg: setup initial calibrations for the hw |
f0832f13 | 633 | * @struct iwl_sensitivity_ranges: range of sensitivity values |
bc47279f | 634 | */ |
5425e490 | 635 | struct iwl_hw_params { |
f3f911d1 ZY |
636 | u8 max_txq_num; |
637 | u8 dma_chnl_num; | |
4ddbb7d0 | 638 | u16 scd_bc_tbls_size; |
a8e74e27 | 639 | u32 tfd_size; |
ec35cf2a TW |
640 | u8 tx_chains_num; |
641 | u8 rx_chains_num; | |
642 | u8 valid_tx_ant; | |
643 | u8 valid_rx_ant; | |
5d08cd1d | 644 | u16 max_rxq_size; |
ec35cf2a | 645 | u16 max_rxq_log; |
2f301227 | 646 | u32 rx_page_order; |
141c43a3 | 647 | u32 rx_wrt_ptr_reg; |
5d08cd1d CH |
648 | u8 max_stations; |
649 | u8 bcast_sta_id; | |
7aafef1c | 650 | u8 ht40_channel; |
2c2f3b33 | 651 | u8 max_beacon_itrvl; /* in 1024 ms */ |
099b40b7 RR |
652 | u32 max_inst_size; |
653 | u32 max_data_size; | |
654 | u32 max_bsm_size; | |
655 | u32 ct_kill_threshold; /* value in hw-dependent units */ | |
672639de WYG |
656 | u32 ct_kill_exit_threshold; /* value in hw-dependent units */ |
657 | /* for 1000, 6000 series and up */ | |
be5d56ed | 658 | u32 calib_init_cfg; |
f0832f13 | 659 | const struct iwl_sensitivity_ranges *sens; |
5d08cd1d CH |
660 | }; |
661 | ||
5d08cd1d | 662 | |
5d08cd1d CH |
663 | /****************************************************************************** |
664 | * | |
a33c2f47 EG |
665 | * Functions implemented in core module which are forward declared here |
666 | * for use by iwl-[4-5].c | |
5d08cd1d | 667 | * |
a33c2f47 EG |
668 | * NOTE: The implementation of these functions are not hardware specific |
669 | * which is why they are in the core module files. | |
5d08cd1d CH |
670 | * |
671 | * Naming convention -- | |
a33c2f47 | 672 | * iwl_ <-- Is part of iwlwifi |
5d08cd1d | 673 | * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) |
bb8c093b CH |
674 | * iwl4965_bg_ <-- Called from work queue context |
675 | * iwl4965_mac_ <-- mac80211 callback | |
5d08cd1d CH |
676 | * |
677 | ****************************************************************************/ | |
5b9f8cd3 EG |
678 | extern void iwl_update_chain_flags(struct iwl_priv *priv); |
679 | extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src); | |
a33c2f47 | 680 | extern const u8 iwl_bcast_addr[ETH_ALEN]; |
b3bbacb7 | 681 | extern int iwl_rxq_stop(struct iwl_priv *priv); |
da1bc453 | 682 | extern void iwl_txq_ctx_stop(struct iwl_priv *priv); |
443cfd45 | 683 | extern int iwl_queue_space(const struct iwl_queue *q); |
fd4abac5 TW |
684 | static inline int iwl_queue_used(const struct iwl_queue *q, int i) |
685 | { | |
c8106d76 | 686 | return q->write_ptr >= q->read_ptr ? |
fd4abac5 TW |
687 | (i >= q->read_ptr && i < q->write_ptr) : |
688 | !(i < q->read_ptr && i >= q->write_ptr); | |
689 | } | |
690 | ||
691 | ||
692 | static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge) | |
693 | { | |
c8c24872 WYG |
694 | /* |
695 | * This is for init calibration result and scan command which | |
696 | * required buffer > TFD_MAX_PAYLOAD_SIZE, | |
697 | * the big buffer at end of command array | |
698 | */ | |
fd4abac5 TW |
699 | if (is_huge) |
700 | return q->n_window; /* must be power of 2 */ | |
701 | ||
702 | /* Otherwise, use normal size buffers */ | |
703 | return index & (q->n_window - 1); | |
704 | } | |
705 | ||
706 | ||
4ddbb7d0 TW |
707 | struct iwl_dma_ptr { |
708 | dma_addr_t dma; | |
709 | void *addr; | |
b481de9c ZY |
710 | size_t size; |
711 | }; | |
712 | ||
b481de9c ZY |
713 | #define IWL_OPERATION_MODE_AUTO 0 |
714 | #define IWL_OPERATION_MODE_HT_ONLY 1 | |
715 | #define IWL_OPERATION_MODE_MIXED 2 | |
716 | #define IWL_OPERATION_MODE_20MHZ 3 | |
717 | ||
3195cdb7 TW |
718 | #define IWL_TX_CRC_SIZE 4 |
719 | #define IWL_TX_DELIMITER_SIZE 4 | |
b481de9c | 720 | |
b481de9c | 721 | #define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000 |
b481de9c | 722 | |
b481de9c | 723 | /* Sensitivity and chain noise calibration */ |
b481de9c | 724 | #define INITIALIZATION_VALUE 0xFFFF |
d8c07e7a WYG |
725 | #define IWL4965_CAL_NUM_BEACONS 20 |
726 | #define IWL_CAL_NUM_BEACONS 16 | |
b481de9c ZY |
727 | #define MAXIMUM_ALLOWED_PATHLOSS 15 |
728 | ||
b481de9c ZY |
729 | #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3 |
730 | ||
731 | #define MAX_FA_OFDM 50 | |
732 | #define MIN_FA_OFDM 5 | |
733 | #define MAX_FA_CCK 50 | |
734 | #define MIN_FA_CCK 5 | |
735 | ||
b481de9c ZY |
736 | #define AUTO_CORR_STEP_OFDM 1 |
737 | ||
b481de9c ZY |
738 | #define AUTO_CORR_STEP_CCK 3 |
739 | #define AUTO_CORR_MAX_TH_CCK 160 | |
740 | ||
b481de9c ZY |
741 | #define NRG_DIFF 2 |
742 | #define NRG_STEP_CCK 2 | |
743 | #define NRG_MARGIN 8 | |
744 | #define MAX_NUMBER_CCK_NO_FA 100 | |
745 | ||
746 | #define AUTO_CORR_CCK_MIN_VAL_DEF (125) | |
747 | ||
748 | #define CHAIN_A 0 | |
749 | #define CHAIN_B 1 | |
750 | #define CHAIN_C 2 | |
751 | #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4 | |
752 | #define ALL_BAND_FILTER 0xFF00 | |
753 | #define IN_BAND_FILTER 0xFF | |
754 | #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF | |
755 | ||
3195cdb7 TW |
756 | #define NRG_NUM_PREV_STAT_L 20 |
757 | #define NUM_RX_CHAINS 3 | |
758 | ||
bb8c093b | 759 | enum iwl4965_false_alarm_state { |
b481de9c ZY |
760 | IWL_FA_TOO_MANY = 0, |
761 | IWL_FA_TOO_FEW = 1, | |
762 | IWL_FA_GOOD_RANGE = 2, | |
763 | }; | |
764 | ||
bb8c093b | 765 | enum iwl4965_chain_noise_state { |
b481de9c | 766 | IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */ |
04816448 GE |
767 | IWL_CHAIN_NOISE_ACCUMULATE, |
768 | IWL_CHAIN_NOISE_CALIBRATED, | |
769 | IWL_CHAIN_NOISE_DONE, | |
b481de9c ZY |
770 | }; |
771 | ||
bb8c093b | 772 | enum iwl4965_calib_enabled_state { |
b481de9c ZY |
773 | IWL_CALIB_DISABLED = 0, /* must be 0 */ |
774 | IWL_CALIB_ENABLED = 1, | |
775 | }; | |
776 | ||
f69f42a6 TW |
777 | |
778 | /* | |
779 | * enum iwl_calib | |
780 | * defines the order in which results of initial calibrations | |
781 | * should be sent to the runtime uCode | |
782 | */ | |
783 | enum iwl_calib { | |
784 | IWL_CALIB_XTAL, | |
819500c5 | 785 | IWL_CALIB_DC, |
f69f42a6 TW |
786 | IWL_CALIB_LO, |
787 | IWL_CALIB_TX_IQ, | |
788 | IWL_CALIB_TX_IQ_PERD, | |
201706ac | 789 | IWL_CALIB_BASE_BAND, |
f69f42a6 TW |
790 | IWL_CALIB_MAX |
791 | }; | |
792 | ||
6e21f2c1 TW |
793 | /* Opaque calibration results */ |
794 | struct iwl_calib_result { | |
795 | void *buf; | |
796 | size_t buf_len; | |
7c616cba TW |
797 | }; |
798 | ||
dbb983b7 RR |
799 | enum ucode_type { |
800 | UCODE_NONE = 0, | |
801 | UCODE_INIT, | |
802 | UCODE_RT | |
803 | }; | |
804 | ||
b481de9c | 805 | /* Sensitivity calib data */ |
f0832f13 | 806 | struct iwl_sensitivity_data { |
b481de9c ZY |
807 | u32 auto_corr_ofdm; |
808 | u32 auto_corr_ofdm_mrc; | |
809 | u32 auto_corr_ofdm_x1; | |
810 | u32 auto_corr_ofdm_mrc_x1; | |
811 | u32 auto_corr_cck; | |
812 | u32 auto_corr_cck_mrc; | |
813 | ||
814 | u32 last_bad_plcp_cnt_ofdm; | |
815 | u32 last_fa_cnt_ofdm; | |
816 | u32 last_bad_plcp_cnt_cck; | |
817 | u32 last_fa_cnt_cck; | |
818 | ||
819 | u32 nrg_curr_state; | |
820 | u32 nrg_prev_state; | |
821 | u32 nrg_value[10]; | |
822 | u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L]; | |
823 | u32 nrg_silence_ref; | |
824 | u32 nrg_energy_idx; | |
825 | u32 nrg_silence_idx; | |
826 | u32 nrg_th_cck; | |
827 | s32 nrg_auto_corr_silence_diff; | |
828 | u32 num_in_cck_no_fa; | |
829 | u32 nrg_th_ofdm; | |
55036d66 WYG |
830 | |
831 | u16 barker_corr_th_min; | |
832 | u16 barker_corr_th_min_mrc; | |
833 | u16 nrg_th_cca; | |
b481de9c ZY |
834 | }; |
835 | ||
836 | /* Chain noise (differential Rx gain) calib data */ | |
f0832f13 | 837 | struct iwl_chain_noise_data { |
04816448 | 838 | u32 active_chains; |
b481de9c ZY |
839 | u32 chain_noise_a; |
840 | u32 chain_noise_b; | |
841 | u32 chain_noise_c; | |
842 | u32 chain_signal_a; | |
843 | u32 chain_signal_b; | |
844 | u32 chain_signal_c; | |
04816448 | 845 | u16 beacon_count; |
b481de9c ZY |
846 | u8 disconn_array[NUM_RX_CHAINS]; |
847 | u8 delta_gain_code[NUM_RX_CHAINS]; | |
848 | u8 radio_write; | |
04816448 | 849 | u8 state; |
b481de9c ZY |
850 | }; |
851 | ||
abceddb4 BC |
852 | #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ |
853 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ | |
b481de9c | 854 | |
20594eb0 WYG |
855 | #define IWL_TRAFFIC_ENTRIES (256) |
856 | #define IWL_TRAFFIC_ENTRY_SIZE (64) | |
5d08cd1d | 857 | |
5d08cd1d CH |
858 | enum { |
859 | MEASUREMENT_READY = (1 << 0), | |
860 | MEASUREMENT_ACTIVE = (1 << 1), | |
861 | }; | |
862 | ||
0848e297 WYG |
863 | enum iwl_nvm_type { |
864 | NVM_DEVICE_TYPE_EEPROM = 0, | |
865 | NVM_DEVICE_TYPE_OTP, | |
866 | }; | |
867 | ||
415e4993 WYG |
868 | /* |
869 | * Two types of OTP memory access modes | |
870 | * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode, | |
871 | * based on physical memory addressing | |
872 | * IWL_OTP_ACCESS_RELATIVE - relative address mode, | |
873 | * based on logical memory addressing | |
874 | */ | |
875 | enum iwl_access_mode { | |
876 | IWL_OTP_ACCESS_ABSOLUTE, | |
877 | IWL_OTP_ACCESS_RELATIVE, | |
878 | }; | |
65b7998a WYG |
879 | |
880 | /** | |
881 | * enum iwl_pa_type - Power Amplifier type | |
882 | * @IWL_PA_SYSTEM: based on uCode configuration | |
65b7998a WYG |
883 | * @IWL_PA_INTERNAL: use Internal only |
884 | */ | |
885 | enum iwl_pa_type { | |
886 | IWL_PA_SYSTEM = 0, | |
740e7f51 | 887 | IWL_PA_INTERNAL = 1, |
65b7998a WYG |
888 | }; |
889 | ||
a83b9141 WYG |
890 | /* interrupt statistics */ |
891 | struct isr_statistics { | |
892 | u32 hw; | |
893 | u32 sw; | |
894 | u32 sw_err; | |
895 | u32 sch; | |
896 | u32 alive; | |
897 | u32 rfkill; | |
898 | u32 ctkill; | |
899 | u32 wakeup; | |
900 | u32 rx; | |
901 | u32 rx_handlers[REPLY_MAX]; | |
902 | u32 tx; | |
903 | u32 unhandled; | |
904 | }; | |
5d08cd1d | 905 | |
22fdf3c9 WYG |
906 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
907 | /* management statistics */ | |
908 | enum iwl_mgmt_stats { | |
909 | MANAGEMENT_ASSOC_REQ = 0, | |
910 | MANAGEMENT_ASSOC_RESP, | |
911 | MANAGEMENT_REASSOC_REQ, | |
912 | MANAGEMENT_REASSOC_RESP, | |
913 | MANAGEMENT_PROBE_REQ, | |
914 | MANAGEMENT_PROBE_RESP, | |
915 | MANAGEMENT_BEACON, | |
916 | MANAGEMENT_ATIM, | |
917 | MANAGEMENT_DISASSOC, | |
918 | MANAGEMENT_AUTH, | |
919 | MANAGEMENT_DEAUTH, | |
920 | MANAGEMENT_ACTION, | |
921 | MANAGEMENT_MAX, | |
922 | }; | |
923 | /* control statistics */ | |
924 | enum iwl_ctrl_stats { | |
925 | CONTROL_BACK_REQ = 0, | |
926 | CONTROL_BACK, | |
927 | CONTROL_PSPOLL, | |
928 | CONTROL_RTS, | |
929 | CONTROL_CTS, | |
930 | CONTROL_ACK, | |
931 | CONTROL_CFEND, | |
932 | CONTROL_CFENDACK, | |
933 | CONTROL_MAX, | |
934 | }; | |
935 | ||
936 | struct traffic_stats { | |
937 | u32 mgmt[MANAGEMENT_MAX]; | |
938 | u32 ctrl[CONTROL_MAX]; | |
939 | u32 data_cnt; | |
940 | u64 data_bytes; | |
941 | }; | |
942 | #else | |
943 | struct traffic_stats { | |
944 | u64 data_bytes; | |
945 | }; | |
946 | #endif | |
947 | ||
0924e519 WYG |
948 | /* |
949 | * iwl_switch_rxon: "channel switch" structure | |
950 | * | |
951 | * @ switch_in_progress: channel switch in progress | |
952 | * @ channel: new channel | |
953 | */ | |
954 | struct iwl_switch_rxon { | |
955 | bool switch_in_progress; | |
956 | __le16 channel; | |
957 | }; | |
958 | ||
a9e1cb6a WYG |
959 | /* |
960 | * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds | |
961 | * to perform continuous uCode event logging operation if enabled | |
962 | */ | |
963 | #define UCODE_TRACE_PERIOD (100) | |
964 | ||
965 | /* | |
966 | * iwl_event_log: current uCode event log position | |
967 | * | |
968 | * @ucode_trace: enable/disable ucode continuous trace timer | |
969 | * @num_wraps: how many times the event buffer wraps | |
970 | * @next_entry: the entry just before the next one that uCode would fill | |
971 | * @non_wraps_count: counter for no wrap detected when dump ucode events | |
972 | * @wraps_once_count: counter for wrap once detected when dump ucode events | |
973 | * @wraps_more_count: counter for wrap more than once detected | |
974 | * when dump ucode events | |
975 | */ | |
976 | struct iwl_event_log { | |
977 | bool ucode_trace; | |
978 | u32 num_wraps; | |
979 | u32 next_entry; | |
980 | int non_wraps_count; | |
981 | int wraps_once_count; | |
982 | int wraps_more_count; | |
983 | }; | |
984 | ||
2be76703 WYG |
985 | /* |
986 | * host interrupt timeout value | |
987 | * used with setting interrupt coalescing timer | |
988 | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | |
989 | * | |
990 | * default interrupt coalescing timer is 64 x 32 = 2048 usecs | |
991 | * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs | |
992 | */ | |
993 | #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) | |
994 | #define IWL_HOST_INT_TIMEOUT_DEF (0x40) | |
995 | #define IWL_HOST_INT_TIMEOUT_MIN (0x0) | |
996 | #define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF) | |
997 | #define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10) | |
998 | #define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0) | |
999 | ||
3e4fb5fa TAN |
1000 | /* |
1001 | * This is the threshold value of plcp error rate per 100mSecs. It is | |
1002 | * used to set and check for the validity of plcp_delta. | |
1003 | */ | |
1004 | #define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (0) | |
1005 | #define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50) | |
1006 | #define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100) | |
6c3872e1 | 1007 | #define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200) |
3e4fb5fa TAN |
1008 | #define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255) |
1009 | ||
8a472da4 WYG |
1010 | #define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3) |
1011 | #define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5) | |
1012 | ||
b74e31a9 WYG |
1013 | /* timer constants use to monitor and recover stuck tx queues in mSecs */ |
1014 | #define IWL_MONITORING_PERIOD (1000) | |
1015 | #define IWL_ONE_HUNDRED_MSECS (100) | |
1016 | #define IWL_SIXTY_SECS (60000) | |
1017 | ||
a93e7973 WYG |
1018 | enum iwl_reset { |
1019 | IWL_RF_RESET = 0, | |
1020 | IWL_FW_RESET, | |
8a472da4 WYG |
1021 | IWL_MAX_FORCE_RESET, |
1022 | }; | |
1023 | ||
1024 | struct iwl_force_reset { | |
1025 | int reset_request_count; | |
1026 | int reset_success_count; | |
1027 | int reset_reject_count; | |
1028 | unsigned long reset_duration; | |
1029 | unsigned long last_force_reset_jiffies; | |
a93e7973 WYG |
1030 | }; |
1031 | ||
c79dd5b5 | 1032 | struct iwl_priv { |
5d08cd1d CH |
1033 | |
1034 | /* ieee device used by generic ieee processing code */ | |
1035 | struct ieee80211_hw *hw; | |
1036 | struct ieee80211_channel *ieee_channels; | |
1037 | struct ieee80211_rate *ieee_rates; | |
82b9a121 | 1038 | struct iwl_cfg *cfg; |
5d08cd1d CH |
1039 | |
1040 | /* temporary frame storage list */ | |
1041 | struct list_head free_frames; | |
1042 | int frames_count; | |
1043 | ||
8318d78a | 1044 | enum ieee80211_band band; |
2f301227 | 1045 | int alloc_rxb_page; |
5d08cd1d | 1046 | |
c79dd5b5 | 1047 | void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv, |
a55360e4 | 1048 | struct iwl_rx_mem_buffer *rxb); |
5d08cd1d | 1049 | |
8318d78a | 1050 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; |
5d08cd1d | 1051 | |
5d08cd1d | 1052 | /* spectrum measurement report caching */ |
2aa6ab86 | 1053 | struct iwl_spectrum_notification measure_report; |
5d08cd1d | 1054 | u8 measurement_status; |
81963d68 | 1055 | |
5d08cd1d CH |
1056 | /* ucode beacon time */ |
1057 | u32 ucode_beacon_time; | |
a13d276f | 1058 | int missed_beacon_threshold; |
5d08cd1d | 1059 | |
3e4fb5fa TAN |
1060 | /* storing the jiffies when the plcp error rate is received */ |
1061 | unsigned long plcp_jiffies; | |
1062 | ||
a93e7973 | 1063 | /* force reset */ |
8a472da4 | 1064 | struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET]; |
a93e7973 | 1065 | |
bb8c093b | 1066 | /* we allocate array of iwl4965_channel_info for NIC's valid channels. |
5d08cd1d | 1067 | * Access via channel # using indirect index array */ |
bf85ea4f | 1068 | struct iwl_channel_info *channel_info; /* channel info array */ |
5d08cd1d CH |
1069 | u8 channel_count; /* # of channels */ |
1070 | ||
5d08cd1d CH |
1071 | /* thermal calibration */ |
1072 | s32 temperature; /* degrees Kelvin */ | |
1073 | s32 last_temperature; | |
1074 | ||
7c616cba | 1075 | /* init calibration results */ |
6e21f2c1 | 1076 | struct iwl_calib_result calib_results[IWL_CALIB_MAX]; |
7c616cba | 1077 | |
5d08cd1d | 1078 | /* Scan related variables */ |
7878a5a4 | 1079 | unsigned long next_scan_jiffies; |
5d08cd1d CH |
1080 | unsigned long scan_start; |
1081 | unsigned long scan_pass_start; | |
1082 | unsigned long scan_start_tsf; | |
805cee5b | 1083 | void *scan; |
5d08cd1d | 1084 | int scan_bands; |
1ecf9fc1 | 1085 | struct cfg80211_scan_request *scan_request; |
afbdd69a | 1086 | bool is_internal_short_scan; |
76eff18b TW |
1087 | u8 scan_tx_ant[IEEE80211_NUM_BANDS]; |
1088 | u8 mgmt_tx_ant; | |
5d08cd1d CH |
1089 | |
1090 | /* spinlock */ | |
1091 | spinlock_t lock; /* protect general shared data */ | |
1092 | spinlock_t hcmd_lock; /* protect hcmd */ | |
a8b50a0a | 1093 | spinlock_t reg_lock; /* protect hw register access */ |
5d08cd1d | 1094 | struct mutex mutex; |
d2dfe6df | 1095 | struct mutex sync_cmd_mutex; /* enable serialization of sync commands */ |
5d08cd1d CH |
1096 | |
1097 | /* basic pci-network driver stuff */ | |
1098 | struct pci_dev *pci_dev; | |
1099 | ||
1100 | /* pci hardware address support */ | |
1101 | void __iomem *hw_base; | |
b661c819 TW |
1102 | u32 hw_rev; |
1103 | u32 hw_wa_rev; | |
1104 | u8 rev_id; | |
5d08cd1d CH |
1105 | |
1106 | /* uCode images, save to reload in case of failure */ | |
b08dfd04 | 1107 | int fw_index; /* firmware we're trying to load */ |
c02b3acd CR |
1108 | u32 ucode_ver; /* version of ucode, copy of |
1109 | iwl_ucode.ver */ | |
5d08cd1d CH |
1110 | struct fw_desc ucode_code; /* runtime inst */ |
1111 | struct fw_desc ucode_data; /* runtime data original */ | |
1112 | struct fw_desc ucode_data_backup; /* runtime data save/restore */ | |
1113 | struct fw_desc ucode_init; /* initialization inst */ | |
1114 | struct fw_desc ucode_init_data; /* initialization data */ | |
1115 | struct fw_desc ucode_boot; /* bootstrap inst */ | |
dbb983b7 RR |
1116 | enum ucode_type ucode_type; |
1117 | u8 ucode_write_complete; /* the image write is complete */ | |
b08dfd04 | 1118 | char firmware_name[25]; |
5d08cd1d CH |
1119 | |
1120 | ||
3195c1f3 | 1121 | struct iwl_rxon_time_cmd rxon_timing; |
5d08cd1d CH |
1122 | |
1123 | /* We declare this const so it can only be | |
1124 | * changed via explicit cast within the | |
1125 | * routines that actually update the physical | |
1126 | * hardware */ | |
c1adf9fb GG |
1127 | const struct iwl_rxon_cmd active_rxon; |
1128 | struct iwl_rxon_cmd staging_rxon; | |
5d08cd1d | 1129 | |
0924e519 WYG |
1130 | struct iwl_switch_rxon switch_rxon; |
1131 | ||
5d08cd1d CH |
1132 | /* 1st responses from initialize and runtime uCode images. |
1133 | * 4965's initialize alive response contains some calibration data. */ | |
885ba202 TW |
1134 | struct iwl_init_alive_resp card_alive_init; |
1135 | struct iwl_alive_resp card_alive; | |
5d08cd1d | 1136 | |
ab53d8af MA |
1137 | unsigned long last_blink_time; |
1138 | u8 last_blink_rate; | |
1139 | u8 allow_blinking; | |
1140 | u64 led_tpt; | |
e932a609 | 1141 | |
5d08cd1d | 1142 | u16 active_rate; |
5d08cd1d | 1143 | |
5d08cd1d | 1144 | u8 start_calib; |
f0832f13 EG |
1145 | struct iwl_sensitivity_data sensitivity_data; |
1146 | struct iwl_chain_noise_data chain_noise_data; | |
5d08cd1d | 1147 | __le16 sensitivity_tbl[HD_TABLE_SIZE]; |
5d08cd1d | 1148 | |
fad95bf5 | 1149 | struct iwl_ht_config current_ht_config; |
5d08cd1d CH |
1150 | u8 last_phy_res[100]; |
1151 | ||
5d08cd1d | 1152 | /* Rate scaling data */ |
5d08cd1d CH |
1153 | u8 retry_rate; |
1154 | ||
1155 | wait_queue_head_t wait_command_queue; | |
1156 | ||
1157 | int activity_timer_active; | |
1158 | ||
1159 | /* Rx and Tx DMA processing queues */ | |
a55360e4 | 1160 | struct iwl_rx_queue rxq; |
88804e2b | 1161 | struct iwl_tx_queue *txq; |
5d08cd1d | 1162 | unsigned long txq_ctx_active_msk; |
4ddbb7d0 TW |
1163 | struct iwl_dma_ptr kw; /* keep warm address */ |
1164 | struct iwl_dma_ptr scd_bc_tbls; | |
1165 | ||
5d08cd1d CH |
1166 | u32 scd_base_addr; /* scheduler sram base address */ |
1167 | ||
1168 | unsigned long status; | |
5d08cd1d | 1169 | |
19758bef | 1170 | /* counts mgmt, ctl, and data packets */ |
22fdf3c9 WYG |
1171 | struct traffic_stats tx_stats; |
1172 | struct traffic_stats rx_stats; | |
19758bef | 1173 | |
a83b9141 WYG |
1174 | /* counts interrupts */ |
1175 | struct isr_statistics isr_stats; | |
1176 | ||
5da4b55f | 1177 | struct iwl_power_mgr power_data; |
3ad3b92a | 1178 | struct iwl_tt_mgmt thermal_throttle; |
5d08cd1d | 1179 | |
8f91aecb | 1180 | struct iwl_notif_statistics statistics; |
92a35bda WYG |
1181 | #ifdef CONFIG_IWLWIFI_DEBUG |
1182 | struct iwl_notif_statistics accum_statistics; | |
e3ef2164 WYG |
1183 | struct iwl_notif_statistics delta_statistics; |
1184 | struct iwl_notif_statistics max_delta; | |
92a35bda | 1185 | #endif |
5d08cd1d CH |
1186 | |
1187 | /* context information */ | |
5d08cd1d CH |
1188 | u8 bssid[ETH_ALEN]; |
1189 | u16 rts_threshold; | |
1190 | u8 mac_addr[ETH_ALEN]; | |
1191 | ||
1192 | /*station table variables */ | |
1193 | spinlock_t sta_lock; | |
1194 | int num_stations; | |
6def9761 | 1195 | struct iwl_station_entry stations[IWL_STATION_COUNT]; |
72e15d71 | 1196 | struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; /* protected by mutex */ |
6974e363 EG |
1197 | u8 default_wep_key; |
1198 | u8 key_mapping_key; | |
80fb47a1 | 1199 | unsigned long ucode_key_table; |
5d08cd1d | 1200 | |
e4e72fb4 JB |
1201 | /* queue refcounts */ |
1202 | #define IWL_MAX_HW_QUEUES 32 | |
1203 | unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; | |
1204 | /* for each AC */ | |
1205 | atomic_t queue_stop_count[4]; | |
1206 | ||
5d08cd1d | 1207 | /* Indication if ieee80211_ops->open has been called */ |
69dc5d9d | 1208 | u8 is_open; |
5d08cd1d CH |
1209 | |
1210 | u8 mac80211_registered; | |
5d08cd1d | 1211 | |
af6b8ee3 | 1212 | /* eeprom -- this is in the card's little endian byte order */ |
073d3f5f | 1213 | u8 *eeprom; |
0848e297 | 1214 | int nvm_device_type; |
073d3f5f | 1215 | struct iwl_eeprom_calib_info *calib_info; |
5d08cd1d | 1216 | |
05c914fe | 1217 | enum nl80211_iftype iw_mode; |
5d08cd1d CH |
1218 | |
1219 | struct sk_buff *ibss_beacon; | |
1220 | ||
1221 | /* Last Rx'd beacon timestamp */ | |
3109ece1 | 1222 | u64 timestamp; |
5d08cd1d | 1223 | u16 beacon_int; |
32bfd35d | 1224 | struct ieee80211_vif *vif; |
5d08cd1d | 1225 | |
ee525d13 JB |
1226 | union { |
1227 | #if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE) | |
1228 | struct { | |
1229 | void *shared_virt; | |
1230 | dma_addr_t shared_phys; | |
1231 | ||
1232 | struct delayed_work thermal_periodic; | |
1233 | struct delayed_work rfkill_poll; | |
1234 | ||
1235 | struct iwl3945_notif_statistics statistics; | |
1236 | ||
1237 | u32 sta_supp_rates; | |
e99f168c JB |
1238 | int last_rx_rssi; /* From Rx packet statistics */ |
1239 | ||
1240 | /* Rx'd packet timing information */ | |
1241 | u32 last_beacon_time; | |
1242 | u64 last_tsf; | |
67d613ae JB |
1243 | |
1244 | /* | |
1245 | * each calibration channel group in the | |
1246 | * EEPROM has a derived clip setting for | |
1247 | * each rate. | |
1248 | */ | |
1249 | const struct iwl3945_clip_group clip_groups[5]; | |
1250 | ||
ee525d13 | 1251 | } _3945; |
a4c8b2a6 JB |
1252 | #endif |
1253 | #if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE) | |
1254 | struct { | |
1255 | /* INT ICT Table */ | |
1256 | __le32 *ict_tbl; | |
1257 | void *ict_tbl_vir; | |
1258 | dma_addr_t ict_tbl_dma; | |
1259 | dma_addr_t aligned_ict_tbl_dma; | |
1260 | int ict_index; | |
1261 | u32 inta; | |
1262 | bool use_ict; | |
d5a0ffa3 WYG |
1263 | /* |
1264 | * reporting the number of tids has AGG on. 0 means | |
1265 | * no AGGREGATION | |
1266 | */ | |
1267 | u8 agg_tids_count; | |
a4c8b2a6 | 1268 | } _agn; |
ee525d13 JB |
1269 | #endif |
1270 | }; | |
1271 | ||
5425e490 | 1272 | struct iwl_hw_params hw_params; |
4ddbb7d0 | 1273 | |
40cefda9 | 1274 | u32 inta_mask; |
5d08cd1d CH |
1275 | /* Current association information needed to configure the |
1276 | * hardware */ | |
1277 | u16 assoc_id; | |
1278 | u16 assoc_capability; | |
5d08cd1d | 1279 | |
1ff50bda | 1280 | struct iwl_qos_info qos_data; |
5d08cd1d CH |
1281 | |
1282 | struct workqueue_struct *workqueue; | |
1283 | ||
5d08cd1d | 1284 | struct work_struct restart; |
5d08cd1d CH |
1285 | struct work_struct scan_completed; |
1286 | struct work_struct rx_replenish; | |
5d08cd1d | 1287 | struct work_struct abort_scan; |
5d08cd1d CH |
1288 | struct work_struct request_scan; |
1289 | struct work_struct beacon_update; | |
a28027cd WYG |
1290 | struct work_struct tt_work; |
1291 | struct work_struct ct_enter; | |
1292 | struct work_struct ct_exit; | |
5d08cd1d CH |
1293 | |
1294 | struct tasklet_struct irq_tasklet; | |
1295 | ||
1296 | struct delayed_work init_alive_start; | |
1297 | struct delayed_work alive_start; | |
5d08cd1d | 1298 | struct delayed_work scan_check; |
4a8a4322 | 1299 | |
630fe9b6 TW |
1300 | /* TX Power */ |
1301 | s8 tx_power_user_lmt; | |
dc1b0973 | 1302 | s8 tx_power_device_lmt; |
ae16fc3c | 1303 | s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */ |
5d08cd1d | 1304 | |
5d08cd1d | 1305 | |
d08853a3 | 1306 | #ifdef CONFIG_IWLWIFI_DEBUG |
5d08cd1d | 1307 | /* debugging info */ |
3d816c77 RC |
1308 | u32 debug_level; /* per device debugging will override global |
1309 | iwl_debug_level if set */ | |
5d08cd1d CH |
1310 | u32 framecnt_to_us; |
1311 | atomic_t restrict_refcnt; | |
1e4247d4 | 1312 | bool disable_ht40; |
712b6cf5 TW |
1313 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1314 | /* debugfs */ | |
20594eb0 WYG |
1315 | u16 tx_traffic_idx; |
1316 | u16 rx_traffic_idx; | |
1317 | u8 *tx_traffic; | |
1318 | u8 *rx_traffic; | |
4c84a8f1 JB |
1319 | struct dentry *debugfs_dir; |
1320 | u32 dbgfs_sram_offset, dbgfs_sram_len; | |
712b6cf5 TW |
1321 | #endif /* CONFIG_IWLWIFI_DEBUGFS */ |
1322 | #endif /* CONFIG_IWLWIFI_DEBUG */ | |
5d08cd1d CH |
1323 | |
1324 | struct work_struct txpower_work; | |
445c2dff TW |
1325 | u32 disable_sens_cal; |
1326 | u32 disable_chain_noise_cal; | |
203566f3 | 1327 | u32 disable_tx_power_cal; |
16e727e8 | 1328 | struct work_struct run_time_calib_work; |
5d08cd1d | 1329 | struct timer_list statistics_periodic; |
a9e1cb6a | 1330 | struct timer_list ucode_trace; |
b74e31a9 | 1331 | struct timer_list monitor_recover; |
086ed117 | 1332 | bool hw_ready; |
a9e1cb6a WYG |
1333 | |
1334 | struct iwl_event_log event_log; | |
c79dd5b5 | 1335 | }; /*iwl_priv */ |
5d08cd1d | 1336 | |
36470749 RR |
1337 | static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id) |
1338 | { | |
1339 | set_bit(txq_id, &priv->txq_ctx_active_msk); | |
1340 | } | |
1341 | ||
1342 | static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id) | |
1343 | { | |
1344 | clear_bit(txq_id, &priv->txq_ctx_active_msk); | |
1345 | } | |
1346 | ||
994d31f7 | 1347 | #ifdef CONFIG_IWLWIFI_DEBUG |
a332f8d6 | 1348 | const char *iwl_get_tx_fail_reason(u32 status); |
3d816c77 RC |
1349 | /* |
1350 | * iwl_get_debug_level: Return active debug level for device | |
1351 | * | |
1352 | * Using sysfs it is possible to set per device debug level. This debug | |
1353 | * level will be used if set, otherwise the global debug level which can be | |
1354 | * set via module parameter is used. | |
1355 | */ | |
1356 | static inline u32 iwl_get_debug_level(struct iwl_priv *priv) | |
1357 | { | |
1358 | if (priv->debug_level) | |
1359 | return priv->debug_level; | |
1360 | else | |
1361 | return iwl_debug_level; | |
1362 | } | |
a332f8d6 TW |
1363 | #else |
1364 | static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; } | |
3d816c77 RC |
1365 | |
1366 | static inline u32 iwl_get_debug_level(struct iwl_priv *priv) | |
1367 | { | |
1368 | return iwl_debug_level; | |
1369 | } | |
a332f8d6 TW |
1370 | #endif |
1371 | ||
1372 | ||
a332f8d6 TW |
1373 | static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv, |
1374 | int txq_id, int idx) | |
1375 | { | |
1376 | if (priv->txq[txq_id].txb[idx].skb[0]) | |
1377 | return (struct ieee80211_hdr *)priv->txq[txq_id]. | |
1378 | txb[idx].skb[0]->data; | |
1379 | return NULL; | |
1380 | } | |
a332f8d6 TW |
1381 | |
1382 | ||
3109ece1 | 1383 | static inline int iwl_is_associated(struct iwl_priv *priv) |
5d08cd1d CH |
1384 | { |
1385 | return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0; | |
1386 | } | |
1387 | ||
bf85ea4f | 1388 | static inline int is_channel_valid(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1389 | { |
1390 | if (ch_info == NULL) | |
1391 | return 0; | |
1392 | return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; | |
1393 | } | |
1394 | ||
bf85ea4f | 1395 | static inline int is_channel_radar(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1396 | { |
1397 | return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; | |
1398 | } | |
1399 | ||
bf85ea4f | 1400 | static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1401 | { |
8318d78a | 1402 | return ch_info->band == IEEE80211_BAND_5GHZ; |
5d08cd1d CH |
1403 | } |
1404 | ||
bf85ea4f | 1405 | static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1406 | { |
8318d78a | 1407 | return ch_info->band == IEEE80211_BAND_2GHZ; |
5d08cd1d CH |
1408 | } |
1409 | ||
bf85ea4f | 1410 | static inline int is_channel_passive(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1411 | { |
1412 | return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0; | |
1413 | } | |
1414 | ||
bf85ea4f | 1415 | static inline int is_channel_ibss(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1416 | { |
1417 | return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0; | |
1418 | } | |
1419 | ||
64a76b50 ZY |
1420 | static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page) |
1421 | { | |
1422 | __free_pages(page, priv->hw_params.rx_page_order); | |
1423 | priv->alloc_rxb_page--; | |
1424 | } | |
1425 | ||
1426 | static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page) | |
1427 | { | |
1428 | free_pages(page, priv->hw_params.rx_page_order); | |
1429 | priv->alloc_rxb_page--; | |
1430 | } | |
be1f3ab6 | 1431 | #endif /* __iwl_dev_h__ */ |