]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/wireless/iwlwifi/iwl-dev.h
iwlwifi: move 3945 clip groups to 3945 data
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h>
38
6bc913bd 39#include "iwl-eeprom.h"
6f83eaa1 40#include "iwl-csr.h"
5d08cd1d 41#include "iwl-prph.h"
dbb6654c 42#include "iwl-fh.h"
0a6857e7 43#include "iwl-debug.h"
dbb6654c
WT
44#include "iwl-4965-hw.h"
45#include "iwl-3945-hw.h"
ab53d8af 46#include "iwl-led.h"
5da4b55f 47#include "iwl-power.h"
e227ceac 48#include "iwl-agn-rs.h"
5d08cd1d 49
fed9017e
RR
50/* configuration for the iwl4965 */
51extern struct iwl_cfg iwl4965_agn_cfg;
5a6a256e
TW
52extern struct iwl_cfg iwl5300_agn_cfg;
53extern struct iwl_cfg iwl5100_agn_cfg;
54extern struct iwl_cfg iwl5350_agn_cfg;
ac592574 55extern struct iwl_cfg iwl5100_bgn_cfg;
47408639 56extern struct iwl_cfg iwl5100_abg_cfg;
7100e924 57extern struct iwl_cfg iwl5150_agn_cfg;
ac592574 58extern struct iwl_cfg iwl5150_abg_cfg;
65b7998a 59extern struct iwl_cfg iwl6000i_2agn_cfg;
5953a62e
WYG
60extern struct iwl_cfg iwl6000i_2abg_cfg;
61extern struct iwl_cfg iwl6000i_2bg_cfg;
e1228374
JS
62extern struct iwl_cfg iwl6000_3agn_cfg;
63extern struct iwl_cfg iwl6050_2agn_cfg;
5953a62e 64extern struct iwl_cfg iwl6050_2abg_cfg;
77dcb6a9 65extern struct iwl_cfg iwl1000_bgn_cfg;
4bd0914f 66extern struct iwl_cfg iwl1000_bg_cfg;
fed9017e 67
672639de
WYG
68struct iwl_tx_queue;
69
cec2d3f3
JS
70/* shared structures from iwl-5000.c */
71extern struct iwl_mod_params iwl50_mod_params;
cc0f555d 72extern struct iwl_ucode_ops iwl5000_ucode;
e8c00dcb
JS
73extern struct iwl_lib_ops iwl5000_lib;
74extern struct iwl_hcmd_ops iwl5000_hcmd;
75extern struct iwl_hcmd_utils_ops iwl5000_hcmd_utils;
76
77/* shared functions from iwl-5000.c */
78extern u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len);
79extern u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd,
80 u8 *data);
81extern void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
82 __le32 *tx_flags);
83extern int iwl5000_calc_rssi(struct iwl_priv *priv,
84 struct iwl_rx_phy_res *rx_resp);
672639de
WYG
85extern void iwl5000_nic_config(struct iwl_priv *priv);
86extern u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv);
87extern const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
88 size_t offset);
89extern void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
90 struct iwl_tx_queue *txq,
91 u16 byte_cnt);
92extern void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
93 struct iwl_tx_queue *txq);
94extern int iwl5000_load_ucode(struct iwl_priv *priv);
95extern void iwl5000_init_alive_start(struct iwl_priv *priv);
96extern int iwl5000_alive_notify(struct iwl_priv *priv);
97extern int iwl5000_hw_set_hw_params(struct iwl_priv *priv);
98extern int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
99 int tx_fifo, int sta_id, int tid, u16 ssn_idx);
100extern int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
101 u16 ssn_idx, u8 tx_fifo);
102extern void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask);
103extern void iwl5000_setup_deferred_work(struct iwl_priv *priv);
104extern void iwl5000_rx_handler_setup(struct iwl_priv *priv);
105extern int iwl5000_hw_valid_rtc_data_addr(u32 addr);
106extern int iwl5000_send_tx_power(struct iwl_priv *priv);
107extern void iwl5000_temperature(struct iwl_priv *priv);
cec2d3f3 108
099b40b7 109/* CT-KILL constants */
672639de
WYG
110#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
111#define CT_KILL_THRESHOLD 114 /* in Celsius */
112#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 113
5d08cd1d
CH
114/* Default noise level to report when noise measurement is not available.
115 * This may be because we're:
116 * 1) Not associated (4965, no beacon statistics being sent to driver)
117 * 2) Scanning (noise measurement does not apply to associated channel)
118 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
119 * Use default noise value of -127 ... this is below the range of measurable
120 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
121 * Also, -127 works better than 0 when averaging frames with/without
122 * noise info (e.g. averaging might be done in app); measured dBm values are
123 * always negative ... using a negative value as the default keeps all
124 * averages within an s8's (used in some apps) range of negative values. */
125#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
126
5d08cd1d
CH
127/*
128 * RTS threshold here is total size [2347] minus 4 FCS bytes
129 * Per spec:
130 * a value of 0 means RTS on all data/management packets
131 * a value > max MSDU size means no RTS
132 * else RTS for data/management frames where MPDU is larger
133 * than RTS value.
134 */
135#define DEFAULT_RTS_THRESHOLD 2347U
136#define MIN_RTS_THRESHOLD 0U
137#define MAX_RTS_THRESHOLD 2347U
138#define MAX_MSDU_SIZE 2304U
139#define MAX_MPDU_SIZE 2346U
140#define DEFAULT_BEACON_INTERVAL 100U
141#define DEFAULT_SHORT_RETRY_LIMIT 7U
142#define DEFAULT_LONG_RETRY_LIMIT 4U
143
a55360e4 144struct iwl_rx_mem_buffer {
2f301227
ZY
145 dma_addr_t page_dma;
146 struct page *page;
5d08cd1d
CH
147 struct list_head list;
148};
149
2f301227
ZY
150#define rxb_addr(r) page_address(r->page)
151
c2acea8e
JB
152/* defined below */
153struct iwl_device_cmd;
154
155struct iwl_cmd_meta {
156 /* only for SYNC commands, iff the reply skb is wanted */
157 struct iwl_host_cmd *source;
158 /*
159 * only for ASYNC commands
160 * (which is somewhat stupid -- look at iwl-sta.c for instance
161 * which duplicates a bunch of code because the callback isn't
162 * invoked for SYNC commands, if it were and its result passed
163 * through it would be simpler...)
164 */
5696aea6
JB
165 void (*callback)(struct iwl_priv *priv,
166 struct iwl_device_cmd *cmd,
2f301227 167 struct iwl_rx_packet *pkt);
c2acea8e
JB
168
169 /* The CMD_SIZE_HUGE flag bit indicates that the command
170 * structure is stored at the end of the shared queue memory. */
171 u32 flags;
172
173 DECLARE_PCI_UNMAP_ADDR(mapping)
174 DECLARE_PCI_UNMAP_LEN(len)
175};
176
5d08cd1d
CH
177/*
178 * Generic queue structure
179 *
180 * Contains common data for Rx and Tx queues
181 */
443cfd45 182struct iwl_queue {
5d08cd1d
CH
183 int n_bd; /* number of BDs in this queue */
184 int write_ptr; /* 1-st empty entry (index) host_w*/
185 int read_ptr; /* last used entry (index) host_r*/
186 dma_addr_t dma_addr; /* physical addr for BD's */
187 int n_window; /* safe queue window */
188 u32 id;
189 int low_mark; /* low watermark, resume queue if free
190 * space more than this */
191 int high_mark; /* high watermark, stop queue if free
192 * space less than this */
193} __attribute__ ((packed));
194
bc47279f 195/* One for each TFD */
8567c63e 196struct iwl_tx_info {
499b1883 197 struct sk_buff *skb[IWL_NUM_OF_TBS - 1];
5d08cd1d
CH
198};
199
200/**
16466903 201 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
202 * @q: generic Rx/Tx queue descriptor
203 * @bd: base of circular buffer of TFDs
c2acea8e
JB
204 * @cmd: array of command/TX buffer pointers
205 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
206 * @dma_addr_cmd: physical address of cmd/tx buffer array
207 * @txb: array of per-TFD driver data
208 * @need_update: indicates need to update read/write index
209 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 210 *
bc47279f
BC
211 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
212 * descriptors) and required locking structures.
5d08cd1d 213 */
188cf6c7
SO
214#define TFD_TX_CMD_SLOTS 256
215#define TFD_CMD_SLOTS 32
216
16466903 217struct iwl_tx_queue {
443cfd45 218 struct iwl_queue q;
59606ffa 219 void *tfds;
c2acea8e
JB
220 struct iwl_device_cmd **cmd;
221 struct iwl_cmd_meta *meta;
8567c63e 222 struct iwl_tx_info *txb;
3fd07a1e
TW
223 u8 need_update;
224 u8 sched_retry;
225 u8 active;
226 u8 swq_id;
5d08cd1d
CH
227};
228
229#define IWL_NUM_SCAN_RATES (2)
230
bb8c093b 231struct iwl4965_channel_tgd_info {
5d08cd1d
CH
232 u8 type;
233 s8 max_power;
234};
235
bb8c093b 236struct iwl4965_channel_tgh_info {
5d08cd1d
CH
237 s64 last_radar_time;
238};
239
d20b3c65
SO
240#define IWL4965_MAX_RATE (33)
241
85d41495
KA
242struct iwl3945_clip_group {
243 /* maximum power level to prevent clipping for each rate, derived by
244 * us from this band's saturation power in EEPROM */
245 const s8 clip_powers[IWL_MAX_RATES];
246};
247
d20b3c65
SO
248/* current Tx power values to use, one for each rate for each channel.
249 * requested power is limited by:
250 * -- regulatory EEPROM limits for this channel
251 * -- hardware capabilities (clip-powers)
252 * -- spectrum management
253 * -- user preference (e.g. iwconfig)
254 * when requested power is set, base power index must also be set. */
255struct iwl3945_channel_power_info {
256 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
257 s8 power_table_index; /* actual (compenst'd) index into gain table */
258 s8 base_power_index; /* gain index for power at factory temp. */
259 s8 requested_power; /* power (dBm) requested for this chnl/rate */
260};
261
262/* current scan Tx power values to use, one for each scan rate for each
263 * channel. */
264struct iwl3945_scan_power_info {
265 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
266 s8 power_table_index; /* actual (compenst'd) index into gain table */
267 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
268};
269
5d08cd1d
CH
270/*
271 * One for each channel, holds all channel setup data
272 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
273 * with one another!
274 */
bf85ea4f 275struct iwl_channel_info {
bb8c093b
CH
276 struct iwl4965_channel_tgd_info tgd;
277 struct iwl4965_channel_tgh_info tgh;
073d3f5f 278 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
279 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
280 * HT40 channel */
5d08cd1d
CH
281
282 u8 channel; /* channel number */
283 u8 flags; /* flags copied from EEPROM */
284 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 285 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
286 s8 min_power; /* always 0 */
287 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
288
289 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
290 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 291 enum ieee80211_band band;
5d08cd1d 292
7aafef1c
WYG
293 /* HT40 channel info */
294 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
295 u8 ht40_flags; /* flags copied from EEPROM */
296 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
d20b3c65
SO
297
298 /* Radio/DSP gain settings for each "normal" data Tx rate.
299 * These include, in addition to RF and DSP gain, a few fields for
300 * remembering/modifying gain settings (indexes). */
301 struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
302
303 /* Radio/DSP gain settings for each scan rate, for directed scans. */
304 struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
5d08cd1d
CH
305};
306
5d08cd1d
CH
307#define IWL_TX_FIFO_AC0 0
308#define IWL_TX_FIFO_AC1 1
309#define IWL_TX_FIFO_AC2 2
310#define IWL_TX_FIFO_AC3 3
311#define IWL_TX_FIFO_HCCA_1 5
312#define IWL_TX_FIFO_HCCA_2 6
313#define IWL_TX_FIFO_NONE 7
314
01a7e084
RC
315/* Minimum number of queues. MAX_NUM is defined in hw specific files.
316 * Set the minimum to accommodate the 4 standard TX queues, 1 command
317 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
318#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 319
bd35f150 320/*
1a716557
JB
321 * Queue #4 is the command queue for 3945/4965/5x00/1000/6x00,
322 * the driver maps it into the appropriate device FIFO for the
323 * uCode.
bd35f150
WYG
324 */
325#define IWL_CMD_QUEUE_NUM 4
326
5d08cd1d
CH
327/* Power management (not Tx power) structures */
328
6f4083aa
TW
329enum iwl_pwr_src {
330 IWL_PWR_SRC_VMAIN,
331 IWL_PWR_SRC_VAUX,
332};
333
5d08cd1d
CH
334#define IEEE80211_DATA_LEN 2304
335#define IEEE80211_4ADDR_LEN 30
336#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
337#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
338
fcab423d 339struct iwl_frame {
5d08cd1d
CH
340 union {
341 struct ieee80211_hdr frame;
4bf64efd 342 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
343 u8 raw[IEEE80211_FRAME_LEN];
344 u8 cmd[360];
345 } u;
346 struct list_head list;
347};
348
5d08cd1d
CH
349#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
350#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
351#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
352
353enum {
c587de0b
TW
354 CMD_SYNC = 0,
355 CMD_SIZE_NORMAL = 0,
356 CMD_NO_SKB = 0,
5d08cd1d 357 CMD_SIZE_HUGE = (1 << 0),
5d08cd1d 358 CMD_ASYNC = (1 << 1),
5d08cd1d
CH
359 CMD_WANT_SKB = (1 << 2),
360};
361
c8c24872 362#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 363
2f301227
ZY
364/*
365 * IWL_LINK_HDR_MAX should include ieee80211_hdr, radiotap header,
366 * SNAP header and alignment. It should also be big enough for 802.11
367 * control frames.
368 */
369#define IWL_LINK_HDR_MAX 64
370
bc47279f 371/**
c2acea8e 372 * struct iwl_device_cmd
bc47279f
BC
373 *
374 * For allocation of the command and tx queues, this establishes the overall
375 * size of the largest command we send to uCode, except for a scan command
376 * (which is relatively huge; space is allocated separately).
377 */
c2acea8e 378struct iwl_device_cmd {
857485c0 379 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 380 union {
5d08cd1d
CH
381 u32 flags;
382 u8 val8;
383 u16 val16;
384 u32 val32;
83d527d9 385 struct iwl_tx_cmd tx;
c8c24872
WYG
386 struct iwl6000_channel_switch_cmd chswitch;
387 u8 payload[DEF_CMD_PAYLOAD_SIZE];
5d08cd1d
CH
388 } __attribute__ ((packed)) cmd;
389} __attribute__ ((packed));
390
c2acea8e
JB
391#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
392
3257e5d4 393
857485c0 394struct iwl_host_cmd {
5d08cd1d 395 const void *data;
2f301227 396 unsigned long reply_page;
5696aea6
JB
397 void (*callback)(struct iwl_priv *priv,
398 struct iwl_device_cmd *cmd,
2f301227 399 struct iwl_rx_packet *pkt);
c2acea8e
JB
400 u32 flags;
401 u16 len;
402 u8 id;
5d08cd1d
CH
403};
404
5d08cd1d
CH
405#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
406#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
407#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
408
409/**
a55360e4 410 * struct iwl_rx_queue - Rx queue
df833b1d
RC
411 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
412 * @dma_addr: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
413 * @read: Shared index to newest available Rx buffer
414 * @write: Shared index to oldest written Rx packet
415 * @free_count: Number of pre-allocated buffers in rx_free
416 * @rx_free: list of free SKBs for use
417 * @rx_used: List of Rx buffers with no SKB
418 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
419 * @rb_stts: driver's pointer to receive buffer status
420 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 421 *
a55360e4 422 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 423 */
a55360e4 424struct iwl_rx_queue {
5d08cd1d
CH
425 __le32 *bd;
426 dma_addr_t dma_addr;
a55360e4
TW
427 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
428 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
429 u32 read;
430 u32 write;
431 u32 free_count;
4752c93c 432 u32 write_actual;
5d08cd1d
CH
433 struct list_head rx_free;
434 struct list_head rx_used;
435 int need_update;
8d86422a
WT
436 struct iwl_rb_status *rb_stts;
437 dma_addr_t rb_stts_dma;
5d08cd1d
CH
438 spinlock_t lock;
439};
440
441#define IWL_SUPPORTED_RATES_IE_LEN 8
442
5d08cd1d
CH
443#define MAX_TID_COUNT 9
444
445#define IWL_INVALID_RATE 0xFF
446#define IWL_INVALID_VALUE -1
447
bc47279f 448/**
6def9761 449 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
450 * @txq_id: Tx queue used for Tx attempt
451 * @frame_count: # frames attempted by Tx command
452 * @wait_for_ba: Expect block-ack before next Tx reply
453 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
454 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
455 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
456 * @rate_n_flags: Rate at which Tx was attempted
457 *
458 * If REPLY_TX indicates that aggregation was attempted, driver must wait
459 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
460 * until block ack arrives.
461 */
6def9761 462struct iwl_ht_agg {
5d08cd1d
CH
463 u16 txq_id;
464 u16 frame_count;
465 u16 wait_for_ba;
466 u16 start_idx;
fe01b477 467 u64 bitmap;
5d08cd1d 468 u32 rate_n_flags;
fe01b477
RR
469#define IWL_AGG_OFF 0
470#define IWL_AGG_ON 1
471#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
472#define IWL_EMPTYING_HW_QUEUE_DELBA 3
473 u8 state;
5d08cd1d 474};
fe01b477 475
5d08cd1d 476
6def9761 477struct iwl_tid_data {
5d08cd1d 478 u16 seq_number;
fe01b477 479 u16 tfds_in_queue;
6def9761 480 struct iwl_ht_agg agg;
5d08cd1d
CH
481};
482
6def9761 483struct iwl_hw_key {
5d08cd1d
CH
484 enum ieee80211_key_alg alg;
485 int keylen;
0211ddda 486 u8 keyidx;
5d08cd1d
CH
487 u8 key[32];
488};
489
a78fe754 490union iwl_ht_rate_supp {
5d08cd1d
CH
491 u16 rates;
492 struct {
493 u8 siso_rate;
494 u8 mimo_rate;
495 };
496};
497
5d08cd1d 498#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
bcc693a1
WYG
499
500/*
501 * Maximal MPDU density for TX aggregation
502 * 4 - 2us density
503 * 5 - 4us density
504 * 6 - 8us density
505 * 7 - 16us density
506 */
507#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
508#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
5d08cd1d 509
fad95bf5 510struct iwl_ht_config {
9e0cc6de 511 /* self configuration data */
c812ee24
JB
512 bool is_ht;
513 bool is_40mhz;
02bb1bea 514 bool single_chain_sufficient;
ba37a3d0 515 enum ieee80211_smps_mode smps; /* current smps mode */
9e0cc6de 516 /* BSS related data */
5d08cd1d 517 u8 extension_chan_offset;
9e0cc6de
RR
518 u8 ht_protection;
519 u8 non_GF_STA_present;
5d08cd1d 520};
5d08cd1d 521
1ff50bda 522union iwl_qos_capabity {
5d08cd1d
CH
523 struct {
524 u8 edca_count:4; /* bit 0-3 */
525 u8 q_ack:1; /* bit 4 */
526 u8 queue_request:1; /* bit 5 */
527 u8 txop_request:1; /* bit 6 */
528 u8 reserved:1; /* bit 7 */
529 } q_AP;
530 struct {
531 u8 acvo_APSD:1; /* bit 0 */
532 u8 acvi_APSD:1; /* bit 1 */
533 u8 ac_bk_APSD:1; /* bit 2 */
534 u8 ac_be_APSD:1; /* bit 3 */
535 u8 q_ack:1; /* bit 4 */
536 u8 max_len:2; /* bit 5-6 */
537 u8 more_data_ack:1; /* bit 7 */
538 } q_STA;
539 u8 val;
540};
541
542/* QoS structures */
1ff50bda 543struct iwl_qos_info {
5d08cd1d 544 int qos_active;
1ff50bda
EG
545 union iwl_qos_capabity qos_cap;
546 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 547};
5d08cd1d 548
6def9761 549struct iwl_station_entry {
133636de 550 struct iwl_addsta_cmd sta;
6def9761 551 struct iwl_tid_data tid[MAX_TID_COUNT];
5d08cd1d 552 u8 used;
6def9761 553 struct iwl_hw_key keyinfo;
5d08cd1d
CH
554};
555
8d9698b3
RC
556/*
557 * iwl_station_priv: Driver's private station information
558 *
559 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
560 * in the structure for use by driver. This structure is places in that
561 * space.
8d9698b3
RC
562 */
563struct iwl_station_priv {
564 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
565 atomic_t pending_frames;
566 bool client;
567 bool asleep;
8d9698b3
RC
568};
569
5d08cd1d
CH
570/* one for each uCode image (inst/data, boot/init/runtime) */
571struct fw_desc {
572 void *v_addr; /* access by driver */
573 dma_addr_t p_addr; /* access by card's busmaster DMA */
574 u32 len; /* bytes */
575};
576
577/* uCode file layout */
cc0f555d
JS
578struct iwl_ucode_header {
579 __le32 ver; /* major/minor/API/serial */
580 union {
581 struct {
582 __le32 inst_size; /* bytes of runtime code */
583 __le32 data_size; /* bytes of runtime data */
584 __le32 init_size; /* bytes of init code */
585 __le32 init_data_size; /* bytes of init data */
586 __le32 boot_size; /* bytes of bootstrap code */
587 u8 data[0]; /* in same order as sizes */
588 } v1;
589 struct {
590 __le32 build; /* build number */
591 __le32 inst_size; /* bytes of runtime code */
592 __le32 data_size; /* bytes of runtime data */
593 __le32 init_size; /* bytes of init code */
594 __le32 init_data_size; /* bytes of init data */
595 __le32 boot_size; /* bytes of bootstrap code */
596 u8 data[0]; /* in same order as sizes */
597 } v2;
598 } u;
5d08cd1d 599};
cc0f555d 600#define UCODE_HEADER_SIZE(ver) ((ver) == 1 ? 24 : 28)
5d08cd1d 601
bb8c093b 602struct iwl4965_ibss_seq {
5d08cd1d
CH
603 u8 mac[ETH_ALEN];
604 u16 seq_num;
605 u16 frag_num;
606 unsigned long packet_time;
607 struct list_head list;
608};
609
f0832f13
EG
610struct iwl_sensitivity_ranges {
611 u16 min_nrg_cck;
612 u16 max_nrg_cck;
613
614 u16 nrg_th_cck;
615 u16 nrg_th_ofdm;
616
617 u16 auto_corr_min_ofdm;
618 u16 auto_corr_min_ofdm_mrc;
619 u16 auto_corr_min_ofdm_x1;
620 u16 auto_corr_min_ofdm_mrc_x1;
621
622 u16 auto_corr_max_ofdm;
623 u16 auto_corr_max_ofdm_mrc;
624 u16 auto_corr_max_ofdm_x1;
625 u16 auto_corr_max_ofdm_mrc_x1;
626
627 u16 auto_corr_max_cck;
628 u16 auto_corr_max_cck_mrc;
629 u16 auto_corr_min_cck;
630 u16 auto_corr_min_cck_mrc;
55036d66
WYG
631
632 u16 barker_corr_th_min;
633 u16 barker_corr_th_min_mrc;
634 u16 nrg_th_cca;
f0832f13
EG
635};
636
099b40b7 637
b5047f78
TW
638#define KELVIN_TO_CELSIUS(x) ((x)-273)
639#define CELSIUS_TO_KELVIN(x) ((x)+273)
640
641
bc47279f 642/**
5425e490 643 * struct iwl_hw_params
bc47279f 644 * @max_txq_num: Max # Tx queues supported
f3f911d1 645 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 646 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 647 * @tfd_size: TFD size
099b40b7
RR
648 * @tx/rx_chains_num: Number of TX/RX chains
649 * @valid_tx/rx_ant: usable antennas
bc47279f 650 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 651 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 652 * @rx_page_order: Rx buffer page order
141c43a3 653 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f
BC
654 * @max_stations:
655 * @bcast_sta_id:
7aafef1c 656 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
657 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
658 * @sw_crypto: 0 for hw, 1 for sw
659 * @max_xxx_size: for ucode uses
660 * @ct_kill_threshold: temperature threshold
a96a27f9 661 * @calib_init_cfg: setup initial calibrations for the hw
f0832f13 662 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 663 */
5425e490 664struct iwl_hw_params {
f3f911d1
ZY
665 u8 max_txq_num;
666 u8 dma_chnl_num;
4ddbb7d0 667 u16 scd_bc_tbls_size;
a8e74e27 668 u32 tfd_size;
ec35cf2a
TW
669 u8 tx_chains_num;
670 u8 rx_chains_num;
671 u8 valid_tx_ant;
672 u8 valid_rx_ant;
5d08cd1d 673 u16 max_rxq_size;
ec35cf2a 674 u16 max_rxq_log;
2f301227 675 u32 rx_page_order;
141c43a3 676 u32 rx_wrt_ptr_reg;
5d08cd1d
CH
677 u8 max_stations;
678 u8 bcast_sta_id;
7aafef1c 679 u8 ht40_channel;
2c2f3b33 680 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
681 u32 max_inst_size;
682 u32 max_data_size;
683 u32 max_bsm_size;
684 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
685 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
686 /* for 1000, 6000 series and up */
be5d56ed 687 u32 calib_init_cfg;
f0832f13 688 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
689};
690
5d08cd1d 691
5d08cd1d
CH
692/******************************************************************************
693 *
a33c2f47
EG
694 * Functions implemented in core module which are forward declared here
695 * for use by iwl-[4-5].c
5d08cd1d 696 *
a33c2f47
EG
697 * NOTE: The implementation of these functions are not hardware specific
698 * which is why they are in the core module files.
5d08cd1d
CH
699 *
700 * Naming convention --
a33c2f47 701 * iwl_ <-- Is part of iwlwifi
5d08cd1d 702 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
703 * iwl4965_bg_ <-- Called from work queue context
704 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
705 *
706 ****************************************************************************/
5b9f8cd3
EG
707extern void iwl_update_chain_flags(struct iwl_priv *priv);
708extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src);
a33c2f47 709extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 710extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 711extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 712extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
713static inline int iwl_queue_used(const struct iwl_queue *q, int i)
714{
c8106d76 715 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
716 (i >= q->read_ptr && i < q->write_ptr) :
717 !(i < q->read_ptr && i >= q->write_ptr);
718}
719
720
721static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
722{
c8c24872
WYG
723 /*
724 * This is for init calibration result and scan command which
725 * required buffer > TFD_MAX_PAYLOAD_SIZE,
726 * the big buffer at end of command array
727 */
fd4abac5
TW
728 if (is_huge)
729 return q->n_window; /* must be power of 2 */
730
731 /* Otherwise, use normal size buffers */
732 return index & (q->n_window - 1);
733}
734
735
4ddbb7d0
TW
736struct iwl_dma_ptr {
737 dma_addr_t dma;
738 void *addr;
b481de9c
ZY
739 size_t size;
740};
741
b481de9c
ZY
742#define IWL_OPERATION_MODE_AUTO 0
743#define IWL_OPERATION_MODE_HT_ONLY 1
744#define IWL_OPERATION_MODE_MIXED 2
745#define IWL_OPERATION_MODE_20MHZ 3
746
3195cdb7
TW
747#define IWL_TX_CRC_SIZE 4
748#define IWL_TX_DELIMITER_SIZE 4
b481de9c 749
b481de9c 750#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 751
b481de9c 752/* Sensitivity and chain noise calibration */
b481de9c 753#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a
WYG
754#define IWL4965_CAL_NUM_BEACONS 20
755#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
756#define MAXIMUM_ALLOWED_PATHLOSS 15
757
b481de9c
ZY
758#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
759
760#define MAX_FA_OFDM 50
761#define MIN_FA_OFDM 5
762#define MAX_FA_CCK 50
763#define MIN_FA_CCK 5
764
b481de9c
ZY
765#define AUTO_CORR_STEP_OFDM 1
766
b481de9c
ZY
767#define AUTO_CORR_STEP_CCK 3
768#define AUTO_CORR_MAX_TH_CCK 160
769
b481de9c
ZY
770#define NRG_DIFF 2
771#define NRG_STEP_CCK 2
772#define NRG_MARGIN 8
773#define MAX_NUMBER_CCK_NO_FA 100
774
775#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
776
777#define CHAIN_A 0
778#define CHAIN_B 1
779#define CHAIN_C 2
780#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
781#define ALL_BAND_FILTER 0xFF00
782#define IN_BAND_FILTER 0xFF
783#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
784
3195cdb7
TW
785#define NRG_NUM_PREV_STAT_L 20
786#define NUM_RX_CHAINS 3
787
bb8c093b 788enum iwl4965_false_alarm_state {
b481de9c
ZY
789 IWL_FA_TOO_MANY = 0,
790 IWL_FA_TOO_FEW = 1,
791 IWL_FA_GOOD_RANGE = 2,
792};
793
bb8c093b 794enum iwl4965_chain_noise_state {
b481de9c 795 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
796 IWL_CHAIN_NOISE_ACCUMULATE,
797 IWL_CHAIN_NOISE_CALIBRATED,
798 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
799};
800
bb8c093b 801enum iwl4965_calib_enabled_state {
b481de9c
ZY
802 IWL_CALIB_DISABLED = 0, /* must be 0 */
803 IWL_CALIB_ENABLED = 1,
804};
805
f69f42a6
TW
806
807/*
808 * enum iwl_calib
809 * defines the order in which results of initial calibrations
810 * should be sent to the runtime uCode
811 */
812enum iwl_calib {
813 IWL_CALIB_XTAL,
819500c5 814 IWL_CALIB_DC,
f69f42a6
TW
815 IWL_CALIB_LO,
816 IWL_CALIB_TX_IQ,
817 IWL_CALIB_TX_IQ_PERD,
201706ac 818 IWL_CALIB_BASE_BAND,
f69f42a6
TW
819 IWL_CALIB_MAX
820};
821
6e21f2c1
TW
822/* Opaque calibration results */
823struct iwl_calib_result {
824 void *buf;
825 size_t buf_len;
7c616cba
TW
826};
827
dbb983b7
RR
828enum ucode_type {
829 UCODE_NONE = 0,
830 UCODE_INIT,
831 UCODE_RT
832};
833
b481de9c 834/* Sensitivity calib data */
f0832f13 835struct iwl_sensitivity_data {
b481de9c
ZY
836 u32 auto_corr_ofdm;
837 u32 auto_corr_ofdm_mrc;
838 u32 auto_corr_ofdm_x1;
839 u32 auto_corr_ofdm_mrc_x1;
840 u32 auto_corr_cck;
841 u32 auto_corr_cck_mrc;
842
843 u32 last_bad_plcp_cnt_ofdm;
844 u32 last_fa_cnt_ofdm;
845 u32 last_bad_plcp_cnt_cck;
846 u32 last_fa_cnt_cck;
847
848 u32 nrg_curr_state;
849 u32 nrg_prev_state;
850 u32 nrg_value[10];
851 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
852 u32 nrg_silence_ref;
853 u32 nrg_energy_idx;
854 u32 nrg_silence_idx;
855 u32 nrg_th_cck;
856 s32 nrg_auto_corr_silence_diff;
857 u32 num_in_cck_no_fa;
858 u32 nrg_th_ofdm;
55036d66
WYG
859
860 u16 barker_corr_th_min;
861 u16 barker_corr_th_min_mrc;
862 u16 nrg_th_cca;
b481de9c
ZY
863};
864
865/* Chain noise (differential Rx gain) calib data */
f0832f13 866struct iwl_chain_noise_data {
04816448 867 u32 active_chains;
b481de9c
ZY
868 u32 chain_noise_a;
869 u32 chain_noise_b;
870 u32 chain_noise_c;
871 u32 chain_signal_a;
872 u32 chain_signal_b;
873 u32 chain_signal_c;
04816448 874 u16 beacon_count;
b481de9c
ZY
875 u8 disconn_array[NUM_RX_CHAINS];
876 u8 delta_gain_code[NUM_RX_CHAINS];
877 u8 radio_write;
04816448 878 u8 state;
b481de9c
ZY
879};
880
abceddb4
BC
881#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
882#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 883
20594eb0
WYG
884#define IWL_TRAFFIC_ENTRIES (256)
885#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 886
5d08cd1d
CH
887enum {
888 MEASUREMENT_READY = (1 << 0),
889 MEASUREMENT_ACTIVE = (1 << 1),
890};
891
0848e297
WYG
892enum iwl_nvm_type {
893 NVM_DEVICE_TYPE_EEPROM = 0,
894 NVM_DEVICE_TYPE_OTP,
895};
896
415e4993
WYG
897/*
898 * Two types of OTP memory access modes
899 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
900 * based on physical memory addressing
901 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
902 * based on logical memory addressing
903 */
904enum iwl_access_mode {
905 IWL_OTP_ACCESS_ABSOLUTE,
906 IWL_OTP_ACCESS_RELATIVE,
907};
65b7998a
WYG
908
909/**
910 * enum iwl_pa_type - Power Amplifier type
911 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
912 * @IWL_PA_INTERNAL: use Internal only
913 */
914enum iwl_pa_type {
915 IWL_PA_SYSTEM = 0,
740e7f51 916 IWL_PA_INTERNAL = 1,
65b7998a
WYG
917};
918
a83b9141
WYG
919/* interrupt statistics */
920struct isr_statistics {
921 u32 hw;
922 u32 sw;
923 u32 sw_err;
924 u32 sch;
925 u32 alive;
926 u32 rfkill;
927 u32 ctkill;
928 u32 wakeup;
929 u32 rx;
930 u32 rx_handlers[REPLY_MAX];
931 u32 tx;
932 u32 unhandled;
933};
5d08cd1d 934
22fdf3c9
WYG
935#ifdef CONFIG_IWLWIFI_DEBUGFS
936/* management statistics */
937enum iwl_mgmt_stats {
938 MANAGEMENT_ASSOC_REQ = 0,
939 MANAGEMENT_ASSOC_RESP,
940 MANAGEMENT_REASSOC_REQ,
941 MANAGEMENT_REASSOC_RESP,
942 MANAGEMENT_PROBE_REQ,
943 MANAGEMENT_PROBE_RESP,
944 MANAGEMENT_BEACON,
945 MANAGEMENT_ATIM,
946 MANAGEMENT_DISASSOC,
947 MANAGEMENT_AUTH,
948 MANAGEMENT_DEAUTH,
949 MANAGEMENT_ACTION,
950 MANAGEMENT_MAX,
951};
952/* control statistics */
953enum iwl_ctrl_stats {
954 CONTROL_BACK_REQ = 0,
955 CONTROL_BACK,
956 CONTROL_PSPOLL,
957 CONTROL_RTS,
958 CONTROL_CTS,
959 CONTROL_ACK,
960 CONTROL_CFEND,
961 CONTROL_CFENDACK,
962 CONTROL_MAX,
963};
964
965struct traffic_stats {
966 u32 mgmt[MANAGEMENT_MAX];
967 u32 ctrl[CONTROL_MAX];
968 u32 data_cnt;
969 u64 data_bytes;
970};
971#else
972struct traffic_stats {
973 u64 data_bytes;
974};
975#endif
976
0924e519
WYG
977/*
978 * iwl_switch_rxon: "channel switch" structure
979 *
980 * @ switch_in_progress: channel switch in progress
981 * @ channel: new channel
982 */
983struct iwl_switch_rxon {
984 bool switch_in_progress;
985 __le16 channel;
986};
987
a9e1cb6a
WYG
988/*
989 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
990 * to perform continuous uCode event logging operation if enabled
991 */
992#define UCODE_TRACE_PERIOD (100)
993
994/*
995 * iwl_event_log: current uCode event log position
996 *
997 * @ucode_trace: enable/disable ucode continuous trace timer
998 * @num_wraps: how many times the event buffer wraps
999 * @next_entry: the entry just before the next one that uCode would fill
1000 * @non_wraps_count: counter for no wrap detected when dump ucode events
1001 * @wraps_once_count: counter for wrap once detected when dump ucode events
1002 * @wraps_more_count: counter for wrap more than once detected
1003 * when dump ucode events
1004 */
1005struct iwl_event_log {
1006 bool ucode_trace;
1007 u32 num_wraps;
1008 u32 next_entry;
1009 int non_wraps_count;
1010 int wraps_once_count;
1011 int wraps_more_count;
1012};
1013
2be76703
WYG
1014/*
1015 * host interrupt timeout value
1016 * used with setting interrupt coalescing timer
1017 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1018 *
1019 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1020 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1021 */
1022#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1023#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1024#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1025#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1026#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1027#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1028
3e4fb5fa
TAN
1029/*
1030 * This is the threshold value of plcp error rate per 100mSecs. It is
1031 * used to set and check for the validity of plcp_delta.
1032 */
1033#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (0)
1034#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1035#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1036#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa
TAN
1037#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
1038
8a472da4
WYG
1039#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1040#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1041
a93e7973
WYG
1042enum iwl_reset {
1043 IWL_RF_RESET = 0,
1044 IWL_FW_RESET,
8a472da4
WYG
1045 IWL_MAX_FORCE_RESET,
1046};
1047
1048struct iwl_force_reset {
1049 int reset_request_count;
1050 int reset_success_count;
1051 int reset_reject_count;
1052 unsigned long reset_duration;
1053 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1054};
1055
c79dd5b5 1056struct iwl_priv {
5d08cd1d
CH
1057
1058 /* ieee device used by generic ieee processing code */
1059 struct ieee80211_hw *hw;
1060 struct ieee80211_channel *ieee_channels;
1061 struct ieee80211_rate *ieee_rates;
82b9a121 1062 struct iwl_cfg *cfg;
5d08cd1d
CH
1063
1064 /* temporary frame storage list */
1065 struct list_head free_frames;
1066 int frames_count;
1067
8318d78a 1068 enum ieee80211_band band;
2f301227 1069 int alloc_rxb_page;
5d08cd1d 1070
c79dd5b5 1071 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1072 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1073
8318d78a 1074 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1075
5d08cd1d 1076 /* spectrum measurement report caching */
2aa6ab86 1077 struct iwl_spectrum_notification measure_report;
5d08cd1d 1078 u8 measurement_status;
81963d68 1079
5d08cd1d
CH
1080 /* ucode beacon time */
1081 u32 ucode_beacon_time;
a13d276f 1082 int missed_beacon_threshold;
5d08cd1d 1083
3e4fb5fa
TAN
1084 /* storing the jiffies when the plcp error rate is received */
1085 unsigned long plcp_jiffies;
1086
a93e7973 1087 /* force reset */
8a472da4 1088 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1089
bb8c093b 1090 /* we allocate array of iwl4965_channel_info for NIC's valid channels.
5d08cd1d 1091 * Access via channel # using indirect index array */
bf85ea4f 1092 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1093 u8 channel_count; /* # of channels */
1094
5d08cd1d
CH
1095 /* thermal calibration */
1096 s32 temperature; /* degrees Kelvin */
1097 s32 last_temperature;
1098
7c616cba 1099 /* init calibration results */
6e21f2c1 1100 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1101
5d08cd1d 1102 /* Scan related variables */
7878a5a4 1103 unsigned long next_scan_jiffies;
5d08cd1d
CH
1104 unsigned long scan_start;
1105 unsigned long scan_pass_start;
1106 unsigned long scan_start_tsf;
805cee5b 1107 void *scan;
5d08cd1d 1108 int scan_bands;
1ecf9fc1 1109 struct cfg80211_scan_request *scan_request;
afbdd69a 1110 bool is_internal_short_scan;
76eff18b
TW
1111 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1112 u8 mgmt_tx_ant;
5d08cd1d
CH
1113
1114 /* spinlock */
1115 spinlock_t lock; /* protect general shared data */
1116 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1117 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d 1118 struct mutex mutex;
d2dfe6df 1119 struct mutex sync_cmd_mutex; /* enable serialization of sync commands */
5d08cd1d
CH
1120
1121 /* basic pci-network driver stuff */
1122 struct pci_dev *pci_dev;
1123
1124 /* pci hardware address support */
1125 void __iomem *hw_base;
b661c819
TW
1126 u32 hw_rev;
1127 u32 hw_wa_rev;
1128 u8 rev_id;
5d08cd1d
CH
1129
1130 /* uCode images, save to reload in case of failure */
b08dfd04 1131 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1132 u32 ucode_ver; /* version of ucode, copy of
1133 iwl_ucode.ver */
5d08cd1d
CH
1134 struct fw_desc ucode_code; /* runtime inst */
1135 struct fw_desc ucode_data; /* runtime data original */
1136 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1137 struct fw_desc ucode_init; /* initialization inst */
1138 struct fw_desc ucode_init_data; /* initialization data */
1139 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
1140 enum ucode_type ucode_type;
1141 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1142 char firmware_name[25];
5d08cd1d
CH
1143
1144
3195c1f3 1145 struct iwl_rxon_time_cmd rxon_timing;
5d08cd1d
CH
1146
1147 /* We declare this const so it can only be
1148 * changed via explicit cast within the
1149 * routines that actually update the physical
1150 * hardware */
c1adf9fb
GG
1151 const struct iwl_rxon_cmd active_rxon;
1152 struct iwl_rxon_cmd staging_rxon;
5d08cd1d 1153
0924e519
WYG
1154 struct iwl_switch_rxon switch_rxon;
1155
5d08cd1d
CH
1156 /* 1st responses from initialize and runtime uCode images.
1157 * 4965's initialize alive response contains some calibration data. */
885ba202
TW
1158 struct iwl_init_alive_resp card_alive_init;
1159 struct iwl_alive_resp card_alive;
5d08cd1d 1160
ab53d8af
MA
1161 unsigned long last_blink_time;
1162 u8 last_blink_rate;
1163 u8 allow_blinking;
1164 u64 led_tpt;
e932a609 1165
5d08cd1d 1166 u16 active_rate;
5d08cd1d 1167
5d08cd1d 1168 u8 assoc_station_added;
5d08cd1d 1169 u8 start_calib;
f0832f13
EG
1170 struct iwl_sensitivity_data sensitivity_data;
1171 struct iwl_chain_noise_data chain_noise_data;
5d08cd1d 1172 __le16 sensitivity_tbl[HD_TABLE_SIZE];
5d08cd1d 1173
fad95bf5 1174 struct iwl_ht_config current_ht_config;
5d08cd1d
CH
1175 u8 last_phy_res[100];
1176
5d08cd1d 1177 /* Rate scaling data */
5d08cd1d
CH
1178 u8 retry_rate;
1179
1180 wait_queue_head_t wait_command_queue;
1181
1182 int activity_timer_active;
1183
1184 /* Rx and Tx DMA processing queues */
a55360e4 1185 struct iwl_rx_queue rxq;
88804e2b 1186 struct iwl_tx_queue *txq;
5d08cd1d 1187 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1188 struct iwl_dma_ptr kw; /* keep warm address */
1189 struct iwl_dma_ptr scd_bc_tbls;
1190
5d08cd1d
CH
1191 u32 scd_base_addr; /* scheduler sram base address */
1192
1193 unsigned long status;
5d08cd1d 1194
5d08cd1d
CH
1195 int last_rx_noise; /* From beacon statistics */
1196
19758bef 1197 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1198 struct traffic_stats tx_stats;
1199 struct traffic_stats rx_stats;
19758bef 1200
a83b9141
WYG
1201 /* counts interrupts */
1202 struct isr_statistics isr_stats;
1203
5da4b55f 1204 struct iwl_power_mgr power_data;
3ad3b92a 1205 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1206
8f91aecb 1207 struct iwl_notif_statistics statistics;
92a35bda
WYG
1208#ifdef CONFIG_IWLWIFI_DEBUG
1209 struct iwl_notif_statistics accum_statistics;
e3ef2164
WYG
1210 struct iwl_notif_statistics delta_statistics;
1211 struct iwl_notif_statistics max_delta;
92a35bda 1212#endif
5d08cd1d
CH
1213
1214 /* context information */
5d08cd1d
CH
1215 u8 bssid[ETH_ALEN];
1216 u16 rts_threshold;
1217 u8 mac_addr[ETH_ALEN];
1218
1219 /*station table variables */
1220 spinlock_t sta_lock;
1221 int num_stations;
6def9761 1222 struct iwl_station_entry stations[IWL_STATION_COUNT];
6974e363
EG
1223 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1224 u8 default_wep_key;
1225 u8 key_mapping_key;
80fb47a1 1226 unsigned long ucode_key_table;
5d08cd1d 1227
e4e72fb4
JB
1228 /* queue refcounts */
1229#define IWL_MAX_HW_QUEUES 32
1230 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1231 /* for each AC */
1232 atomic_t queue_stop_count[4];
1233
5d08cd1d 1234 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1235 u8 is_open;
5d08cd1d
CH
1236
1237 u8 mac80211_registered;
5d08cd1d 1238
af6b8ee3 1239 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1240 u8 *eeprom;
0848e297 1241 int nvm_device_type;
073d3f5f 1242 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1243
05c914fe 1244 enum nl80211_iftype iw_mode;
5d08cd1d
CH
1245
1246 struct sk_buff *ibss_beacon;
1247
1248 /* Last Rx'd beacon timestamp */
3109ece1 1249 u64 timestamp;
5d08cd1d 1250 u16 beacon_int;
32bfd35d 1251 struct ieee80211_vif *vif;
5d08cd1d 1252
ee525d13
JB
1253 union {
1254#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1255 struct {
1256 void *shared_virt;
1257 dma_addr_t shared_phys;
1258
1259 struct delayed_work thermal_periodic;
1260 struct delayed_work rfkill_poll;
1261
1262 struct iwl3945_notif_statistics statistics;
1263
1264 u32 sta_supp_rates;
e99f168c
JB
1265 int last_rx_rssi; /* From Rx packet statistics */
1266
1267 /* Rx'd packet timing information */
1268 u32 last_beacon_time;
1269 u64 last_tsf;
67d613ae
JB
1270
1271 /*
1272 * each calibration channel group in the
1273 * EEPROM has a derived clip setting for
1274 * each rate.
1275 */
1276 const struct iwl3945_clip_group clip_groups[5];
1277
ee525d13 1278 } _3945;
a4c8b2a6
JB
1279#endif
1280#if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE)
1281 struct {
1282 /* INT ICT Table */
1283 __le32 *ict_tbl;
1284 void *ict_tbl_vir;
1285 dma_addr_t ict_tbl_dma;
1286 dma_addr_t aligned_ict_tbl_dma;
1287 int ict_index;
1288 u32 inta;
1289 bool use_ict;
1290 } _agn;
ee525d13
JB
1291#endif
1292 };
1293
5425e490 1294 struct iwl_hw_params hw_params;
4ddbb7d0 1295
40cefda9 1296 u32 inta_mask;
5d08cd1d
CH
1297 /* Current association information needed to configure the
1298 * hardware */
1299 u16 assoc_id;
1300 u16 assoc_capability;
5d08cd1d 1301
1ff50bda 1302 struct iwl_qos_info qos_data;
5d08cd1d
CH
1303
1304 struct workqueue_struct *workqueue;
1305
5d08cd1d 1306 struct work_struct restart;
5d08cd1d
CH
1307 struct work_struct scan_completed;
1308 struct work_struct rx_replenish;
5d08cd1d 1309 struct work_struct abort_scan;
5d08cd1d
CH
1310 struct work_struct request_scan;
1311 struct work_struct beacon_update;
a28027cd
WYG
1312 struct work_struct tt_work;
1313 struct work_struct ct_enter;
1314 struct work_struct ct_exit;
5d08cd1d
CH
1315
1316 struct tasklet_struct irq_tasklet;
1317
1318 struct delayed_work init_alive_start;
1319 struct delayed_work alive_start;
5d08cd1d 1320 struct delayed_work scan_check;
4a8a4322 1321
630fe9b6
TW
1322 /* TX Power */
1323 s8 tx_power_user_lmt;
dc1b0973 1324 s8 tx_power_device_lmt;
ae16fc3c 1325 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
5d08cd1d 1326
5d08cd1d 1327
d08853a3 1328#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1329 /* debugging info */
3d816c77
RC
1330 u32 debug_level; /* per device debugging will override global
1331 iwl_debug_level if set */
5d08cd1d
CH
1332 u32 framecnt_to_us;
1333 atomic_t restrict_refcnt;
1e4247d4 1334 bool disable_ht40;
712b6cf5
TW
1335#ifdef CONFIG_IWLWIFI_DEBUGFS
1336 /* debugfs */
20594eb0
WYG
1337 u16 tx_traffic_idx;
1338 u16 rx_traffic_idx;
1339 u8 *tx_traffic;
1340 u8 *rx_traffic;
4c84a8f1
JB
1341 struct dentry *debugfs_dir;
1342 u32 dbgfs_sram_offset, dbgfs_sram_len;
712b6cf5
TW
1343#endif /* CONFIG_IWLWIFI_DEBUGFS */
1344#endif /* CONFIG_IWLWIFI_DEBUG */
5d08cd1d
CH
1345
1346 struct work_struct txpower_work;
445c2dff
TW
1347 u32 disable_sens_cal;
1348 u32 disable_chain_noise_cal;
203566f3 1349 u32 disable_tx_power_cal;
16e727e8 1350 struct work_struct run_time_calib_work;
5d08cd1d 1351 struct timer_list statistics_periodic;
a9e1cb6a 1352 struct timer_list ucode_trace;
086ed117 1353 bool hw_ready;
a9e1cb6a
WYG
1354
1355 struct iwl_event_log event_log;
c79dd5b5 1356}; /*iwl_priv */
5d08cd1d 1357
36470749
RR
1358static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1359{
1360 set_bit(txq_id, &priv->txq_ctx_active_msk);
1361}
1362
1363static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1364{
1365 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1366}
1367
994d31f7 1368#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6 1369const char *iwl_get_tx_fail_reason(u32 status);
3d816c77
RC
1370/*
1371 * iwl_get_debug_level: Return active debug level for device
1372 *
1373 * Using sysfs it is possible to set per device debug level. This debug
1374 * level will be used if set, otherwise the global debug level which can be
1375 * set via module parameter is used.
1376 */
1377static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1378{
1379 if (priv->debug_level)
1380 return priv->debug_level;
1381 else
1382 return iwl_debug_level;
1383}
a332f8d6
TW
1384#else
1385static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; }
3d816c77
RC
1386
1387static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1388{
1389 return iwl_debug_level;
1390}
a332f8d6
TW
1391#endif
1392
1393
a332f8d6
TW
1394static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1395 int txq_id, int idx)
1396{
1397 if (priv->txq[txq_id].txb[idx].skb[0])
1398 return (struct ieee80211_hdr *)priv->txq[txq_id].
1399 txb[idx].skb[0]->data;
1400 return NULL;
1401}
a332f8d6
TW
1402
1403
3109ece1 1404static inline int iwl_is_associated(struct iwl_priv *priv)
5d08cd1d
CH
1405{
1406 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1407}
1408
bf85ea4f 1409static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1410{
1411 if (ch_info == NULL)
1412 return 0;
1413 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1414}
1415
bf85ea4f 1416static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1417{
1418 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1419}
1420
bf85ea4f 1421static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1422{
8318d78a 1423 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1424}
1425
bf85ea4f 1426static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1427{
8318d78a 1428 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1429}
1430
bf85ea4f 1431static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1432{
1433 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1434}
1435
bf85ea4f 1436static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1437{
1438 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1439}
1440
64a76b50
ZY
1441static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1442{
1443 __free_pages(page, priv->hw_params.rx_page_order);
1444 priv->alloc_rxb_page--;
1445}
1446
1447static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1448{
1449 free_pages(page, priv->hw_params.rx_page_order);
1450 priv->alloc_rxb_page--;
1451}
be1f3ab6 1452#endif /* __iwl_dev_h__ */