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iwlwifi: fix scan races
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
1f447808 5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
d43c36dc 32#include <linux/sched.h>
1d0a082d 33#include <net/mac80211.h>
df48c323 34
6bc913bd 35#include "iwl-eeprom.h"
3e0d4cb1 36#include "iwl-dev.h" /* FIXME: remove */
19335774 37#include "iwl-debug.h"
df48c323 38#include "iwl-core.h"
b661c819 39#include "iwl-io.h"
5da4b55f 40#include "iwl-power.h"
83dde8c9 41#include "iwl-sta.h"
ef850d7c 42#include "iwl-helpers.h"
df48c323 43
1d0a082d 44
df48c323
TW		 45MODULE_DESCRIPTION("iwl core");
46MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 47MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 48MODULE_LICENSE("GPL");
df48c323 49
06702a73
WYG		 50/*
51 * set bt_coex_active to true, uCode will do kill/defer
52 * every time the priority line is asserted (BT is sending signals on the
53 * priority line in the PCIx).
54 * set bt_coex_active to false, uCode will ignore the BT activity and
55 * perform the normal operation
56 *
57 * User might experience transmit issue on some platform due to WiFi/BT
58 * co-exist problem. The possible behaviors are:
59 * Able to scan and finding all the available AP
60 * Not able to associate with any AP
61 * On those platforms, WiFi communication can be restored by set
62 * "bt_coex_active" module parameter to "false"
63 *
64 * default: bt_coex_active = true (BT_COEX_ENABLE)
65 */
66static bool bt_coex_active = true;
67module_param(bt_coex_active, bool, S_IRUGO);
68MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist\n");
69
1933ac4d
WYG		 70static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
71 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
72 0, COEX_UNASSOC_IDLE_FLAGS},
73 {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
74 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
75 {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
76 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
77 {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
78 0, COEX_CALIBRATION_FLAGS},
79 {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
80 0, COEX_PERIODIC_CALIBRATION_FLAGS},
81 {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
82 0, COEX_CONNECTION_ESTAB_FLAGS},
83 {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
84 0, COEX_ASSOCIATED_IDLE_FLAGS},
85 {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
86 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
87 {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
88 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
89 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
90 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
91 {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
92 {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
93 {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
94 0, COEX_STAND_ALONE_DEBUG_FLAGS},
95 {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
96 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
97 {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
98 {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
99};
100
c7de35cd
RR		 101#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
102 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
103 IWL_RATE_SISO_##s##M_PLCP, \
104 IWL_RATE_MIMO2_##s##M_PLCP,\
105 IWL_RATE_MIMO3_##s##M_PLCP,\
106 IWL_RATE_##r##M_IEEE, \
107 IWL_RATE_##ip##M_INDEX, \
108 IWL_RATE_##in##M_INDEX, \
109 IWL_RATE_##rp##M_INDEX, \
110 IWL_RATE_##rn##M_INDEX, \
111 IWL_RATE_##pp##M_INDEX, \
112 IWL_RATE_##np##M_INDEX }
113
a562a9dd
RC		 114u32 iwl_debug_level;
115EXPORT_SYMBOL(iwl_debug_level);
116
ef850d7c
MA		 117static irqreturn_t iwl_isr(int irq, void *data);
118
c7de35cd
RR		 119/*
120 * Parameter order:
121 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
122 *
123 * If there isn't a valid next or previous rate then INV is used which
124 * maps to IWL_RATE_INVALID
125 *
126 */
1826dcc0 127const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 128 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
129 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
130 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
131 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
132 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
133 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
134 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
135 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
136 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
137 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
138 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
139 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
140 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
141 /* FIXME:RS: ^^ should be INV (legacy) */
142};
1826dcc0 143EXPORT_SYMBOL(iwl_rates);
c7de35cd 144
e7d326ac
TW		 145/**
146 * translate ucode response to mac80211 tx status control values
147 */
148void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 149 struct ieee80211_tx_info *info)
e7d326ac 150{
e6a9854b 151 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 152
e6a9854b 153 info->antenna_sel_tx =
e7d326ac
TW		 154 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
155 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 156 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 157 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 158 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
7aafef1c 159 if (rate_n_flags & RATE_MCS_HT40_MSK)
e6a9854b 160 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 161 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 162 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 163 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 164 r->flags |= IEEE80211_TX_RC_SHORT_GI;
31513be8 165 r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
e7d326ac
TW		 166}
167EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
168
169int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
170{
171 int idx = 0;
172
173 /* HT rate format */
174 if (rate_n_flags & RATE_MCS_HT_MSK) {
175 idx = (rate_n_flags & 0xff);
176
60d32215
DH		 177 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
178 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
179 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 180 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
181
182 idx += IWL_FIRST_OFDM_RATE;
183 /* skip 9M not supported in ht*/
184 if (idx >= IWL_RATE_9M_INDEX)
185 idx += 1;
186 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
187 return idx;
188
189 /* legacy rate format, search for match in table */
190 } else {
191 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
192 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
193 return idx;
194 }
195
196 return -1;
197}
198EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
199
31513be8
DH		 200int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
201{
202 int idx = 0;
203 int band_offset = 0;
204
205 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
206 if (rate_n_flags & RATE_MCS_HT_MSK) {
207 idx = (rate_n_flags & 0xff);
208 return idx;
209 /* Legacy rate format, search for match in table */
210 } else {
211 if (band == IEEE80211_BAND_5GHZ)
212 band_offset = IWL_FIRST_OFDM_RATE;
213 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
214 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
215 return idx - band_offset;
216 }
217
218 return -1;
219}
220
76eff18b
TW		 221u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
222{
223 int i;
224 u8 ind = ant;
225 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
226 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
227 if (priv->hw_params.valid_tx_ant & BIT(ind))
228 return ind;
229 }
230 return ant;
231}
47ff65c4 232EXPORT_SYMBOL(iwl_toggle_tx_ant);
57bd1bea
TW		 233
234const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
235EXPORT_SYMBOL(iwl_bcast_addr);
236
237
1d0a082d
AK		 238/* This function both allocates and initializes hw and priv. */
239struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
240 struct ieee80211_ops *hw_ops)
241{
242 struct iwl_priv *priv;
243
244 /* mac80211 allocates memory for this device instance, including
245 * space for this driver's private structure */
246 struct ieee80211_hw *hw =
247 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
248 if (hw == NULL) {
a3139c59
SO		 249 printk(KERN_ERR "%s: Can not allocate network device\n",
250 cfg->name);
1d0a082d
AK		 251 goto out;
252 }
253
254 priv = hw->priv;
255 priv->hw = hw;
256
257out:
258 return hw;
259}
260EXPORT_SYMBOL(iwl_alloc_all);
261
b661c819
TW		 262void iwl_hw_detect(struct iwl_priv *priv)
263{
264 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
265 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
266 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
267}
268EXPORT_SYMBOL(iwl_hw_detect);
269
1053d35f
RR		 270int iwl_hw_nic_init(struct iwl_priv *priv)
271{
272 unsigned long flags;
273 struct iwl_rx_queue *rxq = &priv->rxq;
274 int ret;
275
276 /* nic_init */
1053d35f 277 spin_lock_irqsave(&priv->lock, flags);
1b73af82 278 priv->cfg->ops->lib->apm_ops.init(priv);
74ba67ed 279
2be76703
WYG		 280 /* Set interrupt coalescing calibration timer to default (512 usecs) */
281 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
74ba67ed 282
1053d35f
RR		 283 spin_unlock_irqrestore(&priv->lock, flags);
284
285 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
286
287 priv->cfg->ops->lib->apm_ops.config(priv);
288
289 /* Allocate the RX queue, or reset if it is already allocated */
290 if (!rxq->bd) {
291 ret = iwl_rx_queue_alloc(priv);
292 if (ret) {
15b1687c 293 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 294 return -ENOMEM;
295 }
296 } else
297 iwl_rx_queue_reset(priv, rxq);
298
299 iwl_rx_replenish(priv);
300
301 iwl_rx_init(priv, rxq);
302
303 spin_lock_irqsave(&priv->lock, flags);
304
305 rxq->need_update = 1;
306 iwl_rx_queue_update_write_ptr(priv, rxq);
307
308 spin_unlock_irqrestore(&priv->lock, flags);
309
de0f60ea
ZY		 310 /* Allocate or reset and init all Tx and Command queues */
311 if (!priv->txq) {
312 ret = iwl_txq_ctx_alloc(priv);
313 if (ret)
314 return ret;
315 } else
316 iwl_txq_ctx_reset(priv);
1053d35f
RR		 317
318 set_bit(STATUS_INIT, &priv->status);
319
320 return 0;
321}
322EXPORT_SYMBOL(iwl_hw_nic_init);
323
14d2aac5
AK		 324/*
325 * QoS support
326*/
327void iwl_activate_qos(struct iwl_priv *priv, u8 force)
328{
329 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
330 return;
331
332 priv->qos_data.def_qos_parm.qos_flags = 0;
333
334 if (priv->qos_data.qos_cap.q_AP.queue_request &&
335 !priv->qos_data.qos_cap.q_AP.txop_request)
336 priv->qos_data.def_qos_parm.qos_flags |=
337 QOS_PARAM_FLG_TXOP_TYPE_MSK;
338 if (priv->qos_data.qos_active)
339 priv->qos_data.def_qos_parm.qos_flags |=
340 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
341
342 if (priv->current_ht_config.is_ht)
343 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
344
345 if (force || iwl_is_associated(priv)) {
346 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
347 priv->qos_data.qos_active,
348 priv->qos_data.def_qos_parm.qos_flags);
349
350 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
351 sizeof(struct iwl_qosparam_cmd),
352 &priv->qos_data.def_qos_parm, NULL);
353 }
354}
355EXPORT_SYMBOL(iwl_activate_qos);
356
f2c95b04
WYG		 357/*
358 * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
359 * (802.11b) (802.11a/g)
360 * AC_BK 15 1023 7 0 0
361 * AC_BE 15 1023 3 0 0
362 * AC_VI 7 15 2 6.016ms 3.008ms
363 * AC_VO 3 7 2 3.264ms 1.504ms
364 */
c7de35cd 365void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 366{
367 u16 cw_min = 15;
368 u16 cw_max = 1023;
369 u8 aifs = 2;
30dab79e 370 bool is_legacy = false;
bf85ea4f
AK		 371 unsigned long flags;
372 int i;
373
374 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 375 /* QoS always active in AP and ADHOC mode
376 * In STA mode wait for association
377 */
378 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
379 priv->iw_mode == NL80211_IFTYPE_AP)
380 priv->qos_data.qos_active = 1;
381 else
382 priv->qos_data.qos_active = 0;
bf85ea4f 383
30dab79e
WT		 384 /* check for legacy mode */
385 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
386 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
387 (priv->iw_mode == NL80211_IFTYPE_STATION &&
388 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 389 cw_min = 31;
390 is_legacy = 1;
391 }
392
393 if (priv->qos_data.qos_active)
394 aifs = 3;
395
f2c95b04 396 /* AC_BE */
bf85ea4f
AK		 397 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
398 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
399 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
400 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
401 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
402
403 if (priv->qos_data.qos_active) {
f2c95b04 404 /* AC_BK */
bf85ea4f
AK		 405 i = 1;
406 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
407 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
408 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
409 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
410 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
411
f2c95b04 412 /* AC_VI */
bf85ea4f
AK		 413 i = 2;
414 priv->qos_data.def_qos_parm.ac[i].cw_min =
415 cpu_to_le16((cw_min + 1) / 2 - 1);
416 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 417 cpu_to_le16(cw_min);
bf85ea4f
AK		 418 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
419 if (is_legacy)
420 priv->qos_data.def_qos_parm.ac[i].edca_txop =
421 cpu_to_le16(6016);
422 else
423 priv->qos_data.def_qos_parm.ac[i].edca_txop =
424 cpu_to_le16(3008);
425 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
426
f2c95b04 427 /* AC_VO */
bf85ea4f
AK		 428 i = 3;
429 priv->qos_data.def_qos_parm.ac[i].cw_min =
430 cpu_to_le16((cw_min + 1) / 4 - 1);
431 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 432 cpu_to_le16((cw_min + 1) / 2 - 1);
bf85ea4f
AK		 433 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
434 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
435 if (is_legacy)
436 priv->qos_data.def_qos_parm.ac[i].edca_txop =
437 cpu_to_le16(3264);
438 else
439 priv->qos_data.def_qos_parm.ac[i].edca_txop =
440 cpu_to_le16(1504);
441 } else {
442 for (i = 1; i < 4; i++) {
443 priv->qos_data.def_qos_parm.ac[i].cw_min =
444 cpu_to_le16(cw_min);
445 priv->qos_data.def_qos_parm.ac[i].cw_max =
446 cpu_to_le16(cw_max);
447 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
448 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
449 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
450 }
451 }
e1623446 452 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 453
454 spin_unlock_irqrestore(&priv->lock, flags);
455}
c7de35cd
RR		 456EXPORT_SYMBOL(iwl_reset_qos);
457
d9fe60de
JB		 458#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
459#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 460static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 461 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 462 enum ieee80211_band band)
463{
39130df3
RR		 464 u16 max_bit_rate = 0;
465 u8 rx_chains_num = priv->hw_params.rx_chains_num;
466 u8 tx_chains_num = priv->hw_params.tx_chains_num;
467
c7de35cd 468 ht_info->cap = 0;
d9fe60de 469 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 470
d9fe60de 471 ht_info->ht_supported = true;
c7de35cd 472
b261793d
DH		 473 if (priv->cfg->ht_greenfield_support)
474 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
d9fe60de 475 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
39130df3 476 max_bit_rate = MAX_BIT_RATE_20_MHZ;
7aafef1c 477 if (priv->hw_params.ht40_channel & BIT(band)) {
d9fe60de
JB		 478 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
479 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
480 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 481 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 482 }
c7de35cd
RR		 483
484 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 485 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 486
487 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
488 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
489
d9fe60de 490 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 491 if (rx_chains_num >= 2)
d9fe60de 492 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 493 if (rx_chains_num >= 3)
d9fe60de 494 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 495
496 /* Highest supported Rx data rate */
497 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 498 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
499 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 500
501 /* Tx MCS capabilities */
d9fe60de 502 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 503 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 504 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
505 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
506 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 507 }
c7de35cd 508}
c7de35cd 509
c7de35cd
RR		 510/**
511 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
512 */
534166de 513int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 514{
515 struct iwl_channel_info *ch;
516 struct ieee80211_supported_band *sband;
517 struct ieee80211_channel *channels;
518 struct ieee80211_channel *geo_ch;
519 struct ieee80211_rate *rates;
520 int i = 0;
521
522 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
523 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 524 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 525 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
526 return 0;
527 }
528
529 channels = kzalloc(sizeof(struct ieee80211_channel) *
530 priv->channel_count, GFP_KERNEL);
531 if (!channels)
532 return -ENOMEM;
533
5027309b 534 rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
c7de35cd
RR		 535 GFP_KERNEL);
536 if (!rates) {
537 kfree(channels);
538 return -ENOMEM;
539 }
540
541 /* 5.2GHz channels start after the 2.4GHz channels */
542 sband = &priv->bands[IEEE80211_BAND_5GHZ];
543 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
544 /* just OFDM */
545 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5027309b 546 sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
c7de35cd 547
49779293 548 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 549 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 550 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 551
552 sband = &priv->bands[IEEE80211_BAND_2GHZ];
553 sband->channels = channels;
554 /* OFDM & CCK */
555 sband->bitrates = rates;
5027309b 556 sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
c7de35cd 557
49779293 558 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 559 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 560 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 561
562 priv->ieee_channels = channels;
563 priv->ieee_rates = rates;
564
c7de35cd
RR		 565 for (i = 0; i < priv->channel_count; i++) {
566 ch = &priv->channel_info[i];
567
568 /* FIXME: might be removed if scan is OK */
569 if (!is_channel_valid(ch))
570 continue;
571
572 if (is_channel_a_band(ch))
573 sband = &priv->bands[IEEE80211_BAND_5GHZ];
574 else
575 sband = &priv->bands[IEEE80211_BAND_2GHZ];
576
577 geo_ch = &sband->channels[sband->n_channels++];
578
579 geo_ch->center_freq =
580 ieee80211_channel_to_frequency(ch->channel);
581 geo_ch->max_power = ch->max_power_avg;
582 geo_ch->max_antenna_gain = 0xff;
583 geo_ch->hw_value = ch->channel;
584
585 if (is_channel_valid(ch)) {
586 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
587 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
588
589 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
590 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
591
592 if (ch->flags & EEPROM_CHANNEL_RADAR)
593 geo_ch->flags |= IEEE80211_CHAN_RADAR;
594
7aafef1c 595 geo_ch->flags |= ch->ht40_extension_channel;
4d38c2e8 596
dc1b0973
WYG		 597 if (ch->max_power_avg > priv->tx_power_device_lmt)
598 priv->tx_power_device_lmt = ch->max_power_avg;
c7de35cd
RR		 599 } else {
600 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
601 }
602
e1623446 603 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 604 ch->channel, geo_ch->center_freq,
605 is_channel_a_band(ch) ? "5.2" : "2.4",
606 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
607 "restricted" : "valid",
608 geo_ch->flags);
609 }
610
611 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
612 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 613 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
614 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 615 priv->pci_dev->device,
616 priv->pci_dev->subsystem_device);
c7de35cd
RR		 617 priv->cfg->sku &= ~IWL_SKU_A;
618 }
619
978785a3 620 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 621 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
622 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 623
624 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
625
626 return 0;
627}
534166de 628EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 629
630/*
631 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
632 */
534166de 633void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 634{
635 kfree(priv->ieee_channels);
636 kfree(priv->ieee_rates);
637 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
638}
534166de 639EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 640
37dc70fe
AK		 641/*
642 * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
643 * function.
644 */
645void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
646 __le32 *tx_flags)
647{
648 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
649 *tx_flags |= TX_CMD_FLG_RTS_MSK;
650 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
651 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
652 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
653 *tx_flags |= TX_CMD_FLG_CTS_MSK;
654 }
655}
656EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
657
28a6b07a 658static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd 659{
ba37a3d0 660 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
02bb1bea 661 priv->current_ht_config.single_chain_sufficient;
c7de35cd 662}
963f5517 663
47c5196e
TW		 664static u8 iwl_is_channel_extension(struct iwl_priv *priv,
665 enum ieee80211_band band,
666 u16 channel, u8 extension_chan_offset)
667{
668 const struct iwl_channel_info *ch_info;
669
670 ch_info = iwl_get_channel_info(priv, band, channel);
671 if (!is_channel_valid(ch_info))
672 return 0;
673
d9fe60de 674 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
7aafef1c 675 return !(ch_info->ht40_extension_channel &
689da1b3 676 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 677 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
7aafef1c 678 return !(ch_info->ht40_extension_channel &
689da1b3 679 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e
TW		 680
681 return 0;
682}
683
7aafef1c 684u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
d9fe60de 685 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e 686{
fad95bf5 687 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
47c5196e 688
fad95bf5 689 if (!ht_conf->is_ht || !ht_conf->is_40mhz)
47c5196e
TW		 690 return 0;
691
a2b0f02e
WYG		 692 /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
693 * the bit will not set if it is pure 40MHz case
694 */
47c5196e 695 if (sta_ht_inf) {
a2b0f02e 696 if (!sta_ht_inf->ht_supported)
47c5196e
TW		 697 return 0;
698 }
1e4247d4
WYG		 699#ifdef CONFIG_IWLWIFI_DEBUG
700 if (priv->disable_ht40)
701 return 0;
702#endif
611d3eb7
WYG		 703 return iwl_is_channel_extension(priv, priv->band,
704 le16_to_cpu(priv->staging_rxon.channel),
fad95bf5 705 ht_conf->extension_chan_offset);
47c5196e 706}
7aafef1c 707EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
47c5196e 708
2c2f3b33
TW		 709static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
710{
711 u16 new_val = 0;
712 u16 beacon_factor = 0;
713
714 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
715 new_val = beacon_val / beacon_factor;
716
717 if (!new_val)
718 new_val = max_beacon_val;
719
720 return new_val;
721}
722
723void iwl_setup_rxon_timing(struct iwl_priv *priv)
724{
725 u64 tsf;
726 s32 interval_tm, rem;
727 unsigned long flags;
728 struct ieee80211_conf *conf = NULL;
729 u16 beacon_int;
730
731 conf = ieee80211_get_hw_conf(priv->hw);
732
733 spin_lock_irqsave(&priv->lock, flags);
734 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
735 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
736
737 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
738 beacon_int = priv->beacon_int;
739 priv->rxon_timing.atim_window = 0;
740 } else {
741 beacon_int = priv->vif->bss_conf.beacon_int;
742
743 /* TODO: we need to get atim_window from upper stack
744 * for now we set to 0 */
745 priv->rxon_timing.atim_window = 0;
746 }
747
748 beacon_int = iwl_adjust_beacon_interval(beacon_int,
749 priv->hw_params.max_beacon_itrvl * 1024);
750 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
751
752 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
753 interval_tm = beacon_int * 1024;
754 rem = do_div(tsf, interval_tm);
755 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
756
757 spin_unlock_irqrestore(&priv->lock, flags);
758 IWL_DEBUG_ASSOC(priv,
759 "beacon interval %d beacon timer %d beacon tim %d\n",
760 le16_to_cpu(priv->rxon_timing.beacon_interval),
761 le32_to_cpu(priv->rxon_timing.beacon_init_val),
762 le16_to_cpu(priv->rxon_timing.atim_window));
763}
764EXPORT_SYMBOL(iwl_setup_rxon_timing);
765
8ccde88a
SO		 766void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
767{
768 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
769
770 if (hw_decrypt)
771 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
772 else
773 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
774
775}
776EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
777
778/**
779 * iwl_check_rxon_cmd - validate RXON structure is valid
780 *
781 * NOTE: This is really only useful during development and can eventually
782 * be #ifdef'd out once the driver is stable and folks aren't actively
783 * making changes
784 */
785int iwl_check_rxon_cmd(struct iwl_priv *priv)
786{
787 int error = 0;
788 int counter = 1;
789 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
790
791 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
792 error |= le32_to_cpu(rxon->flags &
793 (RXON_FLG_TGJ_NARROW_BAND_MSK |
794 RXON_FLG_RADAR_DETECT_MSK));
795 if (error)
796 IWL_WARN(priv, "check 24G fields %d | %d\n",
797 counter++, error);
798 } else {
799 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
800 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
801 if (error)
802 IWL_WARN(priv, "check 52 fields %d | %d\n",
803 counter++, error);
804 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
805 if (error)
806 IWL_WARN(priv, "check 52 CCK %d | %d\n",
807 counter++, error);
808 }
809 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
810 if (error)
811 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
812
813 /* make sure basic rates 6Mbps and 1Mbps are supported */
814 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
815 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
816 if (error)
817 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
818
819 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
820 if (error)
821 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
822
823 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
824 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
825 if (error)
826 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
827 counter++, error);
828
829 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
830 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
831 if (error)
832 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
833 counter++, error);
834
835 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
836 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
837 if (error)
838 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
839 counter++, error);
840
841 if (error)
842 IWL_WARN(priv, "Tuning to channel %d\n",
843 le16_to_cpu(rxon->channel));
844
845 if (error) {
846 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
847 return -1;
848 }
849 return 0;
850}
851EXPORT_SYMBOL(iwl_check_rxon_cmd);
852
853/**
854 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
855 * @priv: staging_rxon is compared to active_rxon
856 *
857 * If the RXON structure is changing enough to require a new tune,
858 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
859 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
860 */
861int iwl_full_rxon_required(struct iwl_priv *priv)
862{
863
864 /* These items are only settable from the full RXON command */
865 if (!(iwl_is_associated(priv)) ||
866 compare_ether_addr(priv->staging_rxon.bssid_addr,
867 priv->active_rxon.bssid_addr) ||
868 compare_ether_addr(priv->staging_rxon.node_addr,
869 priv->active_rxon.node_addr) ||
870 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
871 priv->active_rxon.wlap_bssid_addr) ||
872 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
873 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
874 (priv->staging_rxon.air_propagation !=
875 priv->active_rxon.air_propagation) ||
876 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
877 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
878 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
879 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
c2105fa7
DH		 880 (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
881 priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
8ccde88a
SO		 882 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
883 return 1;
884
885 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
886 * be updated with the RXON_ASSOC command -- however only some
887 * flag transitions are allowed using RXON_ASSOC */
888
889 /* Check if we are not switching bands */
890 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
891 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
892 return 1;
893
894 /* Check if we are switching association toggle */
895 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
896 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
897 return 1;
898
899 return 0;
900}
901EXPORT_SYMBOL(iwl_full_rxon_required);
902
903u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
904{
905 int i;
906 int rate_mask;
907
908 /* Set rate mask*/
909 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
910 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
911 else
912 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
913
914 /* Find lowest valid rate */
915 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
916 i = iwl_rates[i].next_ieee) {
917 if (rate_mask & (1 << i))
918 return iwl_rates[i].plcp;
919 }
920
921 /* No valid rate was found. Assign the lowest one */
922 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
923 return IWL_RATE_1M_PLCP;
924 else
925 return IWL_RATE_6M_PLCP;
926}
927EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
928
fad95bf5 929void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
47c5196e 930{
c1adf9fb 931 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e 932
fad95bf5 933 if (!ht_conf->is_ht) {
a2b0f02e 934 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64 935 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
7aafef1c 936 RXON_FLG_HT40_PROT_MSK |
42eb7c64 937 RXON_FLG_HT_PROT_MSK);
47c5196e 938 return;
42eb7c64 939 }
47c5196e 940
a2b0f02e
WYG		 941 /* FIXME: if the definition of ht_protection changed, the "translation"
942 * will be needed for rxon->flags
943 */
fad95bf5 944 rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
a2b0f02e
WYG		 945
946 /* Set up channel bandwidth:
7aafef1c 947 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
a2b0f02e
WYG		 948 /* clear the HT channel mode before set the mode */
949 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
950 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
7aafef1c
WYG		 951 if (iwl_is_ht40_tx_allowed(priv, NULL)) {
952 /* pure ht40 */
fad95bf5 953 if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
a2b0f02e 954 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
508b08e7 955 /* Note: control channel is opposite of extension channel */
fad95bf5 956 switch (ht_conf->extension_chan_offset) {
508b08e7
WYG		 957 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
958 rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
959 break;
960 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
961 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
962 break;
963 }
964 } else {
a2b0f02e 965 /* Note: control channel is opposite of extension channel */
fad95bf5 966 switch (ht_conf->extension_chan_offset) {
a2b0f02e
WYG		 967 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
968 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
969 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
970 break;
971 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
972 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
973 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
974 break;
975 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
976 default:
977 /* channel location only valid if in Mixed mode */
978 IWL_ERR(priv, "invalid extension channel offset\n");
979 break;
980 }
981 }
982 } else {
983 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 984 }
985
45823531
AK		 986 if (priv->cfg->ops->hcmd->set_rxon_chain)
987 priv->cfg->ops->hcmd->set_rxon_chain(priv);
47c5196e 988
02bb1bea 989 IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
ae5eb026 990 "extension channel offset 0x%x\n",
fad95bf5
JB		 991 le32_to_cpu(rxon->flags), ht_conf->ht_protection,
992 ht_conf->extension_chan_offset);
47c5196e
TW		 993 return;
994}
995EXPORT_SYMBOL(iwl_set_rxon_ht);
996
9e5e6c32
TW		 997#define IWL_NUM_RX_CHAINS_MULTIPLE 3
998#define IWL_NUM_RX_CHAINS_SINGLE 2
999#define IWL_NUM_IDLE_CHAINS_DUAL 2
1000#define IWL_NUM_IDLE_CHAINS_SINGLE 1
1001
2b396a12
JB		 1002/*
1003 * Determine how many receiver/antenna chains to use.
1004 *
1005 * More provides better reception via diversity. Fewer saves power
1006 * at the expense of throughput, but only when not in powersave to
1007 * start with.
1008 *
c7de35cd
RR		 1009 * MIMO (dual stream) requires at least 2, but works better with 3.
1010 * This does not determine *which* chains to use, just how many.
1011 */
28a6b07a 1012static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 1013{
c7de35cd 1014 /* # of Rx chains to use when expecting MIMO. */
02bb1bea 1015 if (is_single_rx_stream(priv))
9e5e6c32 1016 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 1017 else
9e5e6c32 1018 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 1019}
c7de35cd 1020
2b396a12 1021/*
3f3e0376
WYG		 1022 * When we are in power saving mode, unless device support spatial
1023 * multiplexing power save, use the active count for rx chain count.
2b396a12 1024 */
28a6b07a
TW		 1025static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
1026{
ba37a3d0
JB		 1027 /* # Rx chains when idling, depending on SMPS mode */
1028 switch (priv->current_ht_config.smps) {
1029 case IEEE80211_SMPS_STATIC:
1030 case IEEE80211_SMPS_DYNAMIC:
1031 return IWL_NUM_IDLE_CHAINS_SINGLE;
1032 case IEEE80211_SMPS_OFF:
1033 return active_cnt;
c15d20c1 1034 default:
ba37a3d0
JB		 1035 WARN(1, "invalid SMPS mode %d",
1036 priv->current_ht_config.smps);
1037 return active_cnt;
3f3e0376 1038 }
c7de35cd
RR		 1039}
1040
04816448
GE		 1041/* up to 4 chains */
1042static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
1043{
1044 u8 res;
1045 res = (chain_bitmap & BIT(0)) >> 0;
1046 res += (chain_bitmap & BIT(1)) >> 1;
1047 res += (chain_bitmap & BIT(2)) >> 2;
9bddbab3 1048 res += (chain_bitmap & BIT(3)) >> 3;
04816448
GE		 1049 return res;
1050}
1051
4c4df78f
CR		 1052/**
1053 * iwl_is_monitor_mode - Determine if interface in monitor mode
1054 *
1055 * priv->iw_mode is set in add_interface, but add_interface is
1056 * never called for monitor mode. The only way mac80211 informs us about
1057 * monitor mode is through configuring filters (call to configure_filter).
1058 */
279b05d4 1059bool iwl_is_monitor_mode(struct iwl_priv *priv)
4c4df78f
CR		 1060{
1061 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
1062}
279b05d4 1063EXPORT_SYMBOL(iwl_is_monitor_mode);
4c4df78f 1064
c7de35cd
RR		 1065/**
1066 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1067 *
1068 * Selects how many and which Rx receivers/antennas/chains to use.
1069 * This should not be used for scan command ... it puts data in wrong place.
1070 */
1071void iwl_set_rxon_chain(struct iwl_priv *priv)
1072{
28a6b07a
TW		 1073 bool is_single = is_single_rx_stream(priv);
1074 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 1075 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1076 u32 active_chains;
28a6b07a 1077 u16 rx_chain;
c7de35cd
RR		 1078
1079 /* Tell uCode which antennas are actually connected.
1080 * Before first association, we assume all antennas are connected.
1081 * Just after first association, iwl_chain_noise_calibration()
1082 * checks which antennas actually *are* connected. */
04816448
GE		 1083 if (priv->chain_noise_data.active_chains)
1084 active_chains = priv->chain_noise_data.active_chains;
1085 else
1086 active_chains = priv->hw_params.valid_rx_ant;
1087
1088 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 1089
1090 /* How many receivers should we use? */
28a6b07a
TW		 1091 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
1092 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
1093
28a6b07a 1094
04816448
GE		 1095 /* correct rx chain count according hw settings
1096 * and chain noise calibration
1097 */
1098 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
1099 if (valid_rx_cnt < active_rx_cnt)
1100 active_rx_cnt = valid_rx_cnt;
1101
1102 if (valid_rx_cnt < idle_rx_cnt)
1103 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 1104
1105 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1106 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1107
7b841727
RF		 1108 /* copied from 'iwl_bg_request_scan()' */
1109 /* Force use of chains B and C (0x6) for Rx for 4965
1110 * Avoid A (0x1) because of its off-channel reception on A-band.
1111 * MIMO is not used here, but value is required */
1112 if (iwl_is_monitor_mode(priv) &&
1113 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
1114 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
fff7a434
WYG		 1115 rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
1116 rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
1117 rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1118 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
7b841727
RF		 1119 }
1120
28a6b07a
TW		 1121 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
1122
9e5e6c32 1123 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 1124 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1125 else
1126 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1127
e1623446 1128 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 1129 priv->staging_rxon.rx_chain,
1130 active_rx_cnt, idle_rx_cnt);
1131
1132 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1133 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 1134}
1135EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 1136
1137/**
17e72782 1138 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 1139 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
1140 * @channel: Any channel valid for the requested phymode
1141
1142 * In addition to setting the staging RXON, priv->phymode is also set.
1143 *
1144 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
1145 * in the staging RXON flag structure based on the phymode
1146 */
17e72782 1147int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 1148{
17e72782
TW		 1149 enum ieee80211_band band = ch->band;
1150 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
1151
8622e705 1152 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 1153 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 1154 channel, band);
1155 return -EINVAL;
1156 }
1157
1158 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1159 (priv->band == band))
1160 return 0;
1161
1162 priv->staging_rxon.channel = cpu_to_le16(channel);
1163 if (band == IEEE80211_BAND_5GHZ)
1164 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1165 else
1166 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1167
1168 priv->band = band;
1169
e1623446 1170 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1171
1172 return 0;
1173}
c7de35cd 1174EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1175
8ccde88a
SO		 1176void iwl_set_flags_for_band(struct iwl_priv *priv,
1177 enum ieee80211_band band)
1178{
1179 if (band == IEEE80211_BAND_5GHZ) {
1180 priv->staging_rxon.flags &=
1181 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1182 | RXON_FLG_CCK_MSK);
1183 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1184 } else {
1185 /* Copied from iwl_post_associate() */
1186 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1187 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1188 else
1189 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1190
1191 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1192 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1193
1194 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1195 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1196 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1197 }
1198}
8ccde88a
SO		 1199
1200/*
1201 * initialize rxon structure with default values from eeprom
1202 */
1203void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1204{
1205 const struct iwl_channel_info *ch_info;
1206
1207 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1208
1209 switch (mode) {
1210 case NL80211_IFTYPE_AP:
1211 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1212 break;
1213
1214 case NL80211_IFTYPE_STATION:
1215 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1216 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1217 break;
1218
1219 case NL80211_IFTYPE_ADHOC:
1220 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1221 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1222 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1223 RXON_FILTER_ACCEPT_GRP_MSK;
1224 break;
1225
8ccde88a
SO		 1226 default:
1227 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1228 break;
1229 }
1230
1231#if 0
1232 /* TODO: Figure out when short_preamble would be set and cache from
1233 * that */
1234 if (!hw_to_local(priv->hw)->short_preamble)
1235 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1236 else
1237 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1238#endif
1239
1240 ch_info = iwl_get_channel_info(priv, priv->band,
1241 le16_to_cpu(priv->active_rxon.channel));
1242
1243 if (!ch_info)
1244 ch_info = &priv->channel_info[0];
1245
1246 /*
1247 * in some case A channels are all non IBSS
1248 * in this case force B/G channel
1249 */
1250 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1251 !(is_channel_ibss(ch_info)))
1252 ch_info = &priv->channel_info[0];
1253
1254 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1255 priv->band = ch_info->band;
1256
1257 iwl_set_flags_for_band(priv, priv->band);
1258
1259 priv->staging_rxon.ofdm_basic_rates =
1260 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1261 priv->staging_rxon.cck_basic_rates =
1262 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1263
a2b0f02e
WYG		 1264 /* clear both MIX and PURE40 mode flag */
1265 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
1266 RXON_FLG_CHANNEL_MODE_PURE_40);
8ccde88a
SO		 1267 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1268 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1269 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1270 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1271 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1272}
1273EXPORT_SYMBOL(iwl_connection_init_rx_config);
1274
782571f4 1275static void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 1276{
1277 const struct ieee80211_supported_band *hw = NULL;
1278 struct ieee80211_rate *rate;
1279 int i;
1280
1281 hw = iwl_get_hw_mode(priv, priv->band);
1282 if (!hw) {
1283 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1284 return;
1285 }
1286
1287 priv->active_rate = 0;
1288 priv->active_rate_basic = 0;
1289
1290 for (i = 0; i < hw->n_bitrates; i++) {
1291 rate = &(hw->bitrates[i]);
5027309b 1292 if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
8ccde88a
SO		 1293 priv->active_rate |= (1 << rate->hw_value);
1294 }
1295
e1623446 1296 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1297 priv->active_rate, priv->active_rate_basic);
1298
1299 /*
1300 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1301 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1302 * OFDM
1303 */
1304 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1305 priv->staging_rxon.cck_basic_rates =
1306 ((priv->active_rate_basic &
1307 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1308 else
1309 priv->staging_rxon.cck_basic_rates =
1310 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1311
1312 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1313 priv->staging_rxon.ofdm_basic_rates =
1314 ((priv->active_rate_basic &
1315 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1316 IWL_FIRST_OFDM_RATE) & 0xFF;
1317 else
1318 priv->staging_rxon.ofdm_basic_rates =
1319 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1320}
8ccde88a
SO		 1321
1322void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1323{
2f301227 1324 struct iwl_rx_packet *pkt = rxb_addr(rxb);
8ccde88a
SO		 1325 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1326 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
4a56e965 1327
0924e519
WYG		 1328 if (priv->switch_rxon.switch_in_progress) {
1329 if (!le32_to_cpu(csa->status) &&
1330 (csa->channel == priv->switch_rxon.channel)) {
1331 rxon->channel = csa->channel;
1332 priv->staging_rxon.channel = csa->channel;
1333 IWL_DEBUG_11H(priv, "CSA notif: channel %d\n",
1334 le16_to_cpu(csa->channel));
1335 } else
1336 IWL_ERR(priv, "CSA notif (fail) : channel %d\n",
1337 le16_to_cpu(csa->channel));
1338
1339 priv->switch_rxon.switch_in_progress = false;
1340 }
8ccde88a
SO		 1341}
1342EXPORT_SYMBOL(iwl_rx_csa);
1343
1344#ifdef CONFIG_IWLWIFI_DEBUG
a643565e 1345void iwl_print_rx_config_cmd(struct iwl_priv *priv)
8ccde88a
SO		 1346{
1347 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1348
e1623446 1349 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
3d816c77 1350 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1351 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1352 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1353 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1354 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1355 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1356 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1357 rxon->ofdm_basic_rates);
e1623446
TW		 1358 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1359 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1360 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1361 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a 1362}
a643565e 1363EXPORT_SYMBOL(iwl_print_rx_config_cmd);
6686d17e 1364#endif
8ccde88a
SO		 1365/**
1366 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1367 */
1368void iwl_irq_handle_error(struct iwl_priv *priv)
1369{
1370 /* Set the FW error flag -- cleared on iwl_down */
1371 set_bit(STATUS_FW_ERROR, &priv->status);
1372
1373 /* Cancel currently queued command. */
1374 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1375
3a3ff72c 1376 priv->cfg->ops->lib->dump_nic_error_log(priv);
696bdee3
WYG		 1377 if (priv->cfg->ops->lib->dump_csr)
1378 priv->cfg->ops->lib->dump_csr(priv);
1b3eb823
WYG		 1379 if (priv->cfg->ops->lib->dump_fh)
1380 priv->cfg->ops->lib->dump_fh(priv, NULL, false);
b03d7d0f 1381 priv->cfg->ops->lib->dump_nic_event_log(priv, false, NULL, false);
8ccde88a 1382#ifdef CONFIG_IWLWIFI_DEBUG
c341ddb2 1383 if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS)
8ccde88a 1384 iwl_print_rx_config_cmd(priv);
8ccde88a
SO		 1385#endif
1386
1387 wake_up_interruptible(&priv->wait_command_queue);
1388
1389 /* Keep the restart process from trying to send host
1390 * commands by clearing the INIT status bit */
1391 clear_bit(STATUS_READY, &priv->status);
1392
1393 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1394 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1395 "Restarting adapter due to uCode error.\n");
1396
8ccde88a
SO		 1397 if (priv->cfg->mod_params->restart_fw)
1398 queue_work(priv->workqueue, &priv->restart);
1399 }
1400}
1401EXPORT_SYMBOL(iwl_irq_handle_error);
1402
d68b603c
AK		 1403int iwl_apm_stop_master(struct iwl_priv *priv)
1404{
5220af0c 1405 int ret = 0;
d68b603c 1406
5220af0c 1407 /* stop device's busmaster DMA activity */
d68b603c
AK		 1408 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1409
5220af0c 1410 ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
d68b603c 1411 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
5220af0c
BC		 1412 if (ret)
1413 IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
d68b603c 1414
d68b603c
AK		 1415 IWL_DEBUG_INFO(priv, "stop master\n");
1416
5220af0c 1417 return ret;
d68b603c
AK		 1418}
1419EXPORT_SYMBOL(iwl_apm_stop_master);
1420
1421void iwl_apm_stop(struct iwl_priv *priv)
1422{
fadb3582
BC		 1423 IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
1424
5220af0c 1425 /* Stop device's DMA activity */
d68b603c
AK		 1426 iwl_apm_stop_master(priv);
1427
5220af0c 1428 /* Reset the entire device */
d68b603c
AK		 1429 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1430
1431 udelay(10);
5220af0c
BC		 1432
1433 /*
1434 * Clear "initialization complete" bit to move adapter from
1435 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
1436 */
d68b603c 1437 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
d68b603c
AK		 1438}
1439EXPORT_SYMBOL(iwl_apm_stop);
1440
fadb3582
BC		 1441
1442/*
1443 * Start up NIC's basic functionality after it has been reset
1444 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1445 * NOTE: This does not load uCode nor start the embedded processor
1446 */
1447int iwl_apm_init(struct iwl_priv *priv)
1448{
1449 int ret = 0;
1450 u16 lctl;
1451
1452 IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
1453
1454 /*
1455 * Use "set_bit" below rather than "write", to preserve any hardware
1456 * bits already set by default after reset.
1457 */
1458
1459 /* Disable L0S exit timer (platform NMI Work/Around) */
1460 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1461 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1462
1463 /*
1464 * Disable L0s without affecting L1;
1465 * don't wait for ICH L0s (ICH bug W/A)
1466 */
1467 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1468 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1469
1470 /* Set FH wait threshold to maximum (HW error during stress W/A) */
1471 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1472
1473 /*
1474 * Enable HAP INTA (interrupt from management bus) to
1475 * wake device's PCI Express link L1a -> L0s
1476 * NOTE: This is no-op for 3945 (non-existant bit)
1477 */
1478 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1479 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
1480
1481 /*
a6c5c731
BC		 1482 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
1483 * Check if BIOS (or OS) enabled L1-ASPM on this device.
1484 * If so (likely), disable L0S, so device moves directly L0->L1;
1485 * costs negligible amount of power savings.
1486 * If not (unlikely), enable L0S, so there is at least some
1487 * power savings, even without L1.
fadb3582
BC		 1488 */
1489 if (priv->cfg->set_l0s) {
1490 lctl = iwl_pcie_link_ctl(priv);
1491 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
1492 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
1493 /* L1-ASPM enabled; disable(!) L0S */
1494 iwl_set_bit(priv, CSR_GIO_REG,
1495 CSR_GIO_REG_VAL_L0S_ENABLED);
1496 IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
1497 } else {
1498 /* L1-ASPM disabled; enable(!) L0S */
1499 iwl_clear_bit(priv, CSR_GIO_REG,
1500 CSR_GIO_REG_VAL_L0S_ENABLED);
1501 IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
1502 }
1503 }
1504
1505 /* Configure analog phase-lock-loop before activating to D0A */
1506 if (priv->cfg->pll_cfg_val)
1507 iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
1508
1509 /*
1510 * Set "initialization complete" bit to move adapter from
1511 * D0U* --> D0A* (powered-up active) state.
1512 */
1513 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1514
1515 /*
1516 * Wait for clock stabilization; once stabilized, access to
1517 * device-internal resources is supported, e.g. iwl_write_prph()
1518 * and accesses to uCode SRAM.
1519 */
1520 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1521 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1522 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1523 if (ret < 0) {
1524 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1525 goto out;
1526 }
1527
1528 /*
1529 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
1530 * BSM (Boostrap State Machine) is only in 3945 and 4965;
1531 * later devices (i.e. 5000 and later) have non-volatile SRAM,
1532 * and don't need BSM to restore data after power-saving sleep.
1533 *
1534 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
1535 * do not disable clocks. This preserves any hardware bits already
1536 * set by default in "CLK_CTRL_REG" after reset.
1537 */
1538 if (priv->cfg->use_bsm)
1539 iwl_write_prph(priv, APMG_CLK_EN_REG,
1540 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
1541 else
1542 iwl_write_prph(priv, APMG_CLK_EN_REG,
1543 APMG_CLK_VAL_DMA_CLK_RQT);
1544 udelay(20);
1545
1546 /* Disable L1-Active */
1547 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1548 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1549
1550out:
1551 return ret;
1552}
1553EXPORT_SYMBOL(iwl_apm_init);
1554
1555
1556
8ccde88a
SO		 1557void iwl_configure_filter(struct ieee80211_hw *hw,
1558 unsigned int changed_flags,
1559 unsigned int *total_flags,
3ac64bee 1560 u64 multicast)
8ccde88a
SO		 1561{
1562 struct iwl_priv *priv = hw->priv;
1563 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1564
e1623446 1565 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1566 changed_flags, *total_flags);
1567
1568 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1569 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1570 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1571 else
1572 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1573 }
1574 if (changed_flags & FIF_ALLMULTI) {
1575 if (*total_flags & FIF_ALLMULTI)
1576 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1577 else
1578 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1579 }
1580 if (changed_flags & FIF_CONTROL) {
1581 if (*total_flags & FIF_CONTROL)
1582 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1583 else
1584 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1585 }
1586 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1587 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1588 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1589 else
1590 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1591 }
1592
1593 /* We avoid iwl_commit_rxon here to commit the new filter flags
1594 * since mac80211 will call ieee80211_hw_config immediately.
1595 * (mc_list is not supported at this time). Otherwise, we need to
1596 * queue a background iwl_commit_rxon work.
1597 */
1598
1599 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1600 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1601}
1602EXPORT_SYMBOL(iwl_configure_filter);
1603
da154e30
RR		 1604int iwl_set_hw_params(struct iwl_priv *priv)
1605{
da154e30
RR		 1606 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1607 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1608 if (priv->cfg->mod_params->amsdu_size_8K)
2f301227 1609 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
da154e30 1610 else
2f301227 1611 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
da154e30 1612
2c2f3b33
TW		 1613 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
1614
49779293
RR		 1615 if (priv->cfg->mod_params->disable_11n)
1616 priv->cfg->sku &= ~IWL_SKU_N;
1617
da154e30
RR		 1618 /* Device-specific setup */
1619 return priv->cfg->ops->lib->set_hw_params(priv);
1620}
1621EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956 1622
630fe9b6
TW		 1623int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1624{
1625 int ret = 0;
5eadd94b
WYG		 1626 s8 prev_tx_power = priv->tx_power_user_lmt;
1627
630fe9b6 1628 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1629 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1630 tx_power,
1631 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1632 return -EINVAL;
1633 }
1634
dc1b0973 1635 if (tx_power > priv->tx_power_device_lmt) {
08f2d58d
WYG		 1636 IWL_WARN(priv,
1637 "Requested user TXPOWER %d above upper limit %d.\n",
dc1b0973 1638 tx_power, priv->tx_power_device_lmt);
630fe9b6
TW		 1639 return -EINVAL;
1640 }
1641
1642 if (priv->tx_power_user_lmt != tx_power)
1643 force = true;
1644
019fb97d 1645 /* if nic is not up don't send command */
5eadd94b
WYG		 1646 if (iwl_is_ready_rf(priv)) {
1647 priv->tx_power_user_lmt = tx_power;
1648 if (force && priv->cfg->ops->lib->send_tx_power)
1649 ret = priv->cfg->ops->lib->send_tx_power(priv);
1650 else if (!priv->cfg->ops->lib->send_tx_power)
1651 ret = -EOPNOTSUPP;
1652 /*
1653 * if fail to set tx_power, restore the orig. tx power
1654 */
1655 if (ret)
1656 priv->tx_power_user_lmt = prev_tx_power;
1657 }
630fe9b6 1658
5eadd94b
WYG		 1659 /*
1660 * Even this is an async host command, the command
1661 * will always report success from uCode
1662 * So once driver can placing the command into the queue
1663 * successfully, driver can use priv->tx_power_user_lmt
1664 * to reflect the current tx power
1665 */
630fe9b6
TW		 1666 return ret;
1667}
1668EXPORT_SYMBOL(iwl_set_tx_power);
1669
ef850d7c
MA		 1670#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1671
1672/* Free dram table */
1673void iwl_free_isr_ict(struct iwl_priv *priv)
1674{
1675 if (priv->ict_tbl_vir) {
f36d04ab
SG		 1676 dma_free_coherent(&priv->pci_dev->dev,
1677 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1678 priv->ict_tbl_vir, priv->ict_tbl_dma);
ef850d7c
MA		 1679 priv->ict_tbl_vir = NULL;
1680 }
1681}
1682EXPORT_SYMBOL(iwl_free_isr_ict);
1683
1684
1685/* allocate dram shared table it is a PAGE_SIZE aligned
1686 * also reset all data related to ICT table interrupt.
1687 */
1688int iwl_alloc_isr_ict(struct iwl_priv *priv)
1689{
1690
1691 if (priv->cfg->use_isr_legacy)
1692 return 0;
1693 /* allocate shrared data table */
f36d04ab
SG		 1694 priv->ict_tbl_vir = dma_alloc_coherent(&priv->pci_dev->dev,
1695 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1696 &priv->ict_tbl_dma, GFP_KERNEL);
ef850d7c
MA		 1697 if (!priv->ict_tbl_vir)
1698 return -ENOMEM;
1699
1700 /* align table to PAGE_SIZE boundry */
1701 priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
1702
1703 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1704 (unsigned long long)priv->ict_tbl_dma,
1705 (unsigned long long)priv->aligned_ict_tbl_dma,
1706 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1707
1708 priv->ict_tbl = priv->ict_tbl_vir +
1709 (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
1710
1711 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
1712 priv->ict_tbl, priv->ict_tbl_vir,
1713 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1714
1715 /* reset table and index to all 0 */
1716 memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1717 priv->ict_index = 0;
1718
40cefda9
MA		 1719 /* add periodic RX interrupt */
1720 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
ef850d7c
MA		 1721 return 0;
1722}
1723EXPORT_SYMBOL(iwl_alloc_isr_ict);
1724
1725/* Device is going up inform it about using ICT interrupt table,
1726 * also we need to tell the driver to start using ICT interrupt.
1727 */
1728int iwl_reset_ict(struct iwl_priv *priv)
1729{
1730 u32 val;
1731 unsigned long flags;
1732
1733 if (!priv->ict_tbl_vir)
1734 return 0;
1735
1736 spin_lock_irqsave(&priv->lock, flags);
1737 iwl_disable_interrupts(priv);
1738
1303dcfd 1739 memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
ef850d7c
MA		 1740
1741 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
1742
1743 val |= CSR_DRAM_INT_TBL_ENABLE;
1744 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1745
1746 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
1747 "aligned dma address %Lx\n",
1748 val, (unsigned long long)priv->aligned_ict_tbl_dma);
1749
1750 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
1751 priv->use_ict = true;
1752 priv->ict_index = 0;
40cefda9 1753 iwl_write32(priv, CSR_INT, priv->inta_mask);
ef850d7c
MA		 1754 iwl_enable_interrupts(priv);
1755 spin_unlock_irqrestore(&priv->lock, flags);
1756
1757 return 0;
1758}
1759EXPORT_SYMBOL(iwl_reset_ict);
1760
1761/* Device is going down disable ict interrupt usage */
1762void iwl_disable_ict(struct iwl_priv *priv)
1763{
1764 unsigned long flags;
1765
1766 spin_lock_irqsave(&priv->lock, flags);
1767 priv->use_ict = false;
1768 spin_unlock_irqrestore(&priv->lock, flags);
1769}
1770EXPORT_SYMBOL(iwl_disable_ict);
1771
1772/* interrupt handler using ict table, with this interrupt driver will
1773 * stop using INTA register to get device's interrupt, reading this register
1774 * is expensive, device will write interrupts in ICT dram table, increment
1775 * index then will fire interrupt to driver, driver will OR all ICT table
1776 * entries from current index up to table entry with 0 value. the result is
1777 * the interrupt we need to service, driver will set the entries back to 0 and
1778 * set index.
1779 */
1780irqreturn_t iwl_isr_ict(int irq, void *data)
1781{
1782 struct iwl_priv *priv = data;
1783 u32 inta, inta_mask;
1784 u32 val = 0;
1785
1786 if (!priv)
1787 return IRQ_NONE;
1788
1789 /* dram interrupt table not set yet,
1790 * use legacy interrupt.
1791 */
1792 if (!priv->use_ict)
1793 return iwl_isr(irq, data);
1794
1795 spin_lock(&priv->lock);
1796
1797 /* Disable (but don't clear!) interrupts here to avoid
1798 * back-to-back ISRs and sporadic interrupts from our NIC.
1799 * If we have something to service, the tasklet will re-enable ints.
1800 * If we *don't* have something, we'll re-enable before leaving here.
1801 */
1802 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1803 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1804
1805
1806 /* Ignore interrupt if there's nothing in NIC to service.
1807 * This may be due to IRQ shared with another device,
1808 * or due to sporadic interrupts thrown from our NIC. */
1809 if (!priv->ict_tbl[priv->ict_index]) {
1810 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1811 goto none;
1812 }
1813
1814 /* read all entries that not 0 start with ict_index */
1815 while (priv->ict_tbl[priv->ict_index]) {
1816
1303dcfd 1817 val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
ef850d7c 1818 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
1303dcfd
JB		 1819 priv->ict_index,
1820 le32_to_cpu(priv->ict_tbl[priv->ict_index]));
ef850d7c
MA		 1821 priv->ict_tbl[priv->ict_index] = 0;
1822 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
1303dcfd 1823 ICT_COUNT);
ef850d7c
MA		 1824
1825 }
1826
1827 /* We should not get this value, just ignore it. */
1828 if (val == 0xffffffff)
1829 val = 0;
1830
2a11df6e
WYG		 1831 /*
1832 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1833 * (bit 15 before shifting it to 31) to clear when using interrupt
1834 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1835 * so we use them to decide on the real state of the Rx bit.
1836 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1837 */
1838 if (val & 0xC0000)
1839 val |= 0x8000;
1840
ef850d7c
MA		 1841 inta = (0xff & val) | ((0xff00 & val) << 16);
1842 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1843 inta, inta_mask, val);
1844
40cefda9 1845 inta &= priv->inta_mask;
ef850d7c
MA		 1846 priv->inta |= inta;
1847
1848 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1849 if (likely(inta))
1850 tasklet_schedule(&priv->irq_tasklet);
1851 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
1852 /* Allow interrupt if was disabled by this handler and
1853 * no tasklet was schedules, We should not enable interrupt,
1854 * tasklet will enable it.
1855 */
1856 iwl_enable_interrupts(priv);
1857 }
1858
1859 spin_unlock(&priv->lock);
1860 return IRQ_HANDLED;
1861
1862 none:
1863 /* re-enable interrupts here since we don't have anything to service.
1864 * only Re-enable if disabled by irq.
1865 */
1866 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1867 iwl_enable_interrupts(priv);
1868
1869 spin_unlock(&priv->lock);
1870 return IRQ_NONE;
1871}
1872EXPORT_SYMBOL(iwl_isr_ict);
1873
1874
1875static irqreturn_t iwl_isr(int irq, void *data)
1876{
1877 struct iwl_priv *priv = data;
1878 u32 inta, inta_mask;
d651ae32 1879#ifdef CONFIG_IWLWIFI_DEBUG
ef850d7c 1880 u32 inta_fh;
d651ae32 1881#endif
ef850d7c
MA		 1882 if (!priv)
1883 return IRQ_NONE;
1884
1885 spin_lock(&priv->lock);
1886
1887 /* Disable (but don't clear!) interrupts here to avoid
1888 * back-to-back ISRs and sporadic interrupts from our NIC.
1889 * If we have something to service, the tasklet will re-enable ints.
1890 * If we *don't* have something, we'll re-enable before leaving here. */
1891 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1892 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1893
1894 /* Discover which interrupts are active/pending */
1895 inta = iwl_read32(priv, CSR_INT);
1896
1897 /* Ignore interrupt if there's nothing in NIC to service.
1898 * This may be due to IRQ shared with another device,
1899 * or due to sporadic interrupts thrown from our NIC. */
1900 if (!inta) {
1901 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1902 goto none;
1903 }
1904
1905 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1906 /* Hardware disappeared. It might have already raised
1907 * an interrupt */
1908 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1909 goto unplugged;
1910 }
1911
1912#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1913 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1914 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1915 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
1916 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1917 }
1918#endif
1919
1920 priv->inta |= inta;
1921 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1922 if (likely(inta))
1923 tasklet_schedule(&priv->irq_tasklet);
1924 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1925 iwl_enable_interrupts(priv);
1926
1927 unplugged:
1928 spin_unlock(&priv->lock);
1929 return IRQ_HANDLED;
1930
1931 none:
1932 /* re-enable interrupts here since we don't have anything to service. */
1933 /* only Re-enable if diabled by irq and no schedules tasklet. */
1934 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1935 iwl_enable_interrupts(priv);
1936
1937 spin_unlock(&priv->lock);
1938 return IRQ_NONE;
1939}
1940
1941irqreturn_t iwl_isr_legacy(int irq, void *data)
f17d08a6
AK		 1942{
1943 struct iwl_priv *priv = data;
1944 u32 inta, inta_mask;
1945 u32 inta_fh;
1946 if (!priv)
1947 return IRQ_NONE;
1948
1949 spin_lock(&priv->lock);
1950
1951 /* Disable (but don't clear!) interrupts here to avoid
1952 * back-to-back ISRs and sporadic interrupts from our NIC.
1953 * If we have something to service, the tasklet will re-enable ints.
1954 * If we *don't* have something, we'll re-enable before leaving here. */
1955 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1956 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1957
1958 /* Discover which interrupts are active/pending */
1959 inta = iwl_read32(priv, CSR_INT);
1960 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1961
1962 /* Ignore interrupt if there's nothing in NIC to service.
1963 * This may be due to IRQ shared with another device,
1964 * or due to sporadic interrupts thrown from our NIC. */
1965 if (!inta && !inta_fh) {
1966 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
1967 goto none;
1968 }
1969
1970 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1971 /* Hardware disappeared. It might have already raised
1972 * an interrupt */
1973 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1974 goto unplugged;
1975 }
1976
1977 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1978 inta, inta_mask, inta_fh);
1979
1980 inta &= ~CSR_INT_BIT_SCD;
1981
1982 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1983 if (likely(inta || inta_fh))
1984 tasklet_schedule(&priv->irq_tasklet);
1985
1986 unplugged:
1987 spin_unlock(&priv->lock);
1988 return IRQ_HANDLED;
1989
1990 none:
1991 /* re-enable interrupts here since we don't have anything to service. */
1992 /* only Re-enable if diabled by irq */
1993 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1994 iwl_enable_interrupts(priv);
1995 spin_unlock(&priv->lock);
1996 return IRQ_NONE;
1997}
ef850d7c 1998EXPORT_SYMBOL(iwl_isr_legacy);
f17d08a6 1999
17f841cd
SO		 2000int iwl_send_bt_config(struct iwl_priv *priv)
2001{
2002 struct iwl_bt_cmd bt_cmd = {
456d0f76
WYG		 2003 .lead_time = BT_LEAD_TIME_DEF,
2004 .max_kill = BT_MAX_KILL_DEF,
17f841cd
SO		 2005 .kill_ack_mask = 0,
2006 .kill_cts_mask = 0,
2007 };
2008
06702a73
WYG		 2009 if (!bt_coex_active)
2010 bt_cmd.flags = BT_COEX_DISABLE;
2011 else
2012 bt_cmd.flags = BT_COEX_ENABLE;
2013
2014 IWL_DEBUG_INFO(priv, "BT coex %s\n",
2015 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
2016
17f841cd
SO		 2017 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
2018 sizeof(struct iwl_bt_cmd), &bt_cmd);
2019}
2020EXPORT_SYMBOL(iwl_send_bt_config);
2021
ef8d5529 2022int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear)
49ea8596 2023{
ef8d5529
WYG		 2024 struct iwl_statistics_cmd statistics_cmd = {
2025 .configuration_flags =
2026 clear ? IWL_STATS_CONF_CLEAR_STATS : 0,
49ea8596 2027 };
ef8d5529
WYG		 2028
2029 if (flags & CMD_ASYNC)
2030 return iwl_send_cmd_pdu_async(priv, REPLY_STATISTICS_CMD,
2031 sizeof(struct iwl_statistics_cmd),
2032 &statistics_cmd, NULL);
2033 else
2034 return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD,
2035 sizeof(struct iwl_statistics_cmd),
2036 &statistics_cmd);
49ea8596
EG		 2037}
2038EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 2039
b0692f2f
EG		 2040/**
2041 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
2042 * using sample data 100 bytes apart. If these sample points are good,
2043 * it's a pretty good bet that everything between them is good, too.
2044 */
2045static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
2046{
2047 u32 val;
2048 int ret = 0;
2049 u32 errcnt = 0;
2050 u32 i;
2051
e1623446 2052 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2053
b0692f2f
EG		 2054 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2055 /* read data comes through single port, auto-incr addr */
2056 /* NOTE: Use the debugless read so we don't flood kernel log
2057 * if IWL_DL_IO is set */
2058 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2059 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2060 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2061 if (val != le32_to_cpu(*image)) {
2062 ret = -EIO;
2063 errcnt++;
2064 if (errcnt >= 3)
2065 break;
2066 }
2067 }
2068
b0692f2f
EG		 2069 return ret;
2070}
2071
2072/**
2073 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
2074 * looking at all data.
2075 */
2076static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
2077 u32 len)
2078{
2079 u32 val;
2080 u32 save_len = len;
2081 int ret = 0;
2082 u32 errcnt;
2083
e1623446 2084 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2085
250bdd21
SO		 2086 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
2087 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2088
2089 errcnt = 0;
2090 for (; len > 0; len -= sizeof(u32), image++) {
2091 /* read data comes through single port, auto-incr addr */
2092 /* NOTE: Use the debugless read so we don't flood kernel log
2093 * if IWL_DL_IO is set */
2094 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2095 if (val != le32_to_cpu(*image)) {
15b1687c 2096 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 2097 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2098 save_len - len, val, le32_to_cpu(*image));
2099 ret = -EIO;
2100 errcnt++;
2101 if (errcnt >= 20)
2102 break;
2103 }
2104 }
2105
b0692f2f 2106 if (!errcnt)
e1623446
TW		 2107 IWL_DEBUG_INFO(priv,
2108 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 2109
2110 return ret;
2111}
2112
2113/**
2114 * iwl_verify_ucode - determine which instruction image is in SRAM,
2115 * and verify its contents
2116 */
2117int iwl_verify_ucode(struct iwl_priv *priv)
2118{
2119 __le32 *image;
2120 u32 len;
2121 int ret;
2122
2123 /* Try bootstrap */
2124 image = (__le32 *)priv->ucode_boot.v_addr;
2125 len = priv->ucode_boot.len;
2126 ret = iwlcore_verify_inst_sparse(priv, image, len);
2127 if (!ret) {
e1623446 2128 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 2129 return 0;
2130 }
2131
2132 /* Try initialize */
2133 image = (__le32 *)priv->ucode_init.v_addr;
2134 len = priv->ucode_init.len;
2135 ret = iwlcore_verify_inst_sparse(priv, image, len);
2136 if (!ret) {
e1623446 2137 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 2138 return 0;
2139 }
2140
2141 /* Try runtime/protocol */
2142 image = (__le32 *)priv->ucode_code.v_addr;
2143 len = priv->ucode_code.len;
2144 ret = iwlcore_verify_inst_sparse(priv, image, len);
2145 if (!ret) {
e1623446 2146 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 2147 return 0;
2148 }
2149
15b1687c 2150 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 2151
2152 /* Since nothing seems to match, show first several data entries in
2153 * instruction SRAM, so maybe visual inspection will give a clue.
2154 * Selection of bootstrap image (vs. other images) is arbitrary. */
2155 image = (__le32 *)priv->ucode_boot.v_addr;
2156 len = priv->ucode_boot.len;
2157 ret = iwl_verify_inst_full(priv, image, len);
2158
2159 return ret;
2160}
2161EXPORT_SYMBOL(iwl_verify_ucode);
2162
56e12615 2163
47f4a587
EG		 2164void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2165{
2166 struct iwl_ct_kill_config cmd;
672639de 2167 struct iwl_ct_kill_throttling_config adv_cmd;
47f4a587
EG		 2168 unsigned long flags;
2169 int ret = 0;
2170
2171 spin_lock_irqsave(&priv->lock, flags);
2172 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2173 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2174 spin_unlock_irqrestore(&priv->lock, flags);
3ad3b92a 2175 priv->thermal_throttle.ct_kill_toggle = false;
47f4a587 2176
480e8407 2177 if (priv->cfg->support_ct_kill_exit) {
672639de
WYG		 2178 adv_cmd.critical_temperature_enter =
2179 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2180 adv_cmd.critical_temperature_exit =
2181 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2182
2183 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2184 sizeof(adv_cmd), &adv_cmd);
d91b1ba3
WYG		 2185 if (ret)
2186 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2187 else
2188 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2189 "succeeded, "
2190 "critical temperature enter is %d,"
2191 "exit is %d\n",
2192 priv->hw_params.ct_kill_threshold,
2193 priv->hw_params.ct_kill_exit_threshold);
480e8407 2194 } else {
672639de
WYG		 2195 cmd.critical_temperature_R =
2196 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 2197
672639de
WYG		 2198 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2199 sizeof(cmd), &cmd);
d91b1ba3
WYG		 2200 if (ret)
2201 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2202 else
2203 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2204 "succeeded, "
2205 "critical temperature is %d\n",
2206 priv->hw_params.ct_kill_threshold);
672639de 2207 }
47f4a587
EG		 2208}
2209EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 2210
0ad91a35 2211
14a08a7f
EG		 2212/*
2213 * CARD_STATE_CMD
2214 *
2215 * Use: Sets the device's internal card state to enable, disable, or halt
2216 *
2217 * When in the 'enable' state the card operates as normal.
2218 * When in the 'disable' state, the card enters into a low power mode.
2219 * When in the 'halt' state, the card is shut down and must be fully
2220 * restarted to come back on.
2221 */
c496294e 2222int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 2223{
2224 struct iwl_host_cmd cmd = {
2225 .id = REPLY_CARD_STATE_CMD,
2226 .len = sizeof(u32),
2227 .data = &flags,
c2acea8e 2228 .flags = meta_flag,
14a08a7f
EG		 2229 };
2230
2231 return iwl_send_cmd(priv, &cmd);
2232}
2233
030f05ed
AK		 2234void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2235 struct iwl_rx_mem_buffer *rxb)
2236{
2237#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 2238 struct iwl_rx_packet *pkt = rxb_addr(rxb);
030f05ed
AK		 2239 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2240 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2241 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2242#endif
2243}
2244EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2245
2246void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2247 struct iwl_rx_mem_buffer *rxb)
2248{
2f301227 2249 struct iwl_rx_packet *pkt = rxb_addr(rxb);
396887a2 2250 u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
030f05ed 2251 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
396887a2
DH		 2252 "notification for %s:\n", len,
2253 get_cmd_string(pkt->hdr.cmd));
2254 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
030f05ed
AK		 2255}
2256EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2257
2258void iwl_rx_reply_error(struct iwl_priv *priv,
2259 struct iwl_rx_mem_buffer *rxb)
2260{
2f301227 2261 struct iwl_rx_packet *pkt = rxb_addr(rxb);
261b9c33
AK		 2262
2263 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2264 "seq 0x%04X ser 0x%08X\n",
2265 le32_to_cpu(pkt->u.err_resp.error_type),
2266 get_cmd_string(pkt->u.err_resp.cmd_id),
2267 pkt->u.err_resp.cmd_id,
2268 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2269 le32_to_cpu(pkt->u.err_resp.error_info));
2270}
2271EXPORT_SYMBOL(iwl_rx_reply_error);
2272
a83b9141
WYG		 2273void iwl_clear_isr_stats(struct iwl_priv *priv)
2274{
2275 memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
2276}
a83b9141 2277
488829f1
AK		 2278int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2279 const struct ieee80211_tx_queue_params *params)
2280{
2281 struct iwl_priv *priv = hw->priv;
2282 unsigned long flags;
2283 int q;
2284
2285 IWL_DEBUG_MAC80211(priv, "enter\n");
2286
2287 if (!iwl_is_ready_rf(priv)) {
2288 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2289 return -EIO;
2290 }
2291
2292 if (queue >= AC_NUM) {
2293 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2294 return 0;
2295 }
2296
2297 q = AC_NUM - 1 - queue;
2298
2299 spin_lock_irqsave(&priv->lock, flags);
2300
2301 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2302 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2303 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2304 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2305 cpu_to_le16((params->txop * 32));
2306
2307 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2308 priv->qos_data.qos_active = 1;
2309
2310 if (priv->iw_mode == NL80211_IFTYPE_AP)
2311 iwl_activate_qos(priv, 1);
2312 else if (priv->assoc_id && iwl_is_associated(priv))
2313 iwl_activate_qos(priv, 0);
2314
2315 spin_unlock_irqrestore(&priv->lock, flags);
2316
2317 IWL_DEBUG_MAC80211(priv, "leave\n");
2318 return 0;
2319}
2320EXPORT_SYMBOL(iwl_mac_conf_tx);
5bbe233b
AK		 2321
2322static void iwl_ht_conf(struct iwl_priv *priv,
02bb1bea 2323 struct ieee80211_bss_conf *bss_conf)
5bbe233b 2324{
fad95bf5 2325 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
5bbe233b
AK		 2326 struct ieee80211_sta *sta;
2327
2328 IWL_DEBUG_MAC80211(priv, "enter: \n");
2329
fad95bf5 2330 if (!ht_conf->is_ht)
5bbe233b
AK		 2331 return;
2332
fad95bf5 2333 ht_conf->ht_protection =
9ed6bcce 2334 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
fad95bf5 2335 ht_conf->non_GF_STA_present =
9ed6bcce 2336 !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5bbe233b 2337
02bb1bea
JB		 2338 ht_conf->single_chain_sufficient = false;
2339
2340 switch (priv->iw_mode) {
2341 case NL80211_IFTYPE_STATION:
2342 rcu_read_lock();
5ed176e1 2343 sta = ieee80211_find_sta(priv->vif, priv->bssid);
02bb1bea
JB		 2344 if (sta) {
2345 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
2346 int maxstreams;
2347
2348 maxstreams = (ht_cap->mcs.tx_params &
2349 IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
2350 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2351 maxstreams += 1;
2352
2353 if ((ht_cap->mcs.rx_mask[1] == 0) &&
2354 (ht_cap->mcs.rx_mask[2] == 0))
2355 ht_conf->single_chain_sufficient = true;
2356 if (maxstreams <= 1)
2357 ht_conf->single_chain_sufficient = true;
2358 } else {
2359 /*
2360 * If at all, this can only happen through a race
2361 * when the AP disconnects us while we're still
2362 * setting up the connection, in that case mac80211
2363 * will soon tell us about that.
2364 */
2365 ht_conf->single_chain_sufficient = true;
2366 }
2367 rcu_read_unlock();
2368 break;
2369 case NL80211_IFTYPE_ADHOC:
2370 ht_conf->single_chain_sufficient = true;
2371 break;
2372 default:
2373 break;
2374 }
5bbe233b
AK		 2375
2376 IWL_DEBUG_MAC80211(priv, "leave\n");
2377}
2378
c91c3efc
AK		 2379static inline void iwl_set_no_assoc(struct iwl_priv *priv)
2380{
2381 priv->assoc_id = 0;
2382 iwl_led_disassociate(priv);
2383 /*
2384 * inform the ucode that there is no longer an
2385 * association and that no more packets should be
2386 * sent
2387 */
2388 priv->staging_rxon.filter_flags &=
2389 ~RXON_FILTER_ASSOC_MSK;
2390 priv->staging_rxon.assoc_id = 0;
2391 iwlcore_commit_rxon(priv);
2392}
2393
5bbe233b
AK		 2394#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
2395void iwl_bss_info_changed(struct ieee80211_hw *hw,
2d0ddec5
JB		 2396 struct ieee80211_vif *vif,
2397 struct ieee80211_bss_conf *bss_conf,
2398 u32 changes)
5bbe233b
AK		 2399{
2400 struct iwl_priv *priv = hw->priv;
3a650292 2401 int ret;
5bbe233b
AK		 2402
2403 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
2404
2d0ddec5
JB		 2405 if (!iwl_is_alive(priv))
2406 return;
2407
2408 mutex_lock(&priv->mutex);
2409
2410 if (changes & BSS_CHANGED_BEACON &&
2411 priv->iw_mode == NL80211_IFTYPE_AP) {
2412 dev_kfree_skb(priv->ibss_beacon);
2413 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
2414 }
2415
d7129e19
JB		 2416 if (changes & BSS_CHANGED_BEACON_INT) {
2417 priv->beacon_int = bss_conf->beacon_int;
2418 /* TODO: in AP mode, do something to make this take effect */
2419 }
2420
2421 if (changes & BSS_CHANGED_BSSID) {
2422 IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
2423
2424 /*
2425 * If there is currently a HW scan going on in the
2426 * background then we need to cancel it else the RXON
2427 * below/in post_associate will fail.
2428 */
2d0ddec5 2429 if (iwl_scan_cancel_timeout(priv, 100)) {
d7129e19 2430 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
2d0ddec5
JB		 2431 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
2432 mutex_unlock(&priv->mutex);
2433 return;
2434 }
2d0ddec5 2435
d7129e19
JB		 2436 /* mac80211 only sets assoc when in STATION mode */
2437 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
2438 bss_conf->assoc) {
2439 memcpy(priv->staging_rxon.bssid_addr,
2440 bss_conf->bssid, ETH_ALEN);
2d0ddec5 2441
d7129e19
JB		 2442 /* currently needed in a few places */
2443 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2444 } else {
2445 priv->staging_rxon.filter_flags &=
2446 ~RXON_FILTER_ASSOC_MSK;
2d0ddec5 2447 }
d7129e19 2448
2d0ddec5
JB		 2449 }
2450
d7129e19
JB		 2451 /*
2452 * This needs to be after setting the BSSID in case
2453 * mac80211 decides to do both changes at once because
2454 * it will invoke post_associate.
2455 */
2d0ddec5
JB		 2456 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2457 changes & BSS_CHANGED_BEACON) {
2458 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2459
2460 if (beacon)
2461 iwl_mac_beacon_update(hw, beacon);
2462 }
2463
5bbe233b
AK		 2464 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
2465 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
2466 bss_conf->use_short_preamble);
2467 if (bss_conf->use_short_preamble)
2468 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2469 else
2470 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2471 }
2472
2473 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
2474 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
2475 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
2476 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2477 else
2478 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2479 }
2480
d7129e19
JB		 2481 if (changes & BSS_CHANGED_BASIC_RATES) {
2482 /* XXX use this information
2483 *
2484 * To do that, remove code from iwl_set_rate() and put something
2485 * like this here:
2486 *
2487 if (A-band)
2488 priv->staging_rxon.ofdm_basic_rates =
2489 bss_conf->basic_rates;
2490 else
2491 priv->staging_rxon.ofdm_basic_rates =
2492 bss_conf->basic_rates >> 4;
2493 priv->staging_rxon.cck_basic_rates =
2494 bss_conf->basic_rates & 0xF;
2495 */
2496 }
2497
5bbe233b
AK		 2498 if (changes & BSS_CHANGED_HT) {
2499 iwl_ht_conf(priv, bss_conf);
45823531
AK		 2500
2501 if (priv->cfg->ops->hcmd->set_rxon_chain)
2502 priv->cfg->ops->hcmd->set_rxon_chain(priv);
5bbe233b
AK		 2503 }
2504
2505 if (changes & BSS_CHANGED_ASSOC) {
2506 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
5bbe233b
AK		 2507 if (bss_conf->assoc) {
2508 priv->assoc_id = bss_conf->aid;
2509 priv->beacon_int = bss_conf->beacon_int;
5bbe233b
AK		 2510 priv->timestamp = bss_conf->timestamp;
2511 priv->assoc_capability = bss_conf->assoc_capability;
2512
e932a609
JB		 2513 iwl_led_associate(priv);
2514
d7129e19
JB		 2515 /*
2516 * We have just associated, don't start scan too early
2517 * leave time for EAPOL exchange to complete.
2518 *
2519 * XXX: do this in mac80211
5bbe233b
AK		 2520 */
2521 priv->next_scan_jiffies = jiffies +
2522 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
d7129e19
JB		 2523 if (!iwl_is_rfkill(priv))
2524 priv->cfg->ops->lib->post_associate(priv);
c91c3efc
AK		 2525 } else
2526 iwl_set_no_assoc(priv);
d7129e19
JB		 2527 }
2528
2529 if (changes && iwl_is_associated(priv) && priv->assoc_id) {
2530 IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
2531 changes);
2532 ret = iwl_send_rxon_assoc(priv);
2533 if (!ret) {
2534 /* Sync active_rxon with latest change. */
2535 memcpy((void *)&priv->active_rxon,
2536 &priv->staging_rxon,
2537 sizeof(struct iwl_rxon_cmd));
5bbe233b 2538 }
5bbe233b 2539 }
d7129e19 2540
c91c3efc
AK		 2541 if (changes & BSS_CHANGED_BEACON_ENABLED) {
2542 if (vif->bss_conf.enable_beacon) {
2543 memcpy(priv->staging_rxon.bssid_addr,
2544 bss_conf->bssid, ETH_ALEN);
2545 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2546 iwlcore_config_ap(priv);
2547 } else
2548 iwl_set_no_assoc(priv);
f513dfff
DH		 2549 }
2550
d7129e19
JB		 2551 mutex_unlock(&priv->mutex);
2552
2d0ddec5 2553 IWL_DEBUG_MAC80211(priv, "leave\n");
5bbe233b
AK		 2554}
2555EXPORT_SYMBOL(iwl_bss_info_changed);
2556
9944b938
AK		 2557int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2558{
2559 struct iwl_priv *priv = hw->priv;
2560 unsigned long flags;
2561 __le64 timestamp;
2562
2563 IWL_DEBUG_MAC80211(priv, "enter\n");
2564
2565 if (!iwl_is_ready_rf(priv)) {
2566 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2567 return -EIO;
2568 }
2569
2570 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2571 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
2572 return -EIO;
2573 }
2574
2575 spin_lock_irqsave(&priv->lock, flags);
2576
2577 if (priv->ibss_beacon)
2578 dev_kfree_skb(priv->ibss_beacon);
2579
2580 priv->ibss_beacon = skb;
2581
2582 priv->assoc_id = 0;
2583 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
2584 priv->timestamp = le64_to_cpu(timestamp);
2585
2586 IWL_DEBUG_MAC80211(priv, "leave\n");
2587 spin_unlock_irqrestore(&priv->lock, flags);
2588
2589 iwl_reset_qos(priv);
2590
2591 priv->cfg->ops->lib->post_associate(priv);
2592
2593
2594 return 0;
2595}
2596EXPORT_SYMBOL(iwl_mac_beacon_update);
2597
727882d6
AK		 2598int iwl_set_mode(struct iwl_priv *priv, int mode)
2599{
2600 if (mode == NL80211_IFTYPE_ADHOC) {
2601 const struct iwl_channel_info *ch_info;
2602
2603 ch_info = iwl_get_channel_info(priv,
2604 priv->band,
2605 le16_to_cpu(priv->staging_rxon.channel));
2606
2607 if (!ch_info || !is_channel_ibss(ch_info)) {
2608 IWL_ERR(priv, "channel %d not IBSS channel\n",
2609 le16_to_cpu(priv->staging_rxon.channel));
2610 return -EINVAL;
2611 }
2612 }
2613
2614 iwl_connection_init_rx_config(priv, mode);
2615
2616 if (priv->cfg->ops->hcmd->set_rxon_chain)
2617 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2618
2619 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2620
c587de0b 2621 iwl_clear_stations_table(priv);
727882d6
AK		 2622
2623 /* dont commit rxon if rf-kill is on*/
2624 if (!iwl_is_ready_rf(priv))
2625 return -EAGAIN;
2626
727882d6
AK		 2627 iwlcore_commit_rxon(priv);
2628
2629 return 0;
2630}
2631EXPORT_SYMBOL(iwl_set_mode);
2632
cbb6ab94 2633int iwl_mac_add_interface(struct ieee80211_hw *hw,
1ed32e4f 2634 struct ieee80211_vif *vif)
cbb6ab94
AK		 2635{
2636 struct iwl_priv *priv = hw->priv;
47e28f41 2637 int err = 0;
cbb6ab94 2638
1ed32e4f 2639 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", vif->type);
cbb6ab94 2640
47e28f41
JB		 2641 mutex_lock(&priv->mutex);
2642
cbb6ab94
AK		 2643 if (priv->vif) {
2644 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
47e28f41
JB		 2645 err = -EOPNOTSUPP;
2646 goto out;
cbb6ab94
AK		 2647 }
2648
1ed32e4f
JB		 2649 priv->vif = vif;
2650 priv->iw_mode = vif->type;
cbb6ab94 2651
1ed32e4f
JB		 2652 if (vif->addr) {
2653 IWL_DEBUG_MAC80211(priv, "Set %pM\n", vif->addr);
2654 memcpy(priv->mac_addr, vif->addr, ETH_ALEN);
cbb6ab94
AK		 2655 }
2656
1ed32e4f 2657 if (iwl_set_mode(priv, vif->type) == -EAGAIN)
cbb6ab94
AK		 2658 /* we are not ready, will run again when ready */
2659 set_bit(STATUS_MODE_PENDING, &priv->status);
2660
47e28f41 2661 out:
cbb6ab94
AK		 2662 mutex_unlock(&priv->mutex);
2663
2664 IWL_DEBUG_MAC80211(priv, "leave\n");
47e28f41 2665 return err;
cbb6ab94
AK		 2666}
2667EXPORT_SYMBOL(iwl_mac_add_interface);
2668
d8052319 2669void iwl_mac_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 2670 struct ieee80211_vif *vif)
d8052319
AK		 2671{
2672 struct iwl_priv *priv = hw->priv;
2673
2674 IWL_DEBUG_MAC80211(priv, "enter\n");
2675
2676 mutex_lock(&priv->mutex);
2677
2678 if (iwl_is_ready_rf(priv)) {
2679 iwl_scan_cancel_timeout(priv, 100);
2680 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2681 iwlcore_commit_rxon(priv);
2682 }
1ed32e4f 2683 if (priv->vif == vif) {
d8052319
AK		 2684 priv->vif = NULL;
2685 memset(priv->bssid, 0, ETH_ALEN);
2686 }
2687 mutex_unlock(&priv->mutex);
2688
2689 IWL_DEBUG_MAC80211(priv, "leave\n");
2690
2691}
2692EXPORT_SYMBOL(iwl_mac_remove_interface);
2693
4808368d
AK		 2694/**
2695 * iwl_mac_config - mac80211 config callback
2696 *
2697 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2698 * be set inappropriately and the driver currently sets the hardware up to
2699 * use it whenever needed.
2700 */
2701int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
2702{
2703 struct iwl_priv *priv = hw->priv;
2704 const struct iwl_channel_info *ch_info;
2705 struct ieee80211_conf *conf = &hw->conf;
fad95bf5 2706 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
4808368d
AK		 2707 unsigned long flags = 0;
2708 int ret = 0;
2709 u16 ch;
2710 int scan_active = 0;
2711
2712 mutex_lock(&priv->mutex);
2713
4808368d
AK		 2714 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2715 conf->channel->hw_value, changed);
2716
2717 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2718 test_bit(STATUS_SCANNING, &priv->status))) {
2719 scan_active = 1;
2720 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
2721 }
2722
ba37a3d0
JB		 2723 if (changed & (IEEE80211_CONF_CHANGE_SMPS |
2724 IEEE80211_CONF_CHANGE_CHANNEL)) {
2725 /* mac80211 uses static for non-HT which is what we want */
2726 priv->current_ht_config.smps = conf->smps_mode;
2727
2728 /*
2729 * Recalculate chain counts.
2730 *
2731 * If monitor mode is enabled then mac80211 will
2732 * set up the SM PS mode to OFF if an HT channel is
2733 * configured.
2734 */
2735 if (priv->cfg->ops->hcmd->set_rxon_chain)
2736 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2737 }
4808368d
AK		 2738
2739 /* during scanning mac80211 will delay channel setting until
2740 * scan finish with changed = 0
2741 */
2742 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2743 if (scan_active)
2744 goto set_ch_out;
2745
2746 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2747 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2748 if (!is_channel_valid(ch_info)) {
2749 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2750 ret = -EINVAL;
2751 goto set_ch_out;
2752 }
2753
2754 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2755 !is_channel_ibss(ch_info)) {
2756 IWL_ERR(priv, "channel %d in band %d not "
2757 "IBSS channel\n",
2758 conf->channel->hw_value, conf->channel->band);
2759 ret = -EINVAL;
2760 goto set_ch_out;
2761 }
2762
4808368d
AK		 2763 spin_lock_irqsave(&priv->lock, flags);
2764
28bd723b
DH		 2765 /* Configure HT40 channels */
2766 ht_conf->is_ht = conf_is_ht(conf);
2767 if (ht_conf->is_ht) {
2768 if (conf_is_ht40_minus(conf)) {
2769 ht_conf->extension_chan_offset =
2770 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
c812ee24 2771 ht_conf->is_40mhz = true;
28bd723b
DH		 2772 } else if (conf_is_ht40_plus(conf)) {
2773 ht_conf->extension_chan_offset =
2774 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
c812ee24 2775 ht_conf->is_40mhz = true;
28bd723b
DH		 2776 } else {
2777 ht_conf->extension_chan_offset =
2778 IEEE80211_HT_PARAM_CHA_SEC_NONE;
c812ee24 2779 ht_conf->is_40mhz = false;
28bd723b
DH		 2780 }
2781 } else
c812ee24 2782 ht_conf->is_40mhz = false;
28bd723b
DH		 2783 /* Default to no protection. Protection mode will later be set
2784 * from BSS config in iwl_ht_conf */
2785 ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
4808368d
AK		 2786
2787 /* if we are switching from ht to 2.4 clear flags
2788 * from any ht related info since 2.4 does not
2789 * support ht */
2790 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2791 priv->staging_rxon.flags = 0;
2792
2793 iwl_set_rxon_channel(priv, conf->channel);
5e2f75b8 2794 iwl_set_rxon_ht(priv, ht_conf);
4808368d
AK		 2795
2796 iwl_set_flags_for_band(priv, conf->channel->band);
2797 spin_unlock_irqrestore(&priv->lock, flags);
0924e519
WYG		 2798 if (iwl_is_associated(priv) &&
2799 (le16_to_cpu(priv->active_rxon.channel) != ch) &&
2800 priv->cfg->ops->lib->set_channel_switch) {
2801 iwl_set_rate(priv);
2802 /*
2803 * at this point, staging_rxon has the
2804 * configuration for channel switch
2805 */
2806 ret = priv->cfg->ops->lib->set_channel_switch(priv,
2807 ch);
2808 if (!ret) {
2809 iwl_print_rx_config_cmd(priv);
2810 goto out;
2811 }
2812 priv->switch_rxon.switch_in_progress = false;
2813 }
4808368d
AK		 2814 set_ch_out:
2815 /* The list of supported rates and rate mask can be different
2816 * for each band; since the band may have changed, reset
2817 * the rate mask to what mac80211 lists */
2818 iwl_set_rate(priv);
2819 }
2820
78f5fb7f
JB		 2821 if (changed & (IEEE80211_CONF_CHANGE_PS |
2822 IEEE80211_CONF_CHANGE_IDLE)) {
e312c24c 2823 ret = iwl_power_update_mode(priv, false);
4808368d 2824 if (ret)
e312c24c 2825 IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
4808368d
AK		 2826 }
2827
2828 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2829 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2830 priv->tx_power_user_lmt, conf->power_level);
2831
2832 iwl_set_tx_power(priv, conf->power_level, false);
2833 }
2834
0cf4c01e
MA		 2835 if (!iwl_is_ready(priv)) {
2836 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2837 goto out;
2838 }
2839
4808368d
AK		 2840 if (scan_active)
2841 goto out;
2842
2843 if (memcmp(&priv->active_rxon,
2844 &priv->staging_rxon, sizeof(priv->staging_rxon)))
2845 iwlcore_commit_rxon(priv);
2846 else
2847 IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
2848
2849
2850out:
2851 IWL_DEBUG_MAC80211(priv, "leave\n");
2852 mutex_unlock(&priv->mutex);
2853 return ret;
2854}
2855EXPORT_SYMBOL(iwl_mac_config);
2856
bd564261
AK		 2857void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
2858{
2859 struct iwl_priv *priv = hw->priv;
2860 unsigned long flags;
2861
2862 mutex_lock(&priv->mutex);
2863 IWL_DEBUG_MAC80211(priv, "enter\n");
2864
2865 spin_lock_irqsave(&priv->lock, flags);
fad95bf5 2866 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
bd564261
AK		 2867 spin_unlock_irqrestore(&priv->lock, flags);
2868
2869 iwl_reset_qos(priv);
2870
2871 spin_lock_irqsave(&priv->lock, flags);
2872 priv->assoc_id = 0;
2873 priv->assoc_capability = 0;
2874 priv->assoc_station_added = 0;
2875
2876 /* new association get rid of ibss beacon skb */
2877 if (priv->ibss_beacon)
2878 dev_kfree_skb(priv->ibss_beacon);
2879
2880 priv->ibss_beacon = NULL;
2881
57c4d7b4 2882 priv->beacon_int = priv->vif->bss_conf.beacon_int;
bd564261
AK		 2883 priv->timestamp = 0;
2884 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
2885 priv->beacon_int = 0;
2886
2887 spin_unlock_irqrestore(&priv->lock, flags);
2888
2889 if (!iwl_is_ready_rf(priv)) {
2890 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2891 mutex_unlock(&priv->mutex);
2892 return;
2893 }
2894
2895 /* we are restarting association process
2896 * clear RXON_FILTER_ASSOC_MSK bit
2897 */
2898 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2899 iwl_scan_cancel_timeout(priv, 100);
2900 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2901 iwlcore_commit_rxon(priv);
2902 }
2903
bd564261 2904 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
bd564261
AK		 2905 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
2906 mutex_unlock(&priv->mutex);
2907 return;
2908 }
2909
2910 iwl_set_rate(priv);
2911
2912 mutex_unlock(&priv->mutex);
2913
2914 IWL_DEBUG_MAC80211(priv, "leave\n");
2915}
2916EXPORT_SYMBOL(iwl_mac_reset_tsf);
2917
88804e2b
WYG		 2918int iwl_alloc_txq_mem(struct iwl_priv *priv)
2919{
2920 if (!priv->txq)
2921 priv->txq = kzalloc(
2922 sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
2923 GFP_KERNEL);
2924 if (!priv->txq) {
2925 IWL_ERR(priv, "Not enough memory for txq \n");
2926 return -ENOMEM;
2927 }
2928 return 0;
2929}
2930EXPORT_SYMBOL(iwl_alloc_txq_mem);
2931
2932void iwl_free_txq_mem(struct iwl_priv *priv)
2933{
2934 kfree(priv->txq);
2935 priv->txq = NULL;
2936}
2937EXPORT_SYMBOL(iwl_free_txq_mem);
2938
1933ac4d
WYG		 2939int iwl_send_wimax_coex(struct iwl_priv *priv)
2940{
2941 struct iwl_wimax_coex_cmd uninitialized_var(coex_cmd);
2942
2943 if (priv->cfg->support_wimax_coexist) {
2944 /* UnMask wake up src at associated sleep */
2945 coex_cmd.flags |= COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
2946
2947 /* UnMask wake up src at unassociated sleep */
2948 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
2949 memcpy(coex_cmd.sta_prio, cu_priorities,
2950 sizeof(struct iwl_wimax_coex_event_entry) *
2951 COEX_NUM_OF_EVENTS);
2952
2953 /* enabling the coexistence feature */
2954 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
2955
2956 /* enabling the priorities tables */
2957 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
2958 } else {
2959 /* coexistence is disabled */
2960 memset(&coex_cmd, 0, sizeof(coex_cmd));
2961 }
2962 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
2963 sizeof(coex_cmd), &coex_cmd);
2964}
2965EXPORT_SYMBOL(iwl_send_wimax_coex);
2966
20594eb0
WYG		 2967#ifdef CONFIG_IWLWIFI_DEBUGFS
2968
2969#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
2970
2971void iwl_reset_traffic_log(struct iwl_priv *priv)
2972{
2973 priv->tx_traffic_idx = 0;
2974 priv->rx_traffic_idx = 0;
2975 if (priv->tx_traffic)
2976 memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2977 if (priv->rx_traffic)
2978 memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2979}
2980
2981int iwl_alloc_traffic_mem(struct iwl_priv *priv)
2982{
2983 u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
2984
2985 if (iwl_debug_level & IWL_DL_TX) {
2986 if (!priv->tx_traffic) {
2987 priv->tx_traffic =
2988 kzalloc(traffic_size, GFP_KERNEL);
2989 if (!priv->tx_traffic)
2990 return -ENOMEM;
2991 }
2992 }
2993 if (iwl_debug_level & IWL_DL_RX) {
2994 if (!priv->rx_traffic) {
2995 priv->rx_traffic =
2996 kzalloc(traffic_size, GFP_KERNEL);
2997 if (!priv->rx_traffic)
2998 return -ENOMEM;
2999 }
3000 }
3001 iwl_reset_traffic_log(priv);
3002 return 0;
3003}
3004EXPORT_SYMBOL(iwl_alloc_traffic_mem);
3005
3006void iwl_free_traffic_mem(struct iwl_priv *priv)
3007{
3008 kfree(priv->tx_traffic);
3009 priv->tx_traffic = NULL;
3010
3011 kfree(priv->rx_traffic);
3012 priv->rx_traffic = NULL;
3013}
3014EXPORT_SYMBOL(iwl_free_traffic_mem);
3015
3016void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
3017 u16 length, struct ieee80211_hdr *header)
3018{
3019 __le16 fc;
3020 u16 len;
3021
3022 if (likely(!(iwl_debug_level & IWL_DL_TX)))
3023 return;
3024
3025 if (!priv->tx_traffic)
3026 return;
3027
3028 fc = header->frame_control;
3029 if (ieee80211_is_data(fc)) {
3030 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3031 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3032 memcpy((priv->tx_traffic +
3033 (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3034 header, len);
3035 priv->tx_traffic_idx =
3036 (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3037 }
3038}
3039EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
3040
3041void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
3042 u16 length, struct ieee80211_hdr *header)
3043{
3044 __le16 fc;
3045 u16 len;
3046
3047 if (likely(!(iwl_debug_level & IWL_DL_RX)))
3048 return;
3049
3050 if (!priv->rx_traffic)
3051 return;
3052
3053 fc = header->frame_control;
3054 if (ieee80211_is_data(fc)) {
3055 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3056 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3057 memcpy((priv->rx_traffic +
3058 (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3059 header, len);
3060 priv->rx_traffic_idx =
3061 (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3062 }
3063}
3064EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
22fdf3c9
WYG		 3065
3066const char *get_mgmt_string(int cmd)
3067{
3068 switch (cmd) {
3069 IWL_CMD(MANAGEMENT_ASSOC_REQ);
3070 IWL_CMD(MANAGEMENT_ASSOC_RESP);
3071 IWL_CMD(MANAGEMENT_REASSOC_REQ);
3072 IWL_CMD(MANAGEMENT_REASSOC_RESP);
3073 IWL_CMD(MANAGEMENT_PROBE_REQ);
3074 IWL_CMD(MANAGEMENT_PROBE_RESP);
3075 IWL_CMD(MANAGEMENT_BEACON);
3076 IWL_CMD(MANAGEMENT_ATIM);
3077 IWL_CMD(MANAGEMENT_DISASSOC);
3078 IWL_CMD(MANAGEMENT_AUTH);
3079 IWL_CMD(MANAGEMENT_DEAUTH);
3080 IWL_CMD(MANAGEMENT_ACTION);
3081 default:
3082 return "UNKNOWN";
3083
3084 }
3085}
3086
3087const char *get_ctrl_string(int cmd)
3088{
3089 switch (cmd) {
3090 IWL_CMD(CONTROL_BACK_REQ);
3091 IWL_CMD(CONTROL_BACK);
3092 IWL_CMD(CONTROL_PSPOLL);
3093 IWL_CMD(CONTROL_RTS);
3094 IWL_CMD(CONTROL_CTS);
3095 IWL_CMD(CONTROL_ACK);
3096 IWL_CMD(CONTROL_CFEND);
3097 IWL_CMD(CONTROL_CFENDACK);
3098 default:
3099 return "UNKNOWN";
3100
3101 }
3102}
3103
7163b8a4 3104void iwl_clear_traffic_stats(struct iwl_priv *priv)
22fdf3c9
WYG		 3105{
3106 memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
22fdf3c9 3107 memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
7163b8a4 3108 priv->led_tpt = 0;
22fdf3c9
WYG		 3109}
3110
3111/*
3112 * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
3113 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
3114 * Use debugFs to display the rx/rx_statistics
3115 * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
3116 * information will be recorded, but DATA pkt still will be recorded
3117 * for the reason of iwl_led.c need to control the led blinking based on
3118 * number of tx and rx data.
3119 *
3120 */
3121void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
3122{
3123 struct traffic_stats *stats;
3124
3125 if (is_tx)
3126 stats = &priv->tx_stats;
3127 else
3128 stats = &priv->rx_stats;
3129
3130 if (ieee80211_is_mgmt(fc)) {
3131 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3132 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
3133 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
3134 break;
3135 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
3136 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
3137 break;
3138 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
3139 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
3140 break;
3141 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
3142 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
3143 break;
3144 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
3145 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
3146 break;
3147 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
3148 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
3149 break;
3150 case cpu_to_le16(IEEE80211_STYPE_BEACON):
3151 stats->mgmt[MANAGEMENT_BEACON]++;
3152 break;
3153 case cpu_to_le16(IEEE80211_STYPE_ATIM):
3154 stats->mgmt[MANAGEMENT_ATIM]++;
3155 break;
3156 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
3157 stats->mgmt[MANAGEMENT_DISASSOC]++;
3158 break;
3159 case cpu_to_le16(IEEE80211_STYPE_AUTH):
3160 stats->mgmt[MANAGEMENT_AUTH]++;
3161 break;
3162 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
3163 stats->mgmt[MANAGEMENT_DEAUTH]++;
3164 break;
3165 case cpu_to_le16(IEEE80211_STYPE_ACTION):
3166 stats->mgmt[MANAGEMENT_ACTION]++;
3167 break;
3168 }
3169 } else if (ieee80211_is_ctl(fc)) {
3170 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3171 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
3172 stats->ctrl[CONTROL_BACK_REQ]++;
3173 break;
3174 case cpu_to_le16(IEEE80211_STYPE_BACK):
3175 stats->ctrl[CONTROL_BACK]++;
3176 break;
3177 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
3178 stats->ctrl[CONTROL_PSPOLL]++;
3179 break;
3180 case cpu_to_le16(IEEE80211_STYPE_RTS):
3181 stats->ctrl[CONTROL_RTS]++;
3182 break;
3183 case cpu_to_le16(IEEE80211_STYPE_CTS):
3184 stats->ctrl[CONTROL_CTS]++;
3185 break;
3186 case cpu_to_le16(IEEE80211_STYPE_ACK):
3187 stats->ctrl[CONTROL_ACK]++;
3188 break;
3189 case cpu_to_le16(IEEE80211_STYPE_CFEND):
3190 stats->ctrl[CONTROL_CFEND]++;
3191 break;
3192 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
3193 stats->ctrl[CONTROL_CFENDACK]++;
3194 break;
3195 }
3196 } else {
3197 /* data */
3198 stats->data_cnt++;
3199 stats->data_bytes += len;
3200 }
d5f4cf71 3201 iwl_leds_background(priv);
22fdf3c9
WYG		 3202}
3203EXPORT_SYMBOL(iwl_update_stats);
20594eb0
WYG		 3204#endif
3205
696bdee3
WYG		 3206const static char *get_csr_string(int cmd)
3207{
3208 switch (cmd) {
3209 IWL_CMD(CSR_HW_IF_CONFIG_REG);
3210 IWL_CMD(CSR_INT_COALESCING);
3211 IWL_CMD(CSR_INT);
3212 IWL_CMD(CSR_INT_MASK);
3213 IWL_CMD(CSR_FH_INT_STATUS);
3214 IWL_CMD(CSR_GPIO_IN);
3215 IWL_CMD(CSR_RESET);
3216 IWL_CMD(CSR_GP_CNTRL);
3217 IWL_CMD(CSR_HW_REV);
3218 IWL_CMD(CSR_EEPROM_REG);
3219 IWL_CMD(CSR_EEPROM_GP);
3220 IWL_CMD(CSR_OTP_GP_REG);
3221 IWL_CMD(CSR_GIO_REG);
3222 IWL_CMD(CSR_GP_UCODE_REG);
3223 IWL_CMD(CSR_GP_DRIVER_REG);
3224 IWL_CMD(CSR_UCODE_DRV_GP1);
3225 IWL_CMD(CSR_UCODE_DRV_GP2);
3226 IWL_CMD(CSR_LED_REG);
3227 IWL_CMD(CSR_DRAM_INT_TBL_REG);
3228 IWL_CMD(CSR_GIO_CHICKEN_BITS);
3229 IWL_CMD(CSR_ANA_PLL_CFG);
3230 IWL_CMD(CSR_HW_REV_WA_REG);
3231 IWL_CMD(CSR_DBG_HPET_MEM_REG);
3232 default:
3233 return "UNKNOWN";
3234
3235 }
3236}
3237
3238void iwl_dump_csr(struct iwl_priv *priv)
3239{
3240 int i;
3241 u32 csr_tbl[] = {
3242 CSR_HW_IF_CONFIG_REG,
3243 CSR_INT_COALESCING,
3244 CSR_INT,
3245 CSR_INT_MASK,
3246 CSR_FH_INT_STATUS,
3247 CSR_GPIO_IN,
3248 CSR_RESET,
3249 CSR_GP_CNTRL,
3250 CSR_HW_REV,
3251 CSR_EEPROM_REG,
3252 CSR_EEPROM_GP,
3253 CSR_OTP_GP_REG,
3254 CSR_GIO_REG,
3255 CSR_GP_UCODE_REG,
3256 CSR_GP_DRIVER_REG,
3257 CSR_UCODE_DRV_GP1,
3258 CSR_UCODE_DRV_GP2,
3259 CSR_LED_REG,
3260 CSR_DRAM_INT_TBL_REG,
3261 CSR_GIO_CHICKEN_BITS,
3262 CSR_ANA_PLL_CFG,
3263 CSR_HW_REV_WA_REG,
3264 CSR_DBG_HPET_MEM_REG
3265 };
3266 IWL_ERR(priv, "CSR values:\n");
3267 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
3268 "CSR_INT_PERIODIC_REG)\n");
3269 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
3270 IWL_ERR(priv, " %25s: 0X%08x\n",
3271 get_csr_string(csr_tbl[i]),
3272 iwl_read32(priv, csr_tbl[i]));
3273 }
3274}
3275EXPORT_SYMBOL(iwl_dump_csr);
3276
1b3eb823
WYG		 3277const static char *get_fh_string(int cmd)
3278{
3279 switch (cmd) {
3280 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
3281 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
3282 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
3283 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
3284 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
3285 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
3286 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
3287 IWL_CMD(FH_TSSR_TX_STATUS_REG);
3288 IWL_CMD(FH_TSSR_TX_ERROR_REG);
3289 default:
3290 return "UNKNOWN";
3291
3292 }
3293}
3294
3295int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
3296{
3297 int i;
3298#ifdef CONFIG_IWLWIFI_DEBUG
3299 int pos = 0;
3300 size_t bufsz = 0;
3301#endif
3302 u32 fh_tbl[] = {
3303 FH_RSCSR_CHNL0_STTS_WPTR_REG,
3304 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
3305 FH_RSCSR_CHNL0_WPTR,
3306 FH_MEM_RCSR_CHNL0_CONFIG_REG,
3307 FH_MEM_RSSR_SHARED_CTRL_REG,
3308 FH_MEM_RSSR_RX_STATUS_REG,
3309 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
3310 FH_TSSR_TX_STATUS_REG,
3311 FH_TSSR_TX_ERROR_REG
3312 };
3313#ifdef CONFIG_IWLWIFI_DEBUG
3314 if (display) {
3315 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
3316 *buf = kmalloc(bufsz, GFP_KERNEL);
3317 if (!*buf)
3318 return -ENOMEM;
3319 pos += scnprintf(*buf + pos, bufsz - pos,
3320 "FH register values:\n");
3321 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
3322 pos += scnprintf(*buf + pos, bufsz - pos,
3323 " %34s: 0X%08x\n",
3324 get_fh_string(fh_tbl[i]),
3325 iwl_read_direct32(priv, fh_tbl[i]));
3326 }
3327 return pos;
3328 }
3329#endif
3330 IWL_ERR(priv, "FH register values:\n");
3331 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
3332 IWL_ERR(priv, " %34s: 0X%08x\n",
3333 get_fh_string(fh_tbl[i]),
3334 iwl_read_direct32(priv, fh_tbl[i]));
3335 }
3336 return 0;
3337}
3338EXPORT_SYMBOL(iwl_dump_fh);
3339
a93e7973 3340static void iwl_force_rf_reset(struct iwl_priv *priv)
afbdd69a
WYG		 3341{
3342 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3343 return;
3344
3345 if (!iwl_is_associated(priv)) {
3346 IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n");
3347 return;
3348 }
3349 /*
3350 * There is no easy and better way to force reset the radio,
3351 * the only known method is switching channel which will force to
3352 * reset and tune the radio.
3353 * Use internal short scan (single channel) operation to should
3354 * achieve this objective.
3355 * Driver should reset the radio when number of consecutive missed
3356 * beacon, or any other uCode error condition detected.
3357 */
3358 IWL_DEBUG_INFO(priv, "perform radio reset.\n");
3359 iwl_internal_short_hw_scan(priv);
afbdd69a 3360}
a93e7973 3361
a93e7973
WYG		 3362
3363int iwl_force_reset(struct iwl_priv *priv, int mode)
3364{
8a472da4
WYG		 3365 struct iwl_force_reset *force_reset;
3366
a93e7973
WYG		 3367 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3368 return -EINVAL;
3369
8a472da4
WYG		 3370 if (mode >= IWL_MAX_FORCE_RESET) {
3371 IWL_DEBUG_INFO(priv, "invalid reset request.\n");
3372 return -EINVAL;
3373 }
3374 force_reset = &priv->force_reset[mode];
3375 force_reset->reset_request_count++;
3376 if (force_reset->last_force_reset_jiffies &&
3377 time_after(force_reset->last_force_reset_jiffies +
3378 force_reset->reset_duration, jiffies)) {
a93e7973 3379 IWL_DEBUG_INFO(priv, "force reset rejected\n");
8a472da4 3380 force_reset->reset_reject_count++;
a93e7973
WYG		 3381 return -EAGAIN;
3382 }
8a472da4
WYG		 3383 force_reset->reset_success_count++;
3384 force_reset->last_force_reset_jiffies = jiffies;
a93e7973 3385 IWL_DEBUG_INFO(priv, "perform force reset (%d)\n", mode);
a93e7973
WYG		 3386 switch (mode) {
3387 case IWL_RF_RESET:
3388 iwl_force_rf_reset(priv);
3389 break;
3390 case IWL_FW_RESET:
3391 IWL_ERR(priv, "On demand firmware reload\n");
3392 /* Set the FW error flag -- cleared on iwl_down */
3393 set_bit(STATUS_FW_ERROR, &priv->status);
3394 wake_up_interruptible(&priv->wait_command_queue);
3395 /*
3396 * Keep the restart process from trying to send host
3397 * commands by clearing the INIT status bit
3398 */
3399 clear_bit(STATUS_READY, &priv->status);
3400 queue_work(priv->workqueue, &priv->restart);
3401 break;
a93e7973 3402 }
a93e7973
WYG		 3403 return 0;
3404}
afbdd69a 3405
6da3a13e
WYG		 3406#ifdef CONFIG_PM
3407
3408int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3409{
3410 struct iwl_priv *priv = pci_get_drvdata(pdev);
3411
3412 /*
3413 * This function is called when system goes into suspend state
3414 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
3415 * first but since iwl_mac_stop() has no knowledge of who the caller is,
3416 * it will not call apm_ops.stop() to stop the DMA operation.
3417 * Calling apm_ops.stop here to make sure we stop the DMA.
3418 */
3419 priv->cfg->ops->lib->apm_ops.stop(priv);
3420
3421 pci_save_state(pdev);
3422 pci_disable_device(pdev);
3423 pci_set_power_state(pdev, PCI_D3hot);
3424
3425 return 0;
3426}
3427EXPORT_SYMBOL(iwl_pci_suspend);
3428
3429int iwl_pci_resume(struct pci_dev *pdev)
3430{
3431 struct iwl_priv *priv = pci_get_drvdata(pdev);
3432 int ret;
3433
3434 pci_set_power_state(pdev, PCI_D0);
3435 ret = pci_enable_device(pdev);
3436 if (ret)
3437 return ret;
3438 pci_restore_state(pdev);
3439 iwl_enable_interrupts(priv);
3440
3441 return 0;
3442}
3443EXPORT_SYMBOL(iwl_pci_resume);
3444
3445#endif /* CONFIG_PM */
Clone of davem's net-next-2.6 tree