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iwlwifi: sta_id cannot be invalid in rs_initialize_lq
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
d43c36dc 36#include <linux/sched.h>
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37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
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41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
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44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
a3139c59
SO
48#define DRV_NAME "iwlagn"
49
6bc913bd 50#include "iwl-eeprom.h"
3e0d4cb1 51#include "iwl-dev.h"
fee1247a 52#include "iwl-core.h"
3395f6e9 53#include "iwl-io.h"
b481de9c 54#include "iwl-helpers.h"
6974e363 55#include "iwl-sta.h"
f0832f13 56#include "iwl-calib.h"
a1175124 57#include "iwl-agn.h"
b481de9c 58
416e1438 59
b481de9c
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60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
b481de9c
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66/*
67 * module name, copyright, version, etc.
b481de9c 68 */
d783b061 69#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 70
0a6857e7 71#ifdef CONFIG_IWLWIFI_DEBUG
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72#define VD "d"
73#else
74#define VD
75#endif
76
81963d68 77#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 78
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79
80MODULE_DESCRIPTION(DRV_DESCRIPTION);
81MODULE_VERSION(DRV_VERSION);
a7b75207 82MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 83MODULE_LICENSE("GPL");
4fc22b21 84MODULE_ALIAS("iwl4965");
b481de9c 85
b481de9c 86/*************** STATION TABLE MANAGEMENT ****
9fbab516 87 * mac80211 should be examined to determine if sta_info is duplicating
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88 * the functionality provided here
89 */
90
91/**************************************************************/
92
b481de9c 93/**
5b9f8cd3 94 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 95 *
01ebd063 96 * The RXON command in staging_rxon is committed to the hardware and
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97 * the active_rxon structure is updated with the new data. This
98 * function correctly transitions out of the RXON_ASSOC_MSK state if
99 * a HW tune is required based on the RXON structure changes.
100 */
e0158e61 101int iwl_commit_rxon(struct iwl_priv *priv)
b481de9c
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102{
103 /* cast away the const for active_rxon in this function */
c1adf9fb 104 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
105 int ret;
106 bool new_assoc =
107 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 108
fee1247a 109 if (!iwl_is_alive(priv))
43d59b32 110 return -EBUSY;
b481de9c
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111
112 /* always get timestamp with Rx frame */
113 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
114
8ccde88a 115 ret = iwl_check_rxon_cmd(priv);
43d59b32 116 if (ret) {
15b1687c 117 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
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118 return -EINVAL;
119 }
120
0924e519
WYG
121 /*
122 * receive commit_rxon request
123 * abort any previous channel switch if still in process
124 */
125 if (priv->switch_rxon.switch_in_progress &&
126 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
127 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
128 le16_to_cpu(priv->switch_rxon.channel));
129 priv->switch_rxon.switch_in_progress = false;
130 }
131
b481de9c 132 /* If we don't need to send a full RXON, we can use
5b9f8cd3 133 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 134 * and other flags for the current radio configuration. */
54559703 135 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
136 ret = iwl_send_rxon_assoc(priv);
137 if (ret) {
15b1687c 138 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 139 return ret;
b481de9c
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140 }
141
142 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 143 iwl_print_rx_config_cmd(priv);
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144 return 0;
145 }
146
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147 /* If we are currently associated and the new config requires
148 * an RXON_ASSOC and the new config wants the associated mask enabled,
149 * we must clear the associated from the active configuration
150 * before we apply the new config */
43d59b32 151 if (iwl_is_associated(priv) && new_assoc) {
e1623446 152 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
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153 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
154
43d59b32 155 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 156 sizeof(struct iwl_rxon_cmd),
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157 &priv->active_rxon);
158
159 /* If the mask clearing failed then we set
160 * active_rxon back to what it was previously */
43d59b32 161 if (ret) {
b481de9c 162 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 163 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 164 return ret;
b481de9c 165 }
7e246191
RC
166 iwl_clear_ucode_stations(priv, false);
167 iwl_restore_stations(priv);
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168 }
169
e1623446 170 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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171 "* with%s RXON_FILTER_ASSOC_MSK\n"
172 "* channel = %d\n"
e174961c 173 "* bssid = %pM\n",
43d59b32 174 (new_assoc ? "" : "out"),
b481de9c 175 le16_to_cpu(priv->staging_rxon.channel),
e174961c 176 priv->staging_rxon.bssid_addr);
b481de9c 177
90e8e424 178 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
179
180 /* Apply the new configuration
7e246191
RC
181 * RXON unassoc clears the station table in uCode so restoration of
182 * stations is needed after it (the RXON command) completes
43d59b32
EG
183 */
184 if (!new_assoc) {
185 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 186 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 187 if (ret) {
15b1687c 188 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
189 return ret;
190 }
7e246191 191 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON. \n");
43d59b32 192 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
7e246191
RC
193 iwl_clear_ucode_stations(priv, false);
194 iwl_restore_stations(priv);
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195 }
196
19cc1087 197 priv->start_calib = 0;
9185159d 198 if (new_assoc) {
47eef9bd
WYG
199 /*
200 * allow CTS-to-self if possible for new association.
201 * this is relevant only for 5000 series and up,
202 * but will not damage 4965
203 */
204 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
205
43d59b32
EG
206 /* Apply the new configuration
207 * RXON assoc doesn't clear the station table in uCode,
208 */
209 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
210 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
211 if (ret) {
15b1687c 212 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
213 return ret;
214 }
215 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 216 }
a643565e 217 iwl_print_rx_config_cmd(priv);
b481de9c 218
36da7d70
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219 iwl_init_sensitivity(priv);
220
221 /* If we issue a new RXON command which required a tune then we must
222 * send a new TXPOWER command or we won't be able to Tx any frames */
223 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
224 if (ret) {
15b1687c 225 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY
226 return ret;
227 }
228
b481de9c
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229 return 0;
230}
231
5b9f8cd3 232void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
233{
234
45823531
AK
235 if (priv->cfg->ops->hcmd->set_rxon_chain)
236 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 237 iwlcore_commit_rxon(priv);
5da4b55f
MA
238}
239
fcab423d 240static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
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241{
242 struct list_head *element;
243
e1623446 244 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
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245 priv->frames_count);
246
247 while (!list_empty(&priv->free_frames)) {
248 element = priv->free_frames.next;
249 list_del(element);
fcab423d 250 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
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251 priv->frames_count--;
252 }
253
254 if (priv->frames_count) {
39aadf8c 255 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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256 priv->frames_count);
257 priv->frames_count = 0;
258 }
259}
260
fcab423d 261static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 262{
fcab423d 263 struct iwl_frame *frame;
b481de9c
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264 struct list_head *element;
265 if (list_empty(&priv->free_frames)) {
266 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
267 if (!frame) {
15b1687c 268 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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269 return NULL;
270 }
271
272 priv->frames_count++;
273 return frame;
274 }
275
276 element = priv->free_frames.next;
277 list_del(element);
fcab423d 278 return list_entry(element, struct iwl_frame, list);
b481de9c
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279}
280
fcab423d 281static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
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282{
283 memset(frame, 0, sizeof(*frame));
284 list_add(&frame->list, &priv->free_frames);
285}
286
47ff65c4 287static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 288 struct ieee80211_hdr *hdr,
73ec1cc2 289 int left)
b481de9c 290{
3109ece1 291 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
292 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
293 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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294 return 0;
295
296 if (priv->ibss_beacon->len > left)
297 return 0;
298
299 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
300
301 return priv->ibss_beacon->len;
302}
303
47ff65c4
DH
304/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
305static void iwl_set_beacon_tim(struct iwl_priv *priv,
306 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
307 u8 *beacon, u32 frame_size)
308{
309 u16 tim_idx;
310 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
311
312 /*
313 * The index is relative to frame start but we start looking at the
314 * variable-length part of the beacon.
315 */
316 tim_idx = mgmt->u.beacon.variable - beacon;
317
318 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
319 while ((tim_idx < (frame_size - 2)) &&
320 (beacon[tim_idx] != WLAN_EID_TIM))
321 tim_idx += beacon[tim_idx+1] + 2;
322
323 /* If TIM field was found, set variables */
324 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
325 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
326 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
327 } else
328 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
329}
330
5b9f8cd3 331static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 332 struct iwl_frame *frame)
4bf64efd
TW
333{
334 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH
335 u32 frame_size;
336 u32 rate_flags;
337 u32 rate;
338 /*
339 * We have to set up the TX command, the TX Beacon command, and the
340 * beacon contents.
341 */
4bf64efd 342
47ff65c4 343 /* Initialize memory */
4bf64efd
TW
344 tx_beacon_cmd = &frame->u.beacon;
345 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
346
47ff65c4 347 /* Set up TX beacon contents */
4bf64efd 348 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 349 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH
350 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
351 return 0;
4bf64efd 352
47ff65c4 353 /* Set up TX command fields */
4bf64efd 354 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH
355 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
356 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
357 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
358 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 359
47ff65c4
DH
360 /* Set up TX beacon command fields */
361 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
362 frame_size);
4bf64efd 363
47ff65c4
DH
364 /* Set up packet rate and flags */
365 rate = iwl_rate_get_lowest_plcp(priv);
366 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
367 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
368 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
369 rate_flags |= RATE_MCS_CCK_MSK;
370 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
371 rate_flags);
4bf64efd
TW
372
373 return sizeof(*tx_beacon_cmd) + frame_size;
374}
5b9f8cd3 375static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 376{
fcab423d 377 struct iwl_frame *frame;
b481de9c
ZY
378 unsigned int frame_size;
379 int rc;
b481de9c 380
fcab423d 381 frame = iwl_get_free_frame(priv);
b481de9c 382 if (!frame) {
15b1687c 383 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
384 "command.\n");
385 return -ENOMEM;
386 }
387
47ff65c4
DH
388 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
389 if (!frame_size) {
390 IWL_ERR(priv, "Error configuring the beacon command\n");
391 iwl_free_frame(priv, frame);
392 return -EINVAL;
393 }
b481de9c 394
857485c0 395 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
396 &frame->u.cmd[0]);
397
fcab423d 398 iwl_free_frame(priv, frame);
b481de9c
ZY
399
400 return rc;
401}
402
7aaa1d79
SO
403static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
404{
405 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
406
407 dma_addr_t addr = get_unaligned_le32(&tb->lo);
408 if (sizeof(dma_addr_t) > sizeof(u32))
409 addr |=
410 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
411
412 return addr;
413}
414
415static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
416{
417 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
418
419 return le16_to_cpu(tb->hi_n_len) >> 4;
420}
421
422static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
423 dma_addr_t addr, u16 len)
424{
425 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
426 u16 hi_n_len = len << 4;
427
428 put_unaligned_le32(addr, &tb->lo);
429 if (sizeof(dma_addr_t) > sizeof(u32))
430 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
431
432 tb->hi_n_len = cpu_to_le16(hi_n_len);
433
434 tfd->num_tbs = idx + 1;
435}
436
437static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
438{
439 return tfd->num_tbs & 0x1f;
440}
441
442/**
443 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
444 * @priv - driver private data
445 * @txq - tx queue
446 *
447 * Does NOT advance any TFD circular buffer read/write indexes
448 * Does NOT free the TFD itself (which is within circular buffer)
449 */
450void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
451{
59606ffa 452 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
453 struct iwl_tfd *tfd;
454 struct pci_dev *dev = priv->pci_dev;
455 int index = txq->q.read_ptr;
456 int i;
457 int num_tbs;
458
459 tfd = &tfd_tmp[index];
460
461 /* Sanity check on number of chunks */
462 num_tbs = iwl_tfd_get_num_tbs(tfd);
463
464 if (num_tbs >= IWL_NUM_OF_TBS) {
465 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
466 /* @todo issue fatal error, it is quite serious situation */
467 return;
468 }
469
470 /* Unmap tx_cmd */
471 if (num_tbs)
472 pci_unmap_single(dev,
c2acea8e
JB
473 pci_unmap_addr(&txq->meta[index], mapping),
474 pci_unmap_len(&txq->meta[index], len),
96891cee 475 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
476
477 /* Unmap chunks, if any. */
478 for (i = 1; i < num_tbs; i++) {
479 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
480 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
481
482 if (txq->txb) {
483 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
484 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
485 }
486 }
487}
488
489int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
490 struct iwl_tx_queue *txq,
491 dma_addr_t addr, u16 len,
492 u8 reset, u8 pad)
493{
494 struct iwl_queue *q;
59606ffa 495 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
496 u32 num_tbs;
497
498 q = &txq->q;
59606ffa
SO
499 tfd_tmp = (struct iwl_tfd *)txq->tfds;
500 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
501
502 if (reset)
503 memset(tfd, 0, sizeof(*tfd));
504
505 num_tbs = iwl_tfd_get_num_tbs(tfd);
506
507 /* Each TFD can point to a maximum 20 Tx buffers */
508 if (num_tbs >= IWL_NUM_OF_TBS) {
509 IWL_ERR(priv, "Error can not send more than %d chunks\n",
510 IWL_NUM_OF_TBS);
511 return -EINVAL;
512 }
513
514 BUG_ON(addr & ~DMA_BIT_MASK(36));
515 if (unlikely(addr & ~IWL_TX_DMA_MASK))
516 IWL_ERR(priv, "Unaligned address = %llx\n",
517 (unsigned long long)addr);
518
519 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
520
521 return 0;
522}
523
a8e74e27
SO
524/*
525 * Tell nic where to find circular buffer of Tx Frame Descriptors for
526 * given Tx queue, and enable the DMA channel used for that queue.
527 *
528 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
529 * channels supported in hardware.
530 */
531int iwl_hw_tx_queue_init(struct iwl_priv *priv,
532 struct iwl_tx_queue *txq)
533{
a8e74e27
SO
534 int txq_id = txq->q.id;
535
a8e74e27
SO
536 /* Circular buffer (TFD queue in DRAM) physical base address */
537 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
538 txq->q.dma_addr >> 8);
539
a8e74e27
SO
540 return 0;
541}
542
b481de9c
ZY
543/******************************************************************************
544 *
545 * Generic RX handler implementations
546 *
547 ******************************************************************************/
885ba202
TW
548static void iwl_rx_reply_alive(struct iwl_priv *priv,
549 struct iwl_rx_mem_buffer *rxb)
b481de9c 550{
2f301227 551 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 552 struct iwl_alive_resp *palive;
b481de9c
ZY
553 struct delayed_work *pwork;
554
555 palive = &pkt->u.alive_frame;
556
e1623446 557 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
558 "0x%01X 0x%01X\n",
559 palive->is_valid, palive->ver_type,
560 palive->ver_subtype);
561
562 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 563 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
564 memcpy(&priv->card_alive_init,
565 &pkt->u.alive_frame,
885ba202 566 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
567 pwork = &priv->init_alive_start;
568 } else {
e1623446 569 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 570 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 571 sizeof(struct iwl_alive_resp));
b481de9c
ZY
572 pwork = &priv->alive_start;
573 }
574
575 /* We delay the ALIVE response by 5ms to
576 * give the HW RF Kill time to activate... */
577 if (palive->is_valid == UCODE_VALID_OK)
578 queue_delayed_work(priv->workqueue, pwork,
579 msecs_to_jiffies(5));
580 else
39aadf8c 581 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
582}
583
5b9f8cd3 584static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 585{
c79dd5b5
TW
586 struct iwl_priv *priv =
587 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
588 struct sk_buff *beacon;
589
590 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 591 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
592
593 if (!beacon) {
15b1687c 594 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
595 return;
596 }
597
598 mutex_lock(&priv->mutex);
599 /* new beacon skb is allocated every time; dispose previous.*/
600 if (priv->ibss_beacon)
601 dev_kfree_skb(priv->ibss_beacon);
602
603 priv->ibss_beacon = beacon;
604 mutex_unlock(&priv->mutex);
605
5b9f8cd3 606 iwl_send_beacon_cmd(priv);
b481de9c
ZY
607}
608
4e39317d 609/**
5b9f8cd3 610 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
611 *
612 * This callback is provided in order to send a statistics request.
613 *
614 * This timer function is continually reset to execute within
615 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
616 * was received. We need to ensure we receive the statistics in order
617 * to update the temperature used for calibrating the TXPOWER.
618 */
5b9f8cd3 619static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
620{
621 struct iwl_priv *priv = (struct iwl_priv *)data;
622
623 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
624 return;
625
61780ee3
MA
626 /* dont send host command if rf-kill is on */
627 if (!iwl_is_ready_rf(priv))
628 return;
629
ef8d5529 630 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG
631}
632
a9e1cb6a
WYG
633
634static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
635 u32 start_idx, u32 num_events,
636 u32 mode)
637{
638 u32 i;
639 u32 ptr; /* SRAM byte address of log data */
640 u32 ev, time, data; /* event log data */
641 unsigned long reg_flags;
642
643 if (mode == 0)
644 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
645 else
646 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
647
648 /* Make sure device is powered up for SRAM reads */
649 spin_lock_irqsave(&priv->reg_lock, reg_flags);
650 if (iwl_grab_nic_access(priv)) {
651 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
652 return;
653 }
654
655 /* Set starting address; reads will auto-increment */
656 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
657 rmb();
658
659 /*
660 * "time" is actually "data" for mode 0 (no timestamp).
661 * place event id # at far right for easier visual parsing.
662 */
663 for (i = 0; i < num_events; i++) {
664 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
665 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
666 if (mode == 0) {
667 trace_iwlwifi_dev_ucode_cont_event(priv,
668 0, time, ev);
669 } else {
670 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
671 trace_iwlwifi_dev_ucode_cont_event(priv,
672 time, data, ev);
673 }
674 }
675 /* Allow device to power down */
676 iwl_release_nic_access(priv);
677 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
678}
679
875295f1 680static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG
681{
682 u32 capacity; /* event log capacity in # entries */
683 u32 base; /* SRAM byte address of event log header */
684 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
685 u32 num_wraps; /* # times uCode wrapped to top of log */
686 u32 next_entry; /* index of next entry to be written by uCode */
687
688 if (priv->ucode_type == UCODE_INIT)
689 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
690 else
691 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
692 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
693 capacity = iwl_read_targ_mem(priv, base);
694 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
695 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
696 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
697 } else
698 return;
699
700 if (num_wraps == priv->event_log.num_wraps) {
701 iwl_print_cont_event_trace(priv,
702 base, priv->event_log.next_entry,
703 next_entry - priv->event_log.next_entry,
704 mode);
705 priv->event_log.non_wraps_count++;
706 } else {
707 if ((num_wraps - priv->event_log.num_wraps) > 1)
708 priv->event_log.wraps_more_count++;
709 else
710 priv->event_log.wraps_once_count++;
711 trace_iwlwifi_dev_ucode_wrap_event(priv,
712 num_wraps - priv->event_log.num_wraps,
713 next_entry, priv->event_log.next_entry);
714 if (next_entry < priv->event_log.next_entry) {
715 iwl_print_cont_event_trace(priv, base,
716 priv->event_log.next_entry,
717 capacity - priv->event_log.next_entry,
718 mode);
719
720 iwl_print_cont_event_trace(priv, base, 0,
721 next_entry, mode);
722 } else {
723 iwl_print_cont_event_trace(priv, base,
724 next_entry, capacity - next_entry,
725 mode);
726
727 iwl_print_cont_event_trace(priv, base, 0,
728 next_entry, mode);
729 }
730 }
731 priv->event_log.num_wraps = num_wraps;
732 priv->event_log.next_entry = next_entry;
733}
734
735/**
736 * iwl_bg_ucode_trace - Timer callback to log ucode event
737 *
738 * The timer is continually set to execute every
739 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
740 * this function is to perform continuous uCode event logging operation
741 * if enabled
742 */
743static void iwl_bg_ucode_trace(unsigned long data)
744{
745 struct iwl_priv *priv = (struct iwl_priv *)data;
746
747 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
748 return;
749
750 if (priv->event_log.ucode_trace) {
751 iwl_continuous_event_trace(priv);
752 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
753 mod_timer(&priv->ucode_trace,
754 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
755 }
756}
757
5b9f8cd3 758static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 759 struct iwl_rx_mem_buffer *rxb)
b481de9c 760{
0a6857e7 761#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 762 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW
763 struct iwl4965_beacon_notif *beacon =
764 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 765 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 766
e1623446 767 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 768 "tsf %d %d rate %d\n",
25a6572c 769 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
770 beacon->beacon_notify_hdr.failure_frame,
771 le32_to_cpu(beacon->ibss_mgr_status),
772 le32_to_cpu(beacon->high_tsf),
773 le32_to_cpu(beacon->low_tsf), rate);
774#endif
775
05c914fe 776 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
777 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
778 queue_work(priv->workqueue, &priv->beacon_update);
779}
780
b481de9c
ZY
781/* Handle notification from uCode that card's power state is changing
782 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 783static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 784 struct iwl_rx_mem_buffer *rxb)
b481de9c 785{
2f301227 786 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
787 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
788 unsigned long status = priv->status;
789
3a41bbd5 790 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 791 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG
792 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
793 (flags & CT_CARD_DISABLED) ?
794 "Reached" : "Not reached");
b481de9c
ZY
795
796 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 797 CT_CARD_DISABLED)) {
b481de9c 798
3395f6e9 799 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
800 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
801
a8b50a0a
MA
802 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
803 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
804
805 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 806 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 807 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 808 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 809 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 810 }
3a41bbd5 811 if (flags & CT_CARD_DISABLED)
39b73fb1 812 iwl_tt_enter_ct_kill(priv);
b481de9c 813 }
3a41bbd5 814 if (!(flags & CT_CARD_DISABLED))
39b73fb1 815 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
816
817 if (flags & HW_CARD_DISABLED)
818 set_bit(STATUS_RF_KILL_HW, &priv->status);
819 else
820 clear_bit(STATUS_RF_KILL_HW, &priv->status);
821
822
b481de9c 823 if (!(flags & RXON_CARD_DISABLED))
2a421b91 824 iwl_scan_cancel(priv);
b481de9c
ZY
825
826 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
827 test_bit(STATUS_RF_KILL_HW, &priv->status)))
828 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
829 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
830 else
831 wake_up_interruptible(&priv->wait_command_queue);
832}
833
5b9f8cd3 834int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 835{
e2e3c57b 836 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 837 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
838 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
839 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
840 ~APMG_PS_CTRL_MSK_PWR_SRC);
841 } else {
842 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
843 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
844 ~APMG_PS_CTRL_MSK_PWR_SRC);
845 }
846
a8b50a0a 847 return 0;
e2e3c57b
TW
848}
849
b481de9c 850/**
5b9f8cd3 851 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
852 *
853 * Setup the RX handlers for each of the reply types sent from the uCode
854 * to the host.
855 *
856 * This function chains into the hardware specific files for them to setup
857 * any hardware specific handlers as well.
858 */
653fa4a0 859static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 860{
885ba202 861 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
862 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
863 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC
864 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
865 iwl_rx_spectrum_measure_notif;
5b9f8cd3 866 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 867 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
868 iwl_rx_pm_debug_statistics_notif;
869 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 870
9fbab516
BC
871 /*
872 * The same handler is used for both the REPLY to a discrete
873 * statistics request from the host as well as for the periodic
874 * statistics notifications (after received beacons) from the uCode.
b481de9c 875 */
ef8d5529 876 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 877 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW
878
879 iwl_setup_rx_scan_handlers(priv);
880
37a44211 881 /* status change handler */
5b9f8cd3 882 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 883
c1354754
TW
884 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
885 iwl_rx_missed_beacon_notif;
37a44211 886 /* Rx handlers */
1781a07f
EG
887 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
888 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
889 /* block ack */
890 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 891 /* Set up hardware specific Rx handlers */
d4789efe 892 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
893}
894
b481de9c 895/**
a55360e4 896 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
897 *
898 * Uses the priv->rx_handlers callback function array to invoke
899 * the appropriate handlers, including command responses,
900 * frame-received notifications, and other notifications.
901 */
a55360e4 902void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 903{
a55360e4 904 struct iwl_rx_mem_buffer *rxb;
db11d634 905 struct iwl_rx_packet *pkt;
a55360e4 906 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
907 u32 r, i;
908 int reclaim;
909 unsigned long flags;
5c0eef96 910 u8 fill_rx = 0;
d68ab680 911 u32 count = 8;
4752c93c 912 int total_empty;
b481de9c 913
6440adb5
BC
914 /* uCode's read index (stored in shared DRAM) indicates the last Rx
915 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 916 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
917 i = rxq->read;
918
919 /* Rx interrupt, but nothing sent from uCode */
920 if (i == r)
e1623446 921 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 922
4752c93c 923 /* calculate total frames need to be restock after handling RX */
7300515d 924 total_empty = r - rxq->write_actual;
4752c93c
MA
925 if (total_empty < 0)
926 total_empty += RX_QUEUE_SIZE;
927
928 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
929 fill_rx = 1;
930
b481de9c
ZY
931 while (i != r) {
932 rxb = rxq->queue[i];
933
9fbab516 934 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
935 * then a bug has been introduced in the queue refilling
936 * routines -- catch it here */
937 BUG_ON(rxb == NULL);
938
939 rxq->queue[i] = NULL;
940
2f301227
ZY
941 pci_unmap_page(priv->pci_dev, rxb->page_dma,
942 PAGE_SIZE << priv->hw_params.rx_page_order,
943 PCI_DMA_FROMDEVICE);
944 pkt = rxb_addr(rxb);
b481de9c 945
be1a71a1
JB
946 trace_iwlwifi_dev_rx(priv, pkt,
947 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
948
b481de9c
ZY
949 /* Reclaim a command buffer only if this packet is a response
950 * to a (driver-originated) command.
951 * If the packet (e.g. Rx frame) originated from uCode,
952 * there is no command buffer to reclaim.
953 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
954 * but apparently a few don't get set; catch them here. */
955 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
956 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 957 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 958 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 959 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
960 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
961 (pkt->hdr.cmd != REPLY_TX);
962
963 /* Based on type of command response or notification,
964 * handle those that need handling via function in
5b9f8cd3 965 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 966 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 967 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 968 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 969 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 970 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
971 } else {
972 /* No handling needed */
e1623446 973 IWL_DEBUG_RX(priv,
b481de9c
ZY
974 "r %d i %d No handler needed for %s, 0x%02x\n",
975 r, i, get_cmd_string(pkt->hdr.cmd),
976 pkt->hdr.cmd);
977 }
978
29b1b268
ZY
979 /*
980 * XXX: After here, we should always check rxb->page
981 * against NULL before touching it or its virtual
982 * memory (pkt). Because some rx_handler might have
983 * already taken or freed the pages.
984 */
985
b481de9c 986 if (reclaim) {
2f301227
ZY
987 /* Invoke any callbacks, transfer the buffer to caller,
988 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 989 * as we reclaim the driver command queue */
29b1b268 990 if (rxb->page)
17b88929 991 iwl_tx_cmd_complete(priv, rxb);
b481de9c 992 else
39aadf8c 993 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
994 }
995
7300515d
ZY
996 /* Reuse the page if possible. For notification packets and
997 * SKBs that fail to Rx correctly, add them back into the
998 * rx_free list for reuse later. */
999 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1000 if (rxb->page != NULL) {
7300515d
ZY
1001 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1002 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1003 PCI_DMA_FROMDEVICE);
1004 list_add_tail(&rxb->list, &rxq->rx_free);
1005 rxq->free_count++;
1006 } else
1007 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1008
b481de9c 1009 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1010
b481de9c 1011 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1012 /* If there are a lot of unused frames,
1013 * restock the Rx queue so ucode wont assert. */
1014 if (fill_rx) {
1015 count++;
1016 if (count >= 8) {
7300515d 1017 rxq->read = i;
4752c93c 1018 iwl_rx_replenish_now(priv);
5c0eef96
MA
1019 count = 0;
1020 }
1021 }
b481de9c
ZY
1022 }
1023
1024 /* Backtrack one entry */
7300515d 1025 rxq->read = i;
4752c93c
MA
1026 if (fill_rx)
1027 iwl_rx_replenish_now(priv);
1028 else
1029 iwl_rx_queue_restock(priv);
a55360e4 1030}
a55360e4 1031
0359facc
MA
1032/* call this function to flush any scheduled tasklet */
1033static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1034{
a96a27f9 1035 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1036 synchronize_irq(priv->pci_dev->irq);
1037 tasklet_kill(&priv->irq_tasklet);
1038}
1039
ef850d7c 1040static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
1041{
1042 u32 inta, handled = 0;
1043 u32 inta_fh;
1044 unsigned long flags;
c2e61da2 1045 u32 i;
0a6857e7 1046#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1047 u32 inta_mask;
1048#endif
1049
1050 spin_lock_irqsave(&priv->lock, flags);
1051
1052 /* Ack/clear/reset pending uCode interrupts.
1053 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1054 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
1055 inta = iwl_read32(priv, CSR_INT);
1056 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1057
1058 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1059 * Any new interrupts that happen after this, either while we're
1060 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
1061 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1062 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1063
0a6857e7 1064#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1065 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1066 /* just for debug */
3395f6e9 1067 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1068 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1069 inta, inta_mask, inta_fh);
1070 }
1071#endif
1072
2f301227
ZY
1073 spin_unlock_irqrestore(&priv->lock, flags);
1074
b481de9c
ZY
1075 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1076 * atomic, make sure that inta covers all the interrupts that
1077 * we've discovered, even if FH interrupt came in just after
1078 * reading CSR_INT. */
6f83eaa1 1079 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1080 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1081 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
1082 inta |= CSR_INT_BIT_FH_TX;
1083
1084 /* Now service all interrupt bits discovered above. */
1085 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1086 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1087
1088 /* Tell the device to stop sending interrupts */
5b9f8cd3 1089 iwl_disable_interrupts(priv);
b481de9c 1090
a83b9141 1091 priv->isr_stats.hw++;
5b9f8cd3 1092 iwl_irq_handle_error(priv);
b481de9c
ZY
1093
1094 handled |= CSR_INT_BIT_HW_ERR;
1095
b481de9c
ZY
1096 return;
1097 }
1098
0a6857e7 1099#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1100 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1101 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1102 if (inta & CSR_INT_BIT_SCD) {
e1623446 1103 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1104 "the frame/frames.\n");
a83b9141
WYG
1105 priv->isr_stats.sch++;
1106 }
b481de9c
ZY
1107
1108 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1109 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1110 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
1111 priv->isr_stats.alive++;
1112 }
b481de9c
ZY
1113 }
1114#endif
1115 /* Safely ignore these bits for debug checks below */
25c03d8e 1116 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1117
9fbab516 1118 /* HW RF KILL switch toggled */
b481de9c
ZY
1119 if (inta & CSR_INT_BIT_RF_KILL) {
1120 int hw_rf_kill = 0;
3395f6e9 1121 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
1122 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1123 hw_rf_kill = 1;
1124
4c423a2b 1125 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1126 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1127
a83b9141
WYG
1128 priv->isr_stats.rfkill++;
1129
a9efa652 1130 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
1131 * the driver allows loading the ucode even if the radio
1132 * is killed. Hence update the killswitch state here. The
1133 * rfkill handler will care about restarting if needed.
a9efa652 1134 */
6cd0b1cb
HS
1135 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1136 if (hw_rf_kill)
1137 set_bit(STATUS_RF_KILL_HW, &priv->status);
1138 else
1139 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1140 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1141 }
b481de9c
ZY
1142
1143 handled |= CSR_INT_BIT_RF_KILL;
1144 }
1145
9fbab516 1146 /* Chip got too hot and stopped itself */
b481de9c 1147 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1148 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1149 priv->isr_stats.ctkill++;
b481de9c
ZY
1150 handled |= CSR_INT_BIT_CT_KILL;
1151 }
1152
1153 /* Error detected by uCode */
1154 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1155 IWL_ERR(priv, "Microcode SW error detected. "
1156 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1157 priv->isr_stats.sw++;
1158 priv->isr_stats.sw_err = inta;
5b9f8cd3 1159 iwl_irq_handle_error(priv);
b481de9c
ZY
1160 handled |= CSR_INT_BIT_SW_ERR;
1161 }
1162
c2e61da2
BC
1163 /*
1164 * uCode wakes up after power-down sleep.
1165 * Tell device about any new tx or host commands enqueued,
1166 * and about any Rx buffers made available while asleep.
1167 */
b481de9c 1168 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1169 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1170 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC
1171 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1172 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1173 priv->isr_stats.wakeup++;
b481de9c
ZY
1174 handled |= CSR_INT_BIT_WAKEUP;
1175 }
1176
1177 /* All uCode command responses, including Tx command responses,
1178 * Rx "responses" (frame-received notification), and other
1179 * notifications from uCode come through here*/
1180 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1181 iwl_rx_handle(priv);
a83b9141 1182 priv->isr_stats.rx++;
b481de9c
ZY
1183 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1184 }
1185
c72cd19f 1186 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1187 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1188 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1189 priv->isr_stats.tx++;
b481de9c 1190 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1191 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR
1192 priv->ucode_write_complete = 1;
1193 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1194 }
1195
a83b9141 1196 if (inta & ~handled) {
15b1687c 1197 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1198 priv->isr_stats.unhandled++;
1199 }
b481de9c 1200
40cefda9 1201 if (inta & ~(priv->inta_mask)) {
39aadf8c 1202 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1203 inta & ~priv->inta_mask);
39aadf8c 1204 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1205 }
1206
1207 /* Re-enable all interrupts */
0359facc
MA
1208 /* only Re-enable if diabled by irq */
1209 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1210 iwl_enable_interrupts(priv);
b481de9c 1211
0a6857e7 1212#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1213 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1214 inta = iwl_read32(priv, CSR_INT);
1215 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1216 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1217 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1218 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1219 }
1220#endif
b481de9c
ZY
1221}
1222
ef850d7c
MA
1223/* tasklet for iwlagn interrupt */
1224static void iwl_irq_tasklet(struct iwl_priv *priv)
1225{
1226 u32 inta = 0;
1227 u32 handled = 0;
1228 unsigned long flags;
8756990f 1229 u32 i;
ef850d7c
MA
1230#ifdef CONFIG_IWLWIFI_DEBUG
1231 u32 inta_mask;
1232#endif
1233
1234 spin_lock_irqsave(&priv->lock, flags);
1235
1236 /* Ack/clear/reset pending uCode interrupts.
1237 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1238 */
a4c8b2a6 1239 iwl_write32(priv, CSR_INT, priv->_agn.inta);
ef850d7c 1240
a4c8b2a6 1241 inta = priv->_agn.inta;
ef850d7c
MA
1242
1243#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1244 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1245 /* just for debug */
1246 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1247 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1248 inta, inta_mask);
1249 }
1250#endif
2f301227
ZY
1251
1252 spin_unlock_irqrestore(&priv->lock, flags);
1253
a4c8b2a6
JB
1254 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1255 priv->_agn.inta = 0;
ef850d7c
MA
1256
1257 /* Now service all interrupt bits discovered above. */
1258 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1259 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1260
1261 /* Tell the device to stop sending interrupts */
1262 iwl_disable_interrupts(priv);
1263
1264 priv->isr_stats.hw++;
1265 iwl_irq_handle_error(priv);
1266
1267 handled |= CSR_INT_BIT_HW_ERR;
1268
ef850d7c
MA
1269 return;
1270 }
1271
1272#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1273 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1274 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1275 if (inta & CSR_INT_BIT_SCD) {
1276 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1277 "the frame/frames.\n");
1278 priv->isr_stats.sch++;
1279 }
1280
1281 /* Alive notification via Rx interrupt will do the real work */
1282 if (inta & CSR_INT_BIT_ALIVE) {
1283 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1284 priv->isr_stats.alive++;
1285 }
1286 }
1287#endif
1288 /* Safely ignore these bits for debug checks below */
1289 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1290
1291 /* HW RF KILL switch toggled */
1292 if (inta & CSR_INT_BIT_RF_KILL) {
1293 int hw_rf_kill = 0;
1294 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1295 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1296 hw_rf_kill = 1;
1297
4c423a2b 1298 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1299 hw_rf_kill ? "disable radio" : "enable radio");
1300
1301 priv->isr_stats.rfkill++;
1302
1303 /* driver only loads ucode once setting the interface up.
1304 * the driver allows loading the ucode even if the radio
1305 * is killed. Hence update the killswitch state here. The
1306 * rfkill handler will care about restarting if needed.
1307 */
1308 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1309 if (hw_rf_kill)
1310 set_bit(STATUS_RF_KILL_HW, &priv->status);
1311 else
1312 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1313 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1314 }
1315
1316 handled |= CSR_INT_BIT_RF_KILL;
1317 }
1318
1319 /* Chip got too hot and stopped itself */
1320 if (inta & CSR_INT_BIT_CT_KILL) {
1321 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1322 priv->isr_stats.ctkill++;
1323 handled |= CSR_INT_BIT_CT_KILL;
1324 }
1325
1326 /* Error detected by uCode */
1327 if (inta & CSR_INT_BIT_SW_ERR) {
1328 IWL_ERR(priv, "Microcode SW error detected. "
1329 " Restarting 0x%X.\n", inta);
1330 priv->isr_stats.sw++;
1331 priv->isr_stats.sw_err = inta;
1332 iwl_irq_handle_error(priv);
1333 handled |= CSR_INT_BIT_SW_ERR;
1334 }
1335
1336 /* uCode wakes up after power-down sleep */
1337 if (inta & CSR_INT_BIT_WAKEUP) {
1338 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1339 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC
1340 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1341 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA
1342
1343 priv->isr_stats.wakeup++;
1344
1345 handled |= CSR_INT_BIT_WAKEUP;
1346 }
1347
1348 /* All uCode command responses, including Tx command responses,
1349 * Rx "responses" (frame-received notification), and other
1350 * notifications from uCode come through here*/
40cefda9
MA
1351 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1352 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1353 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1354 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1355 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1356 iwl_write32(priv, CSR_FH_INT_STATUS,
1357 CSR49_FH_INT_RX_MASK);
1358 }
1359 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1360 handled |= CSR_INT_BIT_RX_PERIODIC;
1361 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1362 }
1363 /* Sending RX interrupt require many steps to be done in the
1364 * the device:
1365 * 1- write interrupt to current index in ICT table.
1366 * 2- dma RX frame.
1367 * 3- update RX shared data to indicate last write index.
1368 * 4- send interrupt.
1369 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC
1370 * but the shared data changes does not reflect this;
1371 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1372 */
74ba67ed
BC
1373
1374 /* Disable periodic interrupt; we use it as just a one-shot. */
1375 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1376 CSR_INT_PERIODIC_DIS);
ef850d7c 1377 iwl_rx_handle(priv);
74ba67ed
BC
1378
1379 /*
1380 * Enable periodic interrupt in 8 msec only if we received
1381 * real RX interrupt (instead of just periodic int), to catch
1382 * any dangling Rx interrupt. If it was just the periodic
1383 * interrupt, there was no dangling Rx activity, and no need
1384 * to extend the periodic interrupt; one-shot is enough.
1385 */
40cefda9 1386 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1387 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA
1388 CSR_INT_PERIODIC_ENA);
1389
ef850d7c 1390 priv->isr_stats.rx++;
ef850d7c
MA
1391 }
1392
c72cd19f 1393 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA
1394 if (inta & CSR_INT_BIT_FH_TX) {
1395 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1396 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA
1397 priv->isr_stats.tx++;
1398 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1399 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA
1400 priv->ucode_write_complete = 1;
1401 wake_up_interruptible(&priv->wait_command_queue);
1402 }
1403
1404 if (inta & ~handled) {
1405 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1406 priv->isr_stats.unhandled++;
1407 }
1408
40cefda9 1409 if (inta & ~(priv->inta_mask)) {
ef850d7c 1410 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1411 inta & ~priv->inta_mask);
ef850d7c
MA
1412 }
1413
ef850d7c
MA
1414 /* Re-enable all interrupts */
1415 /* only Re-enable if diabled by irq */
1416 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1417 iwl_enable_interrupts(priv);
ef850d7c
MA
1418}
1419
a83b9141 1420
b481de9c
ZY
1421/******************************************************************************
1422 *
1423 * uCode download functions
1424 *
1425 ******************************************************************************/
1426
5b9f8cd3 1427static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1428{
98c92211
TW
1429 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1430 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1431 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1432 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1433 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1434 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1435}
1436
5b9f8cd3 1437static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1438{
1439 /* Remove all resets to allow NIC to operate */
1440 iwl_write32(priv, CSR_RESET, 0);
1441}
1442
1443
b08dfd04
JB
1444static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1445static int iwl_mac_setup_register(struct iwl_priv *priv);
1446
1447static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1448{
1449 const char *name_pre = priv->cfg->fw_name_pre;
1450
1451 if (first)
1452 priv->fw_index = priv->cfg->ucode_api_max;
1453 else
1454 priv->fw_index--;
1455
1456 if (priv->fw_index < priv->cfg->ucode_api_min) {
1457 IWL_ERR(priv, "no suitable firmware found!\n");
1458 return -ENOENT;
1459 }
1460
1461 sprintf(priv->firmware_name, "%s%d%s",
1462 name_pre, priv->fw_index, ".ucode");
1463
1464 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1465 priv->firmware_name);
1466
1467 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1468 &priv->pci_dev->dev, GFP_KERNEL, priv,
1469 iwl_ucode_callback);
1470}
1471
b481de9c 1472/**
b08dfd04 1473 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1474 *
b08dfd04
JB
1475 * If loaded successfully, copies the firmware into buffers
1476 * for the card to fetch (via DMA).
b481de9c 1477 */
b08dfd04 1478static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1479{
b08dfd04 1480 struct iwl_priv *priv = context;
cc0f555d 1481 struct iwl_ucode_header *ucode;
a0987a8d
RC
1482 const unsigned int api_max = priv->cfg->ucode_api_max;
1483 const unsigned int api_min = priv->cfg->ucode_api_min;
b481de9c
ZY
1484 u8 *src;
1485 size_t len;
cc0f555d
JS
1486 u32 api_ver, build;
1487 u32 inst_size, data_size, init_size, init_data_size, boot_size;
b08dfd04 1488 int err;
abdc2d62 1489 u16 eeprom_ver;
b481de9c 1490
b08dfd04
JB
1491 if (!ucode_raw) {
1492 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
1493 priv->firmware_name);
1494 goto try_again;
b481de9c
ZY
1495 }
1496
b08dfd04
JB
1497 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1498 priv->firmware_name, ucode_raw->size);
b481de9c 1499
cc0f555d
JS
1500 /* Make sure that we got at least the v1 header! */
1501 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1502 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 1503 goto try_again;
b481de9c
ZY
1504 }
1505
1506 /* Data from ucode file: header followed by uCode images */
cc0f555d 1507 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1508
c02b3acd 1509 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1510 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1511 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1512 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1513 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1514 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1515 init_data_size =
1516 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1517 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1518 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1519
a0987a8d
RC
1520 /* api_ver should match the api version forming part of the
1521 * firmware filename ... but we don't check for that and only rely
877d0310 1522 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1523
1524 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1525 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1526 "Driver supports v%u, firmware is v%u.\n",
1527 api_max, api_ver);
b08dfd04 1528 goto try_again;
a0987a8d 1529 }
b08dfd04 1530
a0987a8d 1531 if (api_ver != api_max)
978785a3 1532 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1533 "got v%u. New firmware can be obtained "
1534 "from http://www.intellinuxwireless.org.\n",
1535 api_max, api_ver);
1536
978785a3
TW
1537 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1538 IWL_UCODE_MAJOR(priv->ucode_ver),
1539 IWL_UCODE_MINOR(priv->ucode_ver),
1540 IWL_UCODE_API(priv->ucode_ver),
1541 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1542
5ebeb5a6
RC
1543 snprintf(priv->hw->wiphy->fw_version,
1544 sizeof(priv->hw->wiphy->fw_version),
1545 "%u.%u.%u.%u",
1546 IWL_UCODE_MAJOR(priv->ucode_ver),
1547 IWL_UCODE_MINOR(priv->ucode_ver),
1548 IWL_UCODE_API(priv->ucode_ver),
1549 IWL_UCODE_SERIAL(priv->ucode_ver));
1550
cc0f555d
JS
1551 if (build)
1552 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1553
abdc2d62
JS
1554 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1555 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1556 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1557 ? "OTP" : "EEPROM", eeprom_ver);
1558
e1623446 1559 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1560 priv->ucode_ver);
e1623446 1561 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1562 inst_size);
e1623446 1563 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1564 data_size);
e1623446 1565 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1566 init_size);
e1623446 1567 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1568 init_data_size);
e1623446 1569 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1570 boot_size);
1571
b08dfd04
JB
1572 /*
1573 * For any of the failures below (before allocating pci memory)
1574 * we will try to load a version with a smaller API -- maybe the
1575 * user just got a corrupted version of the latest API.
1576 */
1577
b481de9c 1578 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1579 if (ucode_raw->size !=
1580 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1581 inst_size + data_size + init_size +
1582 init_data_size + boot_size) {
1583
cc0f555d
JS
1584 IWL_DEBUG_INFO(priv,
1585 "uCode file size %d does not match expected size\n",
1586 (int)ucode_raw->size);
b08dfd04 1587 goto try_again;
b481de9c
ZY
1588 }
1589
1590 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1591 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1592 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1 1593 inst_size);
b08dfd04 1594 goto try_again;
b481de9c
ZY
1595 }
1596
099b40b7 1597 if (data_size > priv->hw_params.max_data_size) {
e1623446 1598 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1 1599 data_size);
b08dfd04 1600 goto try_again;
b481de9c 1601 }
099b40b7 1602 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1603 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1604 init_size);
b08dfd04 1605 goto try_again;
b481de9c 1606 }
099b40b7 1607 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1608 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1 1609 init_data_size);
b08dfd04 1610 goto try_again;
b481de9c 1611 }
099b40b7 1612 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1613 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1614 boot_size);
b08dfd04 1615 goto try_again;
b481de9c
ZY
1616 }
1617
1618 /* Allocate ucode buffers for card's bus-master loading ... */
1619
1620 /* Runtime instructions and 2 copies of data:
1621 * 1) unmodified from disk
1622 * 2) backup cache for save/restore during power-downs */
1623 priv->ucode_code.len = inst_size;
98c92211 1624 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1625
1626 priv->ucode_data.len = data_size;
98c92211 1627 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1628
1629 priv->ucode_data_backup.len = data_size;
98c92211 1630 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1631
1f304e4e
ZY
1632 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1633 !priv->ucode_data_backup.v_addr)
1634 goto err_pci_alloc;
1635
b481de9c 1636 /* Initialization instructions and data */
90e759d1
TW
1637 if (init_size && init_data_size) {
1638 priv->ucode_init.len = init_size;
98c92211 1639 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1640
1641 priv->ucode_init_data.len = init_data_size;
98c92211 1642 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1643
1644 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1645 goto err_pci_alloc;
1646 }
b481de9c
ZY
1647
1648 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1649 if (boot_size) {
1650 priv->ucode_boot.len = boot_size;
98c92211 1651 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1652
90e759d1
TW
1653 if (!priv->ucode_boot.v_addr)
1654 goto err_pci_alloc;
1655 }
b481de9c
ZY
1656
1657 /* Copy images into buffers for card's bus-master reads ... */
1658
1659 /* Runtime instructions (first block of data in file) */
cc0f555d 1660 len = inst_size;
e1623446 1661 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1662 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1663 src += len;
1664
e1623446 1665 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1666 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1667
1668 /* Runtime data (2nd block)
5b9f8cd3 1669 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1670 len = data_size;
e1623446 1671 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1672 memcpy(priv->ucode_data.v_addr, src, len);
1673 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1674 src += len;
b481de9c
ZY
1675
1676 /* Initialization instructions (3rd block) */
1677 if (init_size) {
cc0f555d 1678 len = init_size;
e1623446 1679 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1680 len);
b481de9c 1681 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1682 src += len;
b481de9c
ZY
1683 }
1684
1685 /* Initialization data (4th block) */
1686 if (init_data_size) {
cc0f555d 1687 len = init_data_size;
e1623446 1688 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1689 len);
b481de9c 1690 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1691 src += len;
b481de9c
ZY
1692 }
1693
1694 /* Bootstrap instructions (5th block) */
cc0f555d 1695 len = boot_size;
e1623446 1696 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1697 memcpy(priv->ucode_boot.v_addr, src, len);
1698
b08dfd04
JB
1699 /**************************************************
1700 * This is still part of probe() in a sense...
1701 *
1702 * 9. Setup and register with mac80211 and debugfs
1703 **************************************************/
1704 err = iwl_mac_setup_register(priv);
1705 if (err)
1706 goto out_unbind;
1707
1708 err = iwl_dbgfs_register(priv, DRV_NAME);
1709 if (err)
1710 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1711
b481de9c
ZY
1712 /* We have our copies now, allow OS release its copies */
1713 release_firmware(ucode_raw);
b08dfd04
JB
1714 return;
1715
1716 try_again:
1717 /* try next, if any */
1718 if (iwl_request_firmware(priv, false))
1719 goto out_unbind;
1720 release_firmware(ucode_raw);
1721 return;
b481de9c
ZY
1722
1723 err_pci_alloc:
15b1687c 1724 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 1725 iwl_dealloc_ucode_pci(priv);
b08dfd04
JB
1726 out_unbind:
1727 device_release_driver(&priv->pci_dev->dev);
b481de9c 1728 release_firmware(ucode_raw);
b481de9c
ZY
1729}
1730
b7a79404
RC
1731static const char *desc_lookup_text[] = {
1732 "OK",
1733 "FAIL",
1734 "BAD_PARAM",
1735 "BAD_CHECKSUM",
1736 "NMI_INTERRUPT_WDG",
1737 "SYSASSERT",
1738 "FATAL_ERROR",
1739 "BAD_COMMAND",
1740 "HW_ERROR_TUNE_LOCK",
1741 "HW_ERROR_TEMPERATURE",
1742 "ILLEGAL_CHAN_FREQ",
1743 "VCC_NOT_STABLE",
1744 "FH_ERROR",
1745 "NMI_INTERRUPT_HOST",
1746 "NMI_INTERRUPT_ACTION_PT",
1747 "NMI_INTERRUPT_UNKNOWN",
1748 "UCODE_VERSION_MISMATCH",
1749 "HW_ERROR_ABS_LOCK",
1750 "HW_ERROR_CAL_LOCK_FAIL",
1751 "NMI_INTERRUPT_INST_ACTION_PT",
1752 "NMI_INTERRUPT_DATA_ACTION_PT",
1753 "NMI_TRM_HW_ER",
1754 "NMI_INTERRUPT_TRM",
1755 "NMI_INTERRUPT_BREAK_POINT"
1756 "DEBUG_0",
1757 "DEBUG_1",
1758 "DEBUG_2",
1759 "DEBUG_3",
a7fce6ee 1760 "ADVANCED SYSASSERT"
b7a79404
RC
1761};
1762
1763static const char *desc_lookup(int i)
1764{
1765 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1766
1767 if (i < 0 || i > max)
1768 i = max;
1769
1770 return desc_lookup_text[i];
1771}
1772
1773#define ERROR_START_OFFSET (1 * sizeof(u32))
1774#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1775
1776void iwl_dump_nic_error_log(struct iwl_priv *priv)
1777{
1778 u32 data2, line;
1779 u32 desc, time, count, base, data1;
1780 u32 blink1, blink2, ilink1, ilink2;
1781
1782 if (priv->ucode_type == UCODE_INIT)
1783 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1784 else
1785 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1786
1787 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1788 IWL_ERR(priv,
1789 "Not valid error log pointer 0x%08X for %s uCode\n",
1790 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC
1791 return;
1792 }
1793
1794 count = iwl_read_targ_mem(priv, base);
1795
1796 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1797 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1798 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1799 priv->status, count);
1800 }
1801
1802 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1803 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1804 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1805 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1806 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1807 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1808 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1809 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1810 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1811
be1a71a1
JB
1812 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1813 blink1, blink2, ilink1, ilink2);
1814
b7a79404
RC
1815 IWL_ERR(priv, "Desc Time "
1816 "data1 data2 line\n");
1817 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1818 desc_lookup(desc), desc, time, data1, data2, line);
1819 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1820 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1821 ilink1, ilink2);
1822
1823}
1824
1825#define EVENT_START_OFFSET (4 * sizeof(u32))
1826
1827/**
1828 * iwl_print_event_log - Dump error event log to syslog
1829 *
1830 */
b03d7d0f
WYG
1831static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1832 u32 num_events, u32 mode,
1833 int pos, char **buf, size_t bufsz)
b7a79404
RC
1834{
1835 u32 i;
1836 u32 base; /* SRAM byte address of event log header */
1837 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1838 u32 ptr; /* SRAM byte address of log data */
1839 u32 ev, time, data; /* event log data */
e5854471 1840 unsigned long reg_flags;
b7a79404
RC
1841
1842 if (num_events == 0)
b03d7d0f 1843 return pos;
b7a79404
RC
1844 if (priv->ucode_type == UCODE_INIT)
1845 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1846 else
1847 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1848
1849 if (mode == 0)
1850 event_size = 2 * sizeof(u32);
1851 else
1852 event_size = 3 * sizeof(u32);
1853
1854 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1855
e5854471
BC
1856 /* Make sure device is powered up for SRAM reads */
1857 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1858 iwl_grab_nic_access(priv);
1859
1860 /* Set starting address; reads will auto-increment */
1861 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1862 rmb();
1863
b7a79404
RC
1864 /* "time" is actually "data" for mode 0 (no timestamp).
1865 * place event id # at far right for easier visual parsing. */
1866 for (i = 0; i < num_events; i++) {
e5854471
BC
1867 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1868 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1869 if (mode == 0) {
1870 /* data, ev */
b03d7d0f
WYG
1871 if (bufsz) {
1872 pos += scnprintf(*buf + pos, bufsz - pos,
1873 "EVT_LOG:0x%08x:%04u\n",
1874 time, ev);
1875 } else {
1876 trace_iwlwifi_dev_ucode_event(priv, 0,
1877 time, ev);
1878 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1879 time, ev);
1880 }
b7a79404 1881 } else {
e5854471 1882 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG
1883 if (bufsz) {
1884 pos += scnprintf(*buf + pos, bufsz - pos,
1885 "EVT_LOGT:%010u:0x%08x:%04u\n",
1886 time, data, ev);
1887 } else {
1888 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 1889 time, data, ev);
b03d7d0f
WYG
1890 trace_iwlwifi_dev_ucode_event(priv, time,
1891 data, ev);
1892 }
b7a79404
RC
1893 }
1894 }
e5854471
BC
1895
1896 /* Allow device to power down */
1897 iwl_release_nic_access(priv);
1898 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1899 return pos;
b7a79404
RC
1900}
1901
c341ddb2
WYG
1902/**
1903 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1904 */
b03d7d0f
WYG
1905static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1906 u32 num_wraps, u32 next_entry,
1907 u32 size, u32 mode,
1908 int pos, char **buf, size_t bufsz)
c341ddb2
WYG
1909{
1910 /*
1911 * display the newest DEFAULT_LOG_ENTRIES entries
1912 * i.e the entries just before the next ont that uCode would fill.
1913 */
1914 if (num_wraps) {
1915 if (next_entry < size) {
b03d7d0f
WYG
1916 pos = iwl_print_event_log(priv,
1917 capacity - (size - next_entry),
1918 size - next_entry, mode,
1919 pos, buf, bufsz);
1920 pos = iwl_print_event_log(priv, 0,
1921 next_entry, mode,
1922 pos, buf, bufsz);
c341ddb2 1923 } else
b03d7d0f
WYG
1924 pos = iwl_print_event_log(priv, next_entry - size,
1925 size, mode, pos, buf, bufsz);
c341ddb2 1926 } else {
b03d7d0f
WYG
1927 if (next_entry < size) {
1928 pos = iwl_print_event_log(priv, 0, next_entry,
1929 mode, pos, buf, bufsz);
1930 } else {
1931 pos = iwl_print_event_log(priv, next_entry - size,
1932 size, mode, pos, buf, bufsz);
1933 }
c341ddb2 1934 }
b03d7d0f 1935 return pos;
c341ddb2
WYG
1936}
1937
84c40692
BC
1938/* For sanity check only. Actual size is determined by uCode, typ. 512 */
1939#define MAX_EVENT_LOG_SIZE (512)
1940
c341ddb2
WYG
1941#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
1942
b03d7d0f
WYG
1943int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1944 char **buf, bool display)
b7a79404
RC
1945{
1946 u32 base; /* SRAM byte address of event log header */
1947 u32 capacity; /* event log capacity in # entries */
1948 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1949 u32 num_wraps; /* # times uCode wrapped to top of log */
1950 u32 next_entry; /* index of next entry to be written by uCode */
1951 u32 size; /* # entries that we'll print */
b03d7d0f
WYG
1952 int pos = 0;
1953 size_t bufsz = 0;
b7a79404
RC
1954
1955 if (priv->ucode_type == UCODE_INIT)
1956 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1957 else
1958 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1959
1960 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1961 IWL_ERR(priv,
1962 "Invalid event log pointer 0x%08X for %s uCode\n",
1963 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 1964 return -EINVAL;
b7a79404
RC
1965 }
1966
1967 /* event log header */
1968 capacity = iwl_read_targ_mem(priv, base);
1969 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1970 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1971 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1972
84c40692
BC
1973 if (capacity > MAX_EVENT_LOG_SIZE) {
1974 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1975 capacity, MAX_EVENT_LOG_SIZE);
1976 capacity = MAX_EVENT_LOG_SIZE;
1977 }
1978
1979 if (next_entry > MAX_EVENT_LOG_SIZE) {
1980 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1981 next_entry, MAX_EVENT_LOG_SIZE);
1982 next_entry = MAX_EVENT_LOG_SIZE;
1983 }
1984
b7a79404
RC
1985 size = num_wraps ? capacity : next_entry;
1986
1987 /* bail out if nothing in log */
1988 if (size == 0) {
1989 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 1990 return pos;
b7a79404
RC
1991 }
1992
c341ddb2 1993#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 1994 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG
1995 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1996 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
1997#else
1998 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1999 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2000#endif
2001 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2002 size);
b7a79404 2003
c341ddb2 2004#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG
2005 if (display) {
2006 if (full_log)
2007 bufsz = capacity * 48;
2008 else
2009 bufsz = size * 48;
2010 *buf = kmalloc(bufsz, GFP_KERNEL);
2011 if (!*buf)
937c397e 2012 return -ENOMEM;
b03d7d0f 2013 }
c341ddb2
WYG
2014 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2015 /*
2016 * if uCode has wrapped back to top of log,
2017 * start at the oldest entry,
2018 * i.e the next one that uCode would fill.
2019 */
2020 if (num_wraps)
b03d7d0f
WYG
2021 pos = iwl_print_event_log(priv, next_entry,
2022 capacity - next_entry, mode,
2023 pos, buf, bufsz);
c341ddb2 2024 /* (then/else) start at top of log */
b03d7d0f
WYG
2025 pos = iwl_print_event_log(priv, 0,
2026 next_entry, mode, pos, buf, bufsz);
c341ddb2 2027 } else
b03d7d0f
WYG
2028 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2029 next_entry, size, mode,
2030 pos, buf, bufsz);
c341ddb2 2031#else
b03d7d0f
WYG
2032 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2033 next_entry, size, mode,
2034 pos, buf, bufsz);
b7a79404 2035#endif
b03d7d0f 2036 return pos;
c341ddb2 2037}
b7a79404 2038
b481de9c 2039/**
4a4a9e81 2040 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2041 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2042 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2043 */
4a4a9e81 2044static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2045{
57aab75a 2046 int ret = 0;
b481de9c 2047
e1623446 2048 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2049
2050 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2051 /* We had an error bringing up the hardware, so take it
2052 * all the way back down so we can try again */
e1623446 2053 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2054 goto restart;
2055 }
2056
2057 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2058 * This is a paranoid check, because we would not have gotten the
2059 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2060 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
2061 /* Runtime instruction load was bad;
2062 * take it all the way back down so we can try again */
e1623446 2063 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2064 goto restart;
2065 }
2066
57aab75a
TW
2067 ret = priv->cfg->ops->lib->alive_notify(priv);
2068 if (ret) {
39aadf8c
WT
2069 IWL_WARN(priv,
2070 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
2071 goto restart;
2072 }
2073
5b9f8cd3 2074 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
2075 set_bit(STATUS_ALIVE, &priv->status);
2076
fee1247a 2077 if (iwl_is_rfkill(priv))
b481de9c
ZY
2078 return;
2079
36d6825b 2080 ieee80211_wake_queues(priv->hw);
b481de9c 2081
470ab2dd 2082 priv->active_rate = IWL_RATES_MASK;
b481de9c 2083
2f748dec
WYG
2084 /* Configure Tx antenna selection based on H/W config */
2085 if (priv->cfg->ops->hcmd->set_tx_ant)
2086 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2087
3109ece1 2088 if (iwl_is_associated(priv)) {
c1adf9fb
GG
2089 struct iwl_rxon_cmd *active_rxon =
2090 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
2091 /* apply any changes in staging */
2092 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2093 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2094 } else {
2095 /* Initialize our rx_config data */
5b9f8cd3 2096 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
2097
2098 if (priv->cfg->ops->hcmd->set_rxon_chain)
2099 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2100
b481de9c
ZY
2101 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2102 }
2103
9fbab516 2104 /* Configure Bluetooth device coexistence support */
5b9f8cd3 2105 iwl_send_bt_config(priv);
b481de9c 2106
4a4a9e81
TW
2107 iwl_reset_run_time_calib(priv);
2108
b481de9c 2109 /* Configure the adapter for unassociated operation */
e0158e61 2110 iwlcore_commit_rxon(priv);
b481de9c
ZY
2111
2112 /* At this point, the NIC is initialized and operational */
47f4a587 2113 iwl_rf_kill_ct_config(priv);
5a66926a 2114
e932a609 2115 iwl_leds_init(priv);
fe00b5a5 2116
e1623446 2117 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2118 set_bit(STATUS_READY, &priv->status);
5a66926a 2119 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2120
e312c24c 2121 iwl_power_update_mode(priv, true);
7e246191
RC
2122 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2123
c46fbefa 2124
b481de9c
ZY
2125 return;
2126
2127 restart:
2128 queue_work(priv->workqueue, &priv->restart);
2129}
2130
4e39317d 2131static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2132
5b9f8cd3 2133static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2134{
2135 unsigned long flags;
2136 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2137
e1623446 2138 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2139
b481de9c
ZY
2140 if (!exit_pending)
2141 set_bit(STATUS_EXIT_PENDING, &priv->status);
2142
7e246191 2143 iwl_clear_ucode_stations(priv, true);
b481de9c
ZY
2144
2145 /* Unblock any waiting calls */
2146 wake_up_interruptible_all(&priv->wait_command_queue);
2147
b481de9c
ZY
2148 /* Wipe out the EXIT_PENDING status bit if we are not actually
2149 * exiting the module */
2150 if (!exit_pending)
2151 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2152
2153 /* stop and reset the on-board processor */
3395f6e9 2154 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2155
2156 /* tell the device to stop sending interrupts */
0359facc 2157 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2158 iwl_disable_interrupts(priv);
0359facc
MA
2159 spin_unlock_irqrestore(&priv->lock, flags);
2160 iwl_synchronize_irq(priv);
b481de9c
ZY
2161
2162 if (priv->mac80211_registered)
2163 ieee80211_stop_queues(priv->hw);
2164
5b9f8cd3 2165 /* If we have not previously called iwl_init() then
a60e77e5 2166 * clear all bits but the RF Kill bit and return */
fee1247a 2167 if (!iwl_is_init(priv)) {
b481de9c
ZY
2168 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2169 STATUS_RF_KILL_HW |
9788864e
RC
2170 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2171 STATUS_GEO_CONFIGURED |
052ec3f1
MA
2172 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2173 STATUS_EXIT_PENDING;
b481de9c
ZY
2174 goto exit;
2175 }
2176
6da3a13e 2177 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2178 * bit and continue taking the NIC down. */
b481de9c
ZY
2179 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2180 STATUS_RF_KILL_HW |
9788864e
RC
2181 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2182 STATUS_GEO_CONFIGURED |
b481de9c 2183 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
2184 STATUS_FW_ERROR |
2185 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2186 STATUS_EXIT_PENDING;
b481de9c 2187
ef850d7c
MA
2188 /* device going down, Stop using ICT table */
2189 iwl_disable_ict(priv);
b481de9c 2190
da1bc453 2191 iwl_txq_ctx_stop(priv);
b3bbacb7 2192 iwl_rxq_stop(priv);
b481de9c 2193
309e731a
BC
2194 /* Power-down device's busmaster DMA clocks */
2195 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2196 udelay(5);
2197
309e731a
BC
2198 /* Make sure (redundant) we've released our request to stay awake */
2199 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2200
4d2ccdb9
BC
2201 /* Stop the device, and put it in low power state */
2202 priv->cfg->ops->lib->apm_ops.stop(priv);
2203
b481de9c 2204 exit:
885ba202 2205 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2206
2207 if (priv->ibss_beacon)
2208 dev_kfree_skb(priv->ibss_beacon);
2209 priv->ibss_beacon = NULL;
2210
2211 /* clear out any free frames */
fcab423d 2212 iwl_clear_free_frames(priv);
b481de9c
ZY
2213}
2214
5b9f8cd3 2215static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2216{
2217 mutex_lock(&priv->mutex);
5b9f8cd3 2218 __iwl_down(priv);
b481de9c 2219 mutex_unlock(&priv->mutex);
b24d22b1 2220
4e39317d 2221 iwl_cancel_deferred_work(priv);
b481de9c
ZY
2222}
2223
086ed117
MA
2224#define HW_READY_TIMEOUT (50)
2225
2226static int iwl_set_hw_ready(struct iwl_priv *priv)
2227{
2228 int ret = 0;
2229
2230 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2231 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2232
2233 /* See if we got it */
2234 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2235 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2236 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2237 HW_READY_TIMEOUT);
2238 if (ret != -ETIMEDOUT)
2239 priv->hw_ready = true;
2240 else
2241 priv->hw_ready = false;
2242
2243 IWL_DEBUG_INFO(priv, "hardware %s\n",
2244 (priv->hw_ready == 1) ? "ready" : "not ready");
2245 return ret;
2246}
2247
2248static int iwl_prepare_card_hw(struct iwl_priv *priv)
2249{
2250 int ret = 0;
2251
2252 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
2253
3354a0f6
MA
2254 ret = iwl_set_hw_ready(priv);
2255 if (priv->hw_ready)
2256 return ret;
2257
2258 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
2259 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2260 CSR_HW_IF_CONFIG_REG_PREPARE);
2261
2262 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2263 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2264 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2265
3354a0f6 2266 /* HW should be ready by now, check again. */
086ed117
MA
2267 if (ret != -ETIMEDOUT)
2268 iwl_set_hw_ready(priv);
2269
2270 return ret;
2271}
2272
b481de9c
ZY
2273#define MAX_HW_RESTARTS 5
2274
5b9f8cd3 2275static int __iwl_up(struct iwl_priv *priv)
b481de9c 2276{
57aab75a
TW
2277 int i;
2278 int ret;
b481de9c
ZY
2279
2280 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2281 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2282 return -EIO;
2283 }
2284
e903fbd4 2285 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2286 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
2287 return -EIO;
2288 }
2289
086ed117
MA
2290 iwl_prepare_card_hw(priv);
2291
2292 if (!priv->hw_ready) {
2293 IWL_WARN(priv, "Exit HW not ready\n");
2294 return -EIO;
2295 }
2296
e655b9f0 2297 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2298 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2299 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2300 else
e655b9f0 2301 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2302
c1842d61 2303 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
2304 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2305
5b9f8cd3 2306 iwl_enable_interrupts(priv);
a60e77e5 2307 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2308 return 0;
b481de9c
ZY
2309 }
2310
3395f6e9 2311 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2312
1053d35f 2313 ret = iwl_hw_nic_init(priv);
57aab75a 2314 if (ret) {
15b1687c 2315 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2316 return ret;
b481de9c
ZY
2317 }
2318
2319 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2320 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2321 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2322 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2323
2324 /* clear (again), then enable host interrupts */
3395f6e9 2325 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2326 iwl_enable_interrupts(priv);
b481de9c
ZY
2327
2328 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2329 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2330 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2331
2332 /* Copy original ucode data image from disk into backup cache.
2333 * This will be used to initialize the on-board processor's
2334 * data SRAM for a clean start when the runtime program first loads. */
2335 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2336 priv->ucode_data.len);
b481de9c 2337
b481de9c
ZY
2338 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2339
b481de9c
ZY
2340 /* load bootstrap state machine,
2341 * load bootstrap program into processor's memory,
2342 * prepare to load the "initialize" uCode */
57aab75a 2343 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2344
57aab75a 2345 if (ret) {
15b1687c
WT
2346 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2347 ret);
b481de9c
ZY
2348 continue;
2349 }
2350
2351 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2352 iwl_nic_start(priv);
b481de9c 2353
e1623446 2354 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2355
2356 return 0;
2357 }
2358
2359 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2360 __iwl_down(priv);
64e72c3e 2361 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2362
2363 /* tried to restart and config the device for as long as our
2364 * patience could withstand */
15b1687c 2365 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2366 return -EIO;
2367}
2368
2369
2370/*****************************************************************************
2371 *
2372 * Workqueue callbacks
2373 *
2374 *****************************************************************************/
2375
4a4a9e81 2376static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2377{
c79dd5b5
TW
2378 struct iwl_priv *priv =
2379 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2380
2381 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2382 return;
2383
2384 mutex_lock(&priv->mutex);
f3ccc08c 2385 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2386 mutex_unlock(&priv->mutex);
2387}
2388
4a4a9e81 2389static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2390{
c79dd5b5
TW
2391 struct iwl_priv *priv =
2392 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2393
2394 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2395 return;
2396
258c44a0
MA
2397 /* enable dram interrupt */
2398 iwl_reset_ict(priv);
2399
b481de9c 2400 mutex_lock(&priv->mutex);
4a4a9e81 2401 iwl_alive_start(priv);
b481de9c
ZY
2402 mutex_unlock(&priv->mutex);
2403}
2404
16e727e8
EG
2405static void iwl_bg_run_time_calib_work(struct work_struct *work)
2406{
2407 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2408 run_time_calib_work);
2409
2410 mutex_lock(&priv->mutex);
2411
2412 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2413 test_bit(STATUS_SCANNING, &priv->status)) {
2414 mutex_unlock(&priv->mutex);
2415 return;
2416 }
2417
2418 if (priv->start_calib) {
2419 iwl_chain_noise_calibration(priv, &priv->statistics);
2420
2421 iwl_sensitivity_calibration(priv, &priv->statistics);
2422 }
2423
2424 mutex_unlock(&priv->mutex);
2425 return;
2426}
2427
5b9f8cd3 2428static void iwl_bg_restart(struct work_struct *data)
b481de9c 2429{
c79dd5b5 2430 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2431
2432 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2433 return;
2434
19cc1087
JB
2435 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2436 mutex_lock(&priv->mutex);
2437 priv->vif = NULL;
2438 priv->is_open = 0;
2439 mutex_unlock(&priv->mutex);
2440 iwl_down(priv);
2441 ieee80211_restart_hw(priv->hw);
2442 } else {
2443 iwl_down(priv);
80676518
JB
2444
2445 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2446 return;
2447
2448 mutex_lock(&priv->mutex);
2449 __iwl_up(priv);
2450 mutex_unlock(&priv->mutex);
19cc1087 2451 }
b481de9c
ZY
2452}
2453
5b9f8cd3 2454static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2455{
c79dd5b5
TW
2456 struct iwl_priv *priv =
2457 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2458
2459 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2460 return;
2461
2462 mutex_lock(&priv->mutex);
a55360e4 2463 iwl_rx_replenish(priv);
b481de9c
ZY
2464 mutex_unlock(&priv->mutex);
2465}
2466
7878a5a4
MA
2467#define IWL_DELAY_NEXT_SCAN (HZ*2)
2468
5bbe233b 2469void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2470{
b481de9c 2471 struct ieee80211_conf *conf = NULL;
857485c0 2472 int ret = 0;
1ff50bda 2473 unsigned long flags;
b481de9c 2474
05c914fe 2475 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2476 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2477 return;
2478 }
2479
b481de9c
ZY
2480 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2481 return;
2482
b481de9c 2483
508e32e1 2484 if (!priv->vif || !priv->is_open)
948c171c 2485 return;
508e32e1 2486
2a421b91 2487 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2488
b481de9c
ZY
2489 conf = ieee80211_get_hw_conf(priv->hw);
2490
2491 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2492 iwlcore_commit_rxon(priv);
b481de9c 2493
3195c1f3 2494 iwl_setup_rxon_timing(priv);
857485c0 2495 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2496 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2497 if (ret)
39aadf8c 2498 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2499 "Attempting to continue.\n");
2500
2501 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2502
42eb7c64 2503 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2504
45823531
AK
2505 if (priv->cfg->ops->hcmd->set_rxon_chain)
2506 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2507
b481de9c
ZY
2508 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2509
e1623446 2510 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2511 priv->assoc_id, priv->beacon_int);
2512
2513 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2514 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2515 else
2516 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2517
2518 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2519 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2520 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2521 else
2522 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2523
05c914fe 2524 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2525 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2526
2527 }
2528
e0158e61 2529 iwlcore_commit_rxon(priv);
b481de9c 2530
fe6b23dd
RC
2531 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
2532 priv->assoc_id, priv->active_rxon.bssid_addr);
2533
b481de9c 2534 switch (priv->iw_mode) {
05c914fe 2535 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2536 break;
2537
05c914fe 2538 case NL80211_IFTYPE_ADHOC:
b481de9c 2539
c46fbefa
AK
2540 /* assume default assoc id */
2541 priv->assoc_id = 1;
b481de9c 2542
fe6b23dd 2543 iwl_add_local_station(priv, priv->bssid, true);
5b9f8cd3 2544 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2545
2546 break;
2547
2548 default:
15b1687c 2549 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2550 __func__, priv->iw_mode);
b481de9c
ZY
2551 break;
2552 }
2553
1ff50bda
EG
2554 spin_lock_irqsave(&priv->lock, flags);
2555 iwl_activate_qos(priv, 0);
2556 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2557
04816448
GE
2558 /* the chain noise calibration will enabled PM upon completion
2559 * If chain noise has already been run, then we need to enable
2560 * power management here */
2561 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2562 iwl_power_update_mode(priv, false);
c90a74ba
EG
2563
2564 /* Enable Rx differential gain and sensitivity calibrations */
2565 iwl_chain_noise_reset(priv);
2566 priv->start_calib = 1;
2567
508e32e1
RC
2568}
2569
b481de9c
ZY
2570/*****************************************************************************
2571 *
2572 * mac80211 entry point functions
2573 *
2574 *****************************************************************************/
2575
154b25ce 2576#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2577
f0b6e2e8
RC
2578/*
2579 * Not a mac80211 entry point function, but it fits in with all the
2580 * other mac80211 functions grouped here.
2581 */
158bea07 2582static int iwl_mac_setup_register(struct iwl_priv *priv)
f0b6e2e8
RC
2583{
2584 int ret;
2585 struct ieee80211_hw *hw = priv->hw;
2586 hw->rate_control_algorithm = "iwl-agn-rs";
2587
2588 /* Tell mac80211 our characteristics */
2589 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2590 IEEE80211_HW_NOISE_DBM |
2591 IEEE80211_HW_AMPDU_AGGREGATION |
2592 IEEE80211_HW_SPECTRUM_MGMT;
2593
2594 if (!priv->cfg->broken_powersave)
2595 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2596 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2597
ba37a3d0
JB
2598 if (priv->cfg->sku & IWL_SKU_N)
2599 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2600 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2601
8d9698b3 2602 hw->sta_data_size = sizeof(struct iwl_station_priv);
f0b6e2e8
RC
2603 hw->wiphy->interface_modes =
2604 BIT(NL80211_IFTYPE_STATION) |
2605 BIT(NL80211_IFTYPE_ADHOC);
2606
5be83de5
JB
2607 hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
2608 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC
2609
2610 /*
2611 * For now, disable PS by default because it affects
2612 * RX performance significantly.
2613 */
5be83de5 2614 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 2615
21b2d8bd 2616 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX + 1;
f0b6e2e8
RC
2617 /* we create the 802.11 header and a zero-length SSID element */
2618 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2619
2620 /* Default value; 4 EDCA QOS priorities */
2621 hw->queues = 4;
2622
2623 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2624
2625 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2626 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2627 &priv->bands[IEEE80211_BAND_2GHZ];
2628 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2629 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2630 &priv->bands[IEEE80211_BAND_5GHZ];
2631
2632 ret = ieee80211_register_hw(priv->hw);
2633 if (ret) {
2634 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2635 return ret;
2636 }
2637 priv->mac80211_registered = 1;
2638
2639 return 0;
2640}
2641
2642
5b9f8cd3 2643static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2644{
c79dd5b5 2645 struct iwl_priv *priv = hw->priv;
5a66926a 2646 int ret;
b481de9c 2647
e1623446 2648 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2649
2650 /* we should be verifying the device is ready to be opened */
2651 mutex_lock(&priv->mutex);
5b9f8cd3 2652 ret = __iwl_up(priv);
b481de9c 2653 mutex_unlock(&priv->mutex);
5a66926a 2654
e655b9f0 2655 if (ret)
6cd0b1cb 2656 return ret;
e655b9f0 2657
c1842d61
TW
2658 if (iwl_is_rfkill(priv))
2659 goto out;
2660
e1623446 2661 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2662
fe9b6b72 2663 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2664 * mac80211 will not be run successfully. */
154b25ce
EG
2665 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2666 test_bit(STATUS_READY, &priv->status),
2667 UCODE_READY_TIMEOUT);
2668 if (!ret) {
2669 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2670 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2671 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2672 return -ETIMEDOUT;
5a66926a 2673 }
fe9b6b72 2674 }
0a078ffa 2675
e932a609
JB
2676 iwl_led_start(priv);
2677
c1842d61 2678out:
0a078ffa 2679 priv->is_open = 1;
e1623446 2680 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2681 return 0;
2682}
2683
5b9f8cd3 2684static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2685{
c79dd5b5 2686 struct iwl_priv *priv = hw->priv;
b481de9c 2687
e1623446 2688 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2689
19cc1087 2690 if (!priv->is_open)
e655b9f0 2691 return;
e655b9f0 2692
b481de9c 2693 priv->is_open = 0;
5a66926a 2694
5bddf549 2695 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2696 /* stop mac, cancel any scan request and clear
2697 * RXON_FILTER_ASSOC_MSK BIT
2698 */
5a66926a 2699 mutex_lock(&priv->mutex);
2a421b91 2700 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2701 mutex_unlock(&priv->mutex);
fde3571f
MA
2702 }
2703
5b9f8cd3 2704 iwl_down(priv);
5a66926a
ZY
2705
2706 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2707
2708 /* enable interrupts again in order to receive rfkill changes */
2709 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2710 iwl_enable_interrupts(priv);
948c171c 2711
e1623446 2712 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2713}
2714
5b9f8cd3 2715static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2716{
c79dd5b5 2717 struct iwl_priv *priv = hw->priv;
b481de9c 2718
e1623446 2719 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2720
e1623446 2721 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2722 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2723
e039fa4a 2724 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2725 dev_kfree_skb_any(skb);
2726
e1623446 2727 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2728 return NETDEV_TX_OK;
b481de9c
ZY
2729}
2730
60690a6a 2731void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2732{
857485c0 2733 int ret = 0;
1ff50bda 2734 unsigned long flags;
b481de9c 2735
d986bcd1 2736 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2737 return;
2738
2739 /* The following should be done only at AP bring up */
3195c1f3 2740 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2741
2742 /* RXON - unassoc (to set timing command) */
2743 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2744 iwlcore_commit_rxon(priv);
b481de9c
ZY
2745
2746 /* RXON Timing */
3195c1f3 2747 iwl_setup_rxon_timing(priv);
857485c0 2748 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2749 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2750 if (ret)
39aadf8c 2751 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2752 "Attempting to continue.\n");
2753
f513dfff
DH
2754 /* AP has all antennas */
2755 priv->chain_noise_data.active_chains =
2756 priv->hw_params.valid_rx_ant;
2757 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK
2758 if (priv->cfg->ops->hcmd->set_rxon_chain)
2759 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2760
2761 /* FIXME: what should be the assoc_id for AP? */
2762 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2763 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2764 priv->staging_rxon.flags |=
2765 RXON_FLG_SHORT_PREAMBLE_MSK;
2766 else
2767 priv->staging_rxon.flags &=
2768 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2769
2770 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2771 if (priv->assoc_capability &
2772 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2773 priv->staging_rxon.flags |=
2774 RXON_FLG_SHORT_SLOT_MSK;
2775 else
2776 priv->staging_rxon.flags &=
2777 ~RXON_FLG_SHORT_SLOT_MSK;
2778
05c914fe 2779 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2780 priv->staging_rxon.flags &=
2781 ~RXON_FLG_SHORT_SLOT_MSK;
2782 }
2783 /* restore RXON assoc */
2784 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2785 iwlcore_commit_rxon(priv);
f513dfff 2786 iwl_reset_qos(priv);
1ff50bda
EG
2787 spin_lock_irqsave(&priv->lock, flags);
2788 iwl_activate_qos(priv, 1);
2789 spin_unlock_irqrestore(&priv->lock, flags);
9a9ca65f 2790 iwl_add_bcast_station(priv);
e1493deb 2791 }
5b9f8cd3 2792 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2793
2794 /* FIXME - we need to add code here to detect a totally new
2795 * configuration, reset the AP, unassoc, rxon timing, assoc,
2796 * clear sta table, add BCAST sta... */
2797}
2798
5b9f8cd3 2799static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB
2800 struct ieee80211_vif *vif,
2801 struct ieee80211_key_conf *keyconf,
2802 struct ieee80211_sta *sta,
2803 u32 iv32, u16 *phase1key)
ab885f8c 2804{
ab885f8c 2805
9f58671e 2806 struct iwl_priv *priv = hw->priv;
e1623446 2807 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2808
b3fbdcf4
JB
2809 iwl_update_tkip_key(priv, keyconf,
2810 sta ? sta->addr : iwl_bcast_addr,
2811 iv32, phase1key);
ab885f8c 2812
e1623446 2813 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2814}
2815
5b9f8cd3 2816static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2817 struct ieee80211_vif *vif,
2818 struct ieee80211_sta *sta,
b481de9c
ZY
2819 struct ieee80211_key_conf *key)
2820{
c79dd5b5 2821 struct iwl_priv *priv = hw->priv;
42986796
WT
2822 const u8 *addr;
2823 int ret;
2824 u8 sta_id;
2825 bool is_default_wep_key = false;
b481de9c 2826
e1623446 2827 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2828
90e8e424 2829 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2830 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2831 return -EOPNOTSUPP;
2832 }
42986796 2833 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2834 sta_id = iwl_find_station(priv, addr);
6974e363 2835 if (sta_id == IWL_INVALID_STATION) {
e1623446 2836 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2837 addr);
6974e363 2838 return -EINVAL;
b481de9c 2839
deb09c43 2840 }
b481de9c 2841
6974e363 2842 mutex_lock(&priv->mutex);
2a421b91 2843 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2844
2845 /* If we are getting WEP group key and we didn't receive any key mapping
2846 * so far, we are in legacy wep mode (group key only), otherwise we are
2847 * in 1X mode.
2848 * In legacy wep mode, we use another host command to the uCode */
5425e490 2849 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2850 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2851 if (cmd == SET_KEY)
2852 is_default_wep_key = !priv->key_mapping_key;
2853 else
ccc038ab
EG
2854 is_default_wep_key =
2855 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2856 }
052c4b9f 2857
b481de9c 2858 switch (cmd) {
deb09c43 2859 case SET_KEY:
6974e363
EG
2860 if (is_default_wep_key)
2861 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2862 else
7480513f 2863 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2864
e1623446 2865 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2866 break;
2867 case DISABLE_KEY:
6974e363
EG
2868 if (is_default_wep_key)
2869 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2870 else
3ec47732 2871 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2872
e1623446 2873 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2874 break;
2875 default:
deb09c43 2876 ret = -EINVAL;
b481de9c
ZY
2877 }
2878
72e15d71 2879 mutex_unlock(&priv->mutex);
e1623446 2880 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2881
deb09c43 2882 return ret;
b481de9c
ZY
2883}
2884
5b9f8cd3 2885static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2886 struct ieee80211_vif *vif,
d783b061 2887 enum ieee80211_ampdu_mlme_action action,
17741cdc 2888 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2889{
2890 struct iwl_priv *priv = hw->priv;
5c2207c6 2891 int ret;
d783b061 2892
e1623446 2893 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2894 sta->addr, tid);
d783b061
TW
2895
2896 if (!(priv->cfg->sku & IWL_SKU_N))
2897 return -EACCES;
2898
2899 switch (action) {
2900 case IEEE80211_AMPDU_RX_START:
e1623446 2901 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2902 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2903 case IEEE80211_AMPDU_RX_STOP:
e1623446 2904 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2905 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2906 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2907 return 0;
2908 else
2909 return ret;
d783b061 2910 case IEEE80211_AMPDU_TX_START:
e1623446 2911 IWL_DEBUG_HT(priv, "start Tx\n");
ab9bdc34 2912 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2913 case IEEE80211_AMPDU_TX_STOP:
e1623446 2914 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2915 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2916 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2917 return 0;
2918 else
2919 return ret;
f0527971
WYG
2920 case IEEE80211_AMPDU_TX_OPERATIONAL:
2921 /* do nothing */
2922 return -EOPNOTSUPP;
d783b061 2923 default:
e1623446 2924 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2925 return -EINVAL;
2926 break;
2927 }
2928 return 0;
2929}
9f58671e 2930
5b9f8cd3 2931static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2932 struct ieee80211_low_level_stats *stats)
2933{
bf403db8
EK
2934 struct iwl_priv *priv = hw->priv;
2935
2936 priv = hw->priv;
e1623446
TW
2937 IWL_DEBUG_MAC80211(priv, "enter\n");
2938 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2939
2940 return 0;
2941}
2942
6ab10ff8
JB
2943static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
2944 struct ieee80211_vif *vif,
2945 enum sta_notify_cmd cmd,
2946 struct ieee80211_sta *sta)
2947{
2948 struct iwl_priv *priv = hw->priv;
2949 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
2950 int sta_id;
2951
6ab10ff8 2952 switch (cmd) {
6ab10ff8
JB
2953 case STA_NOTIFY_SLEEP:
2954 WARN_ON(!sta_priv->client);
2955 sta_priv->asleep = true;
2956 if (atomic_read(&sta_priv->pending_frames) > 0)
2957 ieee80211_sta_block_awake(hw, sta, true);
2958 break;
2959 case STA_NOTIFY_AWAKE:
2960 WARN_ON(!sta_priv->client);
49dcc819
DH
2961 if (!sta_priv->asleep)
2962 break;
6ab10ff8
JB
2963 sta_priv->asleep = false;
2964 sta_id = iwl_find_station(priv, sta->addr);
2965 if (sta_id != IWL_INVALID_STATION)
2966 iwl_sta_modify_ps_wake(priv, sta_id);
2967 break;
2968 default:
2969 break;
2970 }
2971}
2972
fe6b23dd
RC
2973/**
2974 * iwl_restore_wepkeys - Restore WEP keys to device
2975 */
2976static void iwl_restore_wepkeys(struct iwl_priv *priv)
2977{
2978 mutex_lock(&priv->mutex);
2979 if (priv->iw_mode == NL80211_IFTYPE_STATION &&
2980 priv->default_wep_key &&
2981 iwl_send_static_wepkey_cmd(priv, 0))
2982 IWL_ERR(priv, "Could not send WEP static key\n");
2983 mutex_unlock(&priv->mutex);
2984}
2985
2986static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
2987 struct ieee80211_vif *vif,
2988 struct ieee80211_sta *sta)
2989{
2990 struct iwl_priv *priv = hw->priv;
2991 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
2992 bool is_ap = priv->iw_mode == NL80211_IFTYPE_STATION;
2993 int ret;
2994 u8 sta_id;
2995
2996 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
2997 sta->addr);
2998
2999 atomic_set(&sta_priv->pending_frames, 0);
3000 if (vif->type == NL80211_IFTYPE_AP)
3001 sta_priv->client = true;
3002
3003 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3004 &sta_id);
3005 if (ret) {
3006 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3007 sta->addr, ret);
3008 /* Should we return success if return code is EEXIST ? */
3009 return ret;
3010 }
3011
3012 iwl_restore_wepkeys(priv);
3013
3014 /* Initialize rate scaling */
3015 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM \n",
3016 sta->addr);
3017 iwl_rs_rate_init(priv, sta, sta_id);
3018
3019 return ret;
3020}
3021
b481de9c
ZY
3022/*****************************************************************************
3023 *
3024 * sysfs attributes
3025 *
3026 *****************************************************************************/
3027
0a6857e7 3028#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3029
3030/*
3031 * The following adds a new attribute to the sysfs representation
c3a739fa 3032 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
3033 * used for controlling the debug level.
3034 *
3035 * See the level definitions in iwl for details.
a562a9dd 3036 *
3d816c77
RC
3037 * The debug_level being managed using sysfs below is a per device debug
3038 * level that is used instead of the global debug level if it (the per
3039 * device debug level) is set.
b481de9c 3040 */
8cf769c6
EK
3041static ssize_t show_debug_level(struct device *d,
3042 struct device_attribute *attr, char *buf)
b481de9c 3043{
3d816c77
RC
3044 struct iwl_priv *priv = dev_get_drvdata(d);
3045 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3046}
8cf769c6
EK
3047static ssize_t store_debug_level(struct device *d,
3048 struct device_attribute *attr,
b481de9c
ZY
3049 const char *buf, size_t count)
3050{
928841b1 3051 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3052 unsigned long val;
3053 int ret;
b481de9c 3054
9257746f
TW
3055 ret = strict_strtoul(buf, 0, &val);
3056 if (ret)
978785a3 3057 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3058 else {
3d816c77 3059 priv->debug_level = val;
20594eb0
WYG
3060 if (iwl_alloc_traffic_mem(priv))
3061 IWL_ERR(priv,
3062 "Not enough memory to generate traffic log\n");
3063 }
b481de9c
ZY
3064 return strnlen(buf, count);
3065}
3066
8cf769c6
EK
3067static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3068 show_debug_level, store_debug_level);
3069
b481de9c 3070
0a6857e7 3071#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3072
b481de9c
ZY
3073
3074static ssize_t show_temperature(struct device *d,
3075 struct device_attribute *attr, char *buf)
3076{
928841b1 3077 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3078
fee1247a 3079 if (!iwl_is_alive(priv))
b481de9c
ZY
3080 return -EAGAIN;
3081
91dbc5bd 3082 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
3083}
3084
3085static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3086
b481de9c
ZY
3087static ssize_t show_tx_power(struct device *d,
3088 struct device_attribute *attr, char *buf)
3089{
928841b1 3090 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
3091
3092 if (!iwl_is_ready_rf(priv))
3093 return sprintf(buf, "off\n");
3094 else
3095 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3096}
3097
3098static ssize_t store_tx_power(struct device *d,
3099 struct device_attribute *attr,
3100 const char *buf, size_t count)
3101{
928841b1 3102 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3103 unsigned long val;
3104 int ret;
b481de9c 3105
9257746f
TW
3106 ret = strict_strtoul(buf, 10, &val);
3107 if (ret)
978785a3 3108 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
3109 else {
3110 ret = iwl_set_tx_power(priv, val, false);
3111 if (ret)
3112 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
3113 ret);
3114 else
3115 ret = count;
3116 }
3117 return ret;
b481de9c
ZY
3118}
3119
3120static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3121
b481de9c
ZY
3122static ssize_t show_statistics(struct device *d,
3123 struct device_attribute *attr, char *buf)
3124{
c79dd5b5 3125 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 3126 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 3127 u32 len = 0, ofs = 0;
3ac7f146 3128 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
3129 int rc = 0;
3130
fee1247a 3131 if (!iwl_is_alive(priv))
b481de9c
ZY
3132 return -EAGAIN;
3133
3134 mutex_lock(&priv->mutex);
ef8d5529 3135 rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
b481de9c
ZY
3136 mutex_unlock(&priv->mutex);
3137
3138 if (rc) {
3139 len = sprintf(buf,
3140 "Error sending statistics request: 0x%08X\n", rc);
3141 return len;
3142 }
3143
3144 while (size && (PAGE_SIZE - len)) {
3145 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3146 PAGE_SIZE - len, 1);
3147 len = strlen(buf);
3148 if (PAGE_SIZE - len)
3149 buf[len++] = '\n';
3150
3151 ofs += 16;
3152 size -= min(size, 16U);
3153 }
3154
3155 return len;
3156}
3157
3158static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3159
01abfbb2
WYG
3160static ssize_t show_rts_ht_protection(struct device *d,
3161 struct device_attribute *attr, char *buf)
3162{
3163 struct iwl_priv *priv = dev_get_drvdata(d);
3164
3165 return sprintf(buf, "%s\n",
3166 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3167}
3168
3169static ssize_t store_rts_ht_protection(struct device *d,
3170 struct device_attribute *attr,
3171 const char *buf, size_t count)
3172{
3173 struct iwl_priv *priv = dev_get_drvdata(d);
3174 unsigned long val;
3175 int ret;
3176
3177 ret = strict_strtoul(buf, 10, &val);
3178 if (ret)
3179 IWL_INFO(priv, "Input is not in decimal form.\n");
3180 else {
3181 if (!iwl_is_associated(priv))
3182 priv->cfg->use_rts_for_ht = val ? true : false;
3183 else
3184 IWL_ERR(priv, "Sta associated with AP - "
3185 "Change protection mechanism is not allowed\n");
3186 ret = count;
3187 }
3188 return ret;
3189}
3190
3191static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3192 show_rts_ht_protection, store_rts_ht_protection);
3193
b481de9c 3194
b481de9c
ZY
3195/*****************************************************************************
3196 *
3197 * driver setup and teardown
3198 *
3199 *****************************************************************************/
3200
4e39317d 3201static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3202{
d21050c7 3203 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3204
3205 init_waitqueue_head(&priv->wait_command_queue);
3206
5b9f8cd3
EG
3207 INIT_WORK(&priv->restart, iwl_bg_restart);
3208 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3209 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3210 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
3211 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3212 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3213
2a421b91 3214 iwl_setup_scan_deferred_work(priv);
bb8c093b 3215
4e39317d
EG
3216 if (priv->cfg->ops->lib->setup_deferred_work)
3217 priv->cfg->ops->lib->setup_deferred_work(priv);
3218
3219 init_timer(&priv->statistics_periodic);
3220 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3221 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3222
a9e1cb6a
WYG
3223 init_timer(&priv->ucode_trace);
3224 priv->ucode_trace.data = (unsigned long)priv;
3225 priv->ucode_trace.function = iwl_bg_ucode_trace;
3226
ef850d7c
MA
3227 if (!priv->cfg->use_isr_legacy)
3228 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3229 iwl_irq_tasklet, (unsigned long)priv);
3230 else
3231 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3232 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
3233}
3234
4e39317d 3235static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3236{
4e39317d
EG
3237 if (priv->cfg->ops->lib->cancel_deferred_work)
3238 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3239
3ae6a054 3240 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3241 cancel_delayed_work(&priv->scan_check);
3242 cancel_delayed_work(&priv->alive_start);
b481de9c 3243 cancel_work_sync(&priv->beacon_update);
4e39317d 3244 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3245 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY
3246}
3247
89f186a8
RC
3248static void iwl_init_hw_rates(struct iwl_priv *priv,
3249 struct ieee80211_rate *rates)
3250{
3251 int i;
3252
3253 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3254 rates[i].bitrate = iwl_rates[i].ieee * 5;
3255 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3256 rates[i].hw_value_short = i;
3257 rates[i].flags = 0;
3258 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3259 /*
3260 * If CCK != 1M then set short preamble rate flag.
3261 */
3262 rates[i].flags |=
3263 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3264 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3265 }
3266 }
3267}
3268
3269static int iwl_init_drv(struct iwl_priv *priv)
3270{
3271 int ret;
3272
3273 priv->ibss_beacon = NULL;
3274
89f186a8
RC
3275 spin_lock_init(&priv->sta_lock);
3276 spin_lock_init(&priv->hcmd_lock);
3277
3278 INIT_LIST_HEAD(&priv->free_frames);
3279
3280 mutex_init(&priv->mutex);
d2dfe6df 3281 mutex_init(&priv->sync_cmd_mutex);
89f186a8 3282
89f186a8
RC
3283 priv->ieee_channels = NULL;
3284 priv->ieee_rates = NULL;
3285 priv->band = IEEE80211_BAND_2GHZ;
3286
3287 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3288 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3289 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
89f186a8 3290
8a472da4
WYG
3291 /* initialize force reset */
3292 priv->force_reset[IWL_RF_RESET].reset_duration =
3293 IWL_DELAY_NEXT_FORCE_RF_RESET;
3294 priv->force_reset[IWL_FW_RESET].reset_duration =
3295 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC
3296
3297 /* Choose which receivers/antennas to use */
3298 if (priv->cfg->ops->hcmd->set_rxon_chain)
3299 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3300
3301 iwl_init_scan_params(priv);
3302
3303 iwl_reset_qos(priv);
3304
3305 priv->qos_data.qos_active = 0;
3306 priv->qos_data.qos_cap.val = 0;
3307
89f186a8
RC
3308 /* Set the tx_power_user_lmt to the lowest power level
3309 * this value will get overwritten by channel max power avg
3310 * from eeprom */
3311 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
3312
3313 ret = iwl_init_channel_map(priv);
3314 if (ret) {
3315 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3316 goto err;
3317 }
3318
3319 ret = iwlcore_init_geos(priv);
3320 if (ret) {
3321 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3322 goto err_free_channel_map;
3323 }
3324 iwl_init_hw_rates(priv, priv->ieee_rates);
3325
3326 return 0;
3327
3328err_free_channel_map:
3329 iwl_free_channel_map(priv);
3330err:
3331 return ret;
3332}
3333
3334static void iwl_uninit_drv(struct iwl_priv *priv)
3335{
3336 iwl_calib_free_results(priv);
3337 iwlcore_free_geos(priv);
3338 iwl_free_channel_map(priv);
3339 kfree(priv->scan);
3340}
3341
5b9f8cd3 3342static struct attribute *iwl_sysfs_entries[] = {
b481de9c 3343 &dev_attr_statistics.attr,
b481de9c 3344 &dev_attr_temperature.attr,
b481de9c 3345 &dev_attr_tx_power.attr,
01abfbb2 3346 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK
3347#ifdef CONFIG_IWLWIFI_DEBUG
3348 &dev_attr_debug_level.attr,
3349#endif
b481de9c
ZY
3350 NULL
3351};
3352
5b9f8cd3 3353static struct attribute_group iwl_attribute_group = {
b481de9c 3354 .name = NULL, /* put in device directory */
5b9f8cd3 3355 .attrs = iwl_sysfs_entries,
b481de9c
ZY
3356};
3357
5b9f8cd3
EG
3358static struct ieee80211_ops iwl_hw_ops = {
3359 .tx = iwl_mac_tx,
3360 .start = iwl_mac_start,
3361 .stop = iwl_mac_stop,
3362 .add_interface = iwl_mac_add_interface,
3363 .remove_interface = iwl_mac_remove_interface,
3364 .config = iwl_mac_config,
5b9f8cd3
EG
3365 .configure_filter = iwl_configure_filter,
3366 .set_key = iwl_mac_set_key,
3367 .update_tkip_key = iwl_mac_update_tkip_key,
3368 .get_stats = iwl_mac_get_stats,
5b9f8cd3
EG
3369 .conf_tx = iwl_mac_conf_tx,
3370 .reset_tsf = iwl_mac_reset_tsf,
3371 .bss_info_changed = iwl_bss_info_changed,
3372 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB
3373 .hw_scan = iwl_mac_hw_scan,
3374 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC
3375 .sta_add = iwlagn_mac_sta_add,
3376 .sta_remove = iwl_mac_sta_remove,
b481de9c
ZY
3377};
3378
5b9f8cd3 3379static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3380{
3381 int err = 0;
c79dd5b5 3382 struct iwl_priv *priv;
b481de9c 3383 struct ieee80211_hw *hw;
82b9a121 3384 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3385 unsigned long flags;
6cd0b1cb 3386 u16 pci_cmd;
b481de9c 3387
316c30d9
AK
3388 /************************
3389 * 1. Allocating HW data
3390 ************************/
3391
6440adb5
BC
3392 /* Disabling hardware scan means that mac80211 will perform scans
3393 * "the hard way", rather than using device's scan. */
1ea87396 3394 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3395 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
3396 dev_printk(KERN_DEBUG, &(pdev->dev),
3397 "Disabling hw_scan\n");
5b9f8cd3 3398 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3399 }
3400
5b9f8cd3 3401 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3402 if (!hw) {
b481de9c
ZY
3403 err = -ENOMEM;
3404 goto out;
3405 }
1d0a082d
AK
3406 priv = hw->priv;
3407 /* At this point both hw and priv are allocated. */
3408
b481de9c
ZY
3409 SET_IEEE80211_DEV(hw, &pdev->dev);
3410
e1623446 3411 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3412 priv->cfg = cfg;
b481de9c 3413 priv->pci_dev = pdev;
40cefda9 3414 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3415
0a6857e7 3416#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3417 atomic_set(&priv->restrict_refcnt, 0);
3418#endif
20594eb0
WYG
3419 if (iwl_alloc_traffic_mem(priv))
3420 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3421
316c30d9
AK
3422 /**************************
3423 * 2. Initializing PCI bus
3424 **************************/
3425 if (pci_enable_device(pdev)) {
3426 err = -ENODEV;
3427 goto out_ieee80211_free_hw;
3428 }
3429
3430 pci_set_master(pdev);
3431
093d874c 3432 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3433 if (!err)
093d874c 3434 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3435 if (err) {
093d874c 3436 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3437 if (!err)
093d874c 3438 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3439 /* both attempts failed: */
316c30d9 3440 if (err) {
978785a3 3441 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3442 goto out_pci_disable_device;
cc2a8ea8 3443 }
316c30d9
AK
3444 }
3445
3446 err = pci_request_regions(pdev, DRV_NAME);
3447 if (err)
3448 goto out_pci_disable_device;
3449
3450 pci_set_drvdata(pdev, priv);
3451
316c30d9
AK
3452
3453 /***********************
3454 * 3. Read REV register
3455 ***********************/
3456 priv->hw_base = pci_iomap(pdev, 0, 0);
3457 if (!priv->hw_base) {
3458 err = -ENODEV;
3459 goto out_pci_release_regions;
3460 }
3461
e1623446 3462 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3463 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3464 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3465
731a29b7 3466 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA
3467 * we should init now
3468 */
3469 spin_lock_init(&priv->reg_lock);
731a29b7 3470 spin_lock_init(&priv->lock);
4843b5a7
RC
3471
3472 /*
3473 * stop and reset the on-board processor just in case it is in a
3474 * strange state ... like being left stranded by a primary kernel
3475 * and this is now the kdump kernel trying to start up
3476 */
3477 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3478
b661c819 3479 iwl_hw_detect(priv);
978785a3 3480 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 3481 priv->cfg->name, priv->hw_rev);
316c30d9 3482
e7b63581
TW
3483 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3484 * PCI Tx retries from interfering with C3 CPU state */
3485 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3486
086ed117
MA
3487 iwl_prepare_card_hw(priv);
3488 if (!priv->hw_ready) {
3489 IWL_WARN(priv, "Failed, HW not ready\n");
3490 goto out_iounmap;
3491 }
3492
91238714
TW
3493 /*****************
3494 * 4. Read EEPROM
3495 *****************/
316c30d9
AK
3496 /* Read the EEPROM */
3497 err = iwl_eeprom_init(priv);
3498 if (err) {
15b1687c 3499 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3500 goto out_iounmap;
3501 }
8614f360
TW
3502 err = iwl_eeprom_check_version(priv);
3503 if (err)
c8f16138 3504 goto out_free_eeprom;
8614f360 3505
02883017 3506 /* extract MAC Address */
316c30d9 3507 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3508 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3509 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3510
3511 /************************
3512 * 5. Setup HW constants
3513 ************************/
da154e30 3514 if (iwl_set_hw_params(priv)) {
15b1687c 3515 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3516 goto out_free_eeprom;
316c30d9
AK
3517 }
3518
3519 /*******************
6ba87956 3520 * 6. Setup priv
316c30d9 3521 *******************/
b481de9c 3522
6ba87956 3523 err = iwl_init_drv(priv);
bf85ea4f 3524 if (err)
399f4900 3525 goto out_free_eeprom;
bf85ea4f 3526 /* At this point both hw and priv are initialized. */
316c30d9 3527
316c30d9 3528 /********************
09f9bf79 3529 * 7. Setup services
316c30d9 3530 ********************/
0359facc 3531 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3532 iwl_disable_interrupts(priv);
0359facc 3533 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3534
6cd0b1cb
HS
3535 pci_enable_msi(priv->pci_dev);
3536
ef850d7c
MA
3537 iwl_alloc_isr_ict(priv);
3538 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3539 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3540 if (err) {
3541 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3542 goto out_disable_msi;
3543 }
5b9f8cd3 3544 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3545 if (err) {
15b1687c 3546 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3547 goto out_free_irq;
316c30d9
AK
3548 }
3549
4e39317d 3550 iwl_setup_deferred_work(priv);
653fa4a0 3551 iwl_setup_rx_handlers(priv);
316c30d9 3552
158bea07
JB
3553 /*********************************************
3554 * 8. Enable interrupts and read RFKILL state
3555 *********************************************/
6ba87956 3556
6cd0b1cb
HS
3557 /* enable interrupts if needed: hw bug w/a */
3558 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3559 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3560 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3561 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3562 }
3563
3564 iwl_enable_interrupts(priv);
3565
6cd0b1cb
HS
3566 /* If platform's RF_KILL switch is NOT set to KILL */
3567 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3568 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3569 else
3570 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3571
a60e77e5
JB
3572 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3573 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3574
58d0f361 3575 iwl_power_initialize(priv);
39b73fb1 3576 iwl_tt_initialize(priv);
158bea07 3577
b08dfd04 3578 err = iwl_request_firmware(priv, true);
158bea07
JB
3579 if (err)
3580 goto out_remove_sysfs;
3581
b481de9c
ZY
3582 return 0;
3583
316c30d9 3584 out_remove_sysfs:
c8f16138
RC
3585 destroy_workqueue(priv->workqueue);
3586 priv->workqueue = NULL;
5b9f8cd3 3587 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3588 out_free_irq:
3589 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3590 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3591 out_disable_msi:
3592 pci_disable_msi(priv->pci_dev);
6ba87956 3593 iwl_uninit_drv(priv);
073d3f5f
TW
3594 out_free_eeprom:
3595 iwl_eeprom_free(priv);
b481de9c
ZY
3596 out_iounmap:
3597 pci_iounmap(pdev, priv->hw_base);
3598 out_pci_release_regions:
316c30d9 3599 pci_set_drvdata(pdev, NULL);
623d563e 3600 pci_release_regions(pdev);
b481de9c
ZY
3601 out_pci_disable_device:
3602 pci_disable_device(pdev);
b481de9c 3603 out_ieee80211_free_hw:
20594eb0 3604 iwl_free_traffic_mem(priv);
d7c76f4c 3605 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3606 out:
3607 return err;
3608}
3609
5b9f8cd3 3610static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3611{
c79dd5b5 3612 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3613 unsigned long flags;
b481de9c
ZY
3614
3615 if (!priv)
3616 return;
3617
e1623446 3618 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3619
67249625 3620 iwl_dbgfs_unregister(priv);
5b9f8cd3 3621 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3622
5b9f8cd3
EG
3623 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3624 * to be called and iwl_down since we are removing the device
0b124c31
GG
3625 * we need to set STATUS_EXIT_PENDING bit.
3626 */
3627 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3628 if (priv->mac80211_registered) {
3629 ieee80211_unregister_hw(priv->hw);
3630 priv->mac80211_registered = 0;
0b124c31 3631 } else {
5b9f8cd3 3632 iwl_down(priv);
c4f55232
RR
3633 }
3634
c166b25a
BC
3635 /*
3636 * Make sure device is reset to low power before unloading driver.
3637 * This may be redundant with iwl_down(), but there are paths to
3638 * run iwl_down() without calling apm_ops.stop(), and there are
3639 * paths to avoid running iwl_down() at all before leaving driver.
3640 * This (inexpensive) call *makes sure* device is reset.
3641 */
3642 priv->cfg->ops->lib->apm_ops.stop(priv);
3643
39b73fb1
WYG
3644 iwl_tt_exit(priv);
3645
0359facc
MA
3646 /* make sure we flush any pending irq or
3647 * tasklet for the driver
3648 */
3649 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3650 iwl_disable_interrupts(priv);
0359facc
MA
3651 spin_unlock_irqrestore(&priv->lock, flags);
3652
3653 iwl_synchronize_irq(priv);
3654
5b9f8cd3 3655 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3656
3657 if (priv->rxq.bd)
a55360e4 3658 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3659 iwl_hw_txq_ctx_free(priv);
b481de9c 3660
073d3f5f 3661 iwl_eeprom_free(priv);
b481de9c 3662
b481de9c 3663
948c171c
MA
3664 /*netif_stop_queue(dev); */
3665 flush_workqueue(priv->workqueue);
3666
5b9f8cd3 3667 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3668 * priv->workqueue... so we can't take down the workqueue
3669 * until now... */
3670 destroy_workqueue(priv->workqueue);
3671 priv->workqueue = NULL;
20594eb0 3672 iwl_free_traffic_mem(priv);
b481de9c 3673
6cd0b1cb
HS
3674 free_irq(priv->pci_dev->irq, priv);
3675 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3676 pci_iounmap(pdev, priv->hw_base);
3677 pci_release_regions(pdev);
3678 pci_disable_device(pdev);
3679 pci_set_drvdata(pdev, NULL);
3680
6ba87956 3681 iwl_uninit_drv(priv);
b481de9c 3682
ef850d7c
MA
3683 iwl_free_isr_ict(priv);
3684
b481de9c
ZY
3685 if (priv->ibss_beacon)
3686 dev_kfree_skb(priv->ibss_beacon);
3687
3688 ieee80211_free_hw(priv->hw);
3689}
3690
b481de9c
ZY
3691
3692/*****************************************************************************
3693 *
3694 * driver and module entry point
3695 *
3696 *****************************************************************************/
3697
fed9017e 3698/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 3699static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 3700#ifdef CONFIG_IWL4965
fed9017e
RR
3701 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3702 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3703#endif /* CONFIG_IWL4965 */
5a6a256e 3704#ifdef CONFIG_IWL5000
ac592574
WYG
3705/* 5100 Series WiFi */
3706 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3707 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3708 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3709 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3710 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3711 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3712 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3713 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3714 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3715 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3716 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3717 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3718 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3719 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3720 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3721 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3722 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3723 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3724 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3725 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3726 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3727 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3728 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3729 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3730
3731/* 5300 Series WiFi */
3732 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3733 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3734 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3735 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3736 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3737 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3738 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3739 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3740 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3741 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3742 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3743 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3744
3745/* 5350 Series WiFi/WiMax */
3746 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3747 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3748 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3749
3750/* 5150 Series Wifi/WiMax */
3751 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3752 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3753 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3754 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3755 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3756 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3757
3758 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3759 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3760 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3761 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG
3762
3763/* 6x00 Series */
5953a62e
WYG
3764 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3765 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3766 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3767 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3768 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3769 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3770 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3771 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3772 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3773 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3774
3775/* 6x50 WiFi/WiMax Series */
5953a62e
WYG
3776 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3777 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3778 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3779 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG
3780 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3781 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3782
77dcb6a9 3783/* 1000 Series WiFi */
4bd0914f
WYG
3784 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3785 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3786 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3787 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3788 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3789 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3790 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3791 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3792 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3793 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3794 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3795 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 3796#endif /* CONFIG_IWL5000 */
7100e924 3797
fed9017e
RR
3798 {0}
3799};
3800MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3801
3802static struct pci_driver iwl_driver = {
b481de9c 3803 .name = DRV_NAME,
fed9017e 3804 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3805 .probe = iwl_pci_probe,
3806 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3807#ifdef CONFIG_PM
5b9f8cd3
EG
3808 .suspend = iwl_pci_suspend,
3809 .resume = iwl_pci_resume,
b481de9c
ZY
3810#endif
3811};
3812
5b9f8cd3 3813static int __init iwl_init(void)
b481de9c
ZY
3814{
3815
3816 int ret;
3817 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3818 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3819
e227ceac 3820 ret = iwlagn_rate_control_register();
897e1cf2 3821 if (ret) {
a3139c59
SO
3822 printk(KERN_ERR DRV_NAME
3823 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3824 return ret;
3825 }
3826
fed9017e 3827 ret = pci_register_driver(&iwl_driver);
b481de9c 3828 if (ret) {
a3139c59 3829 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3830 goto error_register;
b481de9c 3831 }
b481de9c
ZY
3832
3833 return ret;
897e1cf2 3834
897e1cf2 3835error_register:
e227ceac 3836 iwlagn_rate_control_unregister();
897e1cf2 3837 return ret;
b481de9c
ZY
3838}
3839
5b9f8cd3 3840static void __exit iwl_exit(void)
b481de9c 3841{
fed9017e 3842 pci_unregister_driver(&iwl_driver);
e227ceac 3843 iwlagn_rate_control_unregister();
b481de9c
ZY
3844}
3845
5b9f8cd3
EG
3846module_exit(iwl_exit);
3847module_init(iwl_init);
a562a9dd
RC
3848
3849#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3850module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 3851MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 3852module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
3853MODULE_PARM_DESC(debug, "debug output mask");
3854#endif
3855