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iwlwifi: Fix issue on file transfer stalled in HT mode
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
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43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO
47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
b481de9c
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
b481de9c
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64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
80bc5393 75#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
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92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
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101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
e0158e61 105int iwl_commit_rxon(struct iwl_priv *priv)
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106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
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115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
118
8ccde88a 119 ret = iwl_check_rxon_cmd(priv);
43d59b32 120 if (ret) {
15b1687c 121 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
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122 return -EINVAL;
123 }
124
0924e519
WYG
125 /*
126 * receive commit_rxon request
127 * abort any previous channel switch if still in process
128 */
129 if (priv->switch_rxon.switch_in_progress &&
130 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
131 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
132 le16_to_cpu(priv->switch_rxon.channel));
133 priv->switch_rxon.switch_in_progress = false;
134 }
135
b481de9c 136 /* If we don't need to send a full RXON, we can use
5b9f8cd3 137 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 138 * and other flags for the current radio configuration. */
54559703 139 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
140 ret = iwl_send_rxon_assoc(priv);
141 if (ret) {
15b1687c 142 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 143 return ret;
b481de9c
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144 }
145
146 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 147 iwl_print_rx_config_cmd(priv);
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148 return 0;
149 }
150
151 /* station table will be cleared */
152 priv->assoc_station_added = 0;
153
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154 /* If we are currently associated and the new config requires
155 * an RXON_ASSOC and the new config wants the associated mask enabled,
156 * we must clear the associated from the active configuration
157 * before we apply the new config */
43d59b32 158 if (iwl_is_associated(priv) && new_assoc) {
e1623446 159 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
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160 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
161
43d59b32 162 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 163 sizeof(struct iwl_rxon_cmd),
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164 &priv->active_rxon);
165
166 /* If the mask clearing failed then we set
167 * active_rxon back to what it was previously */
43d59b32 168 if (ret) {
b481de9c 169 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 170 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 171 return ret;
b481de9c 172 }
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173 }
174
e1623446 175 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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176 "* with%s RXON_FILTER_ASSOC_MSK\n"
177 "* channel = %d\n"
e174961c 178 "* bssid = %pM\n",
43d59b32 179 (new_assoc ? "" : "out"),
b481de9c 180 le16_to_cpu(priv->staging_rxon.channel),
e174961c 181 priv->staging_rxon.bssid_addr);
b481de9c 182
90e8e424 183 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
184
185 /* Apply the new configuration
186 * RXON unassoc clears the station table in uCode, send it before
187 * we add the bcast station. If assoc bit is set, we will send RXON
188 * after having added the bcast and bssid station.
189 */
190 if (!new_assoc) {
191 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 192 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 193 if (ret) {
15b1687c 194 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
195 return ret;
196 }
197 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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198 }
199
c587de0b 200 iwl_clear_stations_table(priv);
556f8db7 201
19cc1087 202 priv->start_calib = 0;
b481de9c 203
b481de9c 204 /* Add the broadcast address so we can send broadcast frames */
9a9ca65f 205 iwl_add_bcast_station(priv);
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206
207 /* If we have set the ASSOC_MSK and we are in BSS mode then
208 * add the IWL_AP_ID to the station rate table */
9185159d 209 if (new_assoc) {
05c914fe 210 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
211 ret = iwl_rxon_add_station(priv,
212 priv->active_rxon.bssid_addr, 1);
213 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
214 IWL_ERR(priv,
215 "Error adding AP address for TX.\n");
9185159d
TW
216 return -EIO;
217 }
218 priv->assoc_station_added = 1;
219 if (priv->default_wep_key &&
220 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
221 IWL_ERR(priv,
222 "Could not send WEP static key.\n");
b481de9c 223 }
43d59b32 224
47eef9bd
WYG
225 /*
226 * allow CTS-to-self if possible for new association.
227 * this is relevant only for 5000 series and up,
228 * but will not damage 4965
229 */
230 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
231
43d59b32
EG
232 /* Apply the new configuration
233 * RXON assoc doesn't clear the station table in uCode,
234 */
235 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
236 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
237 if (ret) {
15b1687c 238 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
239 return ret;
240 }
241 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 242 }
a643565e 243 iwl_print_rx_config_cmd(priv);
b481de9c 244
36da7d70
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245 iwl_init_sensitivity(priv);
246
247 /* If we issue a new RXON command which required a tune then we must
248 * send a new TXPOWER command or we won't be able to Tx any frames */
249 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
250 if (ret) {
15b1687c 251 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY
252 return ret;
253 }
254
b481de9c
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255 return 0;
256}
257
5b9f8cd3 258void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
259{
260
45823531
AK
261 if (priv->cfg->ops->hcmd->set_rxon_chain)
262 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 263 iwlcore_commit_rxon(priv);
5da4b55f
MA
264}
265
fcab423d 266static void iwl_clear_free_frames(struct iwl_priv *priv)
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267{
268 struct list_head *element;
269
e1623446 270 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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271 priv->frames_count);
272
273 while (!list_empty(&priv->free_frames)) {
274 element = priv->free_frames.next;
275 list_del(element);
fcab423d 276 kfree(list_entry(element, struct iwl_frame, list));
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277 priv->frames_count--;
278 }
279
280 if (priv->frames_count) {
39aadf8c 281 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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282 priv->frames_count);
283 priv->frames_count = 0;
284 }
285}
286
fcab423d 287static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 288{
fcab423d 289 struct iwl_frame *frame;
b481de9c
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290 struct list_head *element;
291 if (list_empty(&priv->free_frames)) {
292 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
293 if (!frame) {
15b1687c 294 IWL_ERR(priv, "Could not allocate frame!\n");
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295 return NULL;
296 }
297
298 priv->frames_count++;
299 return frame;
300 }
301
302 element = priv->free_frames.next;
303 list_del(element);
fcab423d 304 return list_entry(element, struct iwl_frame, list);
b481de9c
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305}
306
fcab423d 307static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
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308{
309 memset(frame, 0, sizeof(*frame));
310 list_add(&frame->list, &priv->free_frames);
311}
312
4bf64efd
TW
313static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
314 struct ieee80211_hdr *hdr,
73ec1cc2 315 int left)
b481de9c 316{
3109ece1 317 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
318 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
319 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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320 return 0;
321
322 if (priv->ibss_beacon->len > left)
323 return 0;
324
325 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
326
327 return priv->ibss_beacon->len;
328}
329
5b9f8cd3 330static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
4bf64efd
TW
331 struct iwl_frame *frame, u8 rate)
332{
333 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
334 unsigned int frame_size;
335
336 tx_beacon_cmd = &frame->u.beacon;
337 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
338
339 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
340 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
341
342 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd
TW
343 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
344
345 BUG_ON(frame_size > MAX_MPDU_SIZE);
346 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
347
348 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
349 tx_beacon_cmd->tx.rate_n_flags =
350 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
351 else
352 tx_beacon_cmd->tx.rate_n_flags =
353 iwl_hw_set_rate_n_flags(rate, 0);
354
355 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
356 TX_CMD_FLG_TSF_MSK |
357 TX_CMD_FLG_STA_RATE_MSK;
358
359 return sizeof(*tx_beacon_cmd) + frame_size;
360}
5b9f8cd3 361static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 362{
fcab423d 363 struct iwl_frame *frame;
b481de9c
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364 unsigned int frame_size;
365 int rc;
366 u8 rate;
367
fcab423d 368 frame = iwl_get_free_frame(priv);
b481de9c
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369
370 if (!frame) {
15b1687c 371 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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372 "command.\n");
373 return -ENOMEM;
374 }
375
5b9f8cd3 376 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 377
5b9f8cd3 378 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 379
857485c0 380 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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381 &frame->u.cmd[0]);
382
fcab423d 383 iwl_free_frame(priv, frame);
b481de9c
ZY
384
385 return rc;
386}
387
7aaa1d79
SO
388static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
389{
390 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
391
392 dma_addr_t addr = get_unaligned_le32(&tb->lo);
393 if (sizeof(dma_addr_t) > sizeof(u32))
394 addr |=
395 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
396
397 return addr;
398}
399
400static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
401{
402 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
403
404 return le16_to_cpu(tb->hi_n_len) >> 4;
405}
406
407static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
408 dma_addr_t addr, u16 len)
409{
410 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
411 u16 hi_n_len = len << 4;
412
413 put_unaligned_le32(addr, &tb->lo);
414 if (sizeof(dma_addr_t) > sizeof(u32))
415 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
416
417 tb->hi_n_len = cpu_to_le16(hi_n_len);
418
419 tfd->num_tbs = idx + 1;
420}
421
422static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
423{
424 return tfd->num_tbs & 0x1f;
425}
426
427/**
428 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
429 * @priv - driver private data
430 * @txq - tx queue
431 *
432 * Does NOT advance any TFD circular buffer read/write indexes
433 * Does NOT free the TFD itself (which is within circular buffer)
434 */
435void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
436{
59606ffa 437 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
438 struct iwl_tfd *tfd;
439 struct pci_dev *dev = priv->pci_dev;
440 int index = txq->q.read_ptr;
441 int i;
442 int num_tbs;
443
444 tfd = &tfd_tmp[index];
445
446 /* Sanity check on number of chunks */
447 num_tbs = iwl_tfd_get_num_tbs(tfd);
448
449 if (num_tbs >= IWL_NUM_OF_TBS) {
450 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
451 /* @todo issue fatal error, it is quite serious situation */
452 return;
453 }
454
455 /* Unmap tx_cmd */
456 if (num_tbs)
457 pci_unmap_single(dev,
c2acea8e
JB
458 pci_unmap_addr(&txq->meta[index], mapping),
459 pci_unmap_len(&txq->meta[index], len),
96891cee 460 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
461
462 /* Unmap chunks, if any. */
463 for (i = 1; i < num_tbs; i++) {
464 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
465 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
466
467 if (txq->txb) {
468 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
469 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
470 }
471 }
472}
473
474int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
475 struct iwl_tx_queue *txq,
476 dma_addr_t addr, u16 len,
477 u8 reset, u8 pad)
478{
479 struct iwl_queue *q;
59606ffa 480 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
481 u32 num_tbs;
482
483 q = &txq->q;
59606ffa
SO
484 tfd_tmp = (struct iwl_tfd *)txq->tfds;
485 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
486
487 if (reset)
488 memset(tfd, 0, sizeof(*tfd));
489
490 num_tbs = iwl_tfd_get_num_tbs(tfd);
491
492 /* Each TFD can point to a maximum 20 Tx buffers */
493 if (num_tbs >= IWL_NUM_OF_TBS) {
494 IWL_ERR(priv, "Error can not send more than %d chunks\n",
495 IWL_NUM_OF_TBS);
496 return -EINVAL;
497 }
498
499 BUG_ON(addr & ~DMA_BIT_MASK(36));
500 if (unlikely(addr & ~IWL_TX_DMA_MASK))
501 IWL_ERR(priv, "Unaligned address = %llx\n",
502 (unsigned long long)addr);
503
504 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
505
506 return 0;
507}
508
a8e74e27
SO
509/*
510 * Tell nic where to find circular buffer of Tx Frame Descriptors for
511 * given Tx queue, and enable the DMA channel used for that queue.
512 *
513 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
514 * channels supported in hardware.
515 */
516int iwl_hw_tx_queue_init(struct iwl_priv *priv,
517 struct iwl_tx_queue *txq)
518{
a8e74e27
SO
519 int txq_id = txq->q.id;
520
a8e74e27
SO
521 /* Circular buffer (TFD queue in DRAM) physical base address */
522 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
523 txq->q.dma_addr >> 8);
524
a8e74e27
SO
525 return 0;
526}
527
b481de9c
ZY
528/******************************************************************************
529 *
530 * Generic RX handler implementations
531 *
532 ******************************************************************************/
885ba202
TW
533static void iwl_rx_reply_alive(struct iwl_priv *priv,
534 struct iwl_rx_mem_buffer *rxb)
b481de9c 535{
2f301227 536 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 537 struct iwl_alive_resp *palive;
b481de9c
ZY
538 struct delayed_work *pwork;
539
540 palive = &pkt->u.alive_frame;
541
e1623446 542 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
543 "0x%01X 0x%01X\n",
544 palive->is_valid, palive->ver_type,
545 palive->ver_subtype);
546
547 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 548 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
549 memcpy(&priv->card_alive_init,
550 &pkt->u.alive_frame,
885ba202 551 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
552 pwork = &priv->init_alive_start;
553 } else {
e1623446 554 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 555 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 556 sizeof(struct iwl_alive_resp));
b481de9c
ZY
557 pwork = &priv->alive_start;
558 }
559
560 /* We delay the ALIVE response by 5ms to
561 * give the HW RF Kill time to activate... */
562 if (palive->is_valid == UCODE_VALID_OK)
563 queue_delayed_work(priv->workqueue, pwork,
564 msecs_to_jiffies(5));
565 else
39aadf8c 566 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
567}
568
5b9f8cd3 569static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 570{
c79dd5b5
TW
571 struct iwl_priv *priv =
572 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
573 struct sk_buff *beacon;
574
575 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 576 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
577
578 if (!beacon) {
15b1687c 579 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
580 return;
581 }
582
583 mutex_lock(&priv->mutex);
584 /* new beacon skb is allocated every time; dispose previous.*/
585 if (priv->ibss_beacon)
586 dev_kfree_skb(priv->ibss_beacon);
587
588 priv->ibss_beacon = beacon;
589 mutex_unlock(&priv->mutex);
590
5b9f8cd3 591 iwl_send_beacon_cmd(priv);
b481de9c
ZY
592}
593
4e39317d 594/**
5b9f8cd3 595 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
596 *
597 * This callback is provided in order to send a statistics request.
598 *
599 * This timer function is continually reset to execute within
600 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
601 * was received. We need to ensure we receive the statistics in order
602 * to update the temperature used for calibrating the TXPOWER.
603 */
5b9f8cd3 604static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
605{
606 struct iwl_priv *priv = (struct iwl_priv *)data;
607
608 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
609 return;
610
61780ee3
MA
611 /* dont send host command if rf-kill is on */
612 if (!iwl_is_ready_rf(priv))
613 return;
614
4e39317d
EG
615 iwl_send_statistics_request(priv, CMD_ASYNC);
616}
617
5b9f8cd3 618static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 619 struct iwl_rx_mem_buffer *rxb)
b481de9c 620{
0a6857e7 621#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 622 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW
623 struct iwl4965_beacon_notif *beacon =
624 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 625 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 626
e1623446 627 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 628 "tsf %d %d rate %d\n",
25a6572c 629 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
630 beacon->beacon_notify_hdr.failure_frame,
631 le32_to_cpu(beacon->ibss_mgr_status),
632 le32_to_cpu(beacon->high_tsf),
633 le32_to_cpu(beacon->low_tsf), rate);
634#endif
635
05c914fe 636 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
637 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
638 queue_work(priv->workqueue, &priv->beacon_update);
639}
640
b481de9c
ZY
641/* Handle notification from uCode that card's power state is changing
642 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 643static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 644 struct iwl_rx_mem_buffer *rxb)
b481de9c 645{
2f301227 646 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
647 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
648 unsigned long status = priv->status;
649
e1623446 650 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
651 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
652 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
653
654 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
655 RF_CARD_DISABLED)) {
656
3395f6e9 657 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
658 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
659
a8b50a0a
MA
660 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
661 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
662
663 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 664 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 665 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 666 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 667 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 668 }
39b73fb1
WYG
669 if (flags & RF_CARD_DISABLED)
670 iwl_tt_enter_ct_kill(priv);
b481de9c 671 }
39b73fb1
WYG
672 if (!(flags & RF_CARD_DISABLED))
673 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
674
675 if (flags & HW_CARD_DISABLED)
676 set_bit(STATUS_RF_KILL_HW, &priv->status);
677 else
678 clear_bit(STATUS_RF_KILL_HW, &priv->status);
679
680
b481de9c 681 if (!(flags & RXON_CARD_DISABLED))
2a421b91 682 iwl_scan_cancel(priv);
b481de9c
ZY
683
684 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
685 test_bit(STATUS_RF_KILL_HW, &priv->status)))
686 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
687 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
688 else
689 wake_up_interruptible(&priv->wait_command_queue);
690}
691
5b9f8cd3 692int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 693{
e2e3c57b 694 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 695 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
696 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
697 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
698 ~APMG_PS_CTRL_MSK_PWR_SRC);
699 } else {
700 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
701 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
702 ~APMG_PS_CTRL_MSK_PWR_SRC);
703 }
704
a8b50a0a 705 return 0;
e2e3c57b
TW
706}
707
b481de9c 708/**
5b9f8cd3 709 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
710 *
711 * Setup the RX handlers for each of the reply types sent from the uCode
712 * to the host.
713 *
714 * This function chains into the hardware specific files for them to setup
715 * any hardware specific handlers as well.
716 */
653fa4a0 717static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 718{
885ba202 719 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
720 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
721 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 722 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 723 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
724 iwl_rx_pm_debug_statistics_notif;
725 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 726
9fbab516
BC
727 /*
728 * The same handler is used for both the REPLY to a discrete
729 * statistics request from the host as well as for the periodic
730 * statistics notifications (after received beacons) from the uCode.
b481de9c 731 */
8f91aecb
EG
732 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
733 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 734
21c339bf 735 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
736 iwl_setup_rx_scan_handlers(priv);
737
37a44211 738 /* status change handler */
5b9f8cd3 739 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 740
c1354754
TW
741 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
742 iwl_rx_missed_beacon_notif;
37a44211 743 /* Rx handlers */
1781a07f
EG
744 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
745 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
746 /* block ack */
747 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 748 /* Set up hardware specific Rx handlers */
d4789efe 749 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
750}
751
b481de9c 752/**
a55360e4 753 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
754 *
755 * Uses the priv->rx_handlers callback function array to invoke
756 * the appropriate handlers, including command responses,
757 * frame-received notifications, and other notifications.
758 */
a55360e4 759void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 760{
a55360e4 761 struct iwl_rx_mem_buffer *rxb;
db11d634 762 struct iwl_rx_packet *pkt;
a55360e4 763 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
764 u32 r, i;
765 int reclaim;
766 unsigned long flags;
5c0eef96 767 u8 fill_rx = 0;
d68ab680 768 u32 count = 8;
4752c93c 769 int total_empty;
b481de9c 770
6440adb5
BC
771 /* uCode's read index (stored in shared DRAM) indicates the last Rx
772 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 773 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
774 i = rxq->read;
775
776 /* Rx interrupt, but nothing sent from uCode */
777 if (i == r)
e1623446 778 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 779
4752c93c 780 /* calculate total frames need to be restock after handling RX */
7300515d 781 total_empty = r - rxq->write_actual;
4752c93c
MA
782 if (total_empty < 0)
783 total_empty += RX_QUEUE_SIZE;
784
785 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
786 fill_rx = 1;
787
b481de9c
ZY
788 while (i != r) {
789 rxb = rxq->queue[i];
790
9fbab516 791 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
792 * then a bug has been introduced in the queue refilling
793 * routines -- catch it here */
794 BUG_ON(rxb == NULL);
795
796 rxq->queue[i] = NULL;
797
2f301227
ZY
798 pci_unmap_page(priv->pci_dev, rxb->page_dma,
799 PAGE_SIZE << priv->hw_params.rx_page_order,
800 PCI_DMA_FROMDEVICE);
801 pkt = rxb_addr(rxb);
b481de9c 802
be1a71a1
JB
803 trace_iwlwifi_dev_rx(priv, pkt,
804 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
805
b481de9c
ZY
806 /* Reclaim a command buffer only if this packet is a response
807 * to a (driver-originated) command.
808 * If the packet (e.g. Rx frame) originated from uCode,
809 * there is no command buffer to reclaim.
810 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
811 * but apparently a few don't get set; catch them here. */
812 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
813 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 814 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 815 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 816 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
817 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
818 (pkt->hdr.cmd != REPLY_TX);
819
820 /* Based on type of command response or notification,
821 * handle those that need handling via function in
5b9f8cd3 822 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 823 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 824 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 825 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 826 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 827 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
828 } else {
829 /* No handling needed */
e1623446 830 IWL_DEBUG_RX(priv,
b481de9c
ZY
831 "r %d i %d No handler needed for %s, 0x%02x\n",
832 r, i, get_cmd_string(pkt->hdr.cmd),
833 pkt->hdr.cmd);
834 }
835
29b1b268
ZY
836 /*
837 * XXX: After here, we should always check rxb->page
838 * against NULL before touching it or its virtual
839 * memory (pkt). Because some rx_handler might have
840 * already taken or freed the pages.
841 */
842
b481de9c 843 if (reclaim) {
2f301227
ZY
844 /* Invoke any callbacks, transfer the buffer to caller,
845 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 846 * as we reclaim the driver command queue */
29b1b268 847 if (rxb->page)
17b88929 848 iwl_tx_cmd_complete(priv, rxb);
b481de9c 849 else
39aadf8c 850 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
851 }
852
7300515d
ZY
853 /* Reuse the page if possible. For notification packets and
854 * SKBs that fail to Rx correctly, add them back into the
855 * rx_free list for reuse later. */
856 spin_lock_irqsave(&rxq->lock, flags);
2f301227 857 if (rxb->page != NULL) {
7300515d
ZY
858 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
859 0, PAGE_SIZE << priv->hw_params.rx_page_order,
860 PCI_DMA_FROMDEVICE);
861 list_add_tail(&rxb->list, &rxq->rx_free);
862 rxq->free_count++;
863 } else
864 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 865
b481de9c 866 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 867
b481de9c 868 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
869 /* If there are a lot of unused frames,
870 * restock the Rx queue so ucode wont assert. */
871 if (fill_rx) {
872 count++;
873 if (count >= 8) {
7300515d 874 rxq->read = i;
4752c93c 875 iwl_rx_replenish_now(priv);
5c0eef96
MA
876 count = 0;
877 }
878 }
b481de9c
ZY
879 }
880
881 /* Backtrack one entry */
7300515d 882 rxq->read = i;
4752c93c
MA
883 if (fill_rx)
884 iwl_rx_replenish_now(priv);
885 else
886 iwl_rx_queue_restock(priv);
a55360e4 887}
a55360e4 888
0359facc
MA
889/* call this function to flush any scheduled tasklet */
890static inline void iwl_synchronize_irq(struct iwl_priv *priv)
891{
a96a27f9 892 /* wait to make sure we flush pending tasklet*/
0359facc
MA
893 synchronize_irq(priv->pci_dev->irq);
894 tasklet_kill(&priv->irq_tasklet);
895}
896
ef850d7c 897static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
898{
899 u32 inta, handled = 0;
900 u32 inta_fh;
901 unsigned long flags;
c2e61da2 902 u32 i;
0a6857e7 903#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
904 u32 inta_mask;
905#endif
906
907 spin_lock_irqsave(&priv->lock, flags);
908
909 /* Ack/clear/reset pending uCode interrupts.
910 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
911 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
912 inta = iwl_read32(priv, CSR_INT);
913 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
914
915 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
916 * Any new interrupts that happen after this, either while we're
917 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
918 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
919 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 920
0a6857e7 921#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 922 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 923 /* just for debug */
3395f6e9 924 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 925 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
926 inta, inta_mask, inta_fh);
927 }
928#endif
929
2f301227
ZY
930 spin_unlock_irqrestore(&priv->lock, flags);
931
b481de9c
ZY
932 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
933 * atomic, make sure that inta covers all the interrupts that
934 * we've discovered, even if FH interrupt came in just after
935 * reading CSR_INT. */
6f83eaa1 936 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 937 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 938 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
939 inta |= CSR_INT_BIT_FH_TX;
940
941 /* Now service all interrupt bits discovered above. */
942 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 943 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
944
945 /* Tell the device to stop sending interrupts */
5b9f8cd3 946 iwl_disable_interrupts(priv);
b481de9c 947
a83b9141 948 priv->isr_stats.hw++;
5b9f8cd3 949 iwl_irq_handle_error(priv);
b481de9c
ZY
950
951 handled |= CSR_INT_BIT_HW_ERR;
952
b481de9c
ZY
953 return;
954 }
955
0a6857e7 956#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 957 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 958 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 959 if (inta & CSR_INT_BIT_SCD) {
e1623446 960 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 961 "the frame/frames.\n");
a83b9141
WYG
962 priv->isr_stats.sch++;
963 }
b481de9c
ZY
964
965 /* Alive notification via Rx interrupt will do the real work */
a83b9141 966 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 967 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
968 priv->isr_stats.alive++;
969 }
b481de9c
ZY
970 }
971#endif
972 /* Safely ignore these bits for debug checks below */
25c03d8e 973 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 974
9fbab516 975 /* HW RF KILL switch toggled */
b481de9c
ZY
976 if (inta & CSR_INT_BIT_RF_KILL) {
977 int hw_rf_kill = 0;
3395f6e9 978 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
979 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
980 hw_rf_kill = 1;
981
4c423a2b 982 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 983 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 984
a83b9141
WYG
985 priv->isr_stats.rfkill++;
986
a9efa652 987 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
988 * the driver allows loading the ucode even if the radio
989 * is killed. Hence update the killswitch state here. The
990 * rfkill handler will care about restarting if needed.
a9efa652 991 */
6cd0b1cb
HS
992 if (!test_bit(STATUS_ALIVE, &priv->status)) {
993 if (hw_rf_kill)
994 set_bit(STATUS_RF_KILL_HW, &priv->status);
995 else
996 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 997 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 998 }
b481de9c
ZY
999
1000 handled |= CSR_INT_BIT_RF_KILL;
1001 }
1002
9fbab516 1003 /* Chip got too hot and stopped itself */
b481de9c 1004 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1005 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1006 priv->isr_stats.ctkill++;
b481de9c
ZY
1007 handled |= CSR_INT_BIT_CT_KILL;
1008 }
1009
1010 /* Error detected by uCode */
1011 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1012 IWL_ERR(priv, "Microcode SW error detected. "
1013 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1014 priv->isr_stats.sw++;
1015 priv->isr_stats.sw_err = inta;
5b9f8cd3 1016 iwl_irq_handle_error(priv);
b481de9c
ZY
1017 handled |= CSR_INT_BIT_SW_ERR;
1018 }
1019
c2e61da2
BC
1020 /*
1021 * uCode wakes up after power-down sleep.
1022 * Tell device about any new tx or host commands enqueued,
1023 * and about any Rx buffers made available while asleep.
1024 */
b481de9c 1025 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1026 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1027 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC
1028 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1029 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1030 priv->isr_stats.wakeup++;
b481de9c
ZY
1031 handled |= CSR_INT_BIT_WAKEUP;
1032 }
1033
1034 /* All uCode command responses, including Tx command responses,
1035 * Rx "responses" (frame-received notification), and other
1036 * notifications from uCode come through here*/
1037 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1038 iwl_rx_handle(priv);
a83b9141 1039 priv->isr_stats.rx++;
1ed2a3d2 1040 iwl_leds_background(priv);
b481de9c
ZY
1041 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1042 }
1043
c72cd19f 1044 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1045 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1046 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1047 priv->isr_stats.tx++;
b481de9c 1048 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1049 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR
1050 priv->ucode_write_complete = 1;
1051 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1052 }
1053
a83b9141 1054 if (inta & ~handled) {
15b1687c 1055 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1056 priv->isr_stats.unhandled++;
1057 }
b481de9c 1058
40cefda9 1059 if (inta & ~(priv->inta_mask)) {
39aadf8c 1060 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1061 inta & ~priv->inta_mask);
39aadf8c 1062 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1063 }
1064
1065 /* Re-enable all interrupts */
0359facc
MA
1066 /* only Re-enable if diabled by irq */
1067 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1068 iwl_enable_interrupts(priv);
b481de9c 1069
0a6857e7 1070#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1071 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1072 inta = iwl_read32(priv, CSR_INT);
1073 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1074 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1075 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1076 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1077 }
1078#endif
b481de9c
ZY
1079}
1080
ef850d7c
MA
1081/* tasklet for iwlagn interrupt */
1082static void iwl_irq_tasklet(struct iwl_priv *priv)
1083{
1084 u32 inta = 0;
1085 u32 handled = 0;
1086 unsigned long flags;
8756990f 1087 u32 i;
ef850d7c
MA
1088#ifdef CONFIG_IWLWIFI_DEBUG
1089 u32 inta_mask;
1090#endif
1091
1092 spin_lock_irqsave(&priv->lock, flags);
1093
1094 /* Ack/clear/reset pending uCode interrupts.
1095 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1096 */
1097 iwl_write32(priv, CSR_INT, priv->inta);
1098
1099 inta = priv->inta;
1100
1101#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1102 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1103 /* just for debug */
1104 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1105 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1106 inta, inta_mask);
1107 }
1108#endif
2f301227
ZY
1109
1110 spin_unlock_irqrestore(&priv->lock, flags);
1111
ef850d7c
MA
1112 /* saved interrupt in inta variable now we can reset priv->inta */
1113 priv->inta = 0;
1114
1115 /* Now service all interrupt bits discovered above. */
1116 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1117 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1118
1119 /* Tell the device to stop sending interrupts */
1120 iwl_disable_interrupts(priv);
1121
1122 priv->isr_stats.hw++;
1123 iwl_irq_handle_error(priv);
1124
1125 handled |= CSR_INT_BIT_HW_ERR;
1126
ef850d7c
MA
1127 return;
1128 }
1129
1130#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1131 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1132 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1133 if (inta & CSR_INT_BIT_SCD) {
1134 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1135 "the frame/frames.\n");
1136 priv->isr_stats.sch++;
1137 }
1138
1139 /* Alive notification via Rx interrupt will do the real work */
1140 if (inta & CSR_INT_BIT_ALIVE) {
1141 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1142 priv->isr_stats.alive++;
1143 }
1144 }
1145#endif
1146 /* Safely ignore these bits for debug checks below */
1147 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1148
1149 /* HW RF KILL switch toggled */
1150 if (inta & CSR_INT_BIT_RF_KILL) {
1151 int hw_rf_kill = 0;
1152 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1153 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1154 hw_rf_kill = 1;
1155
4c423a2b 1156 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1157 hw_rf_kill ? "disable radio" : "enable radio");
1158
1159 priv->isr_stats.rfkill++;
1160
1161 /* driver only loads ucode once setting the interface up.
1162 * the driver allows loading the ucode even if the radio
1163 * is killed. Hence update the killswitch state here. The
1164 * rfkill handler will care about restarting if needed.
1165 */
1166 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1167 if (hw_rf_kill)
1168 set_bit(STATUS_RF_KILL_HW, &priv->status);
1169 else
1170 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1171 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1172 }
1173
1174 handled |= CSR_INT_BIT_RF_KILL;
1175 }
1176
1177 /* Chip got too hot and stopped itself */
1178 if (inta & CSR_INT_BIT_CT_KILL) {
1179 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1180 priv->isr_stats.ctkill++;
1181 handled |= CSR_INT_BIT_CT_KILL;
1182 }
1183
1184 /* Error detected by uCode */
1185 if (inta & CSR_INT_BIT_SW_ERR) {
1186 IWL_ERR(priv, "Microcode SW error detected. "
1187 " Restarting 0x%X.\n", inta);
1188 priv->isr_stats.sw++;
1189 priv->isr_stats.sw_err = inta;
1190 iwl_irq_handle_error(priv);
1191 handled |= CSR_INT_BIT_SW_ERR;
1192 }
1193
1194 /* uCode wakes up after power-down sleep */
1195 if (inta & CSR_INT_BIT_WAKEUP) {
1196 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1197 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC
1198 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1199 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA
1200
1201 priv->isr_stats.wakeup++;
1202
1203 handled |= CSR_INT_BIT_WAKEUP;
1204 }
1205
1206 /* All uCode command responses, including Tx command responses,
1207 * Rx "responses" (frame-received notification), and other
1208 * notifications from uCode come through here*/
40cefda9
MA
1209 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1210 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1211 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1212 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1213 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1214 iwl_write32(priv, CSR_FH_INT_STATUS,
1215 CSR49_FH_INT_RX_MASK);
1216 }
1217 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1218 handled |= CSR_INT_BIT_RX_PERIODIC;
1219 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1220 }
1221 /* Sending RX interrupt require many steps to be done in the
1222 * the device:
1223 * 1- write interrupt to current index in ICT table.
1224 * 2- dma RX frame.
1225 * 3- update RX shared data to indicate last write index.
1226 * 4- send interrupt.
1227 * This could lead to RX race, driver could receive RX interrupt
1228 * but the shared data changes does not reflect this.
1229 * this could lead to RX race, RX periodic will solve this race
1230 */
1231 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1232 CSR_INT_PERIODIC_DIS);
ef850d7c 1233 iwl_rx_handle(priv);
40cefda9
MA
1234 /* Only set RX periodic if real RX is received. */
1235 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1236 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1237 CSR_INT_PERIODIC_ENA);
1238
ef850d7c 1239 priv->isr_stats.rx++;
1ed2a3d2 1240 iwl_leds_background(priv);
ef850d7c
MA
1241 }
1242
c72cd19f 1243 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA
1244 if (inta & CSR_INT_BIT_FH_TX) {
1245 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1246 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA
1247 priv->isr_stats.tx++;
1248 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1249 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA
1250 priv->ucode_write_complete = 1;
1251 wake_up_interruptible(&priv->wait_command_queue);
1252 }
1253
1254 if (inta & ~handled) {
1255 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1256 priv->isr_stats.unhandled++;
1257 }
1258
40cefda9 1259 if (inta & ~(priv->inta_mask)) {
ef850d7c 1260 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1261 inta & ~priv->inta_mask);
ef850d7c
MA
1262 }
1263
ef850d7c
MA
1264 /* Re-enable all interrupts */
1265 /* only Re-enable if diabled by irq */
1266 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1267 iwl_enable_interrupts(priv);
ef850d7c
MA
1268}
1269
a83b9141 1270
b481de9c
ZY
1271/******************************************************************************
1272 *
1273 * uCode download functions
1274 *
1275 ******************************************************************************/
1276
5b9f8cd3 1277static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1278{
98c92211
TW
1279 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1280 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1281 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1282 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1283 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1284 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1285}
1286
5b9f8cd3 1287static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1288{
1289 /* Remove all resets to allow NIC to operate */
1290 iwl_write32(priv, CSR_RESET, 0);
1291}
1292
1293
b481de9c 1294/**
5b9f8cd3 1295 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1296 *
1297 * Copy into buffers for card to fetch via bus-mastering
1298 */
5b9f8cd3 1299static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1300{
cc0f555d 1301 struct iwl_ucode_header *ucode;
a0987a8d 1302 int ret = -EINVAL, index;
b481de9c 1303 const struct firmware *ucode_raw;
a0987a8d
RC
1304 const char *name_pre = priv->cfg->fw_name_pre;
1305 const unsigned int api_max = priv->cfg->ucode_api_max;
1306 const unsigned int api_min = priv->cfg->ucode_api_min;
1307 char buf[25];
b481de9c
ZY
1308 u8 *src;
1309 size_t len;
cc0f555d
JS
1310 u32 api_ver, build;
1311 u32 inst_size, data_size, init_size, init_data_size, boot_size;
abdc2d62 1312 u16 eeprom_ver;
b481de9c
ZY
1313
1314 /* Ask kernel firmware_class module to get the boot firmware off disk.
1315 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1316 for (index = api_max; index >= api_min; index--) {
1317 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1318 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1319 if (ret < 0) {
15b1687c 1320 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1321 buf, ret);
1322 if (ret == -ENOENT)
1323 continue;
1324 else
1325 goto error;
1326 } else {
1327 if (index < api_max)
15b1687c
WT
1328 IWL_ERR(priv, "Loaded firmware %s, "
1329 "which is deprecated. "
1330 "Please use API v%u instead.\n",
a0987a8d 1331 buf, api_max);
15b1687c 1332
e1623446 1333 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1334 buf, ucode_raw->size);
1335 break;
1336 }
b481de9c
ZY
1337 }
1338
a0987a8d
RC
1339 if (ret < 0)
1340 goto error;
b481de9c 1341
cc0f555d
JS
1342 /* Make sure that we got at least the v1 header! */
1343 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1344 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1345 ret = -EINVAL;
b481de9c
ZY
1346 goto err_release;
1347 }
1348
1349 /* Data from ucode file: header followed by uCode images */
cc0f555d 1350 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1351
c02b3acd 1352 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1353 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1354 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1355 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1356 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1357 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1358 init_data_size =
1359 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1360 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1361 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1362
a0987a8d
RC
1363 /* api_ver should match the api version forming part of the
1364 * firmware filename ... but we don't check for that and only rely
877d0310 1365 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1366
1367 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1368 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1369 "Driver supports v%u, firmware is v%u.\n",
1370 api_max, api_ver);
1371 priv->ucode_ver = 0;
1372 ret = -EINVAL;
1373 goto err_release;
1374 }
1375 if (api_ver != api_max)
978785a3 1376 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1377 "got v%u. New firmware can be obtained "
1378 "from http://www.intellinuxwireless.org.\n",
1379 api_max, api_ver);
1380
978785a3
TW
1381 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1382 IWL_UCODE_MAJOR(priv->ucode_ver),
1383 IWL_UCODE_MINOR(priv->ucode_ver),
1384 IWL_UCODE_API(priv->ucode_ver),
1385 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1386
5ebeb5a6
RC
1387 snprintf(priv->hw->wiphy->fw_version,
1388 sizeof(priv->hw->wiphy->fw_version),
1389 "%u.%u.%u.%u",
1390 IWL_UCODE_MAJOR(priv->ucode_ver),
1391 IWL_UCODE_MINOR(priv->ucode_ver),
1392 IWL_UCODE_API(priv->ucode_ver),
1393 IWL_UCODE_SERIAL(priv->ucode_ver));
1394
cc0f555d
JS
1395 if (build)
1396 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1397
abdc2d62
JS
1398 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1399 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1400 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1401 ? "OTP" : "EEPROM", eeprom_ver);
1402
e1623446 1403 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1404 priv->ucode_ver);
e1623446 1405 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1406 inst_size);
e1623446 1407 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1408 data_size);
e1623446 1409 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1410 init_size);
e1623446 1411 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1412 init_data_size);
e1623446 1413 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1414 boot_size);
1415
1416 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1417 if (ucode_raw->size !=
1418 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1419 inst_size + data_size + init_size +
1420 init_data_size + boot_size) {
1421
cc0f555d
JS
1422 IWL_DEBUG_INFO(priv,
1423 "uCode file size %d does not match expected size\n",
1424 (int)ucode_raw->size);
90e759d1 1425 ret = -EINVAL;
b481de9c
ZY
1426 goto err_release;
1427 }
1428
1429 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1430 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1431 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1432 inst_size);
1433 ret = -EINVAL;
b481de9c
ZY
1434 goto err_release;
1435 }
1436
099b40b7 1437 if (data_size > priv->hw_params.max_data_size) {
e1623446 1438 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1439 data_size);
1440 ret = -EINVAL;
b481de9c
ZY
1441 goto err_release;
1442 }
099b40b7 1443 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1444 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1445 init_size);
90e759d1 1446 ret = -EINVAL;
b481de9c
ZY
1447 goto err_release;
1448 }
099b40b7 1449 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1450 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1451 init_data_size);
1452 ret = -EINVAL;
b481de9c
ZY
1453 goto err_release;
1454 }
099b40b7 1455 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1456 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1457 boot_size);
90e759d1 1458 ret = -EINVAL;
b481de9c
ZY
1459 goto err_release;
1460 }
1461
1462 /* Allocate ucode buffers for card's bus-master loading ... */
1463
1464 /* Runtime instructions and 2 copies of data:
1465 * 1) unmodified from disk
1466 * 2) backup cache for save/restore during power-downs */
1467 priv->ucode_code.len = inst_size;
98c92211 1468 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1469
1470 priv->ucode_data.len = data_size;
98c92211 1471 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1472
1473 priv->ucode_data_backup.len = data_size;
98c92211 1474 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1475
1f304e4e
ZY
1476 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1477 !priv->ucode_data_backup.v_addr)
1478 goto err_pci_alloc;
1479
b481de9c 1480 /* Initialization instructions and data */
90e759d1
TW
1481 if (init_size && init_data_size) {
1482 priv->ucode_init.len = init_size;
98c92211 1483 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1484
1485 priv->ucode_init_data.len = init_data_size;
98c92211 1486 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1487
1488 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1489 goto err_pci_alloc;
1490 }
b481de9c
ZY
1491
1492 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1493 if (boot_size) {
1494 priv->ucode_boot.len = boot_size;
98c92211 1495 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1496
90e759d1
TW
1497 if (!priv->ucode_boot.v_addr)
1498 goto err_pci_alloc;
1499 }
b481de9c
ZY
1500
1501 /* Copy images into buffers for card's bus-master reads ... */
1502
1503 /* Runtime instructions (first block of data in file) */
cc0f555d 1504 len = inst_size;
e1623446 1505 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1506 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1507 src += len;
1508
e1623446 1509 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1510 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1511
1512 /* Runtime data (2nd block)
5b9f8cd3 1513 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1514 len = data_size;
e1623446 1515 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1516 memcpy(priv->ucode_data.v_addr, src, len);
1517 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1518 src += len;
b481de9c
ZY
1519
1520 /* Initialization instructions (3rd block) */
1521 if (init_size) {
cc0f555d 1522 len = init_size;
e1623446 1523 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1524 len);
b481de9c 1525 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1526 src += len;
b481de9c
ZY
1527 }
1528
1529 /* Initialization data (4th block) */
1530 if (init_data_size) {
cc0f555d 1531 len = init_data_size;
e1623446 1532 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1533 len);
b481de9c 1534 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1535 src += len;
b481de9c
ZY
1536 }
1537
1538 /* Bootstrap instructions (5th block) */
cc0f555d 1539 len = boot_size;
e1623446 1540 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1541 memcpy(priv->ucode_boot.v_addr, src, len);
1542
1543 /* We have our copies now, allow OS release its copies */
1544 release_firmware(ucode_raw);
1545 return 0;
1546
1547 err_pci_alloc:
15b1687c 1548 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1549 ret = -ENOMEM;
5b9f8cd3 1550 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1551
1552 err_release:
1553 release_firmware(ucode_raw);
1554
1555 error:
90e759d1 1556 return ret;
b481de9c
ZY
1557}
1558
b7a79404
RC
1559#ifdef CONFIG_IWLWIFI_DEBUG
1560static const char *desc_lookup_text[] = {
1561 "OK",
1562 "FAIL",
1563 "BAD_PARAM",
1564 "BAD_CHECKSUM",
1565 "NMI_INTERRUPT_WDG",
1566 "SYSASSERT",
1567 "FATAL_ERROR",
1568 "BAD_COMMAND",
1569 "HW_ERROR_TUNE_LOCK",
1570 "HW_ERROR_TEMPERATURE",
1571 "ILLEGAL_CHAN_FREQ",
1572 "VCC_NOT_STABLE",
1573 "FH_ERROR",
1574 "NMI_INTERRUPT_HOST",
1575 "NMI_INTERRUPT_ACTION_PT",
1576 "NMI_INTERRUPT_UNKNOWN",
1577 "UCODE_VERSION_MISMATCH",
1578 "HW_ERROR_ABS_LOCK",
1579 "HW_ERROR_CAL_LOCK_FAIL",
1580 "NMI_INTERRUPT_INST_ACTION_PT",
1581 "NMI_INTERRUPT_DATA_ACTION_PT",
1582 "NMI_TRM_HW_ER",
1583 "NMI_INTERRUPT_TRM",
1584 "NMI_INTERRUPT_BREAK_POINT"
1585 "DEBUG_0",
1586 "DEBUG_1",
1587 "DEBUG_2",
1588 "DEBUG_3",
1589 "UNKNOWN"
1590};
1591
1592static const char *desc_lookup(int i)
1593{
1594 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1595
1596 if (i < 0 || i > max)
1597 i = max;
1598
1599 return desc_lookup_text[i];
1600}
1601
1602#define ERROR_START_OFFSET (1 * sizeof(u32))
1603#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1604
1605void iwl_dump_nic_error_log(struct iwl_priv *priv)
1606{
1607 u32 data2, line;
1608 u32 desc, time, count, base, data1;
1609 u32 blink1, blink2, ilink1, ilink2;
1610
1611 if (priv->ucode_type == UCODE_INIT)
1612 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1613 else
1614 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1615
1616 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1617 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1618 return;
1619 }
1620
1621 count = iwl_read_targ_mem(priv, base);
1622
1623 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1624 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1625 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1626 priv->status, count);
1627 }
1628
1629 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1630 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1631 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1632 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1633 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1634 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1635 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1636 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1637 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1638
be1a71a1
JB
1639 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1640 blink1, blink2, ilink1, ilink2);
1641
b7a79404
RC
1642 IWL_ERR(priv, "Desc Time "
1643 "data1 data2 line\n");
1644 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1645 desc_lookup(desc), desc, time, data1, data2, line);
1646 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1647 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1648 ilink1, ilink2);
1649
1650}
1651
1652#define EVENT_START_OFFSET (4 * sizeof(u32))
1653
1654/**
1655 * iwl_print_event_log - Dump error event log to syslog
1656 *
1657 */
1658static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1659 u32 num_events, u32 mode)
1660{
1661 u32 i;
1662 u32 base; /* SRAM byte address of event log header */
1663 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1664 u32 ptr; /* SRAM byte address of log data */
1665 u32 ev, time, data; /* event log data */
e5854471 1666 unsigned long reg_flags;
b7a79404
RC
1667
1668 if (num_events == 0)
1669 return;
1670 if (priv->ucode_type == UCODE_INIT)
1671 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1672 else
1673 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1674
1675 if (mode == 0)
1676 event_size = 2 * sizeof(u32);
1677 else
1678 event_size = 3 * sizeof(u32);
1679
1680 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1681
e5854471
BC
1682 /* Make sure device is powered up for SRAM reads */
1683 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1684 iwl_grab_nic_access(priv);
1685
1686 /* Set starting address; reads will auto-increment */
1687 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1688 rmb();
1689
b7a79404
RC
1690 /* "time" is actually "data" for mode 0 (no timestamp).
1691 * place event id # at far right for easier visual parsing. */
1692 for (i = 0; i < num_events; i++) {
e5854471
BC
1693 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1694 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1695 if (mode == 0) {
1696 /* data, ev */
be1a71a1 1697 trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
b7a79404
RC
1698 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1699 } else {
e5854471 1700 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1701 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1702 time, data, ev);
be1a71a1 1703 trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
b7a79404
RC
1704 }
1705 }
e5854471
BC
1706
1707 /* Allow device to power down */
1708 iwl_release_nic_access(priv);
1709 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b7a79404
RC
1710}
1711
84c40692
BC
1712/* For sanity check only. Actual size is determined by uCode, typ. 512 */
1713#define MAX_EVENT_LOG_SIZE (512)
1714
b7a79404
RC
1715void iwl_dump_nic_event_log(struct iwl_priv *priv)
1716{
1717 u32 base; /* SRAM byte address of event log header */
1718 u32 capacity; /* event log capacity in # entries */
1719 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1720 u32 num_wraps; /* # times uCode wrapped to top of log */
1721 u32 next_entry; /* index of next entry to be written by uCode */
1722 u32 size; /* # entries that we'll print */
1723
1724 if (priv->ucode_type == UCODE_INIT)
1725 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1726 else
1727 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1728
1729 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1730 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1731 return;
1732 }
1733
1734 /* event log header */
1735 capacity = iwl_read_targ_mem(priv, base);
1736 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1737 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1738 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1739
84c40692
BC
1740 if (capacity > MAX_EVENT_LOG_SIZE) {
1741 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1742 capacity, MAX_EVENT_LOG_SIZE);
1743 capacity = MAX_EVENT_LOG_SIZE;
1744 }
1745
1746 if (next_entry > MAX_EVENT_LOG_SIZE) {
1747 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1748 next_entry, MAX_EVENT_LOG_SIZE);
1749 next_entry = MAX_EVENT_LOG_SIZE;
1750 }
1751
b7a79404
RC
1752 size = num_wraps ? capacity : next_entry;
1753
1754 /* bail out if nothing in log */
1755 if (size == 0) {
1756 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1757 return;
1758 }
1759
1760 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1761 size, num_wraps);
1762
1763 /* if uCode has wrapped back to top of log, start at the oldest entry,
1764 * i.e the next one that uCode would fill. */
1765 if (num_wraps)
1766 iwl_print_event_log(priv, next_entry,
1767 capacity - next_entry, mode);
1768 /* (then/else) start at top of log */
1769 iwl_print_event_log(priv, 0, next_entry, mode);
1770
1771}
1772#endif
1773
b481de9c 1774/**
4a4a9e81 1775 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1776 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1777 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1778 */
4a4a9e81 1779static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1780{
57aab75a 1781 int ret = 0;
b481de9c 1782
e1623446 1783 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1784
1785 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1786 /* We had an error bringing up the hardware, so take it
1787 * all the way back down so we can try again */
e1623446 1788 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1789 goto restart;
1790 }
1791
1792 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1793 * This is a paranoid check, because we would not have gotten the
1794 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1795 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1796 /* Runtime instruction load was bad;
1797 * take it all the way back down so we can try again */
e1623446 1798 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1799 goto restart;
1800 }
1801
c587de0b 1802 iwl_clear_stations_table(priv);
57aab75a
TW
1803 ret = priv->cfg->ops->lib->alive_notify(priv);
1804 if (ret) {
39aadf8c
WT
1805 IWL_WARN(priv,
1806 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1807 goto restart;
1808 }
1809
5b9f8cd3 1810 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1811 set_bit(STATUS_ALIVE, &priv->status);
1812
fee1247a 1813 if (iwl_is_rfkill(priv))
b481de9c
ZY
1814 return;
1815
36d6825b 1816 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1817
1818 priv->active_rate = priv->rates_mask;
1819 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1820
2f748dec
WYG
1821 /* Configure Tx antenna selection based on H/W config */
1822 if (priv->cfg->ops->hcmd->set_tx_ant)
1823 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
1824
3109ece1 1825 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1826 struct iwl_rxon_cmd *active_rxon =
1827 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1828 /* apply any changes in staging */
1829 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1830 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1831 } else {
1832 /* Initialize our rx_config data */
5b9f8cd3 1833 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
1834
1835 if (priv->cfg->ops->hcmd->set_rxon_chain)
1836 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1837
b481de9c
ZY
1838 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1839 }
1840
9fbab516 1841 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1842 iwl_send_bt_config(priv);
b481de9c 1843
4a4a9e81
TW
1844 iwl_reset_run_time_calib(priv);
1845
b481de9c 1846 /* Configure the adapter for unassociated operation */
e0158e61 1847 iwlcore_commit_rxon(priv);
b481de9c
ZY
1848
1849 /* At this point, the NIC is initialized and operational */
47f4a587 1850 iwl_rf_kill_ct_config(priv);
5a66926a 1851
e932a609 1852 iwl_leds_init(priv);
fe00b5a5 1853
e1623446 1854 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1855 set_bit(STATUS_READY, &priv->status);
5a66926a 1856 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1857
e312c24c 1858 iwl_power_update_mode(priv, true);
c46fbefa 1859
ada17513
MA
1860 /* reassociate for ADHOC mode */
1861 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1862 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1863 priv->vif);
1864 if (beacon)
1865 iwl_mac_beacon_update(priv->hw, beacon);
1866 }
1867
1868
c46fbefa 1869 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1870 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1871
b481de9c
ZY
1872 return;
1873
1874 restart:
1875 queue_work(priv->workqueue, &priv->restart);
1876}
1877
4e39317d 1878static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1879
5b9f8cd3 1880static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1881{
1882 unsigned long flags;
1883 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1884
e1623446 1885 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1886
b481de9c
ZY
1887 if (!exit_pending)
1888 set_bit(STATUS_EXIT_PENDING, &priv->status);
1889
c587de0b 1890 iwl_clear_stations_table(priv);
b481de9c
ZY
1891
1892 /* Unblock any waiting calls */
1893 wake_up_interruptible_all(&priv->wait_command_queue);
1894
b481de9c
ZY
1895 /* Wipe out the EXIT_PENDING status bit if we are not actually
1896 * exiting the module */
1897 if (!exit_pending)
1898 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1899
1900 /* stop and reset the on-board processor */
3395f6e9 1901 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
1902
1903 /* tell the device to stop sending interrupts */
0359facc 1904 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1905 iwl_disable_interrupts(priv);
0359facc
MA
1906 spin_unlock_irqrestore(&priv->lock, flags);
1907 iwl_synchronize_irq(priv);
b481de9c
ZY
1908
1909 if (priv->mac80211_registered)
1910 ieee80211_stop_queues(priv->hw);
1911
5b9f8cd3 1912 /* If we have not previously called iwl_init() then
a60e77e5 1913 * clear all bits but the RF Kill bit and return */
fee1247a 1914 if (!iwl_is_init(priv)) {
b481de9c
ZY
1915 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1916 STATUS_RF_KILL_HW |
9788864e
RC
1917 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1918 STATUS_GEO_CONFIGURED |
052ec3f1
MA
1919 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1920 STATUS_EXIT_PENDING;
b481de9c
ZY
1921 goto exit;
1922 }
1923
6da3a13e 1924 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 1925 * bit and continue taking the NIC down. */
b481de9c
ZY
1926 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1927 STATUS_RF_KILL_HW |
9788864e
RC
1928 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1929 STATUS_GEO_CONFIGURED |
b481de9c 1930 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
1931 STATUS_FW_ERROR |
1932 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1933 STATUS_EXIT_PENDING;
b481de9c 1934
ef850d7c
MA
1935 /* device going down, Stop using ICT table */
1936 iwl_disable_ict(priv);
b481de9c 1937 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1938 iwl_clear_bit(priv, CSR_GP_CNTRL,
9fbab516 1939 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
1940 spin_unlock_irqrestore(&priv->lock, flags);
1941
da1bc453 1942 iwl_txq_ctx_stop(priv);
b3bbacb7 1943 iwl_rxq_stop(priv);
b481de9c 1944
a8b50a0a
MA
1945 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1946 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
1947
1948 udelay(5);
1949
4d2ccdb9
BC
1950 /* Stop the device, and put it in low power state */
1951 priv->cfg->ops->lib->apm_ops.stop(priv);
1952
b481de9c 1953 exit:
885ba202 1954 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
1955
1956 if (priv->ibss_beacon)
1957 dev_kfree_skb(priv->ibss_beacon);
1958 priv->ibss_beacon = NULL;
1959
1960 /* clear out any free frames */
fcab423d 1961 iwl_clear_free_frames(priv);
b481de9c
ZY
1962}
1963
5b9f8cd3 1964static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1965{
1966 mutex_lock(&priv->mutex);
5b9f8cd3 1967 __iwl_down(priv);
b481de9c 1968 mutex_unlock(&priv->mutex);
b24d22b1 1969
4e39317d 1970 iwl_cancel_deferred_work(priv);
b481de9c
ZY
1971}
1972
086ed117
MA
1973#define HW_READY_TIMEOUT (50)
1974
1975static int iwl_set_hw_ready(struct iwl_priv *priv)
1976{
1977 int ret = 0;
1978
1979 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1980 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1981
1982 /* See if we got it */
1983 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1984 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1985 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1986 HW_READY_TIMEOUT);
1987 if (ret != -ETIMEDOUT)
1988 priv->hw_ready = true;
1989 else
1990 priv->hw_ready = false;
1991
1992 IWL_DEBUG_INFO(priv, "hardware %s\n",
1993 (priv->hw_ready == 1) ? "ready" : "not ready");
1994 return ret;
1995}
1996
1997static int iwl_prepare_card_hw(struct iwl_priv *priv)
1998{
1999 int ret = 0;
2000
2001 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
2002
3354a0f6
MA
2003 ret = iwl_set_hw_ready(priv);
2004 if (priv->hw_ready)
2005 return ret;
2006
2007 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
2008 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2009 CSR_HW_IF_CONFIG_REG_PREPARE);
2010
2011 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2012 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2013 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2014
3354a0f6 2015 /* HW should be ready by now, check again. */
086ed117
MA
2016 if (ret != -ETIMEDOUT)
2017 iwl_set_hw_ready(priv);
2018
2019 return ret;
2020}
2021
b481de9c
ZY
2022#define MAX_HW_RESTARTS 5
2023
5b9f8cd3 2024static int __iwl_up(struct iwl_priv *priv)
b481de9c 2025{
57aab75a
TW
2026 int i;
2027 int ret;
b481de9c
ZY
2028
2029 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2030 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2031 return -EIO;
2032 }
2033
e903fbd4 2034 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2035 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
2036 return -EIO;
2037 }
2038
086ed117
MA
2039 iwl_prepare_card_hw(priv);
2040
2041 if (!priv->hw_ready) {
2042 IWL_WARN(priv, "Exit HW not ready\n");
2043 return -EIO;
2044 }
2045
e655b9f0 2046 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2047 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2048 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2049 else
e655b9f0 2050 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2051
c1842d61 2052 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
2053 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2054
5b9f8cd3 2055 iwl_enable_interrupts(priv);
a60e77e5 2056 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2057 return 0;
b481de9c
ZY
2058 }
2059
3395f6e9 2060 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2061
1053d35f 2062 ret = iwl_hw_nic_init(priv);
57aab75a 2063 if (ret) {
15b1687c 2064 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2065 return ret;
b481de9c
ZY
2066 }
2067
2068 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2069 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2070 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2071 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2072
2073 /* clear (again), then enable host interrupts */
3395f6e9 2074 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2075 iwl_enable_interrupts(priv);
b481de9c
ZY
2076
2077 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2078 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2079 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2080
2081 /* Copy original ucode data image from disk into backup cache.
2082 * This will be used to initialize the on-board processor's
2083 * data SRAM for a clean start when the runtime program first loads. */
2084 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2085 priv->ucode_data.len);
b481de9c 2086
b481de9c
ZY
2087 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2088
c587de0b 2089 iwl_clear_stations_table(priv);
b481de9c
ZY
2090
2091 /* load bootstrap state machine,
2092 * load bootstrap program into processor's memory,
2093 * prepare to load the "initialize" uCode */
57aab75a 2094 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2095
57aab75a 2096 if (ret) {
15b1687c
WT
2097 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2098 ret);
b481de9c
ZY
2099 continue;
2100 }
2101
2102 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2103 iwl_nic_start(priv);
b481de9c 2104
e1623446 2105 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2106
2107 return 0;
2108 }
2109
2110 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2111 __iwl_down(priv);
64e72c3e 2112 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2113
2114 /* tried to restart and config the device for as long as our
2115 * patience could withstand */
15b1687c 2116 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2117 return -EIO;
2118}
2119
2120
2121/*****************************************************************************
2122 *
2123 * Workqueue callbacks
2124 *
2125 *****************************************************************************/
2126
4a4a9e81 2127static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2128{
c79dd5b5
TW
2129 struct iwl_priv *priv =
2130 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2131
2132 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2133 return;
2134
2135 mutex_lock(&priv->mutex);
f3ccc08c 2136 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2137 mutex_unlock(&priv->mutex);
2138}
2139
4a4a9e81 2140static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2141{
c79dd5b5
TW
2142 struct iwl_priv *priv =
2143 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2144
2145 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2146 return;
2147
258c44a0
MA
2148 /* enable dram interrupt */
2149 iwl_reset_ict(priv);
2150
b481de9c 2151 mutex_lock(&priv->mutex);
4a4a9e81 2152 iwl_alive_start(priv);
b481de9c
ZY
2153 mutex_unlock(&priv->mutex);
2154}
2155
16e727e8
EG
2156static void iwl_bg_run_time_calib_work(struct work_struct *work)
2157{
2158 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2159 run_time_calib_work);
2160
2161 mutex_lock(&priv->mutex);
2162
2163 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2164 test_bit(STATUS_SCANNING, &priv->status)) {
2165 mutex_unlock(&priv->mutex);
2166 return;
2167 }
2168
2169 if (priv->start_calib) {
2170 iwl_chain_noise_calibration(priv, &priv->statistics);
2171
2172 iwl_sensitivity_calibration(priv, &priv->statistics);
2173 }
2174
2175 mutex_unlock(&priv->mutex);
2176 return;
2177}
2178
5b9f8cd3 2179static void iwl_bg_up(struct work_struct *data)
b481de9c 2180{
c79dd5b5 2181 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2182
2183 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2184 return;
2185
2186 mutex_lock(&priv->mutex);
5b9f8cd3 2187 __iwl_up(priv);
b481de9c
ZY
2188 mutex_unlock(&priv->mutex);
2189}
2190
5b9f8cd3 2191static void iwl_bg_restart(struct work_struct *data)
b481de9c 2192{
c79dd5b5 2193 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2194
2195 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2196 return;
2197
19cc1087
JB
2198 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2199 mutex_lock(&priv->mutex);
2200 priv->vif = NULL;
2201 priv->is_open = 0;
2202 mutex_unlock(&priv->mutex);
2203 iwl_down(priv);
2204 ieee80211_restart_hw(priv->hw);
2205 } else {
2206 iwl_down(priv);
2207 queue_work(priv->workqueue, &priv->up);
2208 }
b481de9c
ZY
2209}
2210
5b9f8cd3 2211static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2212{
c79dd5b5
TW
2213 struct iwl_priv *priv =
2214 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2215
2216 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2217 return;
2218
2219 mutex_lock(&priv->mutex);
a55360e4 2220 iwl_rx_replenish(priv);
b481de9c
ZY
2221 mutex_unlock(&priv->mutex);
2222}
2223
7878a5a4
MA
2224#define IWL_DELAY_NEXT_SCAN (HZ*2)
2225
5bbe233b 2226void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2227{
b481de9c 2228 struct ieee80211_conf *conf = NULL;
857485c0 2229 int ret = 0;
1ff50bda 2230 unsigned long flags;
b481de9c 2231
05c914fe 2232 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2233 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2234 return;
2235 }
2236
e1623446 2237 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2238 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2239
2240
2241 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2242 return;
2243
b481de9c 2244
508e32e1 2245 if (!priv->vif || !priv->is_open)
948c171c 2246 return;
508e32e1 2247
2a421b91 2248 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2249
b481de9c
ZY
2250 conf = ieee80211_get_hw_conf(priv->hw);
2251
2252 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2253 iwlcore_commit_rxon(priv);
b481de9c 2254
3195c1f3 2255 iwl_setup_rxon_timing(priv);
857485c0 2256 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2257 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2258 if (ret)
39aadf8c 2259 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2260 "Attempting to continue.\n");
2261
2262 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2263
42eb7c64 2264 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2265
45823531
AK
2266 if (priv->cfg->ops->hcmd->set_rxon_chain)
2267 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2268
b481de9c
ZY
2269 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2270
e1623446 2271 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2272 priv->assoc_id, priv->beacon_int);
2273
2274 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2275 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2276 else
2277 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2278
2279 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2280 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2281 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2282 else
2283 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2284
05c914fe 2285 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2286 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2287
2288 }
2289
e0158e61 2290 iwlcore_commit_rxon(priv);
b481de9c
ZY
2291
2292 switch (priv->iw_mode) {
05c914fe 2293 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2294 break;
2295
05c914fe 2296 case NL80211_IFTYPE_ADHOC:
b481de9c 2297
c46fbefa
AK
2298 /* assume default assoc id */
2299 priv->assoc_id = 1;
b481de9c 2300
4f40e4d9 2301 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2302 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2303
2304 break;
2305
2306 default:
15b1687c 2307 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2308 __func__, priv->iw_mode);
b481de9c
ZY
2309 break;
2310 }
2311
05c914fe 2312 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2313 priv->assoc_station_added = 1;
2314
1ff50bda
EG
2315 spin_lock_irqsave(&priv->lock, flags);
2316 iwl_activate_qos(priv, 0);
2317 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2318
04816448
GE
2319 /* the chain noise calibration will enabled PM upon completion
2320 * If chain noise has already been run, then we need to enable
2321 * power management here */
2322 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2323 iwl_power_update_mode(priv, false);
c90a74ba
EG
2324
2325 /* Enable Rx differential gain and sensitivity calibrations */
2326 iwl_chain_noise_reset(priv);
2327 priv->start_calib = 1;
2328
508e32e1
RC
2329}
2330
b481de9c
ZY
2331/*****************************************************************************
2332 *
2333 * mac80211 entry point functions
2334 *
2335 *****************************************************************************/
2336
154b25ce 2337#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2338
f0b6e2e8
RC
2339/*
2340 * Not a mac80211 entry point function, but it fits in with all the
2341 * other mac80211 functions grouped here.
2342 */
2343static int iwl_setup_mac(struct iwl_priv *priv)
2344{
2345 int ret;
2346 struct ieee80211_hw *hw = priv->hw;
2347 hw->rate_control_algorithm = "iwl-agn-rs";
2348
2349 /* Tell mac80211 our characteristics */
2350 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2351 IEEE80211_HW_NOISE_DBM |
2352 IEEE80211_HW_AMPDU_AGGREGATION |
2353 IEEE80211_HW_SPECTRUM_MGMT;
2354
2355 if (!priv->cfg->broken_powersave)
2356 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2357 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2358
8d9698b3 2359 hw->sta_data_size = sizeof(struct iwl_station_priv);
f0b6e2e8
RC
2360 hw->wiphy->interface_modes =
2361 BIT(NL80211_IFTYPE_STATION) |
2362 BIT(NL80211_IFTYPE_ADHOC);
2363
2364 hw->wiphy->custom_regulatory = true;
2365
2366 /* Firmware does not support this */
2367 hw->wiphy->disable_beacon_hints = true;
2368
2369 /*
2370 * For now, disable PS by default because it affects
2371 * RX performance significantly.
2372 */
2373 hw->wiphy->ps_default = false;
2374
2375 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2376 /* we create the 802.11 header and a zero-length SSID element */
2377 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2378
2379 /* Default value; 4 EDCA QOS priorities */
2380 hw->queues = 4;
2381
2382 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2383
2384 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2385 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2386 &priv->bands[IEEE80211_BAND_2GHZ];
2387 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2388 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2389 &priv->bands[IEEE80211_BAND_5GHZ];
2390
2391 ret = ieee80211_register_hw(priv->hw);
2392 if (ret) {
2393 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2394 return ret;
2395 }
2396 priv->mac80211_registered = 1;
2397
2398 return 0;
2399}
2400
2401
5b9f8cd3 2402static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2403{
c79dd5b5 2404 struct iwl_priv *priv = hw->priv;
5a66926a 2405 int ret;
b481de9c 2406
e1623446 2407 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2408
2409 /* we should be verifying the device is ready to be opened */
2410 mutex_lock(&priv->mutex);
2411
5a66926a
ZY
2412 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2413 * ucode filename and max sizes are card-specific. */
b481de9c 2414
5a66926a 2415 if (!priv->ucode_code.len) {
5b9f8cd3 2416 ret = iwl_read_ucode(priv);
5a66926a 2417 if (ret) {
15b1687c 2418 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2419 mutex_unlock(&priv->mutex);
6cd0b1cb 2420 return ret;
5a66926a
ZY
2421 }
2422 }
b481de9c 2423
5b9f8cd3 2424 ret = __iwl_up(priv);
5a66926a 2425
b481de9c 2426 mutex_unlock(&priv->mutex);
5a66926a 2427
e655b9f0 2428 if (ret)
6cd0b1cb 2429 return ret;
e655b9f0 2430
c1842d61
TW
2431 if (iwl_is_rfkill(priv))
2432 goto out;
2433
e1623446 2434 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2435
fe9b6b72 2436 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2437 * mac80211 will not be run successfully. */
154b25ce
EG
2438 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2439 test_bit(STATUS_READY, &priv->status),
2440 UCODE_READY_TIMEOUT);
2441 if (!ret) {
2442 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2443 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2444 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2445 return -ETIMEDOUT;
5a66926a 2446 }
fe9b6b72 2447 }
0a078ffa 2448
e932a609
JB
2449 iwl_led_start(priv);
2450
c1842d61 2451out:
0a078ffa 2452 priv->is_open = 1;
e1623446 2453 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2454 return 0;
2455}
2456
5b9f8cd3 2457static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2458{
c79dd5b5 2459 struct iwl_priv *priv = hw->priv;
b481de9c 2460
e1623446 2461 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2462
19cc1087 2463 if (!priv->is_open)
e655b9f0 2464 return;
e655b9f0 2465
b481de9c 2466 priv->is_open = 0;
5a66926a 2467
5bddf549 2468 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2469 /* stop mac, cancel any scan request and clear
2470 * RXON_FILTER_ASSOC_MSK BIT
2471 */
5a66926a 2472 mutex_lock(&priv->mutex);
2a421b91 2473 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2474 mutex_unlock(&priv->mutex);
fde3571f
MA
2475 }
2476
5b9f8cd3 2477 iwl_down(priv);
5a66926a
ZY
2478
2479 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2480
2481 /* enable interrupts again in order to receive rfkill changes */
2482 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2483 iwl_enable_interrupts(priv);
948c171c 2484
e1623446 2485 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2486}
2487
5b9f8cd3 2488static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2489{
c79dd5b5 2490 struct iwl_priv *priv = hw->priv;
b481de9c 2491
e1623446 2492 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2493
e1623446 2494 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2495 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2496
e039fa4a 2497 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2498 dev_kfree_skb_any(skb);
2499
e1623446 2500 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2501 return NETDEV_TX_OK;
b481de9c
ZY
2502}
2503
60690a6a 2504void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2505{
857485c0 2506 int ret = 0;
1ff50bda 2507 unsigned long flags;
b481de9c 2508
d986bcd1 2509 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2510 return;
2511
2512 /* The following should be done only at AP bring up */
3195c1f3 2513 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2514
2515 /* RXON - unassoc (to set timing command) */
2516 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2517 iwlcore_commit_rxon(priv);
b481de9c
ZY
2518
2519 /* RXON Timing */
3195c1f3 2520 iwl_setup_rxon_timing(priv);
857485c0 2521 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2522 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2523 if (ret)
39aadf8c 2524 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2525 "Attempting to continue.\n");
2526
45823531
AK
2527 if (priv->cfg->ops->hcmd->set_rxon_chain)
2528 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2529
2530 /* FIXME: what should be the assoc_id for AP? */
2531 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2532 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2533 priv->staging_rxon.flags |=
2534 RXON_FLG_SHORT_PREAMBLE_MSK;
2535 else
2536 priv->staging_rxon.flags &=
2537 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2538
2539 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2540 if (priv->assoc_capability &
2541 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2542 priv->staging_rxon.flags |=
2543 RXON_FLG_SHORT_SLOT_MSK;
2544 else
2545 priv->staging_rxon.flags &=
2546 ~RXON_FLG_SHORT_SLOT_MSK;
2547
05c914fe 2548 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2549 priv->staging_rxon.flags &=
2550 ~RXON_FLG_SHORT_SLOT_MSK;
2551 }
2552 /* restore RXON assoc */
2553 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2554 iwlcore_commit_rxon(priv);
1ff50bda
EG
2555 spin_lock_irqsave(&priv->lock, flags);
2556 iwl_activate_qos(priv, 1);
2557 spin_unlock_irqrestore(&priv->lock, flags);
9a9ca65f 2558 iwl_add_bcast_station(priv);
e1493deb 2559 }
5b9f8cd3 2560 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2561
2562 /* FIXME - we need to add code here to detect a totally new
2563 * configuration, reset the AP, unassoc, rxon timing, assoc,
2564 * clear sta table, add BCAST sta... */
2565}
2566
5b9f8cd3 2567static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2568 struct ieee80211_key_conf *keyconf, const u8 *addr,
2569 u32 iv32, u16 *phase1key)
2570{
ab885f8c 2571
9f58671e 2572 struct iwl_priv *priv = hw->priv;
e1623446 2573 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2574
9f58671e 2575 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2576
e1623446 2577 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2578}
2579
5b9f8cd3 2580static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2581 struct ieee80211_vif *vif,
2582 struct ieee80211_sta *sta,
b481de9c
ZY
2583 struct ieee80211_key_conf *key)
2584{
c79dd5b5 2585 struct iwl_priv *priv = hw->priv;
42986796
WT
2586 const u8 *addr;
2587 int ret;
2588 u8 sta_id;
2589 bool is_default_wep_key = false;
b481de9c 2590
e1623446 2591 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2592
90e8e424 2593 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2594 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2595 return -EOPNOTSUPP;
2596 }
42986796 2597 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2598 sta_id = iwl_find_station(priv, addr);
6974e363 2599 if (sta_id == IWL_INVALID_STATION) {
e1623446 2600 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2601 addr);
6974e363 2602 return -EINVAL;
b481de9c 2603
deb09c43 2604 }
b481de9c 2605
6974e363 2606 mutex_lock(&priv->mutex);
2a421b91 2607 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2608 mutex_unlock(&priv->mutex);
2609
2610 /* If we are getting WEP group key and we didn't receive any key mapping
2611 * so far, we are in legacy wep mode (group key only), otherwise we are
2612 * in 1X mode.
2613 * In legacy wep mode, we use another host command to the uCode */
5425e490 2614 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2615 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2616 if (cmd == SET_KEY)
2617 is_default_wep_key = !priv->key_mapping_key;
2618 else
ccc038ab
EG
2619 is_default_wep_key =
2620 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2621 }
052c4b9f 2622
b481de9c 2623 switch (cmd) {
deb09c43 2624 case SET_KEY:
6974e363
EG
2625 if (is_default_wep_key)
2626 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2627 else
7480513f 2628 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2629
e1623446 2630 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2631 break;
2632 case DISABLE_KEY:
6974e363
EG
2633 if (is_default_wep_key)
2634 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2635 else
3ec47732 2636 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2637
e1623446 2638 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2639 break;
2640 default:
deb09c43 2641 ret = -EINVAL;
b481de9c
ZY
2642 }
2643
e1623446 2644 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2645
deb09c43 2646 return ret;
b481de9c
ZY
2647}
2648
5b9f8cd3 2649static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
d783b061 2650 enum ieee80211_ampdu_mlme_action action,
17741cdc 2651 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2652{
2653 struct iwl_priv *priv = hw->priv;
5c2207c6 2654 int ret;
d783b061 2655
e1623446 2656 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2657 sta->addr, tid);
d783b061
TW
2658
2659 if (!(priv->cfg->sku & IWL_SKU_N))
2660 return -EACCES;
2661
2662 switch (action) {
2663 case IEEE80211_AMPDU_RX_START:
e1623446 2664 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2665 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2666 case IEEE80211_AMPDU_RX_STOP:
e1623446 2667 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2668 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2669 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2670 return 0;
2671 else
2672 return ret;
d783b061 2673 case IEEE80211_AMPDU_TX_START:
e1623446 2674 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2675 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2676 case IEEE80211_AMPDU_TX_STOP:
e1623446 2677 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2678 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2679 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2680 return 0;
2681 else
2682 return ret;
d783b061 2683 default:
e1623446 2684 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2685 return -EINVAL;
2686 break;
2687 }
2688 return 0;
2689}
9f58671e 2690
5b9f8cd3 2691static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2692 struct ieee80211_low_level_stats *stats)
2693{
bf403db8
EK
2694 struct iwl_priv *priv = hw->priv;
2695
2696 priv = hw->priv;
e1623446
TW
2697 IWL_DEBUG_MAC80211(priv, "enter\n");
2698 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2699
2700 return 0;
2701}
2702
b481de9c
ZY
2703/*****************************************************************************
2704 *
2705 * sysfs attributes
2706 *
2707 *****************************************************************************/
2708
0a6857e7 2709#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2710
2711/*
2712 * The following adds a new attribute to the sysfs representation
c3a739fa 2713 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2714 * used for controlling the debug level.
2715 *
2716 * See the level definitions in iwl for details.
a562a9dd 2717 *
3d816c77
RC
2718 * The debug_level being managed using sysfs below is a per device debug
2719 * level that is used instead of the global debug level if it (the per
2720 * device debug level) is set.
b481de9c 2721 */
8cf769c6
EK
2722static ssize_t show_debug_level(struct device *d,
2723 struct device_attribute *attr, char *buf)
b481de9c 2724{
3d816c77
RC
2725 struct iwl_priv *priv = dev_get_drvdata(d);
2726 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 2727}
8cf769c6
EK
2728static ssize_t store_debug_level(struct device *d,
2729 struct device_attribute *attr,
b481de9c
ZY
2730 const char *buf, size_t count)
2731{
928841b1 2732 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2733 unsigned long val;
2734 int ret;
b481de9c 2735
9257746f
TW
2736 ret = strict_strtoul(buf, 0, &val);
2737 if (ret)
978785a3 2738 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 2739 else {
3d816c77 2740 priv->debug_level = val;
20594eb0
WYG
2741 if (iwl_alloc_traffic_mem(priv))
2742 IWL_ERR(priv,
2743 "Not enough memory to generate traffic log\n");
2744 }
b481de9c
ZY
2745 return strnlen(buf, count);
2746}
2747
8cf769c6
EK
2748static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2749 show_debug_level, store_debug_level);
2750
b481de9c 2751
0a6857e7 2752#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2753
b481de9c
ZY
2754
2755static ssize_t show_temperature(struct device *d,
2756 struct device_attribute *attr, char *buf)
2757{
928841b1 2758 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 2759
fee1247a 2760 if (!iwl_is_alive(priv))
b481de9c
ZY
2761 return -EAGAIN;
2762
91dbc5bd 2763 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2764}
2765
2766static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2767
b481de9c
ZY
2768static ssize_t show_tx_power(struct device *d,
2769 struct device_attribute *attr, char *buf)
2770{
928841b1 2771 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
2772
2773 if (!iwl_is_ready_rf(priv))
2774 return sprintf(buf, "off\n");
2775 else
2776 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2777}
2778
2779static ssize_t store_tx_power(struct device *d,
2780 struct device_attribute *attr,
2781 const char *buf, size_t count)
2782{
928841b1 2783 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2784 unsigned long val;
2785 int ret;
b481de9c 2786
9257746f
TW
2787 ret = strict_strtoul(buf, 10, &val);
2788 if (ret)
978785a3 2789 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
2790 else {
2791 ret = iwl_set_tx_power(priv, val, false);
2792 if (ret)
2793 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
2794 ret);
2795 else
2796 ret = count;
2797 }
2798 return ret;
b481de9c
ZY
2799}
2800
2801static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2802
2803static ssize_t show_flags(struct device *d,
2804 struct device_attribute *attr, char *buf)
2805{
928841b1 2806 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2807
2808 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2809}
2810
2811static ssize_t store_flags(struct device *d,
2812 struct device_attribute *attr,
2813 const char *buf, size_t count)
2814{
928841b1 2815 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2816 unsigned long val;
2817 u32 flags;
2818 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2819 if (ret)
9257746f
TW
2820 return ret;
2821 flags = (u32)val;
b481de9c
ZY
2822
2823 mutex_lock(&priv->mutex);
2824 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2825 /* Cancel any currently running scans... */
2a421b91 2826 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2827 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2828 else {
e1623446 2829 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2830 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2831 iwlcore_commit_rxon(priv);
b481de9c
ZY
2832 }
2833 }
2834 mutex_unlock(&priv->mutex);
2835
2836 return count;
2837}
2838
2839static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2840
2841static ssize_t show_filter_flags(struct device *d,
2842 struct device_attribute *attr, char *buf)
2843{
928841b1 2844 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2845
2846 return sprintf(buf, "0x%04X\n",
2847 le32_to_cpu(priv->active_rxon.filter_flags));
2848}
2849
2850static ssize_t store_filter_flags(struct device *d,
2851 struct device_attribute *attr,
2852 const char *buf, size_t count)
2853{
928841b1 2854 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2855 unsigned long val;
2856 u32 filter_flags;
2857 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2858 if (ret)
9257746f
TW
2859 return ret;
2860 filter_flags = (u32)val;
b481de9c
ZY
2861
2862 mutex_lock(&priv->mutex);
2863 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2864 /* Cancel any currently running scans... */
2a421b91 2865 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2866 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2867 else {
e1623446 2868 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
2869 "0x%04X\n", filter_flags);
2870 priv->staging_rxon.filter_flags =
2871 cpu_to_le32(filter_flags);
e0158e61 2872 iwlcore_commit_rxon(priv);
b481de9c
ZY
2873 }
2874 }
2875 mutex_unlock(&priv->mutex);
2876
2877 return count;
2878}
2879
2880static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2881 store_filter_flags);
2882
b481de9c
ZY
2883
2884static ssize_t show_statistics(struct device *d,
2885 struct device_attribute *attr, char *buf)
2886{
c79dd5b5 2887 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 2888 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 2889 u32 len = 0, ofs = 0;
3ac7f146 2890 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
2891 int rc = 0;
2892
fee1247a 2893 if (!iwl_is_alive(priv))
b481de9c
ZY
2894 return -EAGAIN;
2895
2896 mutex_lock(&priv->mutex);
49ea8596 2897 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
2898 mutex_unlock(&priv->mutex);
2899
2900 if (rc) {
2901 len = sprintf(buf,
2902 "Error sending statistics request: 0x%08X\n", rc);
2903 return len;
2904 }
2905
2906 while (size && (PAGE_SIZE - len)) {
2907 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2908 PAGE_SIZE - len, 1);
2909 len = strlen(buf);
2910 if (PAGE_SIZE - len)
2911 buf[len++] = '\n';
2912
2913 ofs += 16;
2914 size -= min(size, 16U);
2915 }
2916
2917 return len;
2918}
2919
2920static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2921
01abfbb2
WYG
2922static ssize_t show_rts_ht_protection(struct device *d,
2923 struct device_attribute *attr, char *buf)
2924{
2925 struct iwl_priv *priv = dev_get_drvdata(d);
2926
2927 return sprintf(buf, "%s\n",
2928 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
2929}
2930
2931static ssize_t store_rts_ht_protection(struct device *d,
2932 struct device_attribute *attr,
2933 const char *buf, size_t count)
2934{
2935 struct iwl_priv *priv = dev_get_drvdata(d);
2936 unsigned long val;
2937 int ret;
2938
2939 ret = strict_strtoul(buf, 10, &val);
2940 if (ret)
2941 IWL_INFO(priv, "Input is not in decimal form.\n");
2942 else {
2943 if (!iwl_is_associated(priv))
2944 priv->cfg->use_rts_for_ht = val ? true : false;
2945 else
2946 IWL_ERR(priv, "Sta associated with AP - "
2947 "Change protection mechanism is not allowed\n");
2948 ret = count;
2949 }
2950 return ret;
2951}
2952
2953static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
2954 show_rts_ht_protection, store_rts_ht_protection);
2955
b481de9c 2956
b481de9c
ZY
2957/*****************************************************************************
2958 *
2959 * driver setup and teardown
2960 *
2961 *****************************************************************************/
2962
4e39317d 2963static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2964{
d21050c7 2965 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
2966
2967 init_waitqueue_head(&priv->wait_command_queue);
2968
5b9f8cd3
EG
2969 INIT_WORK(&priv->up, iwl_bg_up);
2970 INIT_WORK(&priv->restart, iwl_bg_restart);
2971 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 2972 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 2973 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
2974 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2975 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 2976
2a421b91 2977 iwl_setup_scan_deferred_work(priv);
bb8c093b 2978
4e39317d
EG
2979 if (priv->cfg->ops->lib->setup_deferred_work)
2980 priv->cfg->ops->lib->setup_deferred_work(priv);
2981
2982 init_timer(&priv->statistics_periodic);
2983 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 2984 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 2985
ef850d7c
MA
2986 if (!priv->cfg->use_isr_legacy)
2987 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2988 iwl_irq_tasklet, (unsigned long)priv);
2989 else
2990 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2991 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
2992}
2993
4e39317d 2994static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2995{
4e39317d
EG
2996 if (priv->cfg->ops->lib->cancel_deferred_work)
2997 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 2998
3ae6a054 2999 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3000 cancel_delayed_work(&priv->scan_check);
3001 cancel_delayed_work(&priv->alive_start);
b481de9c 3002 cancel_work_sync(&priv->beacon_update);
4e39317d 3003 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
3004}
3005
89f186a8
RC
3006static void iwl_init_hw_rates(struct iwl_priv *priv,
3007 struct ieee80211_rate *rates)
3008{
3009 int i;
3010
3011 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3012 rates[i].bitrate = iwl_rates[i].ieee * 5;
3013 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3014 rates[i].hw_value_short = i;
3015 rates[i].flags = 0;
3016 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3017 /*
3018 * If CCK != 1M then set short preamble rate flag.
3019 */
3020 rates[i].flags |=
3021 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3022 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3023 }
3024 }
3025}
3026
3027static int iwl_init_drv(struct iwl_priv *priv)
3028{
3029 int ret;
3030
3031 priv->ibss_beacon = NULL;
3032
3033 spin_lock_init(&priv->lock);
3034 spin_lock_init(&priv->sta_lock);
3035 spin_lock_init(&priv->hcmd_lock);
3036
3037 INIT_LIST_HEAD(&priv->free_frames);
3038
3039 mutex_init(&priv->mutex);
3040
3041 /* Clear the driver's (not device's) station table */
3042 iwl_clear_stations_table(priv);
3043
3044 priv->ieee_channels = NULL;
3045 priv->ieee_rates = NULL;
3046 priv->band = IEEE80211_BAND_2GHZ;
3047
3048 priv->iw_mode = NL80211_IFTYPE_STATION;
3f3e0376
WYG
3049 if (priv->cfg->support_sm_ps)
3050 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DYNAMIC;
3051 else
3052 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
89f186a8
RC
3053
3054 /* Choose which receivers/antennas to use */
3055 if (priv->cfg->ops->hcmd->set_rxon_chain)
3056 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3057
3058 iwl_init_scan_params(priv);
3059
3060 iwl_reset_qos(priv);
3061
3062 priv->qos_data.qos_active = 0;
3063 priv->qos_data.qos_cap.val = 0;
3064
3065 priv->rates_mask = IWL_RATES_MASK;
3066 /* Set the tx_power_user_lmt to the lowest power level
3067 * this value will get overwritten by channel max power avg
3068 * from eeprom */
3069 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
3070
3071 ret = iwl_init_channel_map(priv);
3072 if (ret) {
3073 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3074 goto err;
3075 }
3076
3077 ret = iwlcore_init_geos(priv);
3078 if (ret) {
3079 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3080 goto err_free_channel_map;
3081 }
3082 iwl_init_hw_rates(priv, priv->ieee_rates);
3083
3084 return 0;
3085
3086err_free_channel_map:
3087 iwl_free_channel_map(priv);
3088err:
3089 return ret;
3090}
3091
3092static void iwl_uninit_drv(struct iwl_priv *priv)
3093{
3094 iwl_calib_free_results(priv);
3095 iwlcore_free_geos(priv);
3096 iwl_free_channel_map(priv);
3097 kfree(priv->scan);
3098}
3099
5b9f8cd3 3100static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
3101 &dev_attr_flags.attr,
3102 &dev_attr_filter_flags.attr,
b481de9c 3103 &dev_attr_statistics.attr,
b481de9c 3104 &dev_attr_temperature.attr,
b481de9c 3105 &dev_attr_tx_power.attr,
01abfbb2 3106 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK
3107#ifdef CONFIG_IWLWIFI_DEBUG
3108 &dev_attr_debug_level.attr,
3109#endif
b481de9c
ZY
3110 NULL
3111};
3112
5b9f8cd3 3113static struct attribute_group iwl_attribute_group = {
b481de9c 3114 .name = NULL, /* put in device directory */
5b9f8cd3 3115 .attrs = iwl_sysfs_entries,
b481de9c
ZY
3116};
3117
5b9f8cd3
EG
3118static struct ieee80211_ops iwl_hw_ops = {
3119 .tx = iwl_mac_tx,
3120 .start = iwl_mac_start,
3121 .stop = iwl_mac_stop,
3122 .add_interface = iwl_mac_add_interface,
3123 .remove_interface = iwl_mac_remove_interface,
3124 .config = iwl_mac_config,
5b9f8cd3
EG
3125 .configure_filter = iwl_configure_filter,
3126 .set_key = iwl_mac_set_key,
3127 .update_tkip_key = iwl_mac_update_tkip_key,
3128 .get_stats = iwl_mac_get_stats,
3129 .get_tx_stats = iwl_mac_get_tx_stats,
3130 .conf_tx = iwl_mac_conf_tx,
3131 .reset_tsf = iwl_mac_reset_tsf,
3132 .bss_info_changed = iwl_bss_info_changed,
3133 .ampdu_action = iwl_mac_ampdu_action,
cb43dc25 3134 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3135};
3136
5b9f8cd3 3137static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3138{
3139 int err = 0;
c79dd5b5 3140 struct iwl_priv *priv;
b481de9c 3141 struct ieee80211_hw *hw;
82b9a121 3142 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3143 unsigned long flags;
6cd0b1cb 3144 u16 pci_cmd;
b481de9c 3145
316c30d9
AK
3146 /************************
3147 * 1. Allocating HW data
3148 ************************/
3149
6440adb5
BC
3150 /* Disabling hardware scan means that mac80211 will perform scans
3151 * "the hard way", rather than using device's scan. */
1ea87396 3152 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3153 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
3154 dev_printk(KERN_DEBUG, &(pdev->dev),
3155 "Disabling hw_scan\n");
5b9f8cd3 3156 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3157 }
3158
5b9f8cd3 3159 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3160 if (!hw) {
b481de9c
ZY
3161 err = -ENOMEM;
3162 goto out;
3163 }
1d0a082d
AK
3164 priv = hw->priv;
3165 /* At this point both hw and priv are allocated. */
3166
b481de9c
ZY
3167 SET_IEEE80211_DEV(hw, &pdev->dev);
3168
e1623446 3169 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3170 priv->cfg = cfg;
b481de9c 3171 priv->pci_dev = pdev;
40cefda9 3172 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3173
0a6857e7 3174#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3175 atomic_set(&priv->restrict_refcnt, 0);
3176#endif
20594eb0
WYG
3177 if (iwl_alloc_traffic_mem(priv))
3178 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3179
316c30d9
AK
3180 /**************************
3181 * 2. Initializing PCI bus
3182 **************************/
3183 if (pci_enable_device(pdev)) {
3184 err = -ENODEV;
3185 goto out_ieee80211_free_hw;
3186 }
3187
3188 pci_set_master(pdev);
3189
093d874c 3190 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3191 if (!err)
093d874c 3192 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3193 if (err) {
093d874c 3194 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3195 if (!err)
093d874c 3196 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3197 /* both attempts failed: */
316c30d9 3198 if (err) {
978785a3 3199 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3200 goto out_pci_disable_device;
cc2a8ea8 3201 }
316c30d9
AK
3202 }
3203
3204 err = pci_request_regions(pdev, DRV_NAME);
3205 if (err)
3206 goto out_pci_disable_device;
3207
3208 pci_set_drvdata(pdev, priv);
3209
316c30d9
AK
3210
3211 /***********************
3212 * 3. Read REV register
3213 ***********************/
3214 priv->hw_base = pci_iomap(pdev, 0, 0);
3215 if (!priv->hw_base) {
3216 err = -ENODEV;
3217 goto out_pci_release_regions;
3218 }
3219
e1623446 3220 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3221 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3222 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3223
a8b50a0a
MA
3224 /* this spin lock will be used in apm_ops.init and EEPROM access
3225 * we should init now
3226 */
3227 spin_lock_init(&priv->reg_lock);
b661c819 3228 iwl_hw_detect(priv);
978785a3 3229 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 3230 priv->cfg->name, priv->hw_rev);
316c30d9 3231
e7b63581
TW
3232 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3233 * PCI Tx retries from interfering with C3 CPU state */
3234 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3235
086ed117
MA
3236 iwl_prepare_card_hw(priv);
3237 if (!priv->hw_ready) {
3238 IWL_WARN(priv, "Failed, HW not ready\n");
3239 goto out_iounmap;
3240 }
3241
91238714
TW
3242 /*****************
3243 * 4. Read EEPROM
3244 *****************/
316c30d9
AK
3245 /* Read the EEPROM */
3246 err = iwl_eeprom_init(priv);
3247 if (err) {
15b1687c 3248 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3249 goto out_iounmap;
3250 }
8614f360
TW
3251 err = iwl_eeprom_check_version(priv);
3252 if (err)
c8f16138 3253 goto out_free_eeprom;
8614f360 3254
02883017 3255 /* extract MAC Address */
316c30d9 3256 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3257 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3258 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3259
3260 /************************
3261 * 5. Setup HW constants
3262 ************************/
da154e30 3263 if (iwl_set_hw_params(priv)) {
15b1687c 3264 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3265 goto out_free_eeprom;
316c30d9
AK
3266 }
3267
3268 /*******************
6ba87956 3269 * 6. Setup priv
316c30d9 3270 *******************/
b481de9c 3271
6ba87956 3272 err = iwl_init_drv(priv);
bf85ea4f 3273 if (err)
399f4900 3274 goto out_free_eeprom;
bf85ea4f 3275 /* At this point both hw and priv are initialized. */
316c30d9 3276
316c30d9 3277 /********************
09f9bf79 3278 * 7. Setup services
316c30d9 3279 ********************/
0359facc 3280 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3281 iwl_disable_interrupts(priv);
0359facc 3282 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3283
6cd0b1cb
HS
3284 pci_enable_msi(priv->pci_dev);
3285
ef850d7c
MA
3286 iwl_alloc_isr_ict(priv);
3287 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3288 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3289 if (err) {
3290 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3291 goto out_disable_msi;
3292 }
5b9f8cd3 3293 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3294 if (err) {
15b1687c 3295 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3296 goto out_free_irq;
316c30d9
AK
3297 }
3298
4e39317d 3299 iwl_setup_deferred_work(priv);
653fa4a0 3300 iwl_setup_rx_handlers(priv);
316c30d9 3301
6ba87956 3302 /**********************************
09f9bf79 3303 * 8. Setup and register mac80211
6ba87956
TW
3304 **********************************/
3305
6cd0b1cb
HS
3306 /* enable interrupts if needed: hw bug w/a */
3307 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3308 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3309 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3310 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3311 }
3312
3313 iwl_enable_interrupts(priv);
3314
6ba87956
TW
3315 err = iwl_setup_mac(priv);
3316 if (err)
3317 goto out_remove_sysfs;
3318
3319 err = iwl_dbgfs_register(priv, DRV_NAME);
3320 if (err)
a75fbe8d 3321 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
6ba87956 3322
6cd0b1cb
HS
3323 /* If platform's RF_KILL switch is NOT set to KILL */
3324 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3325 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3326 else
3327 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3328
a60e77e5
JB
3329 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3330 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3331
58d0f361 3332 iwl_power_initialize(priv);
39b73fb1 3333 iwl_tt_initialize(priv);
b481de9c
ZY
3334 return 0;
3335
316c30d9 3336 out_remove_sysfs:
c8f16138
RC
3337 destroy_workqueue(priv->workqueue);
3338 priv->workqueue = NULL;
5b9f8cd3 3339 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3340 out_free_irq:
3341 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3342 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3343 out_disable_msi:
3344 pci_disable_msi(priv->pci_dev);
6ba87956 3345 iwl_uninit_drv(priv);
073d3f5f
TW
3346 out_free_eeprom:
3347 iwl_eeprom_free(priv);
b481de9c
ZY
3348 out_iounmap:
3349 pci_iounmap(pdev, priv->hw_base);
3350 out_pci_release_regions:
316c30d9 3351 pci_set_drvdata(pdev, NULL);
623d563e 3352 pci_release_regions(pdev);
b481de9c
ZY
3353 out_pci_disable_device:
3354 pci_disable_device(pdev);
b481de9c 3355 out_ieee80211_free_hw:
20594eb0 3356 iwl_free_traffic_mem(priv);
d7c76f4c 3357 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3358 out:
3359 return err;
3360}
3361
5b9f8cd3 3362static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3363{
c79dd5b5 3364 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3365 unsigned long flags;
b481de9c
ZY
3366
3367 if (!priv)
3368 return;
3369
e1623446 3370 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3371
67249625 3372 iwl_dbgfs_unregister(priv);
5b9f8cd3 3373 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3374
5b9f8cd3
EG
3375 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3376 * to be called and iwl_down since we are removing the device
0b124c31
GG
3377 * we need to set STATUS_EXIT_PENDING bit.
3378 */
3379 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3380 if (priv->mac80211_registered) {
3381 ieee80211_unregister_hw(priv->hw);
3382 priv->mac80211_registered = 0;
0b124c31 3383 } else {
5b9f8cd3 3384 iwl_down(priv);
c4f55232
RR
3385 }
3386
c166b25a
BC
3387 /*
3388 * Make sure device is reset to low power before unloading driver.
3389 * This may be redundant with iwl_down(), but there are paths to
3390 * run iwl_down() without calling apm_ops.stop(), and there are
3391 * paths to avoid running iwl_down() at all before leaving driver.
3392 * This (inexpensive) call *makes sure* device is reset.
3393 */
3394 priv->cfg->ops->lib->apm_ops.stop(priv);
3395
39b73fb1
WYG
3396 iwl_tt_exit(priv);
3397
0359facc
MA
3398 /* make sure we flush any pending irq or
3399 * tasklet for the driver
3400 */
3401 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3402 iwl_disable_interrupts(priv);
0359facc
MA
3403 spin_unlock_irqrestore(&priv->lock, flags);
3404
3405 iwl_synchronize_irq(priv);
3406
5b9f8cd3 3407 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3408
3409 if (priv->rxq.bd)
a55360e4 3410 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3411 iwl_hw_txq_ctx_free(priv);
b481de9c 3412
c587de0b 3413 iwl_clear_stations_table(priv);
073d3f5f 3414 iwl_eeprom_free(priv);
b481de9c 3415
b481de9c 3416
948c171c
MA
3417 /*netif_stop_queue(dev); */
3418 flush_workqueue(priv->workqueue);
3419
5b9f8cd3 3420 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3421 * priv->workqueue... so we can't take down the workqueue
3422 * until now... */
3423 destroy_workqueue(priv->workqueue);
3424 priv->workqueue = NULL;
20594eb0 3425 iwl_free_traffic_mem(priv);
b481de9c 3426
6cd0b1cb
HS
3427 free_irq(priv->pci_dev->irq, priv);
3428 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3429 pci_iounmap(pdev, priv->hw_base);
3430 pci_release_regions(pdev);
3431 pci_disable_device(pdev);
3432 pci_set_drvdata(pdev, NULL);
3433
6ba87956 3434 iwl_uninit_drv(priv);
b481de9c 3435
ef850d7c
MA
3436 iwl_free_isr_ict(priv);
3437
b481de9c
ZY
3438 if (priv->ibss_beacon)
3439 dev_kfree_skb(priv->ibss_beacon);
3440
3441 ieee80211_free_hw(priv->hw);
3442}
3443
b481de9c
ZY
3444
3445/*****************************************************************************
3446 *
3447 * driver and module entry point
3448 *
3449 *****************************************************************************/
3450
fed9017e
RR
3451/* Hardware specific file defines the PCI IDs table for that hardware module */
3452static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3453#ifdef CONFIG_IWL4965
fed9017e
RR
3454 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3455 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3456#endif /* CONFIG_IWL4965 */
5a6a256e 3457#ifdef CONFIG_IWL5000
47408639
EK
3458 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3459 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3460 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3461 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3462 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3463 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3464 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK
3465 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3466 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3467 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW
3468/* 5350 WiFi/WiMax */
3469 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3470 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3471 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW
3472/* 5150 Wifi/WiMax */
3473 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3474 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
5953a62e
WYG
3475
3476/* 6x00 Series */
5953a62e
WYG
3477 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3478 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3479 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3480 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3481 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3482 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3483 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3484 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3485 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3486 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3487
3488/* 6x50 WiFi/WiMax Series */
3489 {IWL_PCI_DEVICE(0x0086, 0x1101, iwl6050_3agn_cfg)},
3490 {IWL_PCI_DEVICE(0x0086, 0x1121, iwl6050_3agn_cfg)},
3491 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3492 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3493 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3494 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
3495 {IWL_PCI_DEVICE(0x0088, 0x1111, iwl6050_3agn_cfg)},
3496 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3497 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3498
77dcb6a9 3499/* 1000 Series WiFi */
4bd0914f
WYG
3500 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3501 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3502 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3503 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3504 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3505 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3506 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3507 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3508 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3509 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3510 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3511 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 3512#endif /* CONFIG_IWL5000 */
7100e924 3513
fed9017e
RR
3514 {0}
3515};
3516MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3517
3518static struct pci_driver iwl_driver = {
b481de9c 3519 .name = DRV_NAME,
fed9017e 3520 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3521 .probe = iwl_pci_probe,
3522 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3523#ifdef CONFIG_PM
5b9f8cd3
EG
3524 .suspend = iwl_pci_suspend,
3525 .resume = iwl_pci_resume,
b481de9c
ZY
3526#endif
3527};
3528
5b9f8cd3 3529static int __init iwl_init(void)
b481de9c
ZY
3530{
3531
3532 int ret;
3533 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3534 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3535
e227ceac 3536 ret = iwlagn_rate_control_register();
897e1cf2 3537 if (ret) {
a3139c59
SO
3538 printk(KERN_ERR DRV_NAME
3539 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3540 return ret;
3541 }
3542
fed9017e 3543 ret = pci_register_driver(&iwl_driver);
b481de9c 3544 if (ret) {
a3139c59 3545 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3546 goto error_register;
b481de9c 3547 }
b481de9c
ZY
3548
3549 return ret;
897e1cf2 3550
897e1cf2 3551error_register:
e227ceac 3552 iwlagn_rate_control_unregister();
897e1cf2 3553 return ret;
b481de9c
ZY
3554}
3555
5b9f8cd3 3556static void __exit iwl_exit(void)
b481de9c 3557{
fed9017e 3558 pci_unregister_driver(&iwl_driver);
e227ceac 3559 iwlagn_rate_control_unregister();
b481de9c
ZY
3560}
3561
5b9f8cd3
EG
3562module_exit(iwl_exit);
3563module_init(iwl_init);
a562a9dd
RC
3564
3565#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3566module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 3567MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 3568module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
3569MODULE_PARM_DESC(debug, "debug output mask");
3570#endif
3571