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iwlagn: simplify WEP key check
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
d43c36dc 36#include <linux/sched.h>
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37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
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41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
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44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
a3139c59
SO
48#define DRV_NAME "iwlagn"
49
6bc913bd 50#include "iwl-eeprom.h"
3e0d4cb1 51#include "iwl-dev.h"
fee1247a 52#include "iwl-core.h"
3395f6e9 53#include "iwl-io.h"
b481de9c 54#include "iwl-helpers.h"
6974e363 55#include "iwl-sta.h"
f0832f13 56#include "iwl-calib.h"
a1175124 57#include "iwl-agn.h"
b481de9c 58
416e1438 59
b481de9c
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60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
b481de9c
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66/*
67 * module name, copyright, version, etc.
b481de9c 68 */
d783b061 69#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 70
0a6857e7 71#ifdef CONFIG_IWLWIFI_DEBUG
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72#define VD "d"
73#else
74#define VD
75#endif
76
81963d68 77#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 78
b481de9c
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79
80MODULE_DESCRIPTION(DRV_DESCRIPTION);
81MODULE_VERSION(DRV_VERSION);
a7b75207 82MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 83MODULE_LICENSE("GPL");
4fc22b21 84MODULE_ALIAS("iwl4965");
b481de9c 85
b481de9c 86/**
5b9f8cd3 87 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 88 *
01ebd063 89 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
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90 * the active_rxon structure is updated with the new data. This
91 * function correctly transitions out of the RXON_ASSOC_MSK state if
92 * a HW tune is required based on the RXON structure changes.
93 */
e0158e61 94int iwl_commit_rxon(struct iwl_priv *priv)
b481de9c
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95{
96 /* cast away the const for active_rxon in this function */
c1adf9fb 97 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
98 int ret;
99 bool new_assoc =
100 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 101
fee1247a 102 if (!iwl_is_alive(priv))
43d59b32 103 return -EBUSY;
b481de9c
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104
105 /* always get timestamp with Rx frame */
106 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
107
8ccde88a 108 ret = iwl_check_rxon_cmd(priv);
43d59b32 109 if (ret) {
15b1687c 110 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY
111 return -EINVAL;
112 }
113
0924e519
WYG
114 /*
115 * receive commit_rxon request
116 * abort any previous channel switch if still in process
117 */
118 if (priv->switch_rxon.switch_in_progress &&
119 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
120 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
121 le16_to_cpu(priv->switch_rxon.channel));
122 priv->switch_rxon.switch_in_progress = false;
123 }
124
b481de9c 125 /* If we don't need to send a full RXON, we can use
5b9f8cd3 126 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 127 * and other flags for the current radio configuration. */
54559703 128 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
129 ret = iwl_send_rxon_assoc(priv);
130 if (ret) {
15b1687c 131 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 132 return ret;
b481de9c
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133 }
134
135 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 136 iwl_print_rx_config_cmd(priv);
b481de9c
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137 return 0;
138 }
139
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140 /* If we are currently associated and the new config requires
141 * an RXON_ASSOC and the new config wants the associated mask enabled,
142 * we must clear the associated from the active configuration
143 * before we apply the new config */
43d59b32 144 if (iwl_is_associated(priv) && new_assoc) {
e1623446 145 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
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146 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
147
43d59b32 148 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 149 sizeof(struct iwl_rxon_cmd),
b481de9c
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150 &priv->active_rxon);
151
152 /* If the mask clearing failed then we set
153 * active_rxon back to what it was previously */
43d59b32 154 if (ret) {
b481de9c 155 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 156 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 157 return ret;
b481de9c 158 }
7e246191
RC
159 iwl_clear_ucode_stations(priv, false);
160 iwl_restore_stations(priv);
335348b1
JB
161 ret = iwl_restore_default_wep_keys(priv);
162 if (ret) {
163 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
164 return ret;
165 }
b481de9c
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166 }
167
e1623446 168 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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169 "* with%s RXON_FILTER_ASSOC_MSK\n"
170 "* channel = %d\n"
e174961c 171 "* bssid = %pM\n",
43d59b32 172 (new_assoc ? "" : "out"),
b481de9c 173 le16_to_cpu(priv->staging_rxon.channel),
e174961c 174 priv->staging_rxon.bssid_addr);
b481de9c 175
90e8e424 176 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
177
178 /* Apply the new configuration
7e246191
RC
179 * RXON unassoc clears the station table in uCode so restoration of
180 * stations is needed after it (the RXON command) completes
43d59b32
EG
181 */
182 if (!new_assoc) {
183 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 184 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 185 if (ret) {
15b1687c 186 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
187 return ret;
188 }
91dd6c27 189 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
43d59b32 190 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
7e246191
RC
191 iwl_clear_ucode_stations(priv, false);
192 iwl_restore_stations(priv);
335348b1
JB
193 ret = iwl_restore_default_wep_keys(priv);
194 if (ret) {
195 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
196 return ret;
197 }
b481de9c
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198 }
199
19cc1087 200 priv->start_calib = 0;
9185159d 201 if (new_assoc) {
47eef9bd
WYG
202 /*
203 * allow CTS-to-self if possible for new association.
204 * this is relevant only for 5000 series and up,
205 * but will not damage 4965
206 */
207 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
208
43d59b32
EG
209 /* Apply the new configuration
210 * RXON assoc doesn't clear the station table in uCode,
211 */
212 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
213 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
214 if (ret) {
15b1687c 215 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
216 return ret;
217 }
218 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 219 }
a643565e 220 iwl_print_rx_config_cmd(priv);
b481de9c 221
36da7d70
ZY
222 iwl_init_sensitivity(priv);
223
224 /* If we issue a new RXON command which required a tune then we must
225 * send a new TXPOWER command or we won't be able to Tx any frames */
226 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
227 if (ret) {
15b1687c 228 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY
229 return ret;
230 }
231
b481de9c
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232 return 0;
233}
234
5b9f8cd3 235void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
236{
237
45823531
AK
238 if (priv->cfg->ops->hcmd->set_rxon_chain)
239 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 240 iwlcore_commit_rxon(priv);
5da4b55f
MA
241}
242
fcab423d 243static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
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244{
245 struct list_head *element;
246
e1623446 247 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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248 priv->frames_count);
249
250 while (!list_empty(&priv->free_frames)) {
251 element = priv->free_frames.next;
252 list_del(element);
fcab423d 253 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
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254 priv->frames_count--;
255 }
256
257 if (priv->frames_count) {
39aadf8c 258 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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259 priv->frames_count);
260 priv->frames_count = 0;
261 }
262}
263
fcab423d 264static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 265{
fcab423d 266 struct iwl_frame *frame;
b481de9c
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267 struct list_head *element;
268 if (list_empty(&priv->free_frames)) {
269 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
270 if (!frame) {
15b1687c 271 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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272 return NULL;
273 }
274
275 priv->frames_count++;
276 return frame;
277 }
278
279 element = priv->free_frames.next;
280 list_del(element);
fcab423d 281 return list_entry(element, struct iwl_frame, list);
b481de9c
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282}
283
fcab423d 284static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
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285{
286 memset(frame, 0, sizeof(*frame));
287 list_add(&frame->list, &priv->free_frames);
288}
289
47ff65c4 290static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 291 struct ieee80211_hdr *hdr,
73ec1cc2 292 int left)
b481de9c 293{
3109ece1 294 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
295 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
296 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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297 return 0;
298
299 if (priv->ibss_beacon->len > left)
300 return 0;
301
302 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
303
304 return priv->ibss_beacon->len;
305}
306
47ff65c4
DH
307/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
308static void iwl_set_beacon_tim(struct iwl_priv *priv,
309 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
310 u8 *beacon, u32 frame_size)
311{
312 u16 tim_idx;
313 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
314
315 /*
316 * The index is relative to frame start but we start looking at the
317 * variable-length part of the beacon.
318 */
319 tim_idx = mgmt->u.beacon.variable - beacon;
320
321 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
322 while ((tim_idx < (frame_size - 2)) &&
323 (beacon[tim_idx] != WLAN_EID_TIM))
324 tim_idx += beacon[tim_idx+1] + 2;
325
326 /* If TIM field was found, set variables */
327 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
328 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
329 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
330 } else
331 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
332}
333
5b9f8cd3 334static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 335 struct iwl_frame *frame)
4bf64efd
TW
336{
337 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH
338 u32 frame_size;
339 u32 rate_flags;
340 u32 rate;
341 /*
342 * We have to set up the TX command, the TX Beacon command, and the
343 * beacon contents.
344 */
4bf64efd 345
47ff65c4 346 /* Initialize memory */
4bf64efd
TW
347 tx_beacon_cmd = &frame->u.beacon;
348 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
349
47ff65c4 350 /* Set up TX beacon contents */
4bf64efd 351 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 352 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH
353 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
354 return 0;
4bf64efd 355
47ff65c4 356 /* Set up TX command fields */
4bf64efd 357 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH
358 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
359 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
360 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
361 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 362
47ff65c4
DH
363 /* Set up TX beacon command fields */
364 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
365 frame_size);
4bf64efd 366
47ff65c4
DH
367 /* Set up packet rate and flags */
368 rate = iwl_rate_get_lowest_plcp(priv);
369 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
370 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
371 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
372 rate_flags |= RATE_MCS_CCK_MSK;
373 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
374 rate_flags);
4bf64efd
TW
375
376 return sizeof(*tx_beacon_cmd) + frame_size;
377}
5b9f8cd3 378static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 379{
fcab423d 380 struct iwl_frame *frame;
b481de9c
ZY
381 unsigned int frame_size;
382 int rc;
b481de9c 383
fcab423d 384 frame = iwl_get_free_frame(priv);
b481de9c 385 if (!frame) {
15b1687c 386 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
387 "command.\n");
388 return -ENOMEM;
389 }
390
47ff65c4
DH
391 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
392 if (!frame_size) {
393 IWL_ERR(priv, "Error configuring the beacon command\n");
394 iwl_free_frame(priv, frame);
395 return -EINVAL;
396 }
b481de9c 397
857485c0 398 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
399 &frame->u.cmd[0]);
400
fcab423d 401 iwl_free_frame(priv, frame);
b481de9c
ZY
402
403 return rc;
404}
405
7aaa1d79
SO
406static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
407{
408 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
409
410 dma_addr_t addr = get_unaligned_le32(&tb->lo);
411 if (sizeof(dma_addr_t) > sizeof(u32))
412 addr |=
413 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
414
415 return addr;
416}
417
418static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
419{
420 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
421
422 return le16_to_cpu(tb->hi_n_len) >> 4;
423}
424
425static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
426 dma_addr_t addr, u16 len)
427{
428 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
429 u16 hi_n_len = len << 4;
430
431 put_unaligned_le32(addr, &tb->lo);
432 if (sizeof(dma_addr_t) > sizeof(u32))
433 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
434
435 tb->hi_n_len = cpu_to_le16(hi_n_len);
436
437 tfd->num_tbs = idx + 1;
438}
439
440static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
441{
442 return tfd->num_tbs & 0x1f;
443}
444
445/**
446 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
447 * @priv - driver private data
448 * @txq - tx queue
449 *
450 * Does NOT advance any TFD circular buffer read/write indexes
451 * Does NOT free the TFD itself (which is within circular buffer)
452 */
453void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
454{
59606ffa 455 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
456 struct iwl_tfd *tfd;
457 struct pci_dev *dev = priv->pci_dev;
458 int index = txq->q.read_ptr;
459 int i;
460 int num_tbs;
461
462 tfd = &tfd_tmp[index];
463
464 /* Sanity check on number of chunks */
465 num_tbs = iwl_tfd_get_num_tbs(tfd);
466
467 if (num_tbs >= IWL_NUM_OF_TBS) {
468 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
469 /* @todo issue fatal error, it is quite serious situation */
470 return;
471 }
472
473 /* Unmap tx_cmd */
474 if (num_tbs)
475 pci_unmap_single(dev,
c2acea8e
JB
476 pci_unmap_addr(&txq->meta[index], mapping),
477 pci_unmap_len(&txq->meta[index], len),
96891cee 478 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
479
480 /* Unmap chunks, if any. */
481 for (i = 1; i < num_tbs; i++) {
482 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
483 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
484
485 if (txq->txb) {
486 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
487 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
488 }
489 }
490}
491
492int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
493 struct iwl_tx_queue *txq,
494 dma_addr_t addr, u16 len,
495 u8 reset, u8 pad)
496{
497 struct iwl_queue *q;
59606ffa 498 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
499 u32 num_tbs;
500
501 q = &txq->q;
59606ffa
SO
502 tfd_tmp = (struct iwl_tfd *)txq->tfds;
503 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
504
505 if (reset)
506 memset(tfd, 0, sizeof(*tfd));
507
508 num_tbs = iwl_tfd_get_num_tbs(tfd);
509
510 /* Each TFD can point to a maximum 20 Tx buffers */
511 if (num_tbs >= IWL_NUM_OF_TBS) {
512 IWL_ERR(priv, "Error can not send more than %d chunks\n",
513 IWL_NUM_OF_TBS);
514 return -EINVAL;
515 }
516
517 BUG_ON(addr & ~DMA_BIT_MASK(36));
518 if (unlikely(addr & ~IWL_TX_DMA_MASK))
519 IWL_ERR(priv, "Unaligned address = %llx\n",
520 (unsigned long long)addr);
521
522 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
523
524 return 0;
525}
526
a8e74e27
SO
527/*
528 * Tell nic where to find circular buffer of Tx Frame Descriptors for
529 * given Tx queue, and enable the DMA channel used for that queue.
530 *
531 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
532 * channels supported in hardware.
533 */
534int iwl_hw_tx_queue_init(struct iwl_priv *priv,
535 struct iwl_tx_queue *txq)
536{
a8e74e27
SO
537 int txq_id = txq->q.id;
538
a8e74e27
SO
539 /* Circular buffer (TFD queue in DRAM) physical base address */
540 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
541 txq->q.dma_addr >> 8);
542
a8e74e27
SO
543 return 0;
544}
545
b481de9c
ZY
546/******************************************************************************
547 *
548 * Generic RX handler implementations
549 *
550 ******************************************************************************/
885ba202
TW
551static void iwl_rx_reply_alive(struct iwl_priv *priv,
552 struct iwl_rx_mem_buffer *rxb)
b481de9c 553{
2f301227 554 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 555 struct iwl_alive_resp *palive;
b481de9c
ZY
556 struct delayed_work *pwork;
557
558 palive = &pkt->u.alive_frame;
559
e1623446 560 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
561 "0x%01X 0x%01X\n",
562 palive->is_valid, palive->ver_type,
563 palive->ver_subtype);
564
565 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 566 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
567 memcpy(&priv->card_alive_init,
568 &pkt->u.alive_frame,
885ba202 569 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
570 pwork = &priv->init_alive_start;
571 } else {
e1623446 572 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 573 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 574 sizeof(struct iwl_alive_resp));
b481de9c
ZY
575 pwork = &priv->alive_start;
576 }
577
578 /* We delay the ALIVE response by 5ms to
579 * give the HW RF Kill time to activate... */
580 if (palive->is_valid == UCODE_VALID_OK)
581 queue_delayed_work(priv->workqueue, pwork,
582 msecs_to_jiffies(5));
583 else
39aadf8c 584 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
585}
586
5b9f8cd3 587static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 588{
c79dd5b5
TW
589 struct iwl_priv *priv =
590 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
591 struct sk_buff *beacon;
592
593 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 594 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
595
596 if (!beacon) {
15b1687c 597 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
598 return;
599 }
600
601 mutex_lock(&priv->mutex);
602 /* new beacon skb is allocated every time; dispose previous.*/
603 if (priv->ibss_beacon)
604 dev_kfree_skb(priv->ibss_beacon);
605
606 priv->ibss_beacon = beacon;
607 mutex_unlock(&priv->mutex);
608
5b9f8cd3 609 iwl_send_beacon_cmd(priv);
b481de9c
ZY
610}
611
4e39317d 612/**
5b9f8cd3 613 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
614 *
615 * This callback is provided in order to send a statistics request.
616 *
617 * This timer function is continually reset to execute within
618 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
619 * was received. We need to ensure we receive the statistics in order
620 * to update the temperature used for calibrating the TXPOWER.
621 */
5b9f8cd3 622static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
623{
624 struct iwl_priv *priv = (struct iwl_priv *)data;
625
626 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
627 return;
628
61780ee3
MA
629 /* dont send host command if rf-kill is on */
630 if (!iwl_is_ready_rf(priv))
631 return;
632
ef8d5529 633 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG
634}
635
a9e1cb6a
WYG
636
637static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
638 u32 start_idx, u32 num_events,
639 u32 mode)
640{
641 u32 i;
642 u32 ptr; /* SRAM byte address of log data */
643 u32 ev, time, data; /* event log data */
644 unsigned long reg_flags;
645
646 if (mode == 0)
647 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
648 else
649 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
650
651 /* Make sure device is powered up for SRAM reads */
652 spin_lock_irqsave(&priv->reg_lock, reg_flags);
653 if (iwl_grab_nic_access(priv)) {
654 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
655 return;
656 }
657
658 /* Set starting address; reads will auto-increment */
659 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
660 rmb();
661
662 /*
663 * "time" is actually "data" for mode 0 (no timestamp).
664 * place event id # at far right for easier visual parsing.
665 */
666 for (i = 0; i < num_events; i++) {
667 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
668 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
669 if (mode == 0) {
670 trace_iwlwifi_dev_ucode_cont_event(priv,
671 0, time, ev);
672 } else {
673 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
674 trace_iwlwifi_dev_ucode_cont_event(priv,
675 time, data, ev);
676 }
677 }
678 /* Allow device to power down */
679 iwl_release_nic_access(priv);
680 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
681}
682
875295f1 683static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG
684{
685 u32 capacity; /* event log capacity in # entries */
686 u32 base; /* SRAM byte address of event log header */
687 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
688 u32 num_wraps; /* # times uCode wrapped to top of log */
689 u32 next_entry; /* index of next entry to be written by uCode */
690
691 if (priv->ucode_type == UCODE_INIT)
692 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
693 else
694 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
695 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
696 capacity = iwl_read_targ_mem(priv, base);
697 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
698 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
699 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
700 } else
701 return;
702
703 if (num_wraps == priv->event_log.num_wraps) {
704 iwl_print_cont_event_trace(priv,
705 base, priv->event_log.next_entry,
706 next_entry - priv->event_log.next_entry,
707 mode);
708 priv->event_log.non_wraps_count++;
709 } else {
710 if ((num_wraps - priv->event_log.num_wraps) > 1)
711 priv->event_log.wraps_more_count++;
712 else
713 priv->event_log.wraps_once_count++;
714 trace_iwlwifi_dev_ucode_wrap_event(priv,
715 num_wraps - priv->event_log.num_wraps,
716 next_entry, priv->event_log.next_entry);
717 if (next_entry < priv->event_log.next_entry) {
718 iwl_print_cont_event_trace(priv, base,
719 priv->event_log.next_entry,
720 capacity - priv->event_log.next_entry,
721 mode);
722
723 iwl_print_cont_event_trace(priv, base, 0,
724 next_entry, mode);
725 } else {
726 iwl_print_cont_event_trace(priv, base,
727 next_entry, capacity - next_entry,
728 mode);
729
730 iwl_print_cont_event_trace(priv, base, 0,
731 next_entry, mode);
732 }
733 }
734 priv->event_log.num_wraps = num_wraps;
735 priv->event_log.next_entry = next_entry;
736}
737
738/**
739 * iwl_bg_ucode_trace - Timer callback to log ucode event
740 *
741 * The timer is continually set to execute every
742 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
743 * this function is to perform continuous uCode event logging operation
744 * if enabled
745 */
746static void iwl_bg_ucode_trace(unsigned long data)
747{
748 struct iwl_priv *priv = (struct iwl_priv *)data;
749
750 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
751 return;
752
753 if (priv->event_log.ucode_trace) {
754 iwl_continuous_event_trace(priv);
755 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
756 mod_timer(&priv->ucode_trace,
757 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
758 }
759}
760
5b9f8cd3 761static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 762 struct iwl_rx_mem_buffer *rxb)
b481de9c 763{
0a6857e7 764#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 765 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW
766 struct iwl4965_beacon_notif *beacon =
767 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 768 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 769
e1623446 770 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 771 "tsf %d %d rate %d\n",
25a6572c 772 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
773 beacon->beacon_notify_hdr.failure_frame,
774 le32_to_cpu(beacon->ibss_mgr_status),
775 le32_to_cpu(beacon->high_tsf),
776 le32_to_cpu(beacon->low_tsf), rate);
777#endif
778
05c914fe 779 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
780 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
781 queue_work(priv->workqueue, &priv->beacon_update);
782}
783
b481de9c
ZY
784/* Handle notification from uCode that card's power state is changing
785 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 786static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 787 struct iwl_rx_mem_buffer *rxb)
b481de9c 788{
2f301227 789 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
790 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
791 unsigned long status = priv->status;
792
3a41bbd5 793 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 794 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG
795 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
796 (flags & CT_CARD_DISABLED) ?
797 "Reached" : "Not reached");
b481de9c
ZY
798
799 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 800 CT_CARD_DISABLED)) {
b481de9c 801
3395f6e9 802 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
803 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
804
a8b50a0a
MA
805 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
806 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
807
808 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 809 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 810 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 811 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 812 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 813 }
3a41bbd5 814 if (flags & CT_CARD_DISABLED)
39b73fb1 815 iwl_tt_enter_ct_kill(priv);
b481de9c 816 }
3a41bbd5 817 if (!(flags & CT_CARD_DISABLED))
39b73fb1 818 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
819
820 if (flags & HW_CARD_DISABLED)
821 set_bit(STATUS_RF_KILL_HW, &priv->status);
822 else
823 clear_bit(STATUS_RF_KILL_HW, &priv->status);
824
825
b481de9c 826 if (!(flags & RXON_CARD_DISABLED))
2a421b91 827 iwl_scan_cancel(priv);
b481de9c
ZY
828
829 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
830 test_bit(STATUS_RF_KILL_HW, &priv->status)))
831 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
832 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
833 else
834 wake_up_interruptible(&priv->wait_command_queue);
835}
836
5b9f8cd3 837int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 838{
e2e3c57b 839 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 840 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
841 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
842 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
843 ~APMG_PS_CTRL_MSK_PWR_SRC);
844 } else {
845 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
846 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
847 ~APMG_PS_CTRL_MSK_PWR_SRC);
848 }
849
a8b50a0a 850 return 0;
e2e3c57b
TW
851}
852
b481de9c 853/**
5b9f8cd3 854 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
855 *
856 * Setup the RX handlers for each of the reply types sent from the uCode
857 * to the host.
858 *
859 * This function chains into the hardware specific files for them to setup
860 * any hardware specific handlers as well.
861 */
653fa4a0 862static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 863{
885ba202 864 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
865 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
866 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC
867 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
868 iwl_rx_spectrum_measure_notif;
5b9f8cd3 869 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 870 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
871 iwl_rx_pm_debug_statistics_notif;
872 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 873
9fbab516
BC
874 /*
875 * The same handler is used for both the REPLY to a discrete
876 * statistics request from the host as well as for the periodic
877 * statistics notifications (after received beacons) from the uCode.
b481de9c 878 */
ef8d5529 879 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 880 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW
881
882 iwl_setup_rx_scan_handlers(priv);
883
37a44211 884 /* status change handler */
5b9f8cd3 885 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 886
c1354754
TW
887 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
888 iwl_rx_missed_beacon_notif;
37a44211 889 /* Rx handlers */
8d801080
WYG
890 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
891 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 892 /* block ack */
74bcdb33 893 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 894 /* Set up hardware specific Rx handlers */
d4789efe 895 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
896}
897
b481de9c 898/**
a55360e4 899 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
900 *
901 * Uses the priv->rx_handlers callback function array to invoke
902 * the appropriate handlers, including command responses,
903 * frame-received notifications, and other notifications.
904 */
a55360e4 905void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 906{
a55360e4 907 struct iwl_rx_mem_buffer *rxb;
db11d634 908 struct iwl_rx_packet *pkt;
a55360e4 909 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
910 u32 r, i;
911 int reclaim;
912 unsigned long flags;
5c0eef96 913 u8 fill_rx = 0;
d68ab680 914 u32 count = 8;
4752c93c 915 int total_empty;
b481de9c 916
6440adb5
BC
917 /* uCode's read index (stored in shared DRAM) indicates the last Rx
918 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 919 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
920 i = rxq->read;
921
922 /* Rx interrupt, but nothing sent from uCode */
923 if (i == r)
e1623446 924 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 925
4752c93c 926 /* calculate total frames need to be restock after handling RX */
7300515d 927 total_empty = r - rxq->write_actual;
4752c93c
MA
928 if (total_empty < 0)
929 total_empty += RX_QUEUE_SIZE;
930
931 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
932 fill_rx = 1;
933
b481de9c
ZY
934 while (i != r) {
935 rxb = rxq->queue[i];
936
9fbab516 937 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
938 * then a bug has been introduced in the queue refilling
939 * routines -- catch it here */
940 BUG_ON(rxb == NULL);
941
942 rxq->queue[i] = NULL;
943
2f301227
ZY
944 pci_unmap_page(priv->pci_dev, rxb->page_dma,
945 PAGE_SIZE << priv->hw_params.rx_page_order,
946 PCI_DMA_FROMDEVICE);
947 pkt = rxb_addr(rxb);
b481de9c 948
be1a71a1
JB
949 trace_iwlwifi_dev_rx(priv, pkt,
950 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
951
b481de9c
ZY
952 /* Reclaim a command buffer only if this packet is a response
953 * to a (driver-originated) command.
954 * If the packet (e.g. Rx frame) originated from uCode,
955 * there is no command buffer to reclaim.
956 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
957 * but apparently a few don't get set; catch them here. */
958 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
959 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 960 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 961 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 962 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
963 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
964 (pkt->hdr.cmd != REPLY_TX);
965
966 /* Based on type of command response or notification,
967 * handle those that need handling via function in
5b9f8cd3 968 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 969 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 970 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 971 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 972 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 973 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
974 } else {
975 /* No handling needed */
e1623446 976 IWL_DEBUG_RX(priv,
b481de9c
ZY
977 "r %d i %d No handler needed for %s, 0x%02x\n",
978 r, i, get_cmd_string(pkt->hdr.cmd),
979 pkt->hdr.cmd);
980 }
981
29b1b268
ZY
982 /*
983 * XXX: After here, we should always check rxb->page
984 * against NULL before touching it or its virtual
985 * memory (pkt). Because some rx_handler might have
986 * already taken or freed the pages.
987 */
988
b481de9c 989 if (reclaim) {
2f301227
ZY
990 /* Invoke any callbacks, transfer the buffer to caller,
991 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 992 * as we reclaim the driver command queue */
29b1b268 993 if (rxb->page)
17b88929 994 iwl_tx_cmd_complete(priv, rxb);
b481de9c 995 else
39aadf8c 996 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
997 }
998
7300515d
ZY
999 /* Reuse the page if possible. For notification packets and
1000 * SKBs that fail to Rx correctly, add them back into the
1001 * rx_free list for reuse later. */
1002 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1003 if (rxb->page != NULL) {
7300515d
ZY
1004 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1005 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1006 PCI_DMA_FROMDEVICE);
1007 list_add_tail(&rxb->list, &rxq->rx_free);
1008 rxq->free_count++;
1009 } else
1010 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1011
b481de9c 1012 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1013
b481de9c 1014 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1015 /* If there are a lot of unused frames,
1016 * restock the Rx queue so ucode wont assert. */
1017 if (fill_rx) {
1018 count++;
1019 if (count >= 8) {
7300515d 1020 rxq->read = i;
54b81550 1021 iwlagn_rx_replenish_now(priv);
5c0eef96
MA
1022 count = 0;
1023 }
1024 }
b481de9c
ZY
1025 }
1026
1027 /* Backtrack one entry */
7300515d 1028 rxq->read = i;
4752c93c 1029 if (fill_rx)
54b81550 1030 iwlagn_rx_replenish_now(priv);
4752c93c 1031 else
54b81550 1032 iwlagn_rx_queue_restock(priv);
a55360e4 1033}
a55360e4 1034
0359facc
MA
1035/* call this function to flush any scheduled tasklet */
1036static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1037{
a96a27f9 1038 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1039 synchronize_irq(priv->pci_dev->irq);
1040 tasklet_kill(&priv->irq_tasklet);
1041}
1042
ef850d7c 1043static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
1044{
1045 u32 inta, handled = 0;
1046 u32 inta_fh;
1047 unsigned long flags;
c2e61da2 1048 u32 i;
0a6857e7 1049#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1050 u32 inta_mask;
1051#endif
1052
1053 spin_lock_irqsave(&priv->lock, flags);
1054
1055 /* Ack/clear/reset pending uCode interrupts.
1056 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1057 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
1058 inta = iwl_read32(priv, CSR_INT);
1059 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1060
1061 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1062 * Any new interrupts that happen after this, either while we're
1063 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
1064 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1065 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1066
0a6857e7 1067#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1068 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1069 /* just for debug */
3395f6e9 1070 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1071 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1072 inta, inta_mask, inta_fh);
1073 }
1074#endif
1075
2f301227
ZY
1076 spin_unlock_irqrestore(&priv->lock, flags);
1077
b481de9c
ZY
1078 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1079 * atomic, make sure that inta covers all the interrupts that
1080 * we've discovered, even if FH interrupt came in just after
1081 * reading CSR_INT. */
6f83eaa1 1082 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1083 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1084 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
1085 inta |= CSR_INT_BIT_FH_TX;
1086
1087 /* Now service all interrupt bits discovered above. */
1088 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1089 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1090
1091 /* Tell the device to stop sending interrupts */
5b9f8cd3 1092 iwl_disable_interrupts(priv);
b481de9c 1093
a83b9141 1094 priv->isr_stats.hw++;
5b9f8cd3 1095 iwl_irq_handle_error(priv);
b481de9c
ZY
1096
1097 handled |= CSR_INT_BIT_HW_ERR;
1098
b481de9c
ZY
1099 return;
1100 }
1101
0a6857e7 1102#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1103 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1104 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1105 if (inta & CSR_INT_BIT_SCD) {
e1623446 1106 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1107 "the frame/frames.\n");
a83b9141
WYG
1108 priv->isr_stats.sch++;
1109 }
b481de9c
ZY
1110
1111 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1112 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1113 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
1114 priv->isr_stats.alive++;
1115 }
b481de9c
ZY
1116 }
1117#endif
1118 /* Safely ignore these bits for debug checks below */
25c03d8e 1119 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1120
9fbab516 1121 /* HW RF KILL switch toggled */
b481de9c
ZY
1122 if (inta & CSR_INT_BIT_RF_KILL) {
1123 int hw_rf_kill = 0;
3395f6e9 1124 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
1125 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1126 hw_rf_kill = 1;
1127
4c423a2b 1128 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1129 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1130
a83b9141
WYG
1131 priv->isr_stats.rfkill++;
1132
a9efa652 1133 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
1134 * the driver allows loading the ucode even if the radio
1135 * is killed. Hence update the killswitch state here. The
1136 * rfkill handler will care about restarting if needed.
a9efa652 1137 */
6cd0b1cb
HS
1138 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1139 if (hw_rf_kill)
1140 set_bit(STATUS_RF_KILL_HW, &priv->status);
1141 else
1142 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1143 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1144 }
b481de9c
ZY
1145
1146 handled |= CSR_INT_BIT_RF_KILL;
1147 }
1148
9fbab516 1149 /* Chip got too hot and stopped itself */
b481de9c 1150 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1151 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1152 priv->isr_stats.ctkill++;
b481de9c
ZY
1153 handled |= CSR_INT_BIT_CT_KILL;
1154 }
1155
1156 /* Error detected by uCode */
1157 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1158 IWL_ERR(priv, "Microcode SW error detected. "
1159 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1160 priv->isr_stats.sw++;
1161 priv->isr_stats.sw_err = inta;
5b9f8cd3 1162 iwl_irq_handle_error(priv);
b481de9c
ZY
1163 handled |= CSR_INT_BIT_SW_ERR;
1164 }
1165
c2e61da2
BC
1166 /*
1167 * uCode wakes up after power-down sleep.
1168 * Tell device about any new tx or host commands enqueued,
1169 * and about any Rx buffers made available while asleep.
1170 */
b481de9c 1171 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1172 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1173 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC
1174 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1175 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1176 priv->isr_stats.wakeup++;
b481de9c
ZY
1177 handled |= CSR_INT_BIT_WAKEUP;
1178 }
1179
1180 /* All uCode command responses, including Tx command responses,
1181 * Rx "responses" (frame-received notification), and other
1182 * notifications from uCode come through here*/
1183 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1184 iwl_rx_handle(priv);
a83b9141 1185 priv->isr_stats.rx++;
b481de9c
ZY
1186 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1187 }
1188
c72cd19f 1189 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1190 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1191 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1192 priv->isr_stats.tx++;
b481de9c 1193 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1194 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR
1195 priv->ucode_write_complete = 1;
1196 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1197 }
1198
a83b9141 1199 if (inta & ~handled) {
15b1687c 1200 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1201 priv->isr_stats.unhandled++;
1202 }
b481de9c 1203
40cefda9 1204 if (inta & ~(priv->inta_mask)) {
39aadf8c 1205 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1206 inta & ~priv->inta_mask);
39aadf8c 1207 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1208 }
1209
1210 /* Re-enable all interrupts */
0359facc
MA
1211 /* only Re-enable if diabled by irq */
1212 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1213 iwl_enable_interrupts(priv);
b481de9c 1214
0a6857e7 1215#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1216 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1217 inta = iwl_read32(priv, CSR_INT);
1218 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1219 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1220 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1221 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1222 }
1223#endif
b481de9c
ZY
1224}
1225
ef850d7c
MA
1226/* tasklet for iwlagn interrupt */
1227static void iwl_irq_tasklet(struct iwl_priv *priv)
1228{
1229 u32 inta = 0;
1230 u32 handled = 0;
1231 unsigned long flags;
8756990f 1232 u32 i;
ef850d7c
MA
1233#ifdef CONFIG_IWLWIFI_DEBUG
1234 u32 inta_mask;
1235#endif
1236
1237 spin_lock_irqsave(&priv->lock, flags);
1238
1239 /* Ack/clear/reset pending uCode interrupts.
1240 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1241 */
48a6be6a
SZ
1242 /* There is a hardware bug in the interrupt mask function that some
1243 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1244 * they are disabled in the CSR_INT_MASK register. Furthermore the
1245 * ICT interrupt handling mechanism has another bug that might cause
1246 * these unmasked interrupts fail to be detected. We workaround the
1247 * hardware bugs here by ACKing all the possible interrupts so that
1248 * interrupt coalescing can still be achieved.
1249 */
0f2df9ea 1250 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1251
a4c8b2a6 1252 inta = priv->_agn.inta;
ef850d7c
MA
1253
1254#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1255 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1256 /* just for debug */
1257 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1258 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1259 inta, inta_mask);
1260 }
1261#endif
2f301227
ZY
1262
1263 spin_unlock_irqrestore(&priv->lock, flags);
1264
a4c8b2a6
JB
1265 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1266 priv->_agn.inta = 0;
ef850d7c
MA
1267
1268 /* Now service all interrupt bits discovered above. */
1269 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1270 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1271
1272 /* Tell the device to stop sending interrupts */
1273 iwl_disable_interrupts(priv);
1274
1275 priv->isr_stats.hw++;
1276 iwl_irq_handle_error(priv);
1277
1278 handled |= CSR_INT_BIT_HW_ERR;
1279
ef850d7c
MA
1280 return;
1281 }
1282
1283#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1284 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1285 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1286 if (inta & CSR_INT_BIT_SCD) {
1287 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1288 "the frame/frames.\n");
1289 priv->isr_stats.sch++;
1290 }
1291
1292 /* Alive notification via Rx interrupt will do the real work */
1293 if (inta & CSR_INT_BIT_ALIVE) {
1294 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1295 priv->isr_stats.alive++;
1296 }
1297 }
1298#endif
1299 /* Safely ignore these bits for debug checks below */
1300 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1301
1302 /* HW RF KILL switch toggled */
1303 if (inta & CSR_INT_BIT_RF_KILL) {
1304 int hw_rf_kill = 0;
1305 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1306 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1307 hw_rf_kill = 1;
1308
4c423a2b 1309 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1310 hw_rf_kill ? "disable radio" : "enable radio");
1311
1312 priv->isr_stats.rfkill++;
1313
1314 /* driver only loads ucode once setting the interface up.
1315 * the driver allows loading the ucode even if the radio
1316 * is killed. Hence update the killswitch state here. The
1317 * rfkill handler will care about restarting if needed.
1318 */
1319 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1320 if (hw_rf_kill)
1321 set_bit(STATUS_RF_KILL_HW, &priv->status);
1322 else
1323 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1324 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1325 }
1326
1327 handled |= CSR_INT_BIT_RF_KILL;
1328 }
1329
1330 /* Chip got too hot and stopped itself */
1331 if (inta & CSR_INT_BIT_CT_KILL) {
1332 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1333 priv->isr_stats.ctkill++;
1334 handled |= CSR_INT_BIT_CT_KILL;
1335 }
1336
1337 /* Error detected by uCode */
1338 if (inta & CSR_INT_BIT_SW_ERR) {
1339 IWL_ERR(priv, "Microcode SW error detected. "
1340 " Restarting 0x%X.\n", inta);
1341 priv->isr_stats.sw++;
1342 priv->isr_stats.sw_err = inta;
1343 iwl_irq_handle_error(priv);
1344 handled |= CSR_INT_BIT_SW_ERR;
1345 }
1346
1347 /* uCode wakes up after power-down sleep */
1348 if (inta & CSR_INT_BIT_WAKEUP) {
1349 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1350 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC
1351 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1352 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA
1353
1354 priv->isr_stats.wakeup++;
1355
1356 handled |= CSR_INT_BIT_WAKEUP;
1357 }
1358
1359 /* All uCode command responses, including Tx command responses,
1360 * Rx "responses" (frame-received notification), and other
1361 * notifications from uCode come through here*/
40cefda9
MA
1362 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1363 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1364 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1365 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1366 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1367 iwl_write32(priv, CSR_FH_INT_STATUS,
1368 CSR49_FH_INT_RX_MASK);
1369 }
1370 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1371 handled |= CSR_INT_BIT_RX_PERIODIC;
1372 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1373 }
1374 /* Sending RX interrupt require many steps to be done in the
1375 * the device:
1376 * 1- write interrupt to current index in ICT table.
1377 * 2- dma RX frame.
1378 * 3- update RX shared data to indicate last write index.
1379 * 4- send interrupt.
1380 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC
1381 * but the shared data changes does not reflect this;
1382 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1383 */
74ba67ed
BC
1384
1385 /* Disable periodic interrupt; we use it as just a one-shot. */
1386 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1387 CSR_INT_PERIODIC_DIS);
ef850d7c 1388 iwl_rx_handle(priv);
74ba67ed
BC
1389
1390 /*
1391 * Enable periodic interrupt in 8 msec only if we received
1392 * real RX interrupt (instead of just periodic int), to catch
1393 * any dangling Rx interrupt. If it was just the periodic
1394 * interrupt, there was no dangling Rx activity, and no need
1395 * to extend the periodic interrupt; one-shot is enough.
1396 */
40cefda9 1397 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1398 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA
1399 CSR_INT_PERIODIC_ENA);
1400
ef850d7c 1401 priv->isr_stats.rx++;
ef850d7c
MA
1402 }
1403
c72cd19f 1404 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA
1405 if (inta & CSR_INT_BIT_FH_TX) {
1406 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1407 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA
1408 priv->isr_stats.tx++;
1409 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1410 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA
1411 priv->ucode_write_complete = 1;
1412 wake_up_interruptible(&priv->wait_command_queue);
1413 }
1414
1415 if (inta & ~handled) {
1416 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1417 priv->isr_stats.unhandled++;
1418 }
1419
40cefda9 1420 if (inta & ~(priv->inta_mask)) {
ef850d7c 1421 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1422 inta & ~priv->inta_mask);
ef850d7c
MA
1423 }
1424
ef850d7c
MA
1425 /* Re-enable all interrupts */
1426 /* only Re-enable if diabled by irq */
1427 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1428 iwl_enable_interrupts(priv);
ef850d7c
MA
1429}
1430
872c8ddc
WYG
1431/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1432#define ACK_CNT_RATIO (50)
1433#define BA_TIMEOUT_CNT (5)
1434#define BA_TIMEOUT_MAX (16)
1435
1436/**
1437 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1438 *
1439 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1440 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1441 * operation state.
1442 */
1443bool iwl_good_ack_health(struct iwl_priv *priv,
1444 struct iwl_rx_packet *pkt)
1445{
1446 bool rc = true;
1447 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1448 int ba_timeout_delta;
1449
1450 actual_ack_cnt_delta =
1451 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1452 le32_to_cpu(priv->statistics.tx.actual_ack_cnt);
1453 expected_ack_cnt_delta =
1454 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1455 le32_to_cpu(priv->statistics.tx.expected_ack_cnt);
1456 ba_timeout_delta =
1457 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1458 le32_to_cpu(priv->statistics.tx.agg.ba_timeout);
1459 if ((priv->_agn.agg_tids_count > 0) &&
1460 (expected_ack_cnt_delta > 0) &&
1461 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1462 < ACK_CNT_RATIO) &&
1463 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1464 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1465 " expected_ack_cnt = %d\n",
1466 actual_ack_cnt_delta, expected_ack_cnt_delta);
1467
1468#ifdef CONFIG_IWLWIFI_DEBUG
1469 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1470 priv->delta_statistics.tx.rx_detected_cnt);
1471 IWL_DEBUG_RADIO(priv,
1472 "ack_or_ba_timeout_collision delta = %d\n",
1473 priv->delta_statistics.tx.
1474 ack_or_ba_timeout_collision);
1475#endif
1476 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1477 ba_timeout_delta);
1478 if (!actual_ack_cnt_delta &&
1479 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1480 rc = false;
1481 }
1482 return rc;
1483}
1484
a83b9141 1485
b481de9c
ZY
1486/******************************************************************************
1487 *
1488 * uCode download functions
1489 *
1490 ******************************************************************************/
1491
5b9f8cd3 1492static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1493{
98c92211
TW
1494 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1495 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1496 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1497 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1498 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1499 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1500}
1501
5b9f8cd3 1502static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1503{
1504 /* Remove all resets to allow NIC to operate */
1505 iwl_write32(priv, CSR_RESET, 0);
1506}
1507
1508
b08dfd04
JB
1509static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1510static int iwl_mac_setup_register(struct iwl_priv *priv);
1511
1512static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1513{
1514 const char *name_pre = priv->cfg->fw_name_pre;
1515
1516 if (first)
1517 priv->fw_index = priv->cfg->ucode_api_max;
1518 else
1519 priv->fw_index--;
1520
1521 if (priv->fw_index < priv->cfg->ucode_api_min) {
1522 IWL_ERR(priv, "no suitable firmware found!\n");
1523 return -ENOENT;
1524 }
1525
1526 sprintf(priv->firmware_name, "%s%d%s",
1527 name_pre, priv->fw_index, ".ucode");
1528
1529 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1530 priv->firmware_name);
1531
1532 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1533 &priv->pci_dev->dev, GFP_KERNEL, priv,
1534 iwl_ucode_callback);
1535}
1536
b481de9c 1537/**
b08dfd04 1538 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1539 *
b08dfd04
JB
1540 * If loaded successfully, copies the firmware into buffers
1541 * for the card to fetch (via DMA).
b481de9c 1542 */
b08dfd04 1543static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1544{
b08dfd04 1545 struct iwl_priv *priv = context;
cc0f555d 1546 struct iwl_ucode_header *ucode;
a0987a8d
RC
1547 const unsigned int api_max = priv->cfg->ucode_api_max;
1548 const unsigned int api_min = priv->cfg->ucode_api_min;
b481de9c
ZY
1549 u8 *src;
1550 size_t len;
cc0f555d
JS
1551 u32 api_ver, build;
1552 u32 inst_size, data_size, init_size, init_data_size, boot_size;
b08dfd04 1553 int err;
abdc2d62 1554 u16 eeprom_ver;
b481de9c 1555
b08dfd04
JB
1556 if (!ucode_raw) {
1557 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
1558 priv->firmware_name);
1559 goto try_again;
b481de9c
ZY
1560 }
1561
b08dfd04
JB
1562 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1563 priv->firmware_name, ucode_raw->size);
b481de9c 1564
cc0f555d
JS
1565 /* Make sure that we got at least the v1 header! */
1566 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1567 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 1568 goto try_again;
b481de9c
ZY
1569 }
1570
1571 /* Data from ucode file: header followed by uCode images */
cc0f555d 1572 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1573
c02b3acd 1574 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1575 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1576 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1577 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1578 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1579 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1580 init_data_size =
1581 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1582 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1583 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1584
a0987a8d
RC
1585 /* api_ver should match the api version forming part of the
1586 * firmware filename ... but we don't check for that and only rely
877d0310 1587 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1588
1589 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1590 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1591 "Driver supports v%u, firmware is v%u.\n",
1592 api_max, api_ver);
b08dfd04 1593 goto try_again;
a0987a8d 1594 }
b08dfd04 1595
a0987a8d 1596 if (api_ver != api_max)
978785a3 1597 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1598 "got v%u. New firmware can be obtained "
1599 "from http://www.intellinuxwireless.org.\n",
1600 api_max, api_ver);
1601
978785a3
TW
1602 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1603 IWL_UCODE_MAJOR(priv->ucode_ver),
1604 IWL_UCODE_MINOR(priv->ucode_ver),
1605 IWL_UCODE_API(priv->ucode_ver),
1606 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1607
5ebeb5a6
RC
1608 snprintf(priv->hw->wiphy->fw_version,
1609 sizeof(priv->hw->wiphy->fw_version),
1610 "%u.%u.%u.%u",
1611 IWL_UCODE_MAJOR(priv->ucode_ver),
1612 IWL_UCODE_MINOR(priv->ucode_ver),
1613 IWL_UCODE_API(priv->ucode_ver),
1614 IWL_UCODE_SERIAL(priv->ucode_ver));
1615
cc0f555d
JS
1616 if (build)
1617 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1618
abdc2d62
JS
1619 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1620 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1621 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1622 ? "OTP" : "EEPROM", eeprom_ver);
1623
e1623446 1624 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1625 priv->ucode_ver);
e1623446 1626 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1627 inst_size);
e1623446 1628 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1629 data_size);
e1623446 1630 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1631 init_size);
e1623446 1632 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1633 init_data_size);
e1623446 1634 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1635 boot_size);
1636
b08dfd04
JB
1637 /*
1638 * For any of the failures below (before allocating pci memory)
1639 * we will try to load a version with a smaller API -- maybe the
1640 * user just got a corrupted version of the latest API.
1641 */
1642
b481de9c 1643 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1644 if (ucode_raw->size !=
1645 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1646 inst_size + data_size + init_size +
1647 init_data_size + boot_size) {
1648
cc0f555d
JS
1649 IWL_DEBUG_INFO(priv,
1650 "uCode file size %d does not match expected size\n",
1651 (int)ucode_raw->size);
b08dfd04 1652 goto try_again;
b481de9c
ZY
1653 }
1654
1655 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1656 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1657 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1 1658 inst_size);
b08dfd04 1659 goto try_again;
b481de9c
ZY
1660 }
1661
099b40b7 1662 if (data_size > priv->hw_params.max_data_size) {
e1623446 1663 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1 1664 data_size);
b08dfd04 1665 goto try_again;
b481de9c 1666 }
099b40b7 1667 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1668 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1669 init_size);
b08dfd04 1670 goto try_again;
b481de9c 1671 }
099b40b7 1672 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1673 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1 1674 init_data_size);
b08dfd04 1675 goto try_again;
b481de9c 1676 }
099b40b7 1677 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1678 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1679 boot_size);
b08dfd04 1680 goto try_again;
b481de9c
ZY
1681 }
1682
1683 /* Allocate ucode buffers for card's bus-master loading ... */
1684
1685 /* Runtime instructions and 2 copies of data:
1686 * 1) unmodified from disk
1687 * 2) backup cache for save/restore during power-downs */
1688 priv->ucode_code.len = inst_size;
98c92211 1689 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1690
1691 priv->ucode_data.len = data_size;
98c92211 1692 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1693
1694 priv->ucode_data_backup.len = data_size;
98c92211 1695 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1696
1f304e4e
ZY
1697 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1698 !priv->ucode_data_backup.v_addr)
1699 goto err_pci_alloc;
1700
b481de9c 1701 /* Initialization instructions and data */
90e759d1
TW
1702 if (init_size && init_data_size) {
1703 priv->ucode_init.len = init_size;
98c92211 1704 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1705
1706 priv->ucode_init_data.len = init_data_size;
98c92211 1707 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1708
1709 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1710 goto err_pci_alloc;
1711 }
b481de9c
ZY
1712
1713 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1714 if (boot_size) {
1715 priv->ucode_boot.len = boot_size;
98c92211 1716 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1717
90e759d1
TW
1718 if (!priv->ucode_boot.v_addr)
1719 goto err_pci_alloc;
1720 }
b481de9c
ZY
1721
1722 /* Copy images into buffers for card's bus-master reads ... */
1723
1724 /* Runtime instructions (first block of data in file) */
cc0f555d 1725 len = inst_size;
e1623446 1726 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1727 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1728 src += len;
1729
e1623446 1730 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1731 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1732
1733 /* Runtime data (2nd block)
5b9f8cd3 1734 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1735 len = data_size;
e1623446 1736 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1737 memcpy(priv->ucode_data.v_addr, src, len);
1738 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1739 src += len;
b481de9c
ZY
1740
1741 /* Initialization instructions (3rd block) */
1742 if (init_size) {
cc0f555d 1743 len = init_size;
e1623446 1744 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1745 len);
b481de9c 1746 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1747 src += len;
b481de9c
ZY
1748 }
1749
1750 /* Initialization data (4th block) */
1751 if (init_data_size) {
cc0f555d 1752 len = init_data_size;
e1623446 1753 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1754 len);
b481de9c 1755 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1756 src += len;
b481de9c
ZY
1757 }
1758
1759 /* Bootstrap instructions (5th block) */
cc0f555d 1760 len = boot_size;
e1623446 1761 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1762 memcpy(priv->ucode_boot.v_addr, src, len);
1763
b08dfd04
JB
1764 /**************************************************
1765 * This is still part of probe() in a sense...
1766 *
1767 * 9. Setup and register with mac80211 and debugfs
1768 **************************************************/
1769 err = iwl_mac_setup_register(priv);
1770 if (err)
1771 goto out_unbind;
1772
1773 err = iwl_dbgfs_register(priv, DRV_NAME);
1774 if (err)
1775 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1776
b481de9c
ZY
1777 /* We have our copies now, allow OS release its copies */
1778 release_firmware(ucode_raw);
b08dfd04
JB
1779 return;
1780
1781 try_again:
1782 /* try next, if any */
1783 if (iwl_request_firmware(priv, false))
1784 goto out_unbind;
1785 release_firmware(ucode_raw);
1786 return;
b481de9c
ZY
1787
1788 err_pci_alloc:
15b1687c 1789 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 1790 iwl_dealloc_ucode_pci(priv);
b08dfd04
JB
1791 out_unbind:
1792 device_release_driver(&priv->pci_dev->dev);
b481de9c 1793 release_firmware(ucode_raw);
b481de9c
ZY
1794}
1795
b7a79404
RC
1796static const char *desc_lookup_text[] = {
1797 "OK",
1798 "FAIL",
1799 "BAD_PARAM",
1800 "BAD_CHECKSUM",
1801 "NMI_INTERRUPT_WDG",
1802 "SYSASSERT",
1803 "FATAL_ERROR",
1804 "BAD_COMMAND",
1805 "HW_ERROR_TUNE_LOCK",
1806 "HW_ERROR_TEMPERATURE",
1807 "ILLEGAL_CHAN_FREQ",
1808 "VCC_NOT_STABLE",
1809 "FH_ERROR",
1810 "NMI_INTERRUPT_HOST",
1811 "NMI_INTERRUPT_ACTION_PT",
1812 "NMI_INTERRUPT_UNKNOWN",
1813 "UCODE_VERSION_MISMATCH",
1814 "HW_ERROR_ABS_LOCK",
1815 "HW_ERROR_CAL_LOCK_FAIL",
1816 "NMI_INTERRUPT_INST_ACTION_PT",
1817 "NMI_INTERRUPT_DATA_ACTION_PT",
1818 "NMI_TRM_HW_ER",
1819 "NMI_INTERRUPT_TRM",
1820 "NMI_INTERRUPT_BREAK_POINT"
1821 "DEBUG_0",
1822 "DEBUG_1",
1823 "DEBUG_2",
1824 "DEBUG_3",
a7fce6ee 1825 "ADVANCED SYSASSERT"
b7a79404
RC
1826};
1827
1828static const char *desc_lookup(int i)
1829{
1830 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1831
1832 if (i < 0 || i > max)
1833 i = max;
1834
1835 return desc_lookup_text[i];
1836}
1837
1838#define ERROR_START_OFFSET (1 * sizeof(u32))
1839#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1840
1841void iwl_dump_nic_error_log(struct iwl_priv *priv)
1842{
1843 u32 data2, line;
1844 u32 desc, time, count, base, data1;
1845 u32 blink1, blink2, ilink1, ilink2;
1846
1847 if (priv->ucode_type == UCODE_INIT)
1848 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1849 else
1850 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1851
1852 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1853 IWL_ERR(priv,
1854 "Not valid error log pointer 0x%08X for %s uCode\n",
1855 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC
1856 return;
1857 }
1858
1859 count = iwl_read_targ_mem(priv, base);
1860
1861 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1862 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1863 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1864 priv->status, count);
1865 }
1866
1867 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1868 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1869 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1870 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1871 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1872 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1873 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1874 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1875 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1876
be1a71a1
JB
1877 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1878 blink1, blink2, ilink1, ilink2);
1879
b7a79404
RC
1880 IWL_ERR(priv, "Desc Time "
1881 "data1 data2 line\n");
1882 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1883 desc_lookup(desc), desc, time, data1, data2, line);
1884 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1885 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1886 ilink1, ilink2);
1887
1888}
1889
1890#define EVENT_START_OFFSET (4 * sizeof(u32))
1891
1892/**
1893 * iwl_print_event_log - Dump error event log to syslog
1894 *
1895 */
b03d7d0f
WYG
1896static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1897 u32 num_events, u32 mode,
1898 int pos, char **buf, size_t bufsz)
b7a79404
RC
1899{
1900 u32 i;
1901 u32 base; /* SRAM byte address of event log header */
1902 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1903 u32 ptr; /* SRAM byte address of log data */
1904 u32 ev, time, data; /* event log data */
e5854471 1905 unsigned long reg_flags;
b7a79404
RC
1906
1907 if (num_events == 0)
b03d7d0f 1908 return pos;
b7a79404
RC
1909 if (priv->ucode_type == UCODE_INIT)
1910 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1911 else
1912 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1913
1914 if (mode == 0)
1915 event_size = 2 * sizeof(u32);
1916 else
1917 event_size = 3 * sizeof(u32);
1918
1919 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1920
e5854471
BC
1921 /* Make sure device is powered up for SRAM reads */
1922 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1923 iwl_grab_nic_access(priv);
1924
1925 /* Set starting address; reads will auto-increment */
1926 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1927 rmb();
1928
b7a79404
RC
1929 /* "time" is actually "data" for mode 0 (no timestamp).
1930 * place event id # at far right for easier visual parsing. */
1931 for (i = 0; i < num_events; i++) {
e5854471
BC
1932 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1933 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1934 if (mode == 0) {
1935 /* data, ev */
b03d7d0f
WYG
1936 if (bufsz) {
1937 pos += scnprintf(*buf + pos, bufsz - pos,
1938 "EVT_LOG:0x%08x:%04u\n",
1939 time, ev);
1940 } else {
1941 trace_iwlwifi_dev_ucode_event(priv, 0,
1942 time, ev);
1943 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1944 time, ev);
1945 }
b7a79404 1946 } else {
e5854471 1947 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG
1948 if (bufsz) {
1949 pos += scnprintf(*buf + pos, bufsz - pos,
1950 "EVT_LOGT:%010u:0x%08x:%04u\n",
1951 time, data, ev);
1952 } else {
1953 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 1954 time, data, ev);
b03d7d0f
WYG
1955 trace_iwlwifi_dev_ucode_event(priv, time,
1956 data, ev);
1957 }
b7a79404
RC
1958 }
1959 }
e5854471
BC
1960
1961 /* Allow device to power down */
1962 iwl_release_nic_access(priv);
1963 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1964 return pos;
b7a79404
RC
1965}
1966
c341ddb2
WYG
1967/**
1968 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1969 */
b03d7d0f
WYG
1970static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1971 u32 num_wraps, u32 next_entry,
1972 u32 size, u32 mode,
1973 int pos, char **buf, size_t bufsz)
c341ddb2
WYG
1974{
1975 /*
1976 * display the newest DEFAULT_LOG_ENTRIES entries
1977 * i.e the entries just before the next ont that uCode would fill.
1978 */
1979 if (num_wraps) {
1980 if (next_entry < size) {
b03d7d0f
WYG
1981 pos = iwl_print_event_log(priv,
1982 capacity - (size - next_entry),
1983 size - next_entry, mode,
1984 pos, buf, bufsz);
1985 pos = iwl_print_event_log(priv, 0,
1986 next_entry, mode,
1987 pos, buf, bufsz);
c341ddb2 1988 } else
b03d7d0f
WYG
1989 pos = iwl_print_event_log(priv, next_entry - size,
1990 size, mode, pos, buf, bufsz);
c341ddb2 1991 } else {
b03d7d0f
WYG
1992 if (next_entry < size) {
1993 pos = iwl_print_event_log(priv, 0, next_entry,
1994 mode, pos, buf, bufsz);
1995 } else {
1996 pos = iwl_print_event_log(priv, next_entry - size,
1997 size, mode, pos, buf, bufsz);
1998 }
c341ddb2 1999 }
b03d7d0f 2000 return pos;
c341ddb2
WYG
2001}
2002
c341ddb2
WYG
2003#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2004
b03d7d0f
WYG
2005int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2006 char **buf, bool display)
b7a79404
RC
2007{
2008 u32 base; /* SRAM byte address of event log header */
2009 u32 capacity; /* event log capacity in # entries */
2010 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2011 u32 num_wraps; /* # times uCode wrapped to top of log */
2012 u32 next_entry; /* index of next entry to be written by uCode */
2013 u32 size; /* # entries that we'll print */
b03d7d0f
WYG
2014 int pos = 0;
2015 size_t bufsz = 0;
b7a79404
RC
2016
2017 if (priv->ucode_type == UCODE_INIT)
2018 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2019 else
2020 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2021
2022 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
2023 IWL_ERR(priv,
2024 "Invalid event log pointer 0x%08X for %s uCode\n",
2025 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2026 return -EINVAL;
b7a79404
RC
2027 }
2028
2029 /* event log header */
2030 capacity = iwl_read_targ_mem(priv, base);
2031 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2032 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2033 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2034
678b385d 2035 if (capacity > priv->cfg->max_event_log_size) {
84c40692 2036 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
678b385d
WYG
2037 capacity, priv->cfg->max_event_log_size);
2038 capacity = priv->cfg->max_event_log_size;
84c40692
BC
2039 }
2040
678b385d 2041 if (next_entry > priv->cfg->max_event_log_size) {
84c40692 2042 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
678b385d
WYG
2043 next_entry, priv->cfg->max_event_log_size);
2044 next_entry = priv->cfg->max_event_log_size;
84c40692
BC
2045 }
2046
b7a79404
RC
2047 size = num_wraps ? capacity : next_entry;
2048
2049 /* bail out if nothing in log */
2050 if (size == 0) {
2051 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2052 return pos;
b7a79404
RC
2053 }
2054
c341ddb2 2055#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2056 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG
2057 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2058 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2059#else
2060 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2061 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2062#endif
2063 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2064 size);
b7a79404 2065
c341ddb2 2066#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG
2067 if (display) {
2068 if (full_log)
2069 bufsz = capacity * 48;
2070 else
2071 bufsz = size * 48;
2072 *buf = kmalloc(bufsz, GFP_KERNEL);
2073 if (!*buf)
937c397e 2074 return -ENOMEM;
b03d7d0f 2075 }
c341ddb2
WYG
2076 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2077 /*
2078 * if uCode has wrapped back to top of log,
2079 * start at the oldest entry,
2080 * i.e the next one that uCode would fill.
2081 */
2082 if (num_wraps)
b03d7d0f
WYG
2083 pos = iwl_print_event_log(priv, next_entry,
2084 capacity - next_entry, mode,
2085 pos, buf, bufsz);
c341ddb2 2086 /* (then/else) start at top of log */
b03d7d0f
WYG
2087 pos = iwl_print_event_log(priv, 0,
2088 next_entry, mode, pos, buf, bufsz);
c341ddb2 2089 } else
b03d7d0f
WYG
2090 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2091 next_entry, size, mode,
2092 pos, buf, bufsz);
c341ddb2 2093#else
b03d7d0f
WYG
2094 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2095 next_entry, size, mode,
2096 pos, buf, bufsz);
b7a79404 2097#endif
b03d7d0f 2098 return pos;
c341ddb2 2099}
b7a79404 2100
b481de9c 2101/**
4a4a9e81 2102 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2103 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2104 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2105 */
4a4a9e81 2106static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2107{
57aab75a 2108 int ret = 0;
b481de9c 2109
e1623446 2110 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2111
2112 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2113 /* We had an error bringing up the hardware, so take it
2114 * all the way back down so we can try again */
e1623446 2115 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2116 goto restart;
2117 }
2118
2119 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2120 * This is a paranoid check, because we would not have gotten the
2121 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2122 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
2123 /* Runtime instruction load was bad;
2124 * take it all the way back down so we can try again */
e1623446 2125 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2126 goto restart;
2127 }
2128
57aab75a
TW
2129 ret = priv->cfg->ops->lib->alive_notify(priv);
2130 if (ret) {
39aadf8c
WT
2131 IWL_WARN(priv,
2132 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
2133 goto restart;
2134 }
2135
5b9f8cd3 2136 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
2137 set_bit(STATUS_ALIVE, &priv->status);
2138
b74e31a9
WYG
2139 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2140 /* Enable timer to monitor the driver queues */
2141 mod_timer(&priv->monitor_recover,
2142 jiffies +
2143 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2144 }
2145
fee1247a 2146 if (iwl_is_rfkill(priv))
b481de9c
ZY
2147 return;
2148
36d6825b 2149 ieee80211_wake_queues(priv->hw);
b481de9c 2150
470ab2dd 2151 priv->active_rate = IWL_RATES_MASK;
b481de9c 2152
2f748dec
WYG
2153 /* Configure Tx antenna selection based on H/W config */
2154 if (priv->cfg->ops->hcmd->set_tx_ant)
2155 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2156
3109ece1 2157 if (iwl_is_associated(priv)) {
c1adf9fb
GG
2158 struct iwl_rxon_cmd *active_rxon =
2159 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
2160 /* apply any changes in staging */
2161 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2162 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2163 } else {
2164 /* Initialize our rx_config data */
5b9f8cd3 2165 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
2166
2167 if (priv->cfg->ops->hcmd->set_rxon_chain)
2168 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2169
b481de9c
ZY
2170 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2171 }
2172
9fbab516 2173 /* Configure Bluetooth device coexistence support */
5b9f8cd3 2174 iwl_send_bt_config(priv);
b481de9c 2175
4a4a9e81
TW
2176 iwl_reset_run_time_calib(priv);
2177
b481de9c 2178 /* Configure the adapter for unassociated operation */
e0158e61 2179 iwlcore_commit_rxon(priv);
b481de9c
ZY
2180
2181 /* At this point, the NIC is initialized and operational */
47f4a587 2182 iwl_rf_kill_ct_config(priv);
5a66926a 2183
e932a609 2184 iwl_leds_init(priv);
fe00b5a5 2185
e1623446 2186 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2187 set_bit(STATUS_READY, &priv->status);
5a66926a 2188 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2189
e312c24c 2190 iwl_power_update_mode(priv, true);
7e246191
RC
2191 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2192
c46fbefa 2193
b481de9c
ZY
2194 return;
2195
2196 restart:
2197 queue_work(priv->workqueue, &priv->restart);
2198}
2199
4e39317d 2200static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2201
5b9f8cd3 2202static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2203{
2204 unsigned long flags;
2205 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2206
e1623446 2207 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2208
b481de9c
ZY
2209 if (!exit_pending)
2210 set_bit(STATUS_EXIT_PENDING, &priv->status);
2211
7e246191 2212 iwl_clear_ucode_stations(priv, true);
b481de9c
ZY
2213
2214 /* Unblock any waiting calls */
2215 wake_up_interruptible_all(&priv->wait_command_queue);
2216
b481de9c
ZY
2217 /* Wipe out the EXIT_PENDING status bit if we are not actually
2218 * exiting the module */
2219 if (!exit_pending)
2220 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2221
2222 /* stop and reset the on-board processor */
3395f6e9 2223 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2224
2225 /* tell the device to stop sending interrupts */
0359facc 2226 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2227 iwl_disable_interrupts(priv);
0359facc
MA
2228 spin_unlock_irqrestore(&priv->lock, flags);
2229 iwl_synchronize_irq(priv);
b481de9c
ZY
2230
2231 if (priv->mac80211_registered)
2232 ieee80211_stop_queues(priv->hw);
2233
5b9f8cd3 2234 /* If we have not previously called iwl_init() then
a60e77e5 2235 * clear all bits but the RF Kill bit and return */
fee1247a 2236 if (!iwl_is_init(priv)) {
b481de9c
ZY
2237 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2238 STATUS_RF_KILL_HW |
9788864e
RC
2239 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2240 STATUS_GEO_CONFIGURED |
052ec3f1
MA
2241 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2242 STATUS_EXIT_PENDING;
b481de9c
ZY
2243 goto exit;
2244 }
2245
6da3a13e 2246 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2247 * bit and continue taking the NIC down. */
b481de9c
ZY
2248 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2249 STATUS_RF_KILL_HW |
9788864e
RC
2250 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2251 STATUS_GEO_CONFIGURED |
b481de9c 2252 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
2253 STATUS_FW_ERROR |
2254 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2255 STATUS_EXIT_PENDING;
b481de9c 2256
ef850d7c
MA
2257 /* device going down, Stop using ICT table */
2258 iwl_disable_ict(priv);
b481de9c 2259
74bcdb33 2260 iwlagn_txq_ctx_stop(priv);
54b81550 2261 iwlagn_rxq_stop(priv);
b481de9c 2262
309e731a
BC
2263 /* Power-down device's busmaster DMA clocks */
2264 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2265 udelay(5);
2266
309e731a
BC
2267 /* Make sure (redundant) we've released our request to stay awake */
2268 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2269
4d2ccdb9
BC
2270 /* Stop the device, and put it in low power state */
2271 priv->cfg->ops->lib->apm_ops.stop(priv);
2272
b481de9c 2273 exit:
885ba202 2274 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2275
2276 if (priv->ibss_beacon)
2277 dev_kfree_skb(priv->ibss_beacon);
2278 priv->ibss_beacon = NULL;
2279
2280 /* clear out any free frames */
fcab423d 2281 iwl_clear_free_frames(priv);
b481de9c
ZY
2282}
2283
5b9f8cd3 2284static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2285{
2286 mutex_lock(&priv->mutex);
5b9f8cd3 2287 __iwl_down(priv);
b481de9c 2288 mutex_unlock(&priv->mutex);
b24d22b1 2289
4e39317d 2290 iwl_cancel_deferred_work(priv);
b481de9c
ZY
2291}
2292
086ed117
MA
2293#define HW_READY_TIMEOUT (50)
2294
2295static int iwl_set_hw_ready(struct iwl_priv *priv)
2296{
2297 int ret = 0;
2298
2299 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2300 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2301
2302 /* See if we got it */
2303 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2304 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2305 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2306 HW_READY_TIMEOUT);
2307 if (ret != -ETIMEDOUT)
2308 priv->hw_ready = true;
2309 else
2310 priv->hw_ready = false;
2311
2312 IWL_DEBUG_INFO(priv, "hardware %s\n",
2313 (priv->hw_ready == 1) ? "ready" : "not ready");
2314 return ret;
2315}
2316
2317static int iwl_prepare_card_hw(struct iwl_priv *priv)
2318{
2319 int ret = 0;
2320
91dd6c27 2321 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2322
3354a0f6
MA
2323 ret = iwl_set_hw_ready(priv);
2324 if (priv->hw_ready)
2325 return ret;
2326
2327 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
2328 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2329 CSR_HW_IF_CONFIG_REG_PREPARE);
2330
2331 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2332 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2333 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2334
3354a0f6 2335 /* HW should be ready by now, check again. */
086ed117
MA
2336 if (ret != -ETIMEDOUT)
2337 iwl_set_hw_ready(priv);
2338
2339 return ret;
2340}
2341
b481de9c
ZY
2342#define MAX_HW_RESTARTS 5
2343
5b9f8cd3 2344static int __iwl_up(struct iwl_priv *priv)
b481de9c 2345{
57aab75a
TW
2346 int i;
2347 int ret;
b481de9c
ZY
2348
2349 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2350 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2351 return -EIO;
2352 }
2353
e903fbd4 2354 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2355 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
2356 return -EIO;
2357 }
2358
086ed117
MA
2359 iwl_prepare_card_hw(priv);
2360
2361 if (!priv->hw_ready) {
2362 IWL_WARN(priv, "Exit HW not ready\n");
2363 return -EIO;
2364 }
2365
e655b9f0 2366 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2367 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2368 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2369 else
e655b9f0 2370 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2371
c1842d61 2372 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
2373 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2374
5b9f8cd3 2375 iwl_enable_interrupts(priv);
a60e77e5 2376 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2377 return 0;
b481de9c
ZY
2378 }
2379
3395f6e9 2380 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2381
74bcdb33 2382 ret = iwlagn_hw_nic_init(priv);
57aab75a 2383 if (ret) {
15b1687c 2384 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2385 return ret;
b481de9c
ZY
2386 }
2387
2388 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2389 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2390 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2391 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2392
2393 /* clear (again), then enable host interrupts */
3395f6e9 2394 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2395 iwl_enable_interrupts(priv);
b481de9c
ZY
2396
2397 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2398 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2399 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2400
2401 /* Copy original ucode data image from disk into backup cache.
2402 * This will be used to initialize the on-board processor's
2403 * data SRAM for a clean start when the runtime program first loads. */
2404 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2405 priv->ucode_data.len);
b481de9c 2406
b481de9c
ZY
2407 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2408
b481de9c
ZY
2409 /* load bootstrap state machine,
2410 * load bootstrap program into processor's memory,
2411 * prepare to load the "initialize" uCode */
57aab75a 2412 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2413
57aab75a 2414 if (ret) {
15b1687c
WT
2415 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2416 ret);
b481de9c
ZY
2417 continue;
2418 }
2419
2420 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2421 iwl_nic_start(priv);
b481de9c 2422
e1623446 2423 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2424
2425 return 0;
2426 }
2427
2428 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2429 __iwl_down(priv);
64e72c3e 2430 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2431
2432 /* tried to restart and config the device for as long as our
2433 * patience could withstand */
15b1687c 2434 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2435 return -EIO;
2436}
2437
2438
2439/*****************************************************************************
2440 *
2441 * Workqueue callbacks
2442 *
2443 *****************************************************************************/
2444
4a4a9e81 2445static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2446{
c79dd5b5
TW
2447 struct iwl_priv *priv =
2448 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2449
2450 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2451 return;
2452
2453 mutex_lock(&priv->mutex);
f3ccc08c 2454 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2455 mutex_unlock(&priv->mutex);
2456}
2457
4a4a9e81 2458static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2459{
c79dd5b5
TW
2460 struct iwl_priv *priv =
2461 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2462
2463 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2464 return;
2465
258c44a0
MA
2466 /* enable dram interrupt */
2467 iwl_reset_ict(priv);
2468
b481de9c 2469 mutex_lock(&priv->mutex);
4a4a9e81 2470 iwl_alive_start(priv);
b481de9c
ZY
2471 mutex_unlock(&priv->mutex);
2472}
2473
16e727e8
EG
2474static void iwl_bg_run_time_calib_work(struct work_struct *work)
2475{
2476 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2477 run_time_calib_work);
2478
2479 mutex_lock(&priv->mutex);
2480
2481 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2482 test_bit(STATUS_SCANNING, &priv->status)) {
2483 mutex_unlock(&priv->mutex);
2484 return;
2485 }
2486
2487 if (priv->start_calib) {
2488 iwl_chain_noise_calibration(priv, &priv->statistics);
2489
2490 iwl_sensitivity_calibration(priv, &priv->statistics);
2491 }
2492
2493 mutex_unlock(&priv->mutex);
2494 return;
2495}
2496
5b9f8cd3 2497static void iwl_bg_restart(struct work_struct *data)
b481de9c 2498{
c79dd5b5 2499 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2500
2501 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2502 return;
2503
19cc1087
JB
2504 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2505 mutex_lock(&priv->mutex);
2506 priv->vif = NULL;
2507 priv->is_open = 0;
2508 mutex_unlock(&priv->mutex);
2509 iwl_down(priv);
2510 ieee80211_restart_hw(priv->hw);
2511 } else {
2512 iwl_down(priv);
80676518
JB
2513
2514 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2515 return;
2516
2517 mutex_lock(&priv->mutex);
2518 __iwl_up(priv);
2519 mutex_unlock(&priv->mutex);
19cc1087 2520 }
b481de9c
ZY
2521}
2522
5b9f8cd3 2523static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2524{
c79dd5b5
TW
2525 struct iwl_priv *priv =
2526 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2527
2528 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2529 return;
2530
2531 mutex_lock(&priv->mutex);
54b81550 2532 iwlagn_rx_replenish(priv);
b481de9c
ZY
2533 mutex_unlock(&priv->mutex);
2534}
2535
7878a5a4
MA
2536#define IWL_DELAY_NEXT_SCAN (HZ*2)
2537
5bbe233b 2538void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2539{
b481de9c 2540 struct ieee80211_conf *conf = NULL;
857485c0 2541 int ret = 0;
b481de9c 2542
05c914fe 2543 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2544 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2545 return;
2546 }
2547
b481de9c
ZY
2548 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2549 return;
2550
b481de9c 2551
508e32e1 2552 if (!priv->vif || !priv->is_open)
948c171c 2553 return;
508e32e1 2554
2a421b91 2555 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2556
b481de9c
ZY
2557 conf = ieee80211_get_hw_conf(priv->hw);
2558
2559 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2560 iwlcore_commit_rxon(priv);
b481de9c 2561
3195c1f3 2562 iwl_setup_rxon_timing(priv);
857485c0 2563 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2564 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2565 if (ret)
39aadf8c 2566 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2567 "Attempting to continue.\n");
2568
2569 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2570
42eb7c64 2571 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2572
45823531
AK
2573 if (priv->cfg->ops->hcmd->set_rxon_chain)
2574 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2575
b481de9c
ZY
2576 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2577
e1623446 2578 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2579 priv->assoc_id, priv->beacon_int);
2580
2581 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2582 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2583 else
2584 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2585
2586 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2587 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2588 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2589 else
2590 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2591
05c914fe 2592 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2593 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2594
2595 }
2596
e0158e61 2597 iwlcore_commit_rxon(priv);
b481de9c 2598
fe6b23dd
RC
2599 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
2600 priv->assoc_id, priv->active_rxon.bssid_addr);
2601
b481de9c 2602 switch (priv->iw_mode) {
05c914fe 2603 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2604 break;
2605
05c914fe 2606 case NL80211_IFTYPE_ADHOC:
b481de9c 2607
c46fbefa
AK
2608 /* assume default assoc id */
2609 priv->assoc_id = 1;
b481de9c 2610
fe6b23dd 2611 iwl_add_local_station(priv, priv->bssid, true);
5b9f8cd3 2612 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2613
2614 break;
2615
2616 default:
15b1687c 2617 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2618 __func__, priv->iw_mode);
b481de9c
ZY
2619 break;
2620 }
2621
04816448
GE
2622 /* the chain noise calibration will enabled PM upon completion
2623 * If chain noise has already been run, then we need to enable
2624 * power management here */
2625 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2626 iwl_power_update_mode(priv, false);
c90a74ba
EG
2627
2628 /* Enable Rx differential gain and sensitivity calibrations */
2629 iwl_chain_noise_reset(priv);
2630 priv->start_calib = 1;
2631
508e32e1
RC
2632}
2633
b481de9c
ZY
2634/*****************************************************************************
2635 *
2636 * mac80211 entry point functions
2637 *
2638 *****************************************************************************/
2639
154b25ce 2640#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2641
f0b6e2e8
RC
2642/*
2643 * Not a mac80211 entry point function, but it fits in with all the
2644 * other mac80211 functions grouped here.
2645 */
158bea07 2646static int iwl_mac_setup_register(struct iwl_priv *priv)
f0b6e2e8
RC
2647{
2648 int ret;
2649 struct ieee80211_hw *hw = priv->hw;
2650 hw->rate_control_algorithm = "iwl-agn-rs";
2651
2652 /* Tell mac80211 our characteristics */
2653 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2654 IEEE80211_HW_NOISE_DBM |
2655 IEEE80211_HW_AMPDU_AGGREGATION |
2656 IEEE80211_HW_SPECTRUM_MGMT;
2657
2658 if (!priv->cfg->broken_powersave)
2659 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2660 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2661
ba37a3d0
JB
2662 if (priv->cfg->sku & IWL_SKU_N)
2663 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2664 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2665
8d9698b3 2666 hw->sta_data_size = sizeof(struct iwl_station_priv);
f0b6e2e8
RC
2667 hw->wiphy->interface_modes =
2668 BIT(NL80211_IFTYPE_STATION) |
2669 BIT(NL80211_IFTYPE_ADHOC);
2670
f6c8f152 2671 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 2672 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC
2673
2674 /*
2675 * For now, disable PS by default because it affects
2676 * RX performance significantly.
2677 */
5be83de5 2678 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 2679
1382c71c 2680 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8
RC
2681 /* we create the 802.11 header and a zero-length SSID element */
2682 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2683
2684 /* Default value; 4 EDCA QOS priorities */
2685 hw->queues = 4;
2686
2687 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2688
2689 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2690 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2691 &priv->bands[IEEE80211_BAND_2GHZ];
2692 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2693 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2694 &priv->bands[IEEE80211_BAND_5GHZ];
2695
2696 ret = ieee80211_register_hw(priv->hw);
2697 if (ret) {
2698 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2699 return ret;
2700 }
2701 priv->mac80211_registered = 1;
2702
2703 return 0;
2704}
2705
2706
5b9f8cd3 2707static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2708{
c79dd5b5 2709 struct iwl_priv *priv = hw->priv;
5a66926a 2710 int ret;
b481de9c 2711
e1623446 2712 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2713
2714 /* we should be verifying the device is ready to be opened */
2715 mutex_lock(&priv->mutex);
5b9f8cd3 2716 ret = __iwl_up(priv);
b481de9c 2717 mutex_unlock(&priv->mutex);
5a66926a 2718
e655b9f0 2719 if (ret)
6cd0b1cb 2720 return ret;
e655b9f0 2721
c1842d61
TW
2722 if (iwl_is_rfkill(priv))
2723 goto out;
2724
e1623446 2725 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2726
fe9b6b72 2727 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2728 * mac80211 will not be run successfully. */
154b25ce
EG
2729 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2730 test_bit(STATUS_READY, &priv->status),
2731 UCODE_READY_TIMEOUT);
2732 if (!ret) {
2733 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2734 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2735 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2736 return -ETIMEDOUT;
5a66926a 2737 }
fe9b6b72 2738 }
0a078ffa 2739
e932a609
JB
2740 iwl_led_start(priv);
2741
c1842d61 2742out:
0a078ffa 2743 priv->is_open = 1;
e1623446 2744 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2745 return 0;
2746}
2747
5b9f8cd3 2748static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2749{
c79dd5b5 2750 struct iwl_priv *priv = hw->priv;
b481de9c 2751
e1623446 2752 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2753
19cc1087 2754 if (!priv->is_open)
e655b9f0 2755 return;
e655b9f0 2756
b481de9c 2757 priv->is_open = 0;
5a66926a 2758
5bddf549 2759 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2760 /* stop mac, cancel any scan request and clear
2761 * RXON_FILTER_ASSOC_MSK BIT
2762 */
5a66926a 2763 mutex_lock(&priv->mutex);
2a421b91 2764 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2765 mutex_unlock(&priv->mutex);
fde3571f
MA
2766 }
2767
5b9f8cd3 2768 iwl_down(priv);
5a66926a
ZY
2769
2770 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2771
2772 /* enable interrupts again in order to receive rfkill changes */
2773 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2774 iwl_enable_interrupts(priv);
948c171c 2775
e1623446 2776 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2777}
2778
5b9f8cd3 2779static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2780{
c79dd5b5 2781 struct iwl_priv *priv = hw->priv;
b481de9c 2782
e1623446 2783 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2784
e1623446 2785 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2786 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2787
74bcdb33 2788 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY
2789 dev_kfree_skb_any(skb);
2790
e1623446 2791 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2792 return NETDEV_TX_OK;
b481de9c
ZY
2793}
2794
60690a6a 2795void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2796{
857485c0 2797 int ret = 0;
b481de9c 2798
d986bcd1 2799 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2800 return;
2801
2802 /* The following should be done only at AP bring up */
3195c1f3 2803 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2804
2805 /* RXON - unassoc (to set timing command) */
2806 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2807 iwlcore_commit_rxon(priv);
b481de9c
ZY
2808
2809 /* RXON Timing */
3195c1f3 2810 iwl_setup_rxon_timing(priv);
857485c0 2811 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2812 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2813 if (ret)
39aadf8c 2814 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2815 "Attempting to continue.\n");
2816
f513dfff
DH
2817 /* AP has all antennas */
2818 priv->chain_noise_data.active_chains =
2819 priv->hw_params.valid_rx_ant;
2820 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK
2821 if (priv->cfg->ops->hcmd->set_rxon_chain)
2822 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2823
2824 /* FIXME: what should be the assoc_id for AP? */
2825 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2826 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2827 priv->staging_rxon.flags |=
2828 RXON_FLG_SHORT_PREAMBLE_MSK;
2829 else
2830 priv->staging_rxon.flags &=
2831 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2832
2833 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2834 if (priv->assoc_capability &
2835 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2836 priv->staging_rxon.flags |=
2837 RXON_FLG_SHORT_SLOT_MSK;
2838 else
2839 priv->staging_rxon.flags &=
2840 ~RXON_FLG_SHORT_SLOT_MSK;
2841
05c914fe 2842 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2843 priv->staging_rxon.flags &=
2844 ~RXON_FLG_SHORT_SLOT_MSK;
2845 }
2846 /* restore RXON assoc */
2847 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2848 iwlcore_commit_rxon(priv);
9a9ca65f 2849 iwl_add_bcast_station(priv);
e1493deb 2850 }
5b9f8cd3 2851 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2852
2853 /* FIXME - we need to add code here to detect a totally new
2854 * configuration, reset the AP, unassoc, rxon timing, assoc,
2855 * clear sta table, add BCAST sta... */
2856}
2857
5b9f8cd3 2858static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB
2859 struct ieee80211_vif *vif,
2860 struct ieee80211_key_conf *keyconf,
2861 struct ieee80211_sta *sta,
2862 u32 iv32, u16 *phase1key)
ab885f8c 2863{
ab885f8c 2864
9f58671e 2865 struct iwl_priv *priv = hw->priv;
e1623446 2866 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2867
b3fbdcf4
JB
2868 iwl_update_tkip_key(priv, keyconf,
2869 sta ? sta->addr : iwl_bcast_addr,
2870 iv32, phase1key);
ab885f8c 2871
e1623446 2872 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2873}
2874
5b9f8cd3 2875static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2876 struct ieee80211_vif *vif,
2877 struct ieee80211_sta *sta,
b481de9c
ZY
2878 struct ieee80211_key_conf *key)
2879{
c79dd5b5 2880 struct iwl_priv *priv = hw->priv;
42986796
WT
2881 const u8 *addr;
2882 int ret;
2883 u8 sta_id;
2884 bool is_default_wep_key = false;
b481de9c 2885
e1623446 2886 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2887
90e8e424 2888 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2889 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2890 return -EOPNOTSUPP;
2891 }
42986796 2892 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2893 sta_id = iwl_find_station(priv, addr);
6974e363 2894 if (sta_id == IWL_INVALID_STATION) {
e1623446 2895 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2896 addr);
6974e363 2897 return -EINVAL;
b481de9c 2898
deb09c43 2899 }
b481de9c 2900
6974e363 2901 mutex_lock(&priv->mutex);
2a421b91 2902 iwl_scan_cancel_timeout(priv, 100);
6974e363 2903
a90178fa
JB
2904 /*
2905 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG
2906 * so far, we are in legacy wep mode (group key only), otherwise we are
2907 * in 1X mode.
a90178fa
JB
2908 * In legacy wep mode, we use another host command to the uCode.
2909 */
2910 if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
6974e363
EG
2911 if (cmd == SET_KEY)
2912 is_default_wep_key = !priv->key_mapping_key;
2913 else
ccc038ab
EG
2914 is_default_wep_key =
2915 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2916 }
052c4b9f 2917
b481de9c 2918 switch (cmd) {
deb09c43 2919 case SET_KEY:
6974e363
EG
2920 if (is_default_wep_key)
2921 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2922 else
7480513f 2923 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2924
e1623446 2925 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2926 break;
2927 case DISABLE_KEY:
6974e363
EG
2928 if (is_default_wep_key)
2929 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2930 else
3ec47732 2931 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2932
e1623446 2933 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2934 break;
2935 default:
deb09c43 2936 ret = -EINVAL;
b481de9c
ZY
2937 }
2938
72e15d71 2939 mutex_unlock(&priv->mutex);
e1623446 2940 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2941
deb09c43 2942 return ret;
b481de9c
ZY
2943}
2944
5b9f8cd3 2945static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2946 struct ieee80211_vif *vif,
d783b061 2947 enum ieee80211_ampdu_mlme_action action,
17741cdc 2948 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2949{
2950 struct iwl_priv *priv = hw->priv;
5c2207c6 2951 int ret;
d783b061 2952
e1623446 2953 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2954 sta->addr, tid);
d783b061
TW
2955
2956 if (!(priv->cfg->sku & IWL_SKU_N))
2957 return -EACCES;
2958
2959 switch (action) {
2960 case IEEE80211_AMPDU_RX_START:
e1623446 2961 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2962 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2963 case IEEE80211_AMPDU_RX_STOP:
e1623446 2964 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2965 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2966 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2967 return 0;
2968 else
2969 return ret;
d783b061 2970 case IEEE80211_AMPDU_TX_START:
e1623446 2971 IWL_DEBUG_HT(priv, "start Tx\n");
74bcdb33 2972 ret = iwlagn_tx_agg_start(priv, sta->addr, tid, ssn);
d5a0ffa3
WYG
2973 if (ret == 0) {
2974 priv->_agn.agg_tids_count++;
2975 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2976 priv->_agn.agg_tids_count);
2977 }
2978 return ret;
d783b061 2979 case IEEE80211_AMPDU_TX_STOP:
e1623446 2980 IWL_DEBUG_HT(priv, "stop Tx\n");
74bcdb33 2981 ret = iwlagn_tx_agg_stop(priv, sta->addr, tid);
d5a0ffa3
WYG
2982 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
2983 priv->_agn.agg_tids_count--;
2984 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2985 priv->_agn.agg_tids_count);
2986 }
5c2207c6
WYG
2987 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2988 return 0;
2989 else
2990 return ret;
f0527971
WYG
2991 case IEEE80211_AMPDU_TX_OPERATIONAL:
2992 /* do nothing */
2993 return -EOPNOTSUPP;
d783b061 2994 default:
e1623446 2995 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2996 return -EINVAL;
2997 break;
2998 }
2999 return 0;
3000}
9f58671e 3001
5b9f8cd3 3002static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
3003 struct ieee80211_low_level_stats *stats)
3004{
bf403db8
EK
3005 struct iwl_priv *priv = hw->priv;
3006
3007 priv = hw->priv;
e1623446
TW
3008 IWL_DEBUG_MAC80211(priv, "enter\n");
3009 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3010
3011 return 0;
3012}
3013
6ab10ff8
JB
3014static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3015 struct ieee80211_vif *vif,
3016 enum sta_notify_cmd cmd,
3017 struct ieee80211_sta *sta)
3018{
3019 struct iwl_priv *priv = hw->priv;
3020 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3021 int sta_id;
3022
6ab10ff8 3023 switch (cmd) {
6ab10ff8
JB
3024 case STA_NOTIFY_SLEEP:
3025 WARN_ON(!sta_priv->client);
3026 sta_priv->asleep = true;
3027 if (atomic_read(&sta_priv->pending_frames) > 0)
3028 ieee80211_sta_block_awake(hw, sta, true);
3029 break;
3030 case STA_NOTIFY_AWAKE:
3031 WARN_ON(!sta_priv->client);
49dcc819
DH
3032 if (!sta_priv->asleep)
3033 break;
6ab10ff8
JB
3034 sta_priv->asleep = false;
3035 sta_id = iwl_find_station(priv, sta->addr);
3036 if (sta_id != IWL_INVALID_STATION)
3037 iwl_sta_modify_ps_wake(priv, sta_id);
3038 break;
3039 default:
3040 break;
3041 }
3042}
3043
fe6b23dd
RC
3044static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3045 struct ieee80211_vif *vif,
3046 struct ieee80211_sta *sta)
3047{
3048 struct iwl_priv *priv = hw->priv;
3049 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3050 bool is_ap = priv->iw_mode == NL80211_IFTYPE_STATION;
3051 int ret;
3052 u8 sta_id;
3053
3054 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3055 sta->addr);
3056
3057 atomic_set(&sta_priv->pending_frames, 0);
3058 if (vif->type == NL80211_IFTYPE_AP)
3059 sta_priv->client = true;
3060
3061 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3062 &sta_id);
3063 if (ret) {
3064 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3065 sta->addr, ret);
3066 /* Should we return success if return code is EEXIST ? */
3067 return ret;
3068 }
3069
fe6b23dd 3070 /* Initialize rate scaling */
91dd6c27 3071 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC
3072 sta->addr);
3073 iwl_rs_rate_init(priv, sta, sta_id);
3074
3075 return ret;
3076}
3077
b481de9c
ZY
3078/*****************************************************************************
3079 *
3080 * sysfs attributes
3081 *
3082 *****************************************************************************/
3083
0a6857e7 3084#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3085
3086/*
3087 * The following adds a new attribute to the sysfs representation
c3a739fa 3088 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
3089 * used for controlling the debug level.
3090 *
3091 * See the level definitions in iwl for details.
a562a9dd 3092 *
3d816c77
RC
3093 * The debug_level being managed using sysfs below is a per device debug
3094 * level that is used instead of the global debug level if it (the per
3095 * device debug level) is set.
b481de9c 3096 */
8cf769c6
EK
3097static ssize_t show_debug_level(struct device *d,
3098 struct device_attribute *attr, char *buf)
b481de9c 3099{
3d816c77
RC
3100 struct iwl_priv *priv = dev_get_drvdata(d);
3101 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3102}
8cf769c6
EK
3103static ssize_t store_debug_level(struct device *d,
3104 struct device_attribute *attr,
b481de9c
ZY
3105 const char *buf, size_t count)
3106{
928841b1 3107 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3108 unsigned long val;
3109 int ret;
b481de9c 3110
9257746f
TW
3111 ret = strict_strtoul(buf, 0, &val);
3112 if (ret)
978785a3 3113 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3114 else {
3d816c77 3115 priv->debug_level = val;
20594eb0
WYG
3116 if (iwl_alloc_traffic_mem(priv))
3117 IWL_ERR(priv,
3118 "Not enough memory to generate traffic log\n");
3119 }
b481de9c
ZY
3120 return strnlen(buf, count);
3121}
3122
8cf769c6
EK
3123static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3124 show_debug_level, store_debug_level);
3125
b481de9c 3126
0a6857e7 3127#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3128
b481de9c
ZY
3129
3130static ssize_t show_temperature(struct device *d,
3131 struct device_attribute *attr, char *buf)
3132{
928841b1 3133 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3134
fee1247a 3135 if (!iwl_is_alive(priv))
b481de9c
ZY
3136 return -EAGAIN;
3137
91dbc5bd 3138 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
3139}
3140
3141static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3142
b481de9c
ZY
3143static ssize_t show_tx_power(struct device *d,
3144 struct device_attribute *attr, char *buf)
3145{
928841b1 3146 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
3147
3148 if (!iwl_is_ready_rf(priv))
3149 return sprintf(buf, "off\n");
3150 else
3151 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3152}
3153
3154static ssize_t store_tx_power(struct device *d,
3155 struct device_attribute *attr,
3156 const char *buf, size_t count)
3157{
928841b1 3158 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3159 unsigned long val;
3160 int ret;
b481de9c 3161
9257746f
TW
3162 ret = strict_strtoul(buf, 10, &val);
3163 if (ret)
978785a3 3164 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
3165 else {
3166 ret = iwl_set_tx_power(priv, val, false);
3167 if (ret)
3168 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
3169 ret);
3170 else
3171 ret = count;
3172 }
3173 return ret;
b481de9c
ZY
3174}
3175
3176static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3177
b481de9c
ZY
3178static ssize_t show_statistics(struct device *d,
3179 struct device_attribute *attr, char *buf)
3180{
c79dd5b5 3181 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 3182 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 3183 u32 len = 0, ofs = 0;
3ac7f146 3184 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
3185 int rc = 0;
3186
fee1247a 3187 if (!iwl_is_alive(priv))
b481de9c
ZY
3188 return -EAGAIN;
3189
3190 mutex_lock(&priv->mutex);
ef8d5529 3191 rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
b481de9c
ZY
3192 mutex_unlock(&priv->mutex);
3193
3194 if (rc) {
3195 len = sprintf(buf,
3196 "Error sending statistics request: 0x%08X\n", rc);
3197 return len;
3198 }
3199
3200 while (size && (PAGE_SIZE - len)) {
3201 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3202 PAGE_SIZE - len, 1);
3203 len = strlen(buf);
3204 if (PAGE_SIZE - len)
3205 buf[len++] = '\n';
3206
3207 ofs += 16;
3208 size -= min(size, 16U);
3209 }
3210
3211 return len;
3212}
3213
3214static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3215
01abfbb2
WYG
3216static ssize_t show_rts_ht_protection(struct device *d,
3217 struct device_attribute *attr, char *buf)
3218{
3219 struct iwl_priv *priv = dev_get_drvdata(d);
3220
3221 return sprintf(buf, "%s\n",
3222 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3223}
3224
3225static ssize_t store_rts_ht_protection(struct device *d,
3226 struct device_attribute *attr,
3227 const char *buf, size_t count)
3228{
3229 struct iwl_priv *priv = dev_get_drvdata(d);
3230 unsigned long val;
3231 int ret;
3232
3233 ret = strict_strtoul(buf, 10, &val);
3234 if (ret)
3235 IWL_INFO(priv, "Input is not in decimal form.\n");
3236 else {
3237 if (!iwl_is_associated(priv))
3238 priv->cfg->use_rts_for_ht = val ? true : false;
3239 else
3240 IWL_ERR(priv, "Sta associated with AP - "
3241 "Change protection mechanism is not allowed\n");
3242 ret = count;
3243 }
3244 return ret;
3245}
3246
3247static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3248 show_rts_ht_protection, store_rts_ht_protection);
3249
b481de9c 3250
b481de9c
ZY
3251/*****************************************************************************
3252 *
3253 * driver setup and teardown
3254 *
3255 *****************************************************************************/
3256
4e39317d 3257static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3258{
d21050c7 3259 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3260
3261 init_waitqueue_head(&priv->wait_command_queue);
3262
5b9f8cd3
EG
3263 INIT_WORK(&priv->restart, iwl_bg_restart);
3264 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3265 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3266 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
3267 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3268 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3269
2a421b91 3270 iwl_setup_scan_deferred_work(priv);
bb8c093b 3271
4e39317d
EG
3272 if (priv->cfg->ops->lib->setup_deferred_work)
3273 priv->cfg->ops->lib->setup_deferred_work(priv);
3274
3275 init_timer(&priv->statistics_periodic);
3276 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3277 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3278
a9e1cb6a
WYG
3279 init_timer(&priv->ucode_trace);
3280 priv->ucode_trace.data = (unsigned long)priv;
3281 priv->ucode_trace.function = iwl_bg_ucode_trace;
3282
b74e31a9
WYG
3283 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3284 init_timer(&priv->monitor_recover);
3285 priv->monitor_recover.data = (unsigned long)priv;
3286 priv->monitor_recover.function =
3287 priv->cfg->ops->lib->recover_from_tx_stall;
3288 }
3289
ef850d7c
MA
3290 if (!priv->cfg->use_isr_legacy)
3291 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3292 iwl_irq_tasklet, (unsigned long)priv);
3293 else
3294 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3295 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
3296}
3297
4e39317d 3298static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3299{
4e39317d
EG
3300 if (priv->cfg->ops->lib->cancel_deferred_work)
3301 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3302
3ae6a054 3303 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3304 cancel_delayed_work(&priv->scan_check);
3305 cancel_delayed_work(&priv->alive_start);
b481de9c 3306 cancel_work_sync(&priv->beacon_update);
4e39317d 3307 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3308 del_timer_sync(&priv->ucode_trace);
b74e31a9
WYG
3309 if (priv->cfg->ops->lib->recover_from_tx_stall)
3310 del_timer_sync(&priv->monitor_recover);
b481de9c
ZY
3311}
3312
89f186a8
RC
3313static void iwl_init_hw_rates(struct iwl_priv *priv,
3314 struct ieee80211_rate *rates)
3315{
3316 int i;
3317
3318 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3319 rates[i].bitrate = iwl_rates[i].ieee * 5;
3320 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3321 rates[i].hw_value_short = i;
3322 rates[i].flags = 0;
3323 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3324 /*
3325 * If CCK != 1M then set short preamble rate flag.
3326 */
3327 rates[i].flags |=
3328 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3329 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3330 }
3331 }
3332}
3333
3334static int iwl_init_drv(struct iwl_priv *priv)
3335{
3336 int ret;
3337
3338 priv->ibss_beacon = NULL;
3339
89f186a8
RC
3340 spin_lock_init(&priv->sta_lock);
3341 spin_lock_init(&priv->hcmd_lock);
3342
3343 INIT_LIST_HEAD(&priv->free_frames);
3344
3345 mutex_init(&priv->mutex);
d2dfe6df 3346 mutex_init(&priv->sync_cmd_mutex);
89f186a8 3347
89f186a8
RC
3348 priv->ieee_channels = NULL;
3349 priv->ieee_rates = NULL;
3350 priv->band = IEEE80211_BAND_2GHZ;
3351
3352 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3353 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3354 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 3355 priv->_agn.agg_tids_count = 0;
89f186a8 3356
8a472da4
WYG
3357 /* initialize force reset */
3358 priv->force_reset[IWL_RF_RESET].reset_duration =
3359 IWL_DELAY_NEXT_FORCE_RF_RESET;
3360 priv->force_reset[IWL_FW_RESET].reset_duration =
3361 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC
3362
3363 /* Choose which receivers/antennas to use */
3364 if (priv->cfg->ops->hcmd->set_rxon_chain)
3365 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3366
3367 iwl_init_scan_params(priv);
3368
89f186a8
RC
3369 /* Set the tx_power_user_lmt to the lowest power level
3370 * this value will get overwritten by channel max power avg
3371 * from eeprom */
b744cb79 3372 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC
3373
3374 ret = iwl_init_channel_map(priv);
3375 if (ret) {
3376 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3377 goto err;
3378 }
3379
3380 ret = iwlcore_init_geos(priv);
3381 if (ret) {
3382 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3383 goto err_free_channel_map;
3384 }
3385 iwl_init_hw_rates(priv, priv->ieee_rates);
3386
3387 return 0;
3388
3389err_free_channel_map:
3390 iwl_free_channel_map(priv);
3391err:
3392 return ret;
3393}
3394
3395static void iwl_uninit_drv(struct iwl_priv *priv)
3396{
3397 iwl_calib_free_results(priv);
3398 iwlcore_free_geos(priv);
3399 iwl_free_channel_map(priv);
3400 kfree(priv->scan);
3401}
3402
5b9f8cd3 3403static struct attribute *iwl_sysfs_entries[] = {
b481de9c 3404 &dev_attr_statistics.attr,
b481de9c 3405 &dev_attr_temperature.attr,
b481de9c 3406 &dev_attr_tx_power.attr,
01abfbb2 3407 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK
3408#ifdef CONFIG_IWLWIFI_DEBUG
3409 &dev_attr_debug_level.attr,
3410#endif
b481de9c
ZY
3411 NULL
3412};
3413
5b9f8cd3 3414static struct attribute_group iwl_attribute_group = {
b481de9c 3415 .name = NULL, /* put in device directory */
5b9f8cd3 3416 .attrs = iwl_sysfs_entries,
b481de9c
ZY
3417};
3418
5b9f8cd3
EG
3419static struct ieee80211_ops iwl_hw_ops = {
3420 .tx = iwl_mac_tx,
3421 .start = iwl_mac_start,
3422 .stop = iwl_mac_stop,
3423 .add_interface = iwl_mac_add_interface,
3424 .remove_interface = iwl_mac_remove_interface,
3425 .config = iwl_mac_config,
5b9f8cd3
EG
3426 .configure_filter = iwl_configure_filter,
3427 .set_key = iwl_mac_set_key,
3428 .update_tkip_key = iwl_mac_update_tkip_key,
3429 .get_stats = iwl_mac_get_stats,
5b9f8cd3
EG
3430 .conf_tx = iwl_mac_conf_tx,
3431 .reset_tsf = iwl_mac_reset_tsf,
3432 .bss_info_changed = iwl_bss_info_changed,
3433 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB
3434 .hw_scan = iwl_mac_hw_scan,
3435 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC
3436 .sta_add = iwlagn_mac_sta_add,
3437 .sta_remove = iwl_mac_sta_remove,
b481de9c
ZY
3438};
3439
5b9f8cd3 3440static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3441{
3442 int err = 0;
c79dd5b5 3443 struct iwl_priv *priv;
b481de9c 3444 struct ieee80211_hw *hw;
82b9a121 3445 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3446 unsigned long flags;
6cd0b1cb 3447 u16 pci_cmd;
b481de9c 3448
316c30d9
AK
3449 /************************
3450 * 1. Allocating HW data
3451 ************************/
3452
6440adb5
BC
3453 /* Disabling hardware scan means that mac80211 will perform scans
3454 * "the hard way", rather than using device's scan. */
1ea87396 3455 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3456 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
3457 dev_printk(KERN_DEBUG, &(pdev->dev),
3458 "Disabling hw_scan\n");
5b9f8cd3 3459 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3460 }
3461
5b9f8cd3 3462 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3463 if (!hw) {
b481de9c
ZY
3464 err = -ENOMEM;
3465 goto out;
3466 }
1d0a082d
AK
3467 priv = hw->priv;
3468 /* At this point both hw and priv are allocated. */
3469
b481de9c
ZY
3470 SET_IEEE80211_DEV(hw, &pdev->dev);
3471
e1623446 3472 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3473 priv->cfg = cfg;
b481de9c 3474 priv->pci_dev = pdev;
40cefda9 3475 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3476
0a6857e7 3477#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3478 atomic_set(&priv->restrict_refcnt, 0);
3479#endif
20594eb0
WYG
3480 if (iwl_alloc_traffic_mem(priv))
3481 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3482
316c30d9
AK
3483 /**************************
3484 * 2. Initializing PCI bus
3485 **************************/
3486 if (pci_enable_device(pdev)) {
3487 err = -ENODEV;
3488 goto out_ieee80211_free_hw;
3489 }
3490
3491 pci_set_master(pdev);
3492
093d874c 3493 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3494 if (!err)
093d874c 3495 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3496 if (err) {
093d874c 3497 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3498 if (!err)
093d874c 3499 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3500 /* both attempts failed: */
316c30d9 3501 if (err) {
978785a3 3502 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3503 goto out_pci_disable_device;
cc2a8ea8 3504 }
316c30d9
AK
3505 }
3506
3507 err = pci_request_regions(pdev, DRV_NAME);
3508 if (err)
3509 goto out_pci_disable_device;
3510
3511 pci_set_drvdata(pdev, priv);
3512
316c30d9
AK
3513
3514 /***********************
3515 * 3. Read REV register
3516 ***********************/
3517 priv->hw_base = pci_iomap(pdev, 0, 0);
3518 if (!priv->hw_base) {
3519 err = -ENODEV;
3520 goto out_pci_release_regions;
3521 }
3522
e1623446 3523 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3524 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3525 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3526
731a29b7 3527 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA
3528 * we should init now
3529 */
3530 spin_lock_init(&priv->reg_lock);
731a29b7 3531 spin_lock_init(&priv->lock);
4843b5a7
RC
3532
3533 /*
3534 * stop and reset the on-board processor just in case it is in a
3535 * strange state ... like being left stranded by a primary kernel
3536 * and this is now the kdump kernel trying to start up
3537 */
3538 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3539
b661c819 3540 iwl_hw_detect(priv);
c11362c0 3541 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 3542 priv->cfg->name, priv->hw_rev);
316c30d9 3543
e7b63581
TW
3544 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3545 * PCI Tx retries from interfering with C3 CPU state */
3546 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3547
086ed117
MA
3548 iwl_prepare_card_hw(priv);
3549 if (!priv->hw_ready) {
3550 IWL_WARN(priv, "Failed, HW not ready\n");
3551 goto out_iounmap;
3552 }
3553
91238714
TW
3554 /*****************
3555 * 4. Read EEPROM
3556 *****************/
316c30d9
AK
3557 /* Read the EEPROM */
3558 err = iwl_eeprom_init(priv);
3559 if (err) {
15b1687c 3560 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3561 goto out_iounmap;
3562 }
8614f360
TW
3563 err = iwl_eeprom_check_version(priv);
3564 if (err)
c8f16138 3565 goto out_free_eeprom;
8614f360 3566
02883017 3567 /* extract MAC Address */
316c30d9 3568 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3569 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3570 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3571
3572 /************************
3573 * 5. Setup HW constants
3574 ************************/
da154e30 3575 if (iwl_set_hw_params(priv)) {
15b1687c 3576 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3577 goto out_free_eeprom;
316c30d9
AK
3578 }
3579
3580 /*******************
6ba87956 3581 * 6. Setup priv
316c30d9 3582 *******************/
b481de9c 3583
6ba87956 3584 err = iwl_init_drv(priv);
bf85ea4f 3585 if (err)
399f4900 3586 goto out_free_eeprom;
bf85ea4f 3587 /* At this point both hw and priv are initialized. */
316c30d9 3588
316c30d9 3589 /********************
09f9bf79 3590 * 7. Setup services
316c30d9 3591 ********************/
0359facc 3592 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3593 iwl_disable_interrupts(priv);
0359facc 3594 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3595
6cd0b1cb
HS
3596 pci_enable_msi(priv->pci_dev);
3597
ef850d7c
MA
3598 iwl_alloc_isr_ict(priv);
3599 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3600 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3601 if (err) {
3602 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3603 goto out_disable_msi;
3604 }
5b9f8cd3 3605 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3606 if (err) {
15b1687c 3607 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3608 goto out_free_irq;
316c30d9
AK
3609 }
3610
4e39317d 3611 iwl_setup_deferred_work(priv);
653fa4a0 3612 iwl_setup_rx_handlers(priv);
316c30d9 3613
158bea07
JB
3614 /*********************************************
3615 * 8. Enable interrupts and read RFKILL state
3616 *********************************************/
6ba87956 3617
6cd0b1cb
HS
3618 /* enable interrupts if needed: hw bug w/a */
3619 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3620 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3621 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3622 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3623 }
3624
3625 iwl_enable_interrupts(priv);
3626
6cd0b1cb
HS
3627 /* If platform's RF_KILL switch is NOT set to KILL */
3628 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3629 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3630 else
3631 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3632
a60e77e5
JB
3633 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3634 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3635
58d0f361 3636 iwl_power_initialize(priv);
39b73fb1 3637 iwl_tt_initialize(priv);
158bea07 3638
b08dfd04 3639 err = iwl_request_firmware(priv, true);
158bea07
JB
3640 if (err)
3641 goto out_remove_sysfs;
3642
b481de9c
ZY
3643 return 0;
3644
316c30d9 3645 out_remove_sysfs:
c8f16138
RC
3646 destroy_workqueue(priv->workqueue);
3647 priv->workqueue = NULL;
5b9f8cd3 3648 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3649 out_free_irq:
3650 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3651 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3652 out_disable_msi:
3653 pci_disable_msi(priv->pci_dev);
6ba87956 3654 iwl_uninit_drv(priv);
073d3f5f
TW
3655 out_free_eeprom:
3656 iwl_eeprom_free(priv);
b481de9c
ZY
3657 out_iounmap:
3658 pci_iounmap(pdev, priv->hw_base);
3659 out_pci_release_regions:
316c30d9 3660 pci_set_drvdata(pdev, NULL);
623d563e 3661 pci_release_regions(pdev);
b481de9c
ZY
3662 out_pci_disable_device:
3663 pci_disable_device(pdev);
b481de9c 3664 out_ieee80211_free_hw:
20594eb0 3665 iwl_free_traffic_mem(priv);
d7c76f4c 3666 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3667 out:
3668 return err;
3669}
3670
5b9f8cd3 3671static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3672{
c79dd5b5 3673 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3674 unsigned long flags;
b481de9c
ZY
3675
3676 if (!priv)
3677 return;
3678
e1623446 3679 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3680
67249625 3681 iwl_dbgfs_unregister(priv);
5b9f8cd3 3682 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3683
5b9f8cd3
EG
3684 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3685 * to be called and iwl_down since we are removing the device
0b124c31
GG
3686 * we need to set STATUS_EXIT_PENDING bit.
3687 */
3688 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3689 if (priv->mac80211_registered) {
3690 ieee80211_unregister_hw(priv->hw);
3691 priv->mac80211_registered = 0;
0b124c31 3692 } else {
5b9f8cd3 3693 iwl_down(priv);
c4f55232
RR
3694 }
3695
c166b25a
BC
3696 /*
3697 * Make sure device is reset to low power before unloading driver.
3698 * This may be redundant with iwl_down(), but there are paths to
3699 * run iwl_down() without calling apm_ops.stop(), and there are
3700 * paths to avoid running iwl_down() at all before leaving driver.
3701 * This (inexpensive) call *makes sure* device is reset.
3702 */
3703 priv->cfg->ops->lib->apm_ops.stop(priv);
3704
39b73fb1
WYG
3705 iwl_tt_exit(priv);
3706
0359facc
MA
3707 /* make sure we flush any pending irq or
3708 * tasklet for the driver
3709 */
3710 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3711 iwl_disable_interrupts(priv);
0359facc
MA
3712 spin_unlock_irqrestore(&priv->lock, flags);
3713
3714 iwl_synchronize_irq(priv);
3715
5b9f8cd3 3716 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3717
3718 if (priv->rxq.bd)
54b81550 3719 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 3720 iwlagn_hw_txq_ctx_free(priv);
b481de9c 3721
073d3f5f 3722 iwl_eeprom_free(priv);
b481de9c 3723
b481de9c 3724
948c171c
MA
3725 /*netif_stop_queue(dev); */
3726 flush_workqueue(priv->workqueue);
3727
5b9f8cd3 3728 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3729 * priv->workqueue... so we can't take down the workqueue
3730 * until now... */
3731 destroy_workqueue(priv->workqueue);
3732 priv->workqueue = NULL;
20594eb0 3733 iwl_free_traffic_mem(priv);
b481de9c 3734
6cd0b1cb
HS
3735 free_irq(priv->pci_dev->irq, priv);
3736 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3737 pci_iounmap(pdev, priv->hw_base);
3738 pci_release_regions(pdev);
3739 pci_disable_device(pdev);
3740 pci_set_drvdata(pdev, NULL);
3741
6ba87956 3742 iwl_uninit_drv(priv);
b481de9c 3743
ef850d7c
MA
3744 iwl_free_isr_ict(priv);
3745
b481de9c
ZY
3746 if (priv->ibss_beacon)
3747 dev_kfree_skb(priv->ibss_beacon);
3748
3749 ieee80211_free_hw(priv->hw);
3750}
3751
b481de9c
ZY
3752
3753/*****************************************************************************
3754 *
3755 * driver and module entry point
3756 *
3757 *****************************************************************************/
3758
fed9017e 3759/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 3760static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 3761#ifdef CONFIG_IWL4965
fed9017e
RR
3762 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3763 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3764#endif /* CONFIG_IWL4965 */
5a6a256e 3765#ifdef CONFIG_IWL5000
ac592574
WYG
3766/* 5100 Series WiFi */
3767 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3768 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3769 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3770 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3771 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3772 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3773 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3774 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3775 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3776 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3777 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3778 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3779 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3780 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3781 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3782 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3783 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3784 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3785 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3786 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3787 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3788 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3789 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3790 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3791
3792/* 5300 Series WiFi */
3793 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3794 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3795 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3796 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3797 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3798 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3799 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3800 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3801 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3802 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3803 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3804 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3805
3806/* 5350 Series WiFi/WiMax */
3807 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3808 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3809 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3810
3811/* 5150 Series Wifi/WiMax */
3812 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3813 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3814 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3815 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3816 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3817 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3818
3819 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3820 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3821 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3822 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG
3823
3824/* 6x00 Series */
5953a62e
WYG
3825 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3826 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3827 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3828 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3829 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3830 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3831 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3832 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3833 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3834 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
0b5af201 3835 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000i_g2_2agn_cfg)},
5953a62e
WYG
3836
3837/* 6x50 WiFi/WiMax Series */
5953a62e
WYG
3838 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3839 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3840 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3841 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG
3842 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3843 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3844
77dcb6a9 3845/* 1000 Series WiFi */
4bd0914f
WYG
3846 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3847 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3848 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3849 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3850 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3851 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3852 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3853 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3854 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3855 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3856 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3857 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 3858#endif /* CONFIG_IWL5000 */
7100e924 3859
fed9017e
RR
3860 {0}
3861};
3862MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3863
3864static struct pci_driver iwl_driver = {
b481de9c 3865 .name = DRV_NAME,
fed9017e 3866 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3867 .probe = iwl_pci_probe,
3868 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3869#ifdef CONFIG_PM
5b9f8cd3
EG
3870 .suspend = iwl_pci_suspend,
3871 .resume = iwl_pci_resume,
b481de9c
ZY
3872#endif
3873};
3874
5b9f8cd3 3875static int __init iwl_init(void)
b481de9c
ZY
3876{
3877
3878 int ret;
3879 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3880 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3881
e227ceac 3882 ret = iwlagn_rate_control_register();
897e1cf2 3883 if (ret) {
a3139c59
SO
3884 printk(KERN_ERR DRV_NAME
3885 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3886 return ret;
3887 }
3888
fed9017e 3889 ret = pci_register_driver(&iwl_driver);
b481de9c 3890 if (ret) {
a3139c59 3891 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3892 goto error_register;
b481de9c 3893 }
b481de9c
ZY
3894
3895 return ret;
897e1cf2 3896
897e1cf2 3897error_register:
e227ceac 3898 iwlagn_rate_control_unregister();
897e1cf2 3899 return ret;
b481de9c
ZY
3900}
3901
5b9f8cd3 3902static void __exit iwl_exit(void)
b481de9c 3903{
fed9017e 3904 pci_unregister_driver(&iwl_driver);
e227ceac 3905 iwlagn_rate_control_unregister();
b481de9c
ZY
3906}
3907
5b9f8cd3
EG
3908module_exit(iwl_exit);
3909module_init(iwl_init);
a562a9dd
RC
3910
3911#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3912module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 3913MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 3914module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
3915MODULE_PARM_DESC(debug, "debug output mask");
3916#endif
3917
2b068618
WYG
3918module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
3919MODULE_PARM_DESC(swcrypto50,
3920 "using crypto in software (default 0 [hardware]) (deprecated)");
3921module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
3922MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
3923module_param_named(queues_num50,
3924 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
3925MODULE_PARM_DESC(queues_num50,
3926 "number of hw queues in 50xx series (deprecated)");
3927module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
3928MODULE_PARM_DESC(queues_num, "number of hw queues.");
3929module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
3930MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
3931module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
3932MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
3933module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
3934 int, S_IRUGO);
3935MODULE_PARM_DESC(amsdu_size_8K50,
3936 "enable 8K amsdu size in 50XX series (deprecated)");
3937module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
3938 int, S_IRUGO);
3939MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
3940module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
3941MODULE_PARM_DESC(fw_restart50,
3942 "restart firmware in case of error (deprecated)");
3943module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
3944MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
3945module_param_named(
3946 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
3947MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");