]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/wireless/iwlwifi/iwl-agn.c
iwlwifi: fix scan races
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
d43c36dc 36#include <linux/sched.h>
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37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
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41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
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44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
a3139c59
SO
48#define DRV_NAME "iwlagn"
49
6bc913bd 50#include "iwl-eeprom.h"
3e0d4cb1 51#include "iwl-dev.h"
fee1247a 52#include "iwl-core.h"
3395f6e9 53#include "iwl-io.h"
b481de9c 54#include "iwl-helpers.h"
6974e363 55#include "iwl-sta.h"
f0832f13 56#include "iwl-calib.h"
b481de9c 57
416e1438 58
b481de9c
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59/******************************************************************************
60 *
61 * module boiler plate
62 *
63 ******************************************************************************/
64
b481de9c
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65/*
66 * module name, copyright, version, etc.
b481de9c 67 */
d783b061 68#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 69
0a6857e7 70#ifdef CONFIG_IWLWIFI_DEBUG
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71#define VD "d"
72#else
73#define VD
74#endif
75
81963d68 76#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 77
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78
79MODULE_DESCRIPTION(DRV_DESCRIPTION);
80MODULE_VERSION(DRV_VERSION);
a7b75207 81MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 82MODULE_LICENSE("GPL");
4fc22b21 83MODULE_ALIAS("iwl4965");
b481de9c 84
b481de9c 85/*************** STATION TABLE MANAGEMENT ****
9fbab516 86 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
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87 * the functionality provided here
88 */
89
90/**************************************************************/
91
b481de9c 92/**
5b9f8cd3 93 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 94 *
01ebd063 95 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
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96 * the active_rxon structure is updated with the new data. This
97 * function correctly transitions out of the RXON_ASSOC_MSK state if
98 * a HW tune is required based on the RXON structure changes.
99 */
e0158e61 100int iwl_commit_rxon(struct iwl_priv *priv)
b481de9c
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101{
102 /* cast away the const for active_rxon in this function */
c1adf9fb 103 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
104 int ret;
105 bool new_assoc =
106 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 107
fee1247a 108 if (!iwl_is_alive(priv))
43d59b32 109 return -EBUSY;
b481de9c
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110
111 /* always get timestamp with Rx frame */
112 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
113
8ccde88a 114 ret = iwl_check_rxon_cmd(priv);
43d59b32 115 if (ret) {
15b1687c 116 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY
117 return -EINVAL;
118 }
119
0924e519
WYG
120 /*
121 * receive commit_rxon request
122 * abort any previous channel switch if still in process
123 */
124 if (priv->switch_rxon.switch_in_progress &&
125 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
126 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
127 le16_to_cpu(priv->switch_rxon.channel));
128 priv->switch_rxon.switch_in_progress = false;
129 }
130
b481de9c 131 /* If we don't need to send a full RXON, we can use
5b9f8cd3 132 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 133 * and other flags for the current radio configuration. */
54559703 134 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
135 ret = iwl_send_rxon_assoc(priv);
136 if (ret) {
15b1687c 137 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 138 return ret;
b481de9c
ZY
139 }
140
141 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 142 iwl_print_rx_config_cmd(priv);
b481de9c
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143 return 0;
144 }
145
146 /* station table will be cleared */
147 priv->assoc_station_added = 0;
148
b481de9c
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149 /* If we are currently associated and the new config requires
150 * an RXON_ASSOC and the new config wants the associated mask enabled,
151 * we must clear the associated from the active configuration
152 * before we apply the new config */
43d59b32 153 if (iwl_is_associated(priv) && new_assoc) {
e1623446 154 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
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155 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
156
43d59b32 157 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 158 sizeof(struct iwl_rxon_cmd),
b481de9c
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159 &priv->active_rxon);
160
161 /* If the mask clearing failed then we set
162 * active_rxon back to what it was previously */
43d59b32 163 if (ret) {
b481de9c 164 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 165 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 166 return ret;
b481de9c 167 }
b481de9c
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168 }
169
e1623446 170 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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171 "* with%s RXON_FILTER_ASSOC_MSK\n"
172 "* channel = %d\n"
e174961c 173 "* bssid = %pM\n",
43d59b32 174 (new_assoc ? "" : "out"),
b481de9c 175 le16_to_cpu(priv->staging_rxon.channel),
e174961c 176 priv->staging_rxon.bssid_addr);
b481de9c 177
90e8e424 178 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
179
180 /* Apply the new configuration
181 * RXON unassoc clears the station table in uCode, send it before
182 * we add the bcast station. If assoc bit is set, we will send RXON
183 * after having added the bcast and bssid station.
184 */
185 if (!new_assoc) {
186 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 187 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 188 if (ret) {
15b1687c 189 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
190 return ret;
191 }
192 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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193 }
194
c587de0b 195 iwl_clear_stations_table(priv);
556f8db7 196
19cc1087 197 priv->start_calib = 0;
b481de9c 198
b481de9c 199 /* Add the broadcast address so we can send broadcast frames */
3459ab5a
RC
200 priv->cfg->ops->lib->add_bcast_station(priv);
201
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202
203 /* If we have set the ASSOC_MSK and we are in BSS mode then
204 * add the IWL_AP_ID to the station rate table */
9185159d 205 if (new_assoc) {
05c914fe 206 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
207 ret = iwl_rxon_add_station(priv,
208 priv->active_rxon.bssid_addr, 1);
209 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
210 IWL_ERR(priv,
211 "Error adding AP address for TX.\n");
9185159d
TW
212 return -EIO;
213 }
214 priv->assoc_station_added = 1;
215 if (priv->default_wep_key &&
216 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
217 IWL_ERR(priv,
218 "Could not send WEP static key.\n");
b481de9c 219 }
43d59b32 220
47eef9bd
WYG
221 /*
222 * allow CTS-to-self if possible for new association.
223 * this is relevant only for 5000 series and up,
224 * but will not damage 4965
225 */
226 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
227
43d59b32
EG
228 /* Apply the new configuration
229 * RXON assoc doesn't clear the station table in uCode,
230 */
231 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
232 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
233 if (ret) {
15b1687c 234 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
235 return ret;
236 }
237 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 238 }
a643565e 239 iwl_print_rx_config_cmd(priv);
b481de9c 240
36da7d70
ZY
241 iwl_init_sensitivity(priv);
242
243 /* If we issue a new RXON command which required a tune then we must
244 * send a new TXPOWER command or we won't be able to Tx any frames */
245 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
246 if (ret) {
15b1687c 247 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY
248 return ret;
249 }
250
b481de9c
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251 return 0;
252}
253
5b9f8cd3 254void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
255{
256
45823531
AK
257 if (priv->cfg->ops->hcmd->set_rxon_chain)
258 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 259 iwlcore_commit_rxon(priv);
5da4b55f
MA
260}
261
fcab423d 262static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
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263{
264 struct list_head *element;
265
e1623446 266 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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267 priv->frames_count);
268
269 while (!list_empty(&priv->free_frames)) {
270 element = priv->free_frames.next;
271 list_del(element);
fcab423d 272 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
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273 priv->frames_count--;
274 }
275
276 if (priv->frames_count) {
39aadf8c 277 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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278 priv->frames_count);
279 priv->frames_count = 0;
280 }
281}
282
fcab423d 283static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 284{
fcab423d 285 struct iwl_frame *frame;
b481de9c
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286 struct list_head *element;
287 if (list_empty(&priv->free_frames)) {
288 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
289 if (!frame) {
15b1687c 290 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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291 return NULL;
292 }
293
294 priv->frames_count++;
295 return frame;
296 }
297
298 element = priv->free_frames.next;
299 list_del(element);
fcab423d 300 return list_entry(element, struct iwl_frame, list);
b481de9c
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301}
302
fcab423d 303static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
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304{
305 memset(frame, 0, sizeof(*frame));
306 list_add(&frame->list, &priv->free_frames);
307}
308
47ff65c4 309static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 310 struct ieee80211_hdr *hdr,
73ec1cc2 311 int left)
b481de9c 312{
3109ece1 313 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
314 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
315 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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316 return 0;
317
318 if (priv->ibss_beacon->len > left)
319 return 0;
320
321 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
322
323 return priv->ibss_beacon->len;
324}
325
47ff65c4
DH
326/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
327static void iwl_set_beacon_tim(struct iwl_priv *priv,
328 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
329 u8 *beacon, u32 frame_size)
330{
331 u16 tim_idx;
332 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
333
334 /*
335 * The index is relative to frame start but we start looking at the
336 * variable-length part of the beacon.
337 */
338 tim_idx = mgmt->u.beacon.variable - beacon;
339
340 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
341 while ((tim_idx < (frame_size - 2)) &&
342 (beacon[tim_idx] != WLAN_EID_TIM))
343 tim_idx += beacon[tim_idx+1] + 2;
344
345 /* If TIM field was found, set variables */
346 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
347 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
348 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
349 } else
350 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
351}
352
5b9f8cd3 353static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 354 struct iwl_frame *frame)
4bf64efd
TW
355{
356 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH
357 u32 frame_size;
358 u32 rate_flags;
359 u32 rate;
360 /*
361 * We have to set up the TX command, the TX Beacon command, and the
362 * beacon contents.
363 */
4bf64efd 364
47ff65c4 365 /* Initialize memory */
4bf64efd
TW
366 tx_beacon_cmd = &frame->u.beacon;
367 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
368
47ff65c4 369 /* Set up TX beacon contents */
4bf64efd 370 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 371 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH
372 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
373 return 0;
4bf64efd 374
47ff65c4 375 /* Set up TX command fields */
4bf64efd 376 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH
377 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
378 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
379 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
380 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 381
47ff65c4
DH
382 /* Set up TX beacon command fields */
383 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
384 frame_size);
4bf64efd 385
47ff65c4
DH
386 /* Set up packet rate and flags */
387 rate = iwl_rate_get_lowest_plcp(priv);
388 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
389 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
390 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
391 rate_flags |= RATE_MCS_CCK_MSK;
392 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
393 rate_flags);
4bf64efd
TW
394
395 return sizeof(*tx_beacon_cmd) + frame_size;
396}
5b9f8cd3 397static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 398{
fcab423d 399 struct iwl_frame *frame;
b481de9c
ZY
400 unsigned int frame_size;
401 int rc;
b481de9c 402
fcab423d 403 frame = iwl_get_free_frame(priv);
b481de9c 404 if (!frame) {
15b1687c 405 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
406 "command.\n");
407 return -ENOMEM;
408 }
409
47ff65c4
DH
410 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
411 if (!frame_size) {
412 IWL_ERR(priv, "Error configuring the beacon command\n");
413 iwl_free_frame(priv, frame);
414 return -EINVAL;
415 }
b481de9c 416
857485c0 417 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
418 &frame->u.cmd[0]);
419
fcab423d 420 iwl_free_frame(priv, frame);
b481de9c
ZY
421
422 return rc;
423}
424
7aaa1d79
SO
425static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
426{
427 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
428
429 dma_addr_t addr = get_unaligned_le32(&tb->lo);
430 if (sizeof(dma_addr_t) > sizeof(u32))
431 addr |=
432 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
433
434 return addr;
435}
436
437static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
438{
439 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
440
441 return le16_to_cpu(tb->hi_n_len) >> 4;
442}
443
444static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
445 dma_addr_t addr, u16 len)
446{
447 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
448 u16 hi_n_len = len << 4;
449
450 put_unaligned_le32(addr, &tb->lo);
451 if (sizeof(dma_addr_t) > sizeof(u32))
452 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
453
454 tb->hi_n_len = cpu_to_le16(hi_n_len);
455
456 tfd->num_tbs = idx + 1;
457}
458
459static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
460{
461 return tfd->num_tbs & 0x1f;
462}
463
464/**
465 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
466 * @priv - driver private data
467 * @txq - tx queue
468 *
469 * Does NOT advance any TFD circular buffer read/write indexes
470 * Does NOT free the TFD itself (which is within circular buffer)
471 */
472void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
473{
59606ffa 474 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
475 struct iwl_tfd *tfd;
476 struct pci_dev *dev = priv->pci_dev;
477 int index = txq->q.read_ptr;
478 int i;
479 int num_tbs;
480
481 tfd = &tfd_tmp[index];
482
483 /* Sanity check on number of chunks */
484 num_tbs = iwl_tfd_get_num_tbs(tfd);
485
486 if (num_tbs >= IWL_NUM_OF_TBS) {
487 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
488 /* @todo issue fatal error, it is quite serious situation */
489 return;
490 }
491
492 /* Unmap tx_cmd */
493 if (num_tbs)
494 pci_unmap_single(dev,
c2acea8e
JB
495 pci_unmap_addr(&txq->meta[index], mapping),
496 pci_unmap_len(&txq->meta[index], len),
96891cee 497 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
498
499 /* Unmap chunks, if any. */
500 for (i = 1; i < num_tbs; i++) {
501 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
502 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
503
504 if (txq->txb) {
505 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
506 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
507 }
508 }
509}
510
511int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
512 struct iwl_tx_queue *txq,
513 dma_addr_t addr, u16 len,
514 u8 reset, u8 pad)
515{
516 struct iwl_queue *q;
59606ffa 517 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
518 u32 num_tbs;
519
520 q = &txq->q;
59606ffa
SO
521 tfd_tmp = (struct iwl_tfd *)txq->tfds;
522 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
523
524 if (reset)
525 memset(tfd, 0, sizeof(*tfd));
526
527 num_tbs = iwl_tfd_get_num_tbs(tfd);
528
529 /* Each TFD can point to a maximum 20 Tx buffers */
530 if (num_tbs >= IWL_NUM_OF_TBS) {
531 IWL_ERR(priv, "Error can not send more than %d chunks\n",
532 IWL_NUM_OF_TBS);
533 return -EINVAL;
534 }
535
536 BUG_ON(addr & ~DMA_BIT_MASK(36));
537 if (unlikely(addr & ~IWL_TX_DMA_MASK))
538 IWL_ERR(priv, "Unaligned address = %llx\n",
539 (unsigned long long)addr);
540
541 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
542
543 return 0;
544}
545
a8e74e27
SO
546/*
547 * Tell nic where to find circular buffer of Tx Frame Descriptors for
548 * given Tx queue, and enable the DMA channel used for that queue.
549 *
550 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
551 * channels supported in hardware.
552 */
553int iwl_hw_tx_queue_init(struct iwl_priv *priv,
554 struct iwl_tx_queue *txq)
555{
a8e74e27
SO
556 int txq_id = txq->q.id;
557
a8e74e27
SO
558 /* Circular buffer (TFD queue in DRAM) physical base address */
559 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
560 txq->q.dma_addr >> 8);
561
a8e74e27
SO
562 return 0;
563}
564
b481de9c
ZY
565/******************************************************************************
566 *
567 * Generic RX handler implementations
568 *
569 ******************************************************************************/
885ba202
TW
570static void iwl_rx_reply_alive(struct iwl_priv *priv,
571 struct iwl_rx_mem_buffer *rxb)
b481de9c 572{
2f301227 573 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 574 struct iwl_alive_resp *palive;
b481de9c
ZY
575 struct delayed_work *pwork;
576
577 palive = &pkt->u.alive_frame;
578
e1623446 579 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
580 "0x%01X 0x%01X\n",
581 palive->is_valid, palive->ver_type,
582 palive->ver_subtype);
583
584 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 585 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
586 memcpy(&priv->card_alive_init,
587 &pkt->u.alive_frame,
885ba202 588 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
589 pwork = &priv->init_alive_start;
590 } else {
e1623446 591 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 592 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 593 sizeof(struct iwl_alive_resp));
b481de9c
ZY
594 pwork = &priv->alive_start;
595 }
596
597 /* We delay the ALIVE response by 5ms to
598 * give the HW RF Kill time to activate... */
599 if (palive->is_valid == UCODE_VALID_OK)
600 queue_delayed_work(priv->workqueue, pwork,
601 msecs_to_jiffies(5));
602 else
39aadf8c 603 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
604}
605
5b9f8cd3 606static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 607{
c79dd5b5
TW
608 struct iwl_priv *priv =
609 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
610 struct sk_buff *beacon;
611
612 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 613 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
614
615 if (!beacon) {
15b1687c 616 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
617 return;
618 }
619
620 mutex_lock(&priv->mutex);
621 /* new beacon skb is allocated every time; dispose previous.*/
622 if (priv->ibss_beacon)
623 dev_kfree_skb(priv->ibss_beacon);
624
625 priv->ibss_beacon = beacon;
626 mutex_unlock(&priv->mutex);
627
5b9f8cd3 628 iwl_send_beacon_cmd(priv);
b481de9c
ZY
629}
630
4e39317d 631/**
5b9f8cd3 632 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
633 *
634 * This callback is provided in order to send a statistics request.
635 *
636 * This timer function is continually reset to execute within
637 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
638 * was received. We need to ensure we receive the statistics in order
639 * to update the temperature used for calibrating the TXPOWER.
640 */
5b9f8cd3 641static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
642{
643 struct iwl_priv *priv = (struct iwl_priv *)data;
644
645 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
646 return;
647
61780ee3
MA
648 /* dont send host command if rf-kill is on */
649 if (!iwl_is_ready_rf(priv))
650 return;
651
ef8d5529 652 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG
653}
654
a9e1cb6a
WYG
655
656static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
657 u32 start_idx, u32 num_events,
658 u32 mode)
659{
660 u32 i;
661 u32 ptr; /* SRAM byte address of log data */
662 u32 ev, time, data; /* event log data */
663 unsigned long reg_flags;
664
665 if (mode == 0)
666 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
667 else
668 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
669
670 /* Make sure device is powered up for SRAM reads */
671 spin_lock_irqsave(&priv->reg_lock, reg_flags);
672 if (iwl_grab_nic_access(priv)) {
673 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
674 return;
675 }
676
677 /* Set starting address; reads will auto-increment */
678 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
679 rmb();
680
681 /*
682 * "time" is actually "data" for mode 0 (no timestamp).
683 * place event id # at far right for easier visual parsing.
684 */
685 for (i = 0; i < num_events; i++) {
686 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
687 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
688 if (mode == 0) {
689 trace_iwlwifi_dev_ucode_cont_event(priv,
690 0, time, ev);
691 } else {
692 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
693 trace_iwlwifi_dev_ucode_cont_event(priv,
694 time, data, ev);
695 }
696 }
697 /* Allow device to power down */
698 iwl_release_nic_access(priv);
699 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
700}
701
875295f1 702static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG
703{
704 u32 capacity; /* event log capacity in # entries */
705 u32 base; /* SRAM byte address of event log header */
706 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
707 u32 num_wraps; /* # times uCode wrapped to top of log */
708 u32 next_entry; /* index of next entry to be written by uCode */
709
710 if (priv->ucode_type == UCODE_INIT)
711 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
712 else
713 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
714 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
715 capacity = iwl_read_targ_mem(priv, base);
716 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
717 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
718 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
719 } else
720 return;
721
722 if (num_wraps == priv->event_log.num_wraps) {
723 iwl_print_cont_event_trace(priv,
724 base, priv->event_log.next_entry,
725 next_entry - priv->event_log.next_entry,
726 mode);
727 priv->event_log.non_wraps_count++;
728 } else {
729 if ((num_wraps - priv->event_log.num_wraps) > 1)
730 priv->event_log.wraps_more_count++;
731 else
732 priv->event_log.wraps_once_count++;
733 trace_iwlwifi_dev_ucode_wrap_event(priv,
734 num_wraps - priv->event_log.num_wraps,
735 next_entry, priv->event_log.next_entry);
736 if (next_entry < priv->event_log.next_entry) {
737 iwl_print_cont_event_trace(priv, base,
738 priv->event_log.next_entry,
739 capacity - priv->event_log.next_entry,
740 mode);
741
742 iwl_print_cont_event_trace(priv, base, 0,
743 next_entry, mode);
744 } else {
745 iwl_print_cont_event_trace(priv, base,
746 next_entry, capacity - next_entry,
747 mode);
748
749 iwl_print_cont_event_trace(priv, base, 0,
750 next_entry, mode);
751 }
752 }
753 priv->event_log.num_wraps = num_wraps;
754 priv->event_log.next_entry = next_entry;
755}
756
757/**
758 * iwl_bg_ucode_trace - Timer callback to log ucode event
759 *
760 * The timer is continually set to execute every
761 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
762 * this function is to perform continuous uCode event logging operation
763 * if enabled
764 */
765static void iwl_bg_ucode_trace(unsigned long data)
766{
767 struct iwl_priv *priv = (struct iwl_priv *)data;
768
769 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
770 return;
771
772 if (priv->event_log.ucode_trace) {
773 iwl_continuous_event_trace(priv);
774 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
775 mod_timer(&priv->ucode_trace,
776 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
777 }
778}
779
5b9f8cd3 780static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 781 struct iwl_rx_mem_buffer *rxb)
b481de9c 782{
0a6857e7 783#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 784 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW
785 struct iwl4965_beacon_notif *beacon =
786 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 787 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 788
e1623446 789 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 790 "tsf %d %d rate %d\n",
25a6572c 791 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
792 beacon->beacon_notify_hdr.failure_frame,
793 le32_to_cpu(beacon->ibss_mgr_status),
794 le32_to_cpu(beacon->high_tsf),
795 le32_to_cpu(beacon->low_tsf), rate);
796#endif
797
05c914fe 798 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
799 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
800 queue_work(priv->workqueue, &priv->beacon_update);
801}
802
b481de9c
ZY
803/* Handle notification from uCode that card's power state is changing
804 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 805static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 806 struct iwl_rx_mem_buffer *rxb)
b481de9c 807{
2f301227 808 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
809 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
810 unsigned long status = priv->status;
811
3a41bbd5 812 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 813 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG
814 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
815 (flags & CT_CARD_DISABLED) ?
816 "Reached" : "Not reached");
b481de9c
ZY
817
818 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 819 CT_CARD_DISABLED)) {
b481de9c 820
3395f6e9 821 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
822 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
823
a8b50a0a
MA
824 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
825 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
826
827 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 828 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 829 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 830 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 831 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 832 }
3a41bbd5 833 if (flags & CT_CARD_DISABLED)
39b73fb1 834 iwl_tt_enter_ct_kill(priv);
b481de9c 835 }
3a41bbd5 836 if (!(flags & CT_CARD_DISABLED))
39b73fb1 837 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
838
839 if (flags & HW_CARD_DISABLED)
840 set_bit(STATUS_RF_KILL_HW, &priv->status);
841 else
842 clear_bit(STATUS_RF_KILL_HW, &priv->status);
843
844
b481de9c 845 if (!(flags & RXON_CARD_DISABLED))
2a421b91 846 iwl_scan_cancel(priv);
b481de9c
ZY
847
848 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
849 test_bit(STATUS_RF_KILL_HW, &priv->status)))
850 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
851 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
852 else
853 wake_up_interruptible(&priv->wait_command_queue);
854}
855
5b9f8cd3 856int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 857{
e2e3c57b 858 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 859 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
860 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
861 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
862 ~APMG_PS_CTRL_MSK_PWR_SRC);
863 } else {
864 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
865 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
866 ~APMG_PS_CTRL_MSK_PWR_SRC);
867 }
868
a8b50a0a 869 return 0;
e2e3c57b
TW
870}
871
b481de9c 872/**
5b9f8cd3 873 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
874 *
875 * Setup the RX handlers for each of the reply types sent from the uCode
876 * to the host.
877 *
878 * This function chains into the hardware specific files for them to setup
879 * any hardware specific handlers as well.
880 */
653fa4a0 881static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 882{
885ba202 883 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
884 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
885 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC
886 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
887 iwl_rx_spectrum_measure_notif;
5b9f8cd3 888 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 889 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
890 iwl_rx_pm_debug_statistics_notif;
891 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 892
9fbab516
BC
893 /*
894 * The same handler is used for both the REPLY to a discrete
895 * statistics request from the host as well as for the periodic
896 * statistics notifications (after received beacons) from the uCode.
b481de9c 897 */
ef8d5529 898 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 899 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW
900
901 iwl_setup_rx_scan_handlers(priv);
902
37a44211 903 /* status change handler */
5b9f8cd3 904 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 905
c1354754
TW
906 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
907 iwl_rx_missed_beacon_notif;
37a44211 908 /* Rx handlers */
1781a07f
EG
909 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
910 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
911 /* block ack */
912 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 913 /* Set up hardware specific Rx handlers */
d4789efe 914 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
915}
916
b481de9c 917/**
a55360e4 918 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
919 *
920 * Uses the priv->rx_handlers callback function array to invoke
921 * the appropriate handlers, including command responses,
922 * frame-received notifications, and other notifications.
923 */
a55360e4 924void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 925{
a55360e4 926 struct iwl_rx_mem_buffer *rxb;
db11d634 927 struct iwl_rx_packet *pkt;
a55360e4 928 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
929 u32 r, i;
930 int reclaim;
931 unsigned long flags;
5c0eef96 932 u8 fill_rx = 0;
d68ab680 933 u32 count = 8;
4752c93c 934 int total_empty;
b481de9c 935
6440adb5
BC
936 /* uCode's read index (stored in shared DRAM) indicates the last Rx
937 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 938 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
939 i = rxq->read;
940
941 /* Rx interrupt, but nothing sent from uCode */
942 if (i == r)
e1623446 943 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 944
4752c93c 945 /* calculate total frames need to be restock after handling RX */
7300515d 946 total_empty = r - rxq->write_actual;
4752c93c
MA
947 if (total_empty < 0)
948 total_empty += RX_QUEUE_SIZE;
949
950 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
951 fill_rx = 1;
952
b481de9c
ZY
953 while (i != r) {
954 rxb = rxq->queue[i];
955
9fbab516 956 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
957 * then a bug has been introduced in the queue refilling
958 * routines -- catch it here */
959 BUG_ON(rxb == NULL);
960
961 rxq->queue[i] = NULL;
962
2f301227
ZY
963 pci_unmap_page(priv->pci_dev, rxb->page_dma,
964 PAGE_SIZE << priv->hw_params.rx_page_order,
965 PCI_DMA_FROMDEVICE);
966 pkt = rxb_addr(rxb);
b481de9c 967
be1a71a1
JB
968 trace_iwlwifi_dev_rx(priv, pkt,
969 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
970
b481de9c
ZY
971 /* Reclaim a command buffer only if this packet is a response
972 * to a (driver-originated) command.
973 * If the packet (e.g. Rx frame) originated from uCode,
974 * there is no command buffer to reclaim.
975 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
976 * but apparently a few don't get set; catch them here. */
977 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
978 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 979 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 980 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 981 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
982 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
983 (pkt->hdr.cmd != REPLY_TX);
984
985 /* Based on type of command response or notification,
986 * handle those that need handling via function in
5b9f8cd3 987 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 988 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 989 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 990 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 991 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 992 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
993 } else {
994 /* No handling needed */
e1623446 995 IWL_DEBUG_RX(priv,
b481de9c
ZY
996 "r %d i %d No handler needed for %s, 0x%02x\n",
997 r, i, get_cmd_string(pkt->hdr.cmd),
998 pkt->hdr.cmd);
999 }
1000
29b1b268
ZY
1001 /*
1002 * XXX: After here, we should always check rxb->page
1003 * against NULL before touching it or its virtual
1004 * memory (pkt). Because some rx_handler might have
1005 * already taken or freed the pages.
1006 */
1007
b481de9c 1008 if (reclaim) {
2f301227
ZY
1009 /* Invoke any callbacks, transfer the buffer to caller,
1010 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1011 * as we reclaim the driver command queue */
29b1b268 1012 if (rxb->page)
17b88929 1013 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1014 else
39aadf8c 1015 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1016 }
1017
7300515d
ZY
1018 /* Reuse the page if possible. For notification packets and
1019 * SKBs that fail to Rx correctly, add them back into the
1020 * rx_free list for reuse later. */
1021 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1022 if (rxb->page != NULL) {
7300515d
ZY
1023 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1024 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1025 PCI_DMA_FROMDEVICE);
1026 list_add_tail(&rxb->list, &rxq->rx_free);
1027 rxq->free_count++;
1028 } else
1029 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1030
b481de9c 1031 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1032
b481de9c 1033 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1034 /* If there are a lot of unused frames,
1035 * restock the Rx queue so ucode wont assert. */
1036 if (fill_rx) {
1037 count++;
1038 if (count >= 8) {
7300515d 1039 rxq->read = i;
4752c93c 1040 iwl_rx_replenish_now(priv);
5c0eef96
MA
1041 count = 0;
1042 }
1043 }
b481de9c
ZY
1044 }
1045
1046 /* Backtrack one entry */
7300515d 1047 rxq->read = i;
4752c93c
MA
1048 if (fill_rx)
1049 iwl_rx_replenish_now(priv);
1050 else
1051 iwl_rx_queue_restock(priv);
a55360e4 1052}
a55360e4 1053
0359facc
MA
1054/* call this function to flush any scheduled tasklet */
1055static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1056{
a96a27f9 1057 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1058 synchronize_irq(priv->pci_dev->irq);
1059 tasklet_kill(&priv->irq_tasklet);
1060}
1061
ef850d7c 1062static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
1063{
1064 u32 inta, handled = 0;
1065 u32 inta_fh;
1066 unsigned long flags;
c2e61da2 1067 u32 i;
0a6857e7 1068#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1069 u32 inta_mask;
1070#endif
1071
1072 spin_lock_irqsave(&priv->lock, flags);
1073
1074 /* Ack/clear/reset pending uCode interrupts.
1075 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1076 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
1077 inta = iwl_read32(priv, CSR_INT);
1078 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1079
1080 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1081 * Any new interrupts that happen after this, either while we're
1082 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
1083 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1084 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1085
0a6857e7 1086#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1087 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1088 /* just for debug */
3395f6e9 1089 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1090 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1091 inta, inta_mask, inta_fh);
1092 }
1093#endif
1094
2f301227
ZY
1095 spin_unlock_irqrestore(&priv->lock, flags);
1096
b481de9c
ZY
1097 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1098 * atomic, make sure that inta covers all the interrupts that
1099 * we've discovered, even if FH interrupt came in just after
1100 * reading CSR_INT. */
6f83eaa1 1101 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1102 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1103 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
1104 inta |= CSR_INT_BIT_FH_TX;
1105
1106 /* Now service all interrupt bits discovered above. */
1107 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1108 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1109
1110 /* Tell the device to stop sending interrupts */
5b9f8cd3 1111 iwl_disable_interrupts(priv);
b481de9c 1112
a83b9141 1113 priv->isr_stats.hw++;
5b9f8cd3 1114 iwl_irq_handle_error(priv);
b481de9c
ZY
1115
1116 handled |= CSR_INT_BIT_HW_ERR;
1117
b481de9c
ZY
1118 return;
1119 }
1120
0a6857e7 1121#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1122 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1123 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1124 if (inta & CSR_INT_BIT_SCD) {
e1623446 1125 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1126 "the frame/frames.\n");
a83b9141
WYG
1127 priv->isr_stats.sch++;
1128 }
b481de9c
ZY
1129
1130 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1131 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1132 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
1133 priv->isr_stats.alive++;
1134 }
b481de9c
ZY
1135 }
1136#endif
1137 /* Safely ignore these bits for debug checks below */
25c03d8e 1138 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1139
9fbab516 1140 /* HW RF KILL switch toggled */
b481de9c
ZY
1141 if (inta & CSR_INT_BIT_RF_KILL) {
1142 int hw_rf_kill = 0;
3395f6e9 1143 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
1144 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1145 hw_rf_kill = 1;
1146
4c423a2b 1147 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1148 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1149
a83b9141
WYG
1150 priv->isr_stats.rfkill++;
1151
a9efa652 1152 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
1153 * the driver allows loading the ucode even if the radio
1154 * is killed. Hence update the killswitch state here. The
1155 * rfkill handler will care about restarting if needed.
a9efa652 1156 */
6cd0b1cb
HS
1157 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1158 if (hw_rf_kill)
1159 set_bit(STATUS_RF_KILL_HW, &priv->status);
1160 else
1161 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1162 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1163 }
b481de9c
ZY
1164
1165 handled |= CSR_INT_BIT_RF_KILL;
1166 }
1167
9fbab516 1168 /* Chip got too hot and stopped itself */
b481de9c 1169 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1170 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1171 priv->isr_stats.ctkill++;
b481de9c
ZY
1172 handled |= CSR_INT_BIT_CT_KILL;
1173 }
1174
1175 /* Error detected by uCode */
1176 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1177 IWL_ERR(priv, "Microcode SW error detected. "
1178 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1179 priv->isr_stats.sw++;
1180 priv->isr_stats.sw_err = inta;
5b9f8cd3 1181 iwl_irq_handle_error(priv);
b481de9c
ZY
1182 handled |= CSR_INT_BIT_SW_ERR;
1183 }
1184
c2e61da2
BC
1185 /*
1186 * uCode wakes up after power-down sleep.
1187 * Tell device about any new tx or host commands enqueued,
1188 * and about any Rx buffers made available while asleep.
1189 */
b481de9c 1190 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1191 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1192 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC
1193 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1194 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1195 priv->isr_stats.wakeup++;
b481de9c
ZY
1196 handled |= CSR_INT_BIT_WAKEUP;
1197 }
1198
1199 /* All uCode command responses, including Tx command responses,
1200 * Rx "responses" (frame-received notification), and other
1201 * notifications from uCode come through here*/
1202 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1203 iwl_rx_handle(priv);
a83b9141 1204 priv->isr_stats.rx++;
b481de9c
ZY
1205 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1206 }
1207
c72cd19f 1208 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1209 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1210 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1211 priv->isr_stats.tx++;
b481de9c 1212 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1213 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR
1214 priv->ucode_write_complete = 1;
1215 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1216 }
1217
a83b9141 1218 if (inta & ~handled) {
15b1687c 1219 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1220 priv->isr_stats.unhandled++;
1221 }
b481de9c 1222
40cefda9 1223 if (inta & ~(priv->inta_mask)) {
39aadf8c 1224 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1225 inta & ~priv->inta_mask);
39aadf8c 1226 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1227 }
1228
1229 /* Re-enable all interrupts */
0359facc
MA
1230 /* only Re-enable if diabled by irq */
1231 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1232 iwl_enable_interrupts(priv);
b481de9c 1233
0a6857e7 1234#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1235 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1236 inta = iwl_read32(priv, CSR_INT);
1237 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1238 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1239 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1240 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1241 }
1242#endif
b481de9c
ZY
1243}
1244
ef850d7c
MA
1245/* tasklet for iwlagn interrupt */
1246static void iwl_irq_tasklet(struct iwl_priv *priv)
1247{
1248 u32 inta = 0;
1249 u32 handled = 0;
1250 unsigned long flags;
8756990f 1251 u32 i;
ef850d7c
MA
1252#ifdef CONFIG_IWLWIFI_DEBUG
1253 u32 inta_mask;
1254#endif
1255
1256 spin_lock_irqsave(&priv->lock, flags);
1257
1258 /* Ack/clear/reset pending uCode interrupts.
1259 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1260 */
48a6be6a
SZ
1261 /* There is a hardware bug in the interrupt mask function that some
1262 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1263 * they are disabled in the CSR_INT_MASK register. Furthermore the
1264 * ICT interrupt handling mechanism has another bug that might cause
1265 * these unmasked interrupts fail to be detected. We workaround the
1266 * hardware bugs here by ACKing all the possible interrupts so that
1267 * interrupt coalescing can still be achieved.
1268 */
1269 iwl_write32(priv, CSR_INT, priv->inta | ~priv->inta_mask);
ef850d7c
MA
1270
1271 inta = priv->inta;
1272
1273#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1274 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1275 /* just for debug */
1276 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1277 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1278 inta, inta_mask);
1279 }
1280#endif
2f301227
ZY
1281
1282 spin_unlock_irqrestore(&priv->lock, flags);
1283
ef850d7c
MA
1284 /* saved interrupt in inta variable now we can reset priv->inta */
1285 priv->inta = 0;
1286
1287 /* Now service all interrupt bits discovered above. */
1288 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1289 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1290
1291 /* Tell the device to stop sending interrupts */
1292 iwl_disable_interrupts(priv);
1293
1294 priv->isr_stats.hw++;
1295 iwl_irq_handle_error(priv);
1296
1297 handled |= CSR_INT_BIT_HW_ERR;
1298
ef850d7c
MA
1299 return;
1300 }
1301
1302#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1303 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1304 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1305 if (inta & CSR_INT_BIT_SCD) {
1306 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1307 "the frame/frames.\n");
1308 priv->isr_stats.sch++;
1309 }
1310
1311 /* Alive notification via Rx interrupt will do the real work */
1312 if (inta & CSR_INT_BIT_ALIVE) {
1313 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1314 priv->isr_stats.alive++;
1315 }
1316 }
1317#endif
1318 /* Safely ignore these bits for debug checks below */
1319 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1320
1321 /* HW RF KILL switch toggled */
1322 if (inta & CSR_INT_BIT_RF_KILL) {
1323 int hw_rf_kill = 0;
1324 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1325 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1326 hw_rf_kill = 1;
1327
4c423a2b 1328 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1329 hw_rf_kill ? "disable radio" : "enable radio");
1330
1331 priv->isr_stats.rfkill++;
1332
1333 /* driver only loads ucode once setting the interface up.
1334 * the driver allows loading the ucode even if the radio
1335 * is killed. Hence update the killswitch state here. The
1336 * rfkill handler will care about restarting if needed.
1337 */
1338 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1339 if (hw_rf_kill)
1340 set_bit(STATUS_RF_KILL_HW, &priv->status);
1341 else
1342 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1343 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1344 }
1345
1346 handled |= CSR_INT_BIT_RF_KILL;
1347 }
1348
1349 /* Chip got too hot and stopped itself */
1350 if (inta & CSR_INT_BIT_CT_KILL) {
1351 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1352 priv->isr_stats.ctkill++;
1353 handled |= CSR_INT_BIT_CT_KILL;
1354 }
1355
1356 /* Error detected by uCode */
1357 if (inta & CSR_INT_BIT_SW_ERR) {
1358 IWL_ERR(priv, "Microcode SW error detected. "
1359 " Restarting 0x%X.\n", inta);
1360 priv->isr_stats.sw++;
1361 priv->isr_stats.sw_err = inta;
1362 iwl_irq_handle_error(priv);
1363 handled |= CSR_INT_BIT_SW_ERR;
1364 }
1365
1366 /* uCode wakes up after power-down sleep */
1367 if (inta & CSR_INT_BIT_WAKEUP) {
1368 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1369 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC
1370 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1371 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA
1372
1373 priv->isr_stats.wakeup++;
1374
1375 handled |= CSR_INT_BIT_WAKEUP;
1376 }
1377
1378 /* All uCode command responses, including Tx command responses,
1379 * Rx "responses" (frame-received notification), and other
1380 * notifications from uCode come through here*/
40cefda9
MA
1381 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1382 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1383 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1384 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1385 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1386 iwl_write32(priv, CSR_FH_INT_STATUS,
1387 CSR49_FH_INT_RX_MASK);
1388 }
1389 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1390 handled |= CSR_INT_BIT_RX_PERIODIC;
1391 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1392 }
1393 /* Sending RX interrupt require many steps to be done in the
1394 * the device:
1395 * 1- write interrupt to current index in ICT table.
1396 * 2- dma RX frame.
1397 * 3- update RX shared data to indicate last write index.
1398 * 4- send interrupt.
1399 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC
1400 * but the shared data changes does not reflect this;
1401 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1402 */
74ba67ed
BC
1403
1404 /* Disable periodic interrupt; we use it as just a one-shot. */
1405 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1406 CSR_INT_PERIODIC_DIS);
ef850d7c 1407 iwl_rx_handle(priv);
74ba67ed
BC
1408
1409 /*
1410 * Enable periodic interrupt in 8 msec only if we received
1411 * real RX interrupt (instead of just periodic int), to catch
1412 * any dangling Rx interrupt. If it was just the periodic
1413 * interrupt, there was no dangling Rx activity, and no need
1414 * to extend the periodic interrupt; one-shot is enough.
1415 */
40cefda9 1416 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1417 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA
1418 CSR_INT_PERIODIC_ENA);
1419
ef850d7c 1420 priv->isr_stats.rx++;
ef850d7c
MA
1421 }
1422
c72cd19f 1423 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA
1424 if (inta & CSR_INT_BIT_FH_TX) {
1425 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1426 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA
1427 priv->isr_stats.tx++;
1428 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1429 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA
1430 priv->ucode_write_complete = 1;
1431 wake_up_interruptible(&priv->wait_command_queue);
1432 }
1433
1434 if (inta & ~handled) {
1435 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1436 priv->isr_stats.unhandled++;
1437 }
1438
40cefda9 1439 if (inta & ~(priv->inta_mask)) {
ef850d7c 1440 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1441 inta & ~priv->inta_mask);
ef850d7c
MA
1442 }
1443
ef850d7c
MA
1444 /* Re-enable all interrupts */
1445 /* only Re-enable if diabled by irq */
1446 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1447 iwl_enable_interrupts(priv);
ef850d7c
MA
1448}
1449
a83b9141 1450
b481de9c
ZY
1451/******************************************************************************
1452 *
1453 * uCode download functions
1454 *
1455 ******************************************************************************/
1456
5b9f8cd3 1457static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1458{
98c92211
TW
1459 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1460 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1461 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1462 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1463 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1464 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1465}
1466
5b9f8cd3 1467static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1468{
1469 /* Remove all resets to allow NIC to operate */
1470 iwl_write32(priv, CSR_RESET, 0);
1471}
1472
1473
b08dfd04
JB
1474static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1475static int iwl_mac_setup_register(struct iwl_priv *priv);
1476
1477static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1478{
1479 const char *name_pre = priv->cfg->fw_name_pre;
1480
1481 if (first)
1482 priv->fw_index = priv->cfg->ucode_api_max;
1483 else
1484 priv->fw_index--;
1485
1486 if (priv->fw_index < priv->cfg->ucode_api_min) {
1487 IWL_ERR(priv, "no suitable firmware found!\n");
1488 return -ENOENT;
1489 }
1490
1491 sprintf(priv->firmware_name, "%s%d%s",
1492 name_pre, priv->fw_index, ".ucode");
1493
1494 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1495 priv->firmware_name);
1496
1497 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1498 &priv->pci_dev->dev, GFP_KERNEL, priv,
1499 iwl_ucode_callback);
1500}
1501
b481de9c 1502/**
b08dfd04 1503 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1504 *
b08dfd04
JB
1505 * If loaded successfully, copies the firmware into buffers
1506 * for the card to fetch (via DMA).
b481de9c 1507 */
b08dfd04 1508static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1509{
b08dfd04 1510 struct iwl_priv *priv = context;
cc0f555d 1511 struct iwl_ucode_header *ucode;
a0987a8d
RC
1512 const unsigned int api_max = priv->cfg->ucode_api_max;
1513 const unsigned int api_min = priv->cfg->ucode_api_min;
b481de9c
ZY
1514 u8 *src;
1515 size_t len;
cc0f555d
JS
1516 u32 api_ver, build;
1517 u32 inst_size, data_size, init_size, init_data_size, boot_size;
b08dfd04 1518 int err;
abdc2d62 1519 u16 eeprom_ver;
b481de9c 1520
b08dfd04
JB
1521 if (!ucode_raw) {
1522 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
1523 priv->firmware_name);
1524 goto try_again;
b481de9c
ZY
1525 }
1526
b08dfd04
JB
1527 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1528 priv->firmware_name, ucode_raw->size);
b481de9c 1529
cc0f555d
JS
1530 /* Make sure that we got at least the v1 header! */
1531 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1532 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 1533 goto try_again;
b481de9c
ZY
1534 }
1535
1536 /* Data from ucode file: header followed by uCode images */
cc0f555d 1537 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1538
c02b3acd 1539 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1540 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1541 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1542 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1543 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1544 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1545 init_data_size =
1546 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1547 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1548 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1549
a0987a8d
RC
1550 /* api_ver should match the api version forming part of the
1551 * firmware filename ... but we don't check for that and only rely
877d0310 1552 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1553
1554 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1555 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1556 "Driver supports v%u, firmware is v%u.\n",
1557 api_max, api_ver);
b08dfd04 1558 goto try_again;
a0987a8d 1559 }
b08dfd04 1560
a0987a8d 1561 if (api_ver != api_max)
978785a3 1562 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1563 "got v%u. New firmware can be obtained "
1564 "from http://www.intellinuxwireless.org.\n",
1565 api_max, api_ver);
1566
978785a3
TW
1567 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1568 IWL_UCODE_MAJOR(priv->ucode_ver),
1569 IWL_UCODE_MINOR(priv->ucode_ver),
1570 IWL_UCODE_API(priv->ucode_ver),
1571 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1572
5ebeb5a6
RC
1573 snprintf(priv->hw->wiphy->fw_version,
1574 sizeof(priv->hw->wiphy->fw_version),
1575 "%u.%u.%u.%u",
1576 IWL_UCODE_MAJOR(priv->ucode_ver),
1577 IWL_UCODE_MINOR(priv->ucode_ver),
1578 IWL_UCODE_API(priv->ucode_ver),
1579 IWL_UCODE_SERIAL(priv->ucode_ver));
1580
cc0f555d
JS
1581 if (build)
1582 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1583
abdc2d62
JS
1584 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1585 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1586 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1587 ? "OTP" : "EEPROM", eeprom_ver);
1588
e1623446 1589 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1590 priv->ucode_ver);
e1623446 1591 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1592 inst_size);
e1623446 1593 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1594 data_size);
e1623446 1595 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1596 init_size);
e1623446 1597 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1598 init_data_size);
e1623446 1599 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1600 boot_size);
1601
b08dfd04
JB
1602 /*
1603 * For any of the failures below (before allocating pci memory)
1604 * we will try to load a version with a smaller API -- maybe the
1605 * user just got a corrupted version of the latest API.
1606 */
1607
b481de9c 1608 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1609 if (ucode_raw->size !=
1610 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1611 inst_size + data_size + init_size +
1612 init_data_size + boot_size) {
1613
cc0f555d
JS
1614 IWL_DEBUG_INFO(priv,
1615 "uCode file size %d does not match expected size\n",
1616 (int)ucode_raw->size);
b08dfd04 1617 goto try_again;
b481de9c
ZY
1618 }
1619
1620 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1621 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1622 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1 1623 inst_size);
b08dfd04 1624 goto try_again;
b481de9c
ZY
1625 }
1626
099b40b7 1627 if (data_size > priv->hw_params.max_data_size) {
e1623446 1628 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1 1629 data_size);
b08dfd04 1630 goto try_again;
b481de9c 1631 }
099b40b7 1632 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1633 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1634 init_size);
b08dfd04 1635 goto try_again;
b481de9c 1636 }
099b40b7 1637 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1638 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1 1639 init_data_size);
b08dfd04 1640 goto try_again;
b481de9c 1641 }
099b40b7 1642 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1643 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1644 boot_size);
b08dfd04 1645 goto try_again;
b481de9c
ZY
1646 }
1647
1648 /* Allocate ucode buffers for card's bus-master loading ... */
1649
1650 /* Runtime instructions and 2 copies of data:
1651 * 1) unmodified from disk
1652 * 2) backup cache for save/restore during power-downs */
1653 priv->ucode_code.len = inst_size;
98c92211 1654 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1655
1656 priv->ucode_data.len = data_size;
98c92211 1657 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1658
1659 priv->ucode_data_backup.len = data_size;
98c92211 1660 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1661
1f304e4e
ZY
1662 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1663 !priv->ucode_data_backup.v_addr)
1664 goto err_pci_alloc;
1665
b481de9c 1666 /* Initialization instructions and data */
90e759d1
TW
1667 if (init_size && init_data_size) {
1668 priv->ucode_init.len = init_size;
98c92211 1669 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1670
1671 priv->ucode_init_data.len = init_data_size;
98c92211 1672 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1673
1674 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1675 goto err_pci_alloc;
1676 }
b481de9c
ZY
1677
1678 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1679 if (boot_size) {
1680 priv->ucode_boot.len = boot_size;
98c92211 1681 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1682
90e759d1
TW
1683 if (!priv->ucode_boot.v_addr)
1684 goto err_pci_alloc;
1685 }
b481de9c
ZY
1686
1687 /* Copy images into buffers for card's bus-master reads ... */
1688
1689 /* Runtime instructions (first block of data in file) */
cc0f555d 1690 len = inst_size;
e1623446 1691 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1692 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1693 src += len;
1694
e1623446 1695 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1696 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1697
1698 /* Runtime data (2nd block)
5b9f8cd3 1699 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1700 len = data_size;
e1623446 1701 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1702 memcpy(priv->ucode_data.v_addr, src, len);
1703 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1704 src += len;
b481de9c
ZY
1705
1706 /* Initialization instructions (3rd block) */
1707 if (init_size) {
cc0f555d 1708 len = init_size;
e1623446 1709 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1710 len);
b481de9c 1711 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1712 src += len;
b481de9c
ZY
1713 }
1714
1715 /* Initialization data (4th block) */
1716 if (init_data_size) {
cc0f555d 1717 len = init_data_size;
e1623446 1718 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1719 len);
b481de9c 1720 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1721 src += len;
b481de9c
ZY
1722 }
1723
1724 /* Bootstrap instructions (5th block) */
cc0f555d 1725 len = boot_size;
e1623446 1726 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1727 memcpy(priv->ucode_boot.v_addr, src, len);
1728
b08dfd04
JB
1729 /**************************************************
1730 * This is still part of probe() in a sense...
1731 *
1732 * 9. Setup and register with mac80211 and debugfs
1733 **************************************************/
1734 err = iwl_mac_setup_register(priv);
1735 if (err)
1736 goto out_unbind;
1737
1738 err = iwl_dbgfs_register(priv, DRV_NAME);
1739 if (err)
1740 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1741
b481de9c
ZY
1742 /* We have our copies now, allow OS release its copies */
1743 release_firmware(ucode_raw);
b08dfd04
JB
1744 return;
1745
1746 try_again:
1747 /* try next, if any */
1748 if (iwl_request_firmware(priv, false))
1749 goto out_unbind;
1750 release_firmware(ucode_raw);
1751 return;
b481de9c
ZY
1752
1753 err_pci_alloc:
15b1687c 1754 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 1755 iwl_dealloc_ucode_pci(priv);
b08dfd04
JB
1756 out_unbind:
1757 device_release_driver(&priv->pci_dev->dev);
b481de9c 1758 release_firmware(ucode_raw);
b481de9c
ZY
1759}
1760
b7a79404
RC
1761static const char *desc_lookup_text[] = {
1762 "OK",
1763 "FAIL",
1764 "BAD_PARAM",
1765 "BAD_CHECKSUM",
1766 "NMI_INTERRUPT_WDG",
1767 "SYSASSERT",
1768 "FATAL_ERROR",
1769 "BAD_COMMAND",
1770 "HW_ERROR_TUNE_LOCK",
1771 "HW_ERROR_TEMPERATURE",
1772 "ILLEGAL_CHAN_FREQ",
1773 "VCC_NOT_STABLE",
1774 "FH_ERROR",
1775 "NMI_INTERRUPT_HOST",
1776 "NMI_INTERRUPT_ACTION_PT",
1777 "NMI_INTERRUPT_UNKNOWN",
1778 "UCODE_VERSION_MISMATCH",
1779 "HW_ERROR_ABS_LOCK",
1780 "HW_ERROR_CAL_LOCK_FAIL",
1781 "NMI_INTERRUPT_INST_ACTION_PT",
1782 "NMI_INTERRUPT_DATA_ACTION_PT",
1783 "NMI_TRM_HW_ER",
1784 "NMI_INTERRUPT_TRM",
1785 "NMI_INTERRUPT_BREAK_POINT"
1786 "DEBUG_0",
1787 "DEBUG_1",
1788 "DEBUG_2",
1789 "DEBUG_3",
a7fce6ee 1790 "ADVANCED SYSASSERT"
b7a79404
RC
1791};
1792
1793static const char *desc_lookup(int i)
1794{
1795 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1796
1797 if (i < 0 || i > max)
1798 i = max;
1799
1800 return desc_lookup_text[i];
1801}
1802
1803#define ERROR_START_OFFSET (1 * sizeof(u32))
1804#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1805
1806void iwl_dump_nic_error_log(struct iwl_priv *priv)
1807{
1808 u32 data2, line;
1809 u32 desc, time, count, base, data1;
1810 u32 blink1, blink2, ilink1, ilink2;
1811
1812 if (priv->ucode_type == UCODE_INIT)
1813 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1814 else
1815 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1816
1817 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1818 IWL_ERR(priv,
1819 "Not valid error log pointer 0x%08X for %s uCode\n",
1820 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC
1821 return;
1822 }
1823
1824 count = iwl_read_targ_mem(priv, base);
1825
1826 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1827 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1828 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1829 priv->status, count);
1830 }
1831
1832 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1833 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1834 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1835 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1836 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1837 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1838 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1839 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1840 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1841
be1a71a1
JB
1842 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1843 blink1, blink2, ilink1, ilink2);
1844
b7a79404
RC
1845 IWL_ERR(priv, "Desc Time "
1846 "data1 data2 line\n");
1847 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1848 desc_lookup(desc), desc, time, data1, data2, line);
1849 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1850 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1851 ilink1, ilink2);
1852
1853}
1854
1855#define EVENT_START_OFFSET (4 * sizeof(u32))
1856
1857/**
1858 * iwl_print_event_log - Dump error event log to syslog
1859 *
1860 */
b03d7d0f
WYG
1861static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1862 u32 num_events, u32 mode,
1863 int pos, char **buf, size_t bufsz)
b7a79404
RC
1864{
1865 u32 i;
1866 u32 base; /* SRAM byte address of event log header */
1867 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1868 u32 ptr; /* SRAM byte address of log data */
1869 u32 ev, time, data; /* event log data */
e5854471 1870 unsigned long reg_flags;
b7a79404
RC
1871
1872 if (num_events == 0)
b03d7d0f 1873 return pos;
b7a79404
RC
1874 if (priv->ucode_type == UCODE_INIT)
1875 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1876 else
1877 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1878
1879 if (mode == 0)
1880 event_size = 2 * sizeof(u32);
1881 else
1882 event_size = 3 * sizeof(u32);
1883
1884 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1885
e5854471
BC
1886 /* Make sure device is powered up for SRAM reads */
1887 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1888 iwl_grab_nic_access(priv);
1889
1890 /* Set starting address; reads will auto-increment */
1891 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1892 rmb();
1893
b7a79404
RC
1894 /* "time" is actually "data" for mode 0 (no timestamp).
1895 * place event id # at far right for easier visual parsing. */
1896 for (i = 0; i < num_events; i++) {
e5854471
BC
1897 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1898 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1899 if (mode == 0) {
1900 /* data, ev */
b03d7d0f
WYG
1901 if (bufsz) {
1902 pos += scnprintf(*buf + pos, bufsz - pos,
1903 "EVT_LOG:0x%08x:%04u\n",
1904 time, ev);
1905 } else {
1906 trace_iwlwifi_dev_ucode_event(priv, 0,
1907 time, ev);
1908 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1909 time, ev);
1910 }
b7a79404 1911 } else {
e5854471 1912 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG
1913 if (bufsz) {
1914 pos += scnprintf(*buf + pos, bufsz - pos,
1915 "EVT_LOGT:%010u:0x%08x:%04u\n",
1916 time, data, ev);
1917 } else {
1918 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 1919 time, data, ev);
b03d7d0f
WYG
1920 trace_iwlwifi_dev_ucode_event(priv, time,
1921 data, ev);
1922 }
b7a79404
RC
1923 }
1924 }
e5854471
BC
1925
1926 /* Allow device to power down */
1927 iwl_release_nic_access(priv);
1928 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1929 return pos;
b7a79404
RC
1930}
1931
c341ddb2
WYG
1932/**
1933 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1934 */
b03d7d0f
WYG
1935static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1936 u32 num_wraps, u32 next_entry,
1937 u32 size, u32 mode,
1938 int pos, char **buf, size_t bufsz)
c341ddb2
WYG
1939{
1940 /*
1941 * display the newest DEFAULT_LOG_ENTRIES entries
1942 * i.e the entries just before the next ont that uCode would fill.
1943 */
1944 if (num_wraps) {
1945 if (next_entry < size) {
b03d7d0f
WYG
1946 pos = iwl_print_event_log(priv,
1947 capacity - (size - next_entry),
1948 size - next_entry, mode,
1949 pos, buf, bufsz);
1950 pos = iwl_print_event_log(priv, 0,
1951 next_entry, mode,
1952 pos, buf, bufsz);
c341ddb2 1953 } else
b03d7d0f
WYG
1954 pos = iwl_print_event_log(priv, next_entry - size,
1955 size, mode, pos, buf, bufsz);
c341ddb2 1956 } else {
b03d7d0f
WYG
1957 if (next_entry < size) {
1958 pos = iwl_print_event_log(priv, 0, next_entry,
1959 mode, pos, buf, bufsz);
1960 } else {
1961 pos = iwl_print_event_log(priv, next_entry - size,
1962 size, mode, pos, buf, bufsz);
1963 }
c341ddb2 1964 }
b03d7d0f 1965 return pos;
c341ddb2
WYG
1966}
1967
84c40692
BC
1968/* For sanity check only. Actual size is determined by uCode, typ. 512 */
1969#define MAX_EVENT_LOG_SIZE (512)
1970
c341ddb2
WYG
1971#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
1972
b03d7d0f
WYG
1973int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1974 char **buf, bool display)
b7a79404
RC
1975{
1976 u32 base; /* SRAM byte address of event log header */
1977 u32 capacity; /* event log capacity in # entries */
1978 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1979 u32 num_wraps; /* # times uCode wrapped to top of log */
1980 u32 next_entry; /* index of next entry to be written by uCode */
1981 u32 size; /* # entries that we'll print */
b03d7d0f
WYG
1982 int pos = 0;
1983 size_t bufsz = 0;
b7a79404
RC
1984
1985 if (priv->ucode_type == UCODE_INIT)
1986 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1987 else
1988 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1989
1990 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1991 IWL_ERR(priv,
1992 "Invalid event log pointer 0x%08X for %s uCode\n",
1993 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 1994 return -EINVAL;
b7a79404
RC
1995 }
1996
1997 /* event log header */
1998 capacity = iwl_read_targ_mem(priv, base);
1999 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2000 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2001 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2002
84c40692
BC
2003 if (capacity > MAX_EVENT_LOG_SIZE) {
2004 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2005 capacity, MAX_EVENT_LOG_SIZE);
2006 capacity = MAX_EVENT_LOG_SIZE;
2007 }
2008
2009 if (next_entry > MAX_EVENT_LOG_SIZE) {
2010 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2011 next_entry, MAX_EVENT_LOG_SIZE);
2012 next_entry = MAX_EVENT_LOG_SIZE;
2013 }
2014
b7a79404
RC
2015 size = num_wraps ? capacity : next_entry;
2016
2017 /* bail out if nothing in log */
2018 if (size == 0) {
2019 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2020 return pos;
b7a79404
RC
2021 }
2022
c341ddb2 2023#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2024 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG
2025 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2026 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2027#else
2028 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2029 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2030#endif
2031 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2032 size);
b7a79404 2033
c341ddb2 2034#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG
2035 if (display) {
2036 if (full_log)
2037 bufsz = capacity * 48;
2038 else
2039 bufsz = size * 48;
2040 *buf = kmalloc(bufsz, GFP_KERNEL);
2041 if (!*buf)
937c397e 2042 return -ENOMEM;
b03d7d0f 2043 }
c341ddb2
WYG
2044 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2045 /*
2046 * if uCode has wrapped back to top of log,
2047 * start at the oldest entry,
2048 * i.e the next one that uCode would fill.
2049 */
2050 if (num_wraps)
b03d7d0f
WYG
2051 pos = iwl_print_event_log(priv, next_entry,
2052 capacity - next_entry, mode,
2053 pos, buf, bufsz);
c341ddb2 2054 /* (then/else) start at top of log */
b03d7d0f
WYG
2055 pos = iwl_print_event_log(priv, 0,
2056 next_entry, mode, pos, buf, bufsz);
c341ddb2 2057 } else
b03d7d0f
WYG
2058 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2059 next_entry, size, mode,
2060 pos, buf, bufsz);
c341ddb2 2061#else
b03d7d0f
WYG
2062 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2063 next_entry, size, mode,
2064 pos, buf, bufsz);
b7a79404 2065#endif
b03d7d0f 2066 return pos;
c341ddb2 2067}
b7a79404 2068
b481de9c 2069/**
4a4a9e81 2070 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2071 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2072 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2073 */
4a4a9e81 2074static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2075{
57aab75a 2076 int ret = 0;
b481de9c 2077
e1623446 2078 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2079
2080 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2081 /* We had an error bringing up the hardware, so take it
2082 * all the way back down so we can try again */
e1623446 2083 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2084 goto restart;
2085 }
2086
2087 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2088 * This is a paranoid check, because we would not have gotten the
2089 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2090 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
2091 /* Runtime instruction load was bad;
2092 * take it all the way back down so we can try again */
e1623446 2093 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2094 goto restart;
2095 }
2096
c587de0b 2097 iwl_clear_stations_table(priv);
57aab75a
TW
2098 ret = priv->cfg->ops->lib->alive_notify(priv);
2099 if (ret) {
39aadf8c
WT
2100 IWL_WARN(priv,
2101 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
2102 goto restart;
2103 }
2104
5b9f8cd3 2105 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
2106 set_bit(STATUS_ALIVE, &priv->status);
2107
fee1247a 2108 if (iwl_is_rfkill(priv))
b481de9c
ZY
2109 return;
2110
36d6825b 2111 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
2112
2113 priv->active_rate = priv->rates_mask;
2114 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2115
2f748dec
WYG
2116 /* Configure Tx antenna selection based on H/W config */
2117 if (priv->cfg->ops->hcmd->set_tx_ant)
2118 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2119
3109ece1 2120 if (iwl_is_associated(priv)) {
c1adf9fb
GG
2121 struct iwl_rxon_cmd *active_rxon =
2122 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
2123 /* apply any changes in staging */
2124 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2125 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2126 } else {
2127 /* Initialize our rx_config data */
5b9f8cd3 2128 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
2129
2130 if (priv->cfg->ops->hcmd->set_rxon_chain)
2131 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2132
b481de9c
ZY
2133 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2134 }
2135
9fbab516 2136 /* Configure Bluetooth device coexistence support */
5b9f8cd3 2137 iwl_send_bt_config(priv);
b481de9c 2138
4a4a9e81
TW
2139 iwl_reset_run_time_calib(priv);
2140
b481de9c 2141 /* Configure the adapter for unassociated operation */
e0158e61 2142 iwlcore_commit_rxon(priv);
b481de9c
ZY
2143
2144 /* At this point, the NIC is initialized and operational */
47f4a587 2145 iwl_rf_kill_ct_config(priv);
5a66926a 2146
e932a609 2147 iwl_leds_init(priv);
fe00b5a5 2148
e1623446 2149 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2150 set_bit(STATUS_READY, &priv->status);
5a66926a 2151 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2152
e312c24c 2153 iwl_power_update_mode(priv, true);
c46fbefa 2154
ada17513
MA
2155 /* reassociate for ADHOC mode */
2156 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2157 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2158 priv->vif);
2159 if (beacon)
2160 iwl_mac_beacon_update(priv->hw, beacon);
2161 }
2162
2163
c46fbefa 2164 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 2165 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 2166
b481de9c
ZY
2167 return;
2168
2169 restart:
2170 queue_work(priv->workqueue, &priv->restart);
2171}
2172
4e39317d 2173static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2174
5b9f8cd3 2175static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2176{
2177 unsigned long flags;
2178 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2179
e1623446 2180 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2181
b481de9c
ZY
2182 if (!exit_pending)
2183 set_bit(STATUS_EXIT_PENDING, &priv->status);
2184
c587de0b 2185 iwl_clear_stations_table(priv);
b481de9c
ZY
2186
2187 /* Unblock any waiting calls */
2188 wake_up_interruptible_all(&priv->wait_command_queue);
2189
b481de9c
ZY
2190 /* Wipe out the EXIT_PENDING status bit if we are not actually
2191 * exiting the module */
2192 if (!exit_pending)
2193 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2194
2195 /* stop and reset the on-board processor */
3395f6e9 2196 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2197
2198 /* tell the device to stop sending interrupts */
0359facc 2199 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2200 iwl_disable_interrupts(priv);
0359facc
MA
2201 spin_unlock_irqrestore(&priv->lock, flags);
2202 iwl_synchronize_irq(priv);
b481de9c
ZY
2203
2204 if (priv->mac80211_registered)
2205 ieee80211_stop_queues(priv->hw);
2206
5b9f8cd3 2207 /* If we have not previously called iwl_init() then
a60e77e5 2208 * clear all bits but the RF Kill bit and return */
fee1247a 2209 if (!iwl_is_init(priv)) {
b481de9c
ZY
2210 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2211 STATUS_RF_KILL_HW |
9788864e
RC
2212 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2213 STATUS_GEO_CONFIGURED |
052ec3f1
MA
2214 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2215 STATUS_EXIT_PENDING;
b481de9c
ZY
2216 goto exit;
2217 }
2218
6da3a13e 2219 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2220 * bit and continue taking the NIC down. */
b481de9c
ZY
2221 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2222 STATUS_RF_KILL_HW |
9788864e
RC
2223 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2224 STATUS_GEO_CONFIGURED |
b481de9c 2225 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
2226 STATUS_FW_ERROR |
2227 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2228 STATUS_EXIT_PENDING;
b481de9c 2229
ef850d7c
MA
2230 /* device going down, Stop using ICT table */
2231 iwl_disable_ict(priv);
b481de9c 2232
da1bc453 2233 iwl_txq_ctx_stop(priv);
b3bbacb7 2234 iwl_rxq_stop(priv);
b481de9c 2235
309e731a
BC
2236 /* Power-down device's busmaster DMA clocks */
2237 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2238 udelay(5);
2239
309e731a
BC
2240 /* Make sure (redundant) we've released our request to stay awake */
2241 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2242
4d2ccdb9
BC
2243 /* Stop the device, and put it in low power state */
2244 priv->cfg->ops->lib->apm_ops.stop(priv);
2245
b481de9c 2246 exit:
885ba202 2247 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2248
2249 if (priv->ibss_beacon)
2250 dev_kfree_skb(priv->ibss_beacon);
2251 priv->ibss_beacon = NULL;
2252
2253 /* clear out any free frames */
fcab423d 2254 iwl_clear_free_frames(priv);
b481de9c
ZY
2255}
2256
5b9f8cd3 2257static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2258{
2259 mutex_lock(&priv->mutex);
5b9f8cd3 2260 __iwl_down(priv);
b481de9c 2261 mutex_unlock(&priv->mutex);
b24d22b1 2262
4e39317d 2263 iwl_cancel_deferred_work(priv);
b481de9c
ZY
2264}
2265
086ed117
MA
2266#define HW_READY_TIMEOUT (50)
2267
2268static int iwl_set_hw_ready(struct iwl_priv *priv)
2269{
2270 int ret = 0;
2271
2272 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2273 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2274
2275 /* See if we got it */
2276 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2277 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2278 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2279 HW_READY_TIMEOUT);
2280 if (ret != -ETIMEDOUT)
2281 priv->hw_ready = true;
2282 else
2283 priv->hw_ready = false;
2284
2285 IWL_DEBUG_INFO(priv, "hardware %s\n",
2286 (priv->hw_ready == 1) ? "ready" : "not ready");
2287 return ret;
2288}
2289
2290static int iwl_prepare_card_hw(struct iwl_priv *priv)
2291{
2292 int ret = 0;
2293
2294 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
2295
3354a0f6
MA
2296 ret = iwl_set_hw_ready(priv);
2297 if (priv->hw_ready)
2298 return ret;
2299
2300 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
2301 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2302 CSR_HW_IF_CONFIG_REG_PREPARE);
2303
2304 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2305 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2306 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2307
3354a0f6 2308 /* HW should be ready by now, check again. */
086ed117
MA
2309 if (ret != -ETIMEDOUT)
2310 iwl_set_hw_ready(priv);
2311
2312 return ret;
2313}
2314
b481de9c
ZY
2315#define MAX_HW_RESTARTS 5
2316
5b9f8cd3 2317static int __iwl_up(struct iwl_priv *priv)
b481de9c 2318{
57aab75a
TW
2319 int i;
2320 int ret;
b481de9c
ZY
2321
2322 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2323 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2324 return -EIO;
2325 }
2326
e903fbd4 2327 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2328 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
2329 return -EIO;
2330 }
2331
086ed117
MA
2332 iwl_prepare_card_hw(priv);
2333
2334 if (!priv->hw_ready) {
2335 IWL_WARN(priv, "Exit HW not ready\n");
2336 return -EIO;
2337 }
2338
e655b9f0 2339 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2340 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2341 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2342 else
e655b9f0 2343 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2344
c1842d61 2345 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
2346 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2347
5b9f8cd3 2348 iwl_enable_interrupts(priv);
a60e77e5 2349 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2350 return 0;
b481de9c
ZY
2351 }
2352
3395f6e9 2353 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2354
1053d35f 2355 ret = iwl_hw_nic_init(priv);
57aab75a 2356 if (ret) {
15b1687c 2357 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2358 return ret;
b481de9c
ZY
2359 }
2360
2361 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2362 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2363 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2364 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2365
2366 /* clear (again), then enable host interrupts */
3395f6e9 2367 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2368 iwl_enable_interrupts(priv);
b481de9c
ZY
2369
2370 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2371 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2372 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2373
2374 /* Copy original ucode data image from disk into backup cache.
2375 * This will be used to initialize the on-board processor's
2376 * data SRAM for a clean start when the runtime program first loads. */
2377 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2378 priv->ucode_data.len);
b481de9c 2379
b481de9c
ZY
2380 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2381
c587de0b 2382 iwl_clear_stations_table(priv);
b481de9c
ZY
2383
2384 /* load bootstrap state machine,
2385 * load bootstrap program into processor's memory,
2386 * prepare to load the "initialize" uCode */
57aab75a 2387 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2388
57aab75a 2389 if (ret) {
15b1687c
WT
2390 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2391 ret);
b481de9c
ZY
2392 continue;
2393 }
2394
2395 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2396 iwl_nic_start(priv);
b481de9c 2397
e1623446 2398 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2399
2400 return 0;
2401 }
2402
2403 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2404 __iwl_down(priv);
64e72c3e 2405 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2406
2407 /* tried to restart and config the device for as long as our
2408 * patience could withstand */
15b1687c 2409 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2410 return -EIO;
2411}
2412
2413
2414/*****************************************************************************
2415 *
2416 * Workqueue callbacks
2417 *
2418 *****************************************************************************/
2419
4a4a9e81 2420static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2421{
c79dd5b5
TW
2422 struct iwl_priv *priv =
2423 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2424
2425 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2426 return;
2427
2428 mutex_lock(&priv->mutex);
f3ccc08c 2429 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2430 mutex_unlock(&priv->mutex);
2431}
2432
4a4a9e81 2433static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2434{
c79dd5b5
TW
2435 struct iwl_priv *priv =
2436 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2437
2438 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2439 return;
2440
258c44a0
MA
2441 /* enable dram interrupt */
2442 iwl_reset_ict(priv);
2443
b481de9c 2444 mutex_lock(&priv->mutex);
4a4a9e81 2445 iwl_alive_start(priv);
b481de9c
ZY
2446 mutex_unlock(&priv->mutex);
2447}
2448
16e727e8
EG
2449static void iwl_bg_run_time_calib_work(struct work_struct *work)
2450{
2451 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2452 run_time_calib_work);
2453
2454 mutex_lock(&priv->mutex);
2455
2456 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2457 test_bit(STATUS_SCANNING, &priv->status)) {
2458 mutex_unlock(&priv->mutex);
2459 return;
2460 }
2461
2462 if (priv->start_calib) {
2463 iwl_chain_noise_calibration(priv, &priv->statistics);
2464
2465 iwl_sensitivity_calibration(priv, &priv->statistics);
2466 }
2467
2468 mutex_unlock(&priv->mutex);
2469 return;
2470}
2471
5b9f8cd3 2472static void iwl_bg_restart(struct work_struct *data)
b481de9c 2473{
c79dd5b5 2474 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2475
2476 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2477 return;
2478
19cc1087
JB
2479 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2480 mutex_lock(&priv->mutex);
2481 priv->vif = NULL;
2482 priv->is_open = 0;
2483 mutex_unlock(&priv->mutex);
2484 iwl_down(priv);
2485 ieee80211_restart_hw(priv->hw);
2486 } else {
2487 iwl_down(priv);
80676518
JB
2488
2489 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2490 return;
2491
2492 mutex_lock(&priv->mutex);
2493 __iwl_up(priv);
2494 mutex_unlock(&priv->mutex);
19cc1087 2495 }
b481de9c
ZY
2496}
2497
5b9f8cd3 2498static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2499{
c79dd5b5
TW
2500 struct iwl_priv *priv =
2501 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2502
2503 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2504 return;
2505
2506 mutex_lock(&priv->mutex);
a55360e4 2507 iwl_rx_replenish(priv);
b481de9c
ZY
2508 mutex_unlock(&priv->mutex);
2509}
2510
7878a5a4
MA
2511#define IWL_DELAY_NEXT_SCAN (HZ*2)
2512
5bbe233b 2513void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2514{
b481de9c 2515 struct ieee80211_conf *conf = NULL;
857485c0 2516 int ret = 0;
1ff50bda 2517 unsigned long flags;
b481de9c 2518
05c914fe 2519 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2520 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2521 return;
2522 }
2523
e1623446 2524 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2525 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2526
2527
2528 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2529 return;
2530
b481de9c 2531
508e32e1 2532 if (!priv->vif || !priv->is_open)
948c171c 2533 return;
508e32e1 2534
2a421b91 2535 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2536
b481de9c
ZY
2537 conf = ieee80211_get_hw_conf(priv->hw);
2538
2539 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2540 iwlcore_commit_rxon(priv);
b481de9c 2541
3195c1f3 2542 iwl_setup_rxon_timing(priv);
857485c0 2543 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2544 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2545 if (ret)
39aadf8c 2546 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2547 "Attempting to continue.\n");
2548
2549 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2550
42eb7c64 2551 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2552
45823531
AK
2553 if (priv->cfg->ops->hcmd->set_rxon_chain)
2554 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2555
b481de9c
ZY
2556 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2557
e1623446 2558 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2559 priv->assoc_id, priv->beacon_int);
2560
2561 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2562 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2563 else
2564 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2565
2566 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2567 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2568 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2569 else
2570 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2571
05c914fe 2572 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2573 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2574
2575 }
2576
e0158e61 2577 iwlcore_commit_rxon(priv);
b481de9c
ZY
2578
2579 switch (priv->iw_mode) {
05c914fe 2580 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2581 break;
2582
05c914fe 2583 case NL80211_IFTYPE_ADHOC:
b481de9c 2584
c46fbefa
AK
2585 /* assume default assoc id */
2586 priv->assoc_id = 1;
b481de9c 2587
4f40e4d9 2588 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2589 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2590
2591 break;
2592
2593 default:
15b1687c 2594 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2595 __func__, priv->iw_mode);
b481de9c
ZY
2596 break;
2597 }
2598
05c914fe 2599 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2600 priv->assoc_station_added = 1;
2601
1ff50bda
EG
2602 spin_lock_irqsave(&priv->lock, flags);
2603 iwl_activate_qos(priv, 0);
2604 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2605
04816448
GE
2606 /* the chain noise calibration will enabled PM upon completion
2607 * If chain noise has already been run, then we need to enable
2608 * power management here */
2609 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2610 iwl_power_update_mode(priv, false);
c90a74ba
EG
2611
2612 /* Enable Rx differential gain and sensitivity calibrations */
2613 iwl_chain_noise_reset(priv);
2614 priv->start_calib = 1;
2615
508e32e1
RC
2616}
2617
b481de9c
ZY
2618/*****************************************************************************
2619 *
2620 * mac80211 entry point functions
2621 *
2622 *****************************************************************************/
2623
154b25ce 2624#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2625
f0b6e2e8
RC
2626/*
2627 * Not a mac80211 entry point function, but it fits in with all the
2628 * other mac80211 functions grouped here.
2629 */
158bea07 2630static int iwl_mac_setup_register(struct iwl_priv *priv)
f0b6e2e8
RC
2631{
2632 int ret;
2633 struct ieee80211_hw *hw = priv->hw;
2634 hw->rate_control_algorithm = "iwl-agn-rs";
2635
2636 /* Tell mac80211 our characteristics */
2637 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2638 IEEE80211_HW_NOISE_DBM |
2639 IEEE80211_HW_AMPDU_AGGREGATION |
2640 IEEE80211_HW_SPECTRUM_MGMT;
2641
2642 if (!priv->cfg->broken_powersave)
2643 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2644 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2645
ba37a3d0
JB
2646 if (priv->cfg->sku & IWL_SKU_N)
2647 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2648 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2649
8d9698b3 2650 hw->sta_data_size = sizeof(struct iwl_station_priv);
f0b6e2e8
RC
2651 hw->wiphy->interface_modes =
2652 BIT(NL80211_IFTYPE_STATION) |
2653 BIT(NL80211_IFTYPE_ADHOC);
2654
f6c8f152 2655 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 2656 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC
2657
2658 /*
2659 * For now, disable PS by default because it affects
2660 * RX performance significantly.
2661 */
5be83de5 2662 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 2663
1382c71c 2664 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8
RC
2665 /* we create the 802.11 header and a zero-length SSID element */
2666 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2667
2668 /* Default value; 4 EDCA QOS priorities */
2669 hw->queues = 4;
2670
2671 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2672
2673 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2674 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2675 &priv->bands[IEEE80211_BAND_2GHZ];
2676 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2677 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2678 &priv->bands[IEEE80211_BAND_5GHZ];
2679
2680 ret = ieee80211_register_hw(priv->hw);
2681 if (ret) {
2682 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2683 return ret;
2684 }
2685 priv->mac80211_registered = 1;
2686
2687 return 0;
2688}
2689
2690
5b9f8cd3 2691static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2692{
c79dd5b5 2693 struct iwl_priv *priv = hw->priv;
5a66926a 2694 int ret;
b481de9c 2695
e1623446 2696 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2697
2698 /* we should be verifying the device is ready to be opened */
2699 mutex_lock(&priv->mutex);
5b9f8cd3 2700 ret = __iwl_up(priv);
b481de9c 2701 mutex_unlock(&priv->mutex);
5a66926a 2702
e655b9f0 2703 if (ret)
6cd0b1cb 2704 return ret;
e655b9f0 2705
c1842d61
TW
2706 if (iwl_is_rfkill(priv))
2707 goto out;
2708
e1623446 2709 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2710
fe9b6b72 2711 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2712 * mac80211 will not be run successfully. */
154b25ce
EG
2713 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2714 test_bit(STATUS_READY, &priv->status),
2715 UCODE_READY_TIMEOUT);
2716 if (!ret) {
2717 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2718 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2719 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2720 return -ETIMEDOUT;
5a66926a 2721 }
fe9b6b72 2722 }
0a078ffa 2723
e932a609
JB
2724 iwl_led_start(priv);
2725
c1842d61 2726out:
0a078ffa 2727 priv->is_open = 1;
e1623446 2728 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2729 return 0;
2730}
2731
5b9f8cd3 2732static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2733{
c79dd5b5 2734 struct iwl_priv *priv = hw->priv;
b481de9c 2735
e1623446 2736 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2737
19cc1087 2738 if (!priv->is_open)
e655b9f0 2739 return;
e655b9f0 2740
b481de9c 2741 priv->is_open = 0;
5a66926a 2742
5bddf549 2743 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2744 /* stop mac, cancel any scan request and clear
2745 * RXON_FILTER_ASSOC_MSK BIT
2746 */
5a66926a 2747 mutex_lock(&priv->mutex);
2a421b91 2748 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2749 mutex_unlock(&priv->mutex);
fde3571f
MA
2750 }
2751
5b9f8cd3 2752 iwl_down(priv);
5a66926a
ZY
2753
2754 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2755
2756 /* enable interrupts again in order to receive rfkill changes */
2757 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2758 iwl_enable_interrupts(priv);
948c171c 2759
e1623446 2760 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2761}
2762
5b9f8cd3 2763static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2764{
c79dd5b5 2765 struct iwl_priv *priv = hw->priv;
b481de9c 2766
e1623446 2767 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2768
e1623446 2769 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2770 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2771
e039fa4a 2772 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2773 dev_kfree_skb_any(skb);
2774
e1623446 2775 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2776 return NETDEV_TX_OK;
b481de9c
ZY
2777}
2778
60690a6a 2779void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2780{
857485c0 2781 int ret = 0;
1ff50bda 2782 unsigned long flags;
b481de9c 2783
d986bcd1 2784 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2785 return;
2786
2787 /* The following should be done only at AP bring up */
3195c1f3 2788 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2789
2790 /* RXON - unassoc (to set timing command) */
2791 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2792 iwlcore_commit_rxon(priv);
b481de9c
ZY
2793
2794 /* RXON Timing */
3195c1f3 2795 iwl_setup_rxon_timing(priv);
857485c0 2796 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2797 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2798 if (ret)
39aadf8c 2799 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2800 "Attempting to continue.\n");
2801
f513dfff
DH
2802 /* AP has all antennas */
2803 priv->chain_noise_data.active_chains =
2804 priv->hw_params.valid_rx_ant;
2805 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK
2806 if (priv->cfg->ops->hcmd->set_rxon_chain)
2807 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2808
2809 /* FIXME: what should be the assoc_id for AP? */
2810 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2811 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2812 priv->staging_rxon.flags |=
2813 RXON_FLG_SHORT_PREAMBLE_MSK;
2814 else
2815 priv->staging_rxon.flags &=
2816 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2817
2818 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2819 if (priv->assoc_capability &
2820 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2821 priv->staging_rxon.flags |=
2822 RXON_FLG_SHORT_SLOT_MSK;
2823 else
2824 priv->staging_rxon.flags &=
2825 ~RXON_FLG_SHORT_SLOT_MSK;
2826
05c914fe 2827 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2828 priv->staging_rxon.flags &=
2829 ~RXON_FLG_SHORT_SLOT_MSK;
2830 }
2831 /* restore RXON assoc */
2832 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2833 iwlcore_commit_rxon(priv);
f513dfff 2834 iwl_reset_qos(priv);
1ff50bda
EG
2835 spin_lock_irqsave(&priv->lock, flags);
2836 iwl_activate_qos(priv, 1);
2837 spin_unlock_irqrestore(&priv->lock, flags);
9a9ca65f 2838 iwl_add_bcast_station(priv);
e1493deb 2839 }
5b9f8cd3 2840 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2841
2842 /* FIXME - we need to add code here to detect a totally new
2843 * configuration, reset the AP, unassoc, rxon timing, assoc,
2844 * clear sta table, add BCAST sta... */
2845}
2846
5b9f8cd3 2847static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB
2848 struct ieee80211_vif *vif,
2849 struct ieee80211_key_conf *keyconf,
2850 struct ieee80211_sta *sta,
2851 u32 iv32, u16 *phase1key)
ab885f8c 2852{
ab885f8c 2853
9f58671e 2854 struct iwl_priv *priv = hw->priv;
e1623446 2855 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2856
b3fbdcf4
JB
2857 iwl_update_tkip_key(priv, keyconf,
2858 sta ? sta->addr : iwl_bcast_addr,
2859 iv32, phase1key);
ab885f8c 2860
e1623446 2861 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2862}
2863
5b9f8cd3 2864static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2865 struct ieee80211_vif *vif,
2866 struct ieee80211_sta *sta,
b481de9c
ZY
2867 struct ieee80211_key_conf *key)
2868{
c79dd5b5 2869 struct iwl_priv *priv = hw->priv;
42986796
WT
2870 const u8 *addr;
2871 int ret;
2872 u8 sta_id;
2873 bool is_default_wep_key = false;
b481de9c 2874
e1623446 2875 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2876
90e8e424 2877 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2878 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2879 return -EOPNOTSUPP;
2880 }
42986796 2881 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2882 sta_id = iwl_find_station(priv, addr);
6974e363 2883 if (sta_id == IWL_INVALID_STATION) {
e1623446 2884 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2885 addr);
6974e363 2886 return -EINVAL;
b481de9c 2887
deb09c43 2888 }
b481de9c 2889
6974e363 2890 mutex_lock(&priv->mutex);
2a421b91 2891 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2892 mutex_unlock(&priv->mutex);
2893
2894 /* If we are getting WEP group key and we didn't receive any key mapping
2895 * so far, we are in legacy wep mode (group key only), otherwise we are
2896 * in 1X mode.
2897 * In legacy wep mode, we use another host command to the uCode */
5425e490 2898 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2899 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2900 if (cmd == SET_KEY)
2901 is_default_wep_key = !priv->key_mapping_key;
2902 else
ccc038ab
EG
2903 is_default_wep_key =
2904 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2905 }
052c4b9f 2906
b481de9c 2907 switch (cmd) {
deb09c43 2908 case SET_KEY:
6974e363
EG
2909 if (is_default_wep_key)
2910 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2911 else
7480513f 2912 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2913
e1623446 2914 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2915 break;
2916 case DISABLE_KEY:
6974e363
EG
2917 if (is_default_wep_key)
2918 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2919 else
3ec47732 2920 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2921
e1623446 2922 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2923 break;
2924 default:
deb09c43 2925 ret = -EINVAL;
b481de9c
ZY
2926 }
2927
e1623446 2928 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2929
deb09c43 2930 return ret;
b481de9c
ZY
2931}
2932
5b9f8cd3 2933static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2934 struct ieee80211_vif *vif,
d783b061 2935 enum ieee80211_ampdu_mlme_action action,
17741cdc 2936 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2937{
2938 struct iwl_priv *priv = hw->priv;
5c2207c6 2939 int ret;
d783b061 2940
e1623446 2941 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2942 sta->addr, tid);
d783b061
TW
2943
2944 if (!(priv->cfg->sku & IWL_SKU_N))
2945 return -EACCES;
2946
2947 switch (action) {
2948 case IEEE80211_AMPDU_RX_START:
e1623446 2949 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2950 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2951 case IEEE80211_AMPDU_RX_STOP:
e1623446 2952 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2953 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2954 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2955 return 0;
2956 else
2957 return ret;
d783b061 2958 case IEEE80211_AMPDU_TX_START:
e1623446 2959 IWL_DEBUG_HT(priv, "start Tx\n");
ab9bdc34 2960 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2961 case IEEE80211_AMPDU_TX_STOP:
e1623446 2962 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2963 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2964 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2965 return 0;
2966 else
2967 return ret;
f0527971
WYG
2968 case IEEE80211_AMPDU_TX_OPERATIONAL:
2969 /* do nothing */
2970 return -EOPNOTSUPP;
d783b061 2971 default:
e1623446 2972 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2973 return -EINVAL;
2974 break;
2975 }
2976 return 0;
2977}
9f58671e 2978
5b9f8cd3 2979static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2980 struct ieee80211_low_level_stats *stats)
2981{
bf403db8
EK
2982 struct iwl_priv *priv = hw->priv;
2983
2984 priv = hw->priv;
e1623446
TW
2985 IWL_DEBUG_MAC80211(priv, "enter\n");
2986 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2987
2988 return 0;
2989}
2990
6ab10ff8
JB
2991static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
2992 struct ieee80211_vif *vif,
2993 enum sta_notify_cmd cmd,
2994 struct ieee80211_sta *sta)
2995{
2996 struct iwl_priv *priv = hw->priv;
2997 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
2998 int sta_id;
2999
3000 /*
3001 * TODO: We really should use this callback to
3002 * actually maintain the station table in
3003 * the device.
3004 */
3005
3006 switch (cmd) {
3007 case STA_NOTIFY_ADD:
3008 atomic_set(&sta_priv->pending_frames, 0);
3009 if (vif->type == NL80211_IFTYPE_AP)
3010 sta_priv->client = true;
3011 break;
3012 case STA_NOTIFY_SLEEP:
3013 WARN_ON(!sta_priv->client);
3014 sta_priv->asleep = true;
3015 if (atomic_read(&sta_priv->pending_frames) > 0)
3016 ieee80211_sta_block_awake(hw, sta, true);
3017 break;
3018 case STA_NOTIFY_AWAKE:
3019 WARN_ON(!sta_priv->client);
49dcc819
DH
3020 if (!sta_priv->asleep)
3021 break;
6ab10ff8
JB
3022 sta_priv->asleep = false;
3023 sta_id = iwl_find_station(priv, sta->addr);
3024 if (sta_id != IWL_INVALID_STATION)
3025 iwl_sta_modify_ps_wake(priv, sta_id);
3026 break;
3027 default:
3028 break;
3029 }
3030}
3031
b481de9c
ZY
3032/*****************************************************************************
3033 *
3034 * sysfs attributes
3035 *
3036 *****************************************************************************/
3037
0a6857e7 3038#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3039
3040/*
3041 * The following adds a new attribute to the sysfs representation
c3a739fa 3042 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
3043 * used for controlling the debug level.
3044 *
3045 * See the level definitions in iwl for details.
a562a9dd 3046 *
3d816c77
RC
3047 * The debug_level being managed using sysfs below is a per device debug
3048 * level that is used instead of the global debug level if it (the per
3049 * device debug level) is set.
b481de9c 3050 */
8cf769c6
EK
3051static ssize_t show_debug_level(struct device *d,
3052 struct device_attribute *attr, char *buf)
b481de9c 3053{
3d816c77
RC
3054 struct iwl_priv *priv = dev_get_drvdata(d);
3055 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3056}
8cf769c6
EK
3057static ssize_t store_debug_level(struct device *d,
3058 struct device_attribute *attr,
b481de9c
ZY
3059 const char *buf, size_t count)
3060{
928841b1 3061 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3062 unsigned long val;
3063 int ret;
b481de9c 3064
9257746f
TW
3065 ret = strict_strtoul(buf, 0, &val);
3066 if (ret)
978785a3 3067 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3068 else {
3d816c77 3069 priv->debug_level = val;
20594eb0
WYG
3070 if (iwl_alloc_traffic_mem(priv))
3071 IWL_ERR(priv,
3072 "Not enough memory to generate traffic log\n");
3073 }
b481de9c
ZY
3074 return strnlen(buf, count);
3075}
3076
8cf769c6
EK
3077static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3078 show_debug_level, store_debug_level);
3079
b481de9c 3080
0a6857e7 3081#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3082
b481de9c
ZY
3083
3084static ssize_t show_temperature(struct device *d,
3085 struct device_attribute *attr, char *buf)
3086{
928841b1 3087 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3088
fee1247a 3089 if (!iwl_is_alive(priv))
b481de9c
ZY
3090 return -EAGAIN;
3091
91dbc5bd 3092 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
3093}
3094
3095static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3096
b481de9c
ZY
3097static ssize_t show_tx_power(struct device *d,
3098 struct device_attribute *attr, char *buf)
3099{
928841b1 3100 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
3101
3102 if (!iwl_is_ready_rf(priv))
3103 return sprintf(buf, "off\n");
3104 else
3105 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3106}
3107
3108static ssize_t store_tx_power(struct device *d,
3109 struct device_attribute *attr,
3110 const char *buf, size_t count)
3111{
928841b1 3112 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3113 unsigned long val;
3114 int ret;
b481de9c 3115
9257746f
TW
3116 ret = strict_strtoul(buf, 10, &val);
3117 if (ret)
978785a3 3118 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
3119 else {
3120 ret = iwl_set_tx_power(priv, val, false);
3121 if (ret)
3122 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
3123 ret);
3124 else
3125 ret = count;
3126 }
3127 return ret;
b481de9c
ZY
3128}
3129
3130static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3131
3132static ssize_t show_flags(struct device *d,
3133 struct device_attribute *attr, char *buf)
3134{
928841b1 3135 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3136
3137 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
3138}
3139
3140static ssize_t store_flags(struct device *d,
3141 struct device_attribute *attr,
3142 const char *buf, size_t count)
3143{
928841b1 3144 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3145 unsigned long val;
3146 u32 flags;
3147 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 3148 if (ret)
9257746f
TW
3149 return ret;
3150 flags = (u32)val;
b481de9c
ZY
3151
3152 mutex_lock(&priv->mutex);
3153 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
3154 /* Cancel any currently running scans... */
2a421b91 3155 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3156 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3157 else {
e1623446 3158 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 3159 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3160 iwlcore_commit_rxon(priv);
b481de9c
ZY
3161 }
3162 }
3163 mutex_unlock(&priv->mutex);
3164
3165 return count;
3166}
3167
3168static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3169
3170static ssize_t show_filter_flags(struct device *d,
3171 struct device_attribute *attr, char *buf)
3172{
928841b1 3173 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3174
3175 return sprintf(buf, "0x%04X\n",
3176 le32_to_cpu(priv->active_rxon.filter_flags));
3177}
3178
3179static ssize_t store_filter_flags(struct device *d,
3180 struct device_attribute *attr,
3181 const char *buf, size_t count)
3182{
928841b1 3183 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3184 unsigned long val;
3185 u32 filter_flags;
3186 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 3187 if (ret)
9257746f
TW
3188 return ret;
3189 filter_flags = (u32)val;
b481de9c
ZY
3190
3191 mutex_lock(&priv->mutex);
3192 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
3193 /* Cancel any currently running scans... */
2a421b91 3194 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3195 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3196 else {
e1623446 3197 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
3198 "0x%04X\n", filter_flags);
3199 priv->staging_rxon.filter_flags =
3200 cpu_to_le32(filter_flags);
e0158e61 3201 iwlcore_commit_rxon(priv);
b481de9c
ZY
3202 }
3203 }
3204 mutex_unlock(&priv->mutex);
3205
3206 return count;
3207}
3208
3209static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3210 store_filter_flags);
3211
b481de9c
ZY
3212
3213static ssize_t show_statistics(struct device *d,
3214 struct device_attribute *attr, char *buf)
3215{
c79dd5b5 3216 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 3217 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 3218 u32 len = 0, ofs = 0;
3ac7f146 3219 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
3220 int rc = 0;
3221
fee1247a 3222 if (!iwl_is_alive(priv))
b481de9c
ZY
3223 return -EAGAIN;
3224
3225 mutex_lock(&priv->mutex);
ef8d5529 3226 rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
b481de9c
ZY
3227 mutex_unlock(&priv->mutex);
3228
3229 if (rc) {
3230 len = sprintf(buf,
3231 "Error sending statistics request: 0x%08X\n", rc);
3232 return len;
3233 }
3234
3235 while (size && (PAGE_SIZE - len)) {
3236 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3237 PAGE_SIZE - len, 1);
3238 len = strlen(buf);
3239 if (PAGE_SIZE - len)
3240 buf[len++] = '\n';
3241
3242 ofs += 16;
3243 size -= min(size, 16U);
3244 }
3245
3246 return len;
3247}
3248
3249static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3250
01abfbb2
WYG
3251static ssize_t show_rts_ht_protection(struct device *d,
3252 struct device_attribute *attr, char *buf)
3253{
3254 struct iwl_priv *priv = dev_get_drvdata(d);
3255
3256 return sprintf(buf, "%s\n",
3257 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3258}
3259
3260static ssize_t store_rts_ht_protection(struct device *d,
3261 struct device_attribute *attr,
3262 const char *buf, size_t count)
3263{
3264 struct iwl_priv *priv = dev_get_drvdata(d);
3265 unsigned long val;
3266 int ret;
3267
3268 ret = strict_strtoul(buf, 10, &val);
3269 if (ret)
3270 IWL_INFO(priv, "Input is not in decimal form.\n");
3271 else {
3272 if (!iwl_is_associated(priv))
3273 priv->cfg->use_rts_for_ht = val ? true : false;
3274 else
3275 IWL_ERR(priv, "Sta associated with AP - "
3276 "Change protection mechanism is not allowed\n");
3277 ret = count;
3278 }
3279 return ret;
3280}
3281
3282static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3283 show_rts_ht_protection, store_rts_ht_protection);
3284
b481de9c 3285
b481de9c
ZY
3286/*****************************************************************************
3287 *
3288 * driver setup and teardown
3289 *
3290 *****************************************************************************/
3291
4e39317d 3292static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3293{
d21050c7 3294 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3295
3296 init_waitqueue_head(&priv->wait_command_queue);
3297
5b9f8cd3
EG
3298 INIT_WORK(&priv->restart, iwl_bg_restart);
3299 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3300 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3301 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
3302 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3303 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3304
2a421b91 3305 iwl_setup_scan_deferred_work(priv);
bb8c093b 3306
4e39317d
EG
3307 if (priv->cfg->ops->lib->setup_deferred_work)
3308 priv->cfg->ops->lib->setup_deferred_work(priv);
3309
3310 init_timer(&priv->statistics_periodic);
3311 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3312 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3313
a9e1cb6a
WYG
3314 init_timer(&priv->ucode_trace);
3315 priv->ucode_trace.data = (unsigned long)priv;
3316 priv->ucode_trace.function = iwl_bg_ucode_trace;
3317
ef850d7c
MA
3318 if (!priv->cfg->use_isr_legacy)
3319 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3320 iwl_irq_tasklet, (unsigned long)priv);
3321 else
3322 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3323 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
3324}
3325
4e39317d 3326static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3327{
4e39317d
EG
3328 if (priv->cfg->ops->lib->cancel_deferred_work)
3329 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3330
3ae6a054 3331 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 3332 cancel_delayed_work(&priv->scan_check);
88be0264 3333 cancel_work_sync(&priv->start_internal_scan);
b481de9c 3334 cancel_delayed_work(&priv->alive_start);
b481de9c 3335 cancel_work_sync(&priv->beacon_update);
4e39317d 3336 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3337 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY
3338}
3339
89f186a8
RC
3340static void iwl_init_hw_rates(struct iwl_priv *priv,
3341 struct ieee80211_rate *rates)
3342{
3343 int i;
3344
3345 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3346 rates[i].bitrate = iwl_rates[i].ieee * 5;
3347 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3348 rates[i].hw_value_short = i;
3349 rates[i].flags = 0;
3350 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3351 /*
3352 * If CCK != 1M then set short preamble rate flag.
3353 */
3354 rates[i].flags |=
3355 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3356 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3357 }
3358 }
3359}
3360
3361static int iwl_init_drv(struct iwl_priv *priv)
3362{
3363 int ret;
3364
3365 priv->ibss_beacon = NULL;
3366
89f186a8
RC
3367 spin_lock_init(&priv->sta_lock);
3368 spin_lock_init(&priv->hcmd_lock);
3369
3370 INIT_LIST_HEAD(&priv->free_frames);
3371
3372 mutex_init(&priv->mutex);
d2dfe6df 3373 mutex_init(&priv->sync_cmd_mutex);
89f186a8
RC
3374
3375 /* Clear the driver's (not device's) station table */
3376 iwl_clear_stations_table(priv);
3377
3378 priv->ieee_channels = NULL;
3379 priv->ieee_rates = NULL;
3380 priv->band = IEEE80211_BAND_2GHZ;
3381
3382 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3383 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3384 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
89f186a8 3385
8a472da4
WYG
3386 /* initialize force reset */
3387 priv->force_reset[IWL_RF_RESET].reset_duration =
3388 IWL_DELAY_NEXT_FORCE_RF_RESET;
3389 priv->force_reset[IWL_FW_RESET].reset_duration =
3390 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC
3391
3392 /* Choose which receivers/antennas to use */
3393 if (priv->cfg->ops->hcmd->set_rxon_chain)
3394 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3395
3396 iwl_init_scan_params(priv);
3397
3398 iwl_reset_qos(priv);
3399
3400 priv->qos_data.qos_active = 0;
3401 priv->qos_data.qos_cap.val = 0;
3402
3403 priv->rates_mask = IWL_RATES_MASK;
3404 /* Set the tx_power_user_lmt to the lowest power level
3405 * this value will get overwritten by channel max power avg
3406 * from eeprom */
3407 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
3408
3409 ret = iwl_init_channel_map(priv);
3410 if (ret) {
3411 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3412 goto err;
3413 }
3414
3415 ret = iwlcore_init_geos(priv);
3416 if (ret) {
3417 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3418 goto err_free_channel_map;
3419 }
3420 iwl_init_hw_rates(priv, priv->ieee_rates);
3421
3422 return 0;
3423
3424err_free_channel_map:
3425 iwl_free_channel_map(priv);
3426err:
3427 return ret;
3428}
3429
3430static void iwl_uninit_drv(struct iwl_priv *priv)
3431{
3432 iwl_calib_free_results(priv);
3433 iwlcore_free_geos(priv);
3434 iwl_free_channel_map(priv);
3435 kfree(priv->scan);
3436}
3437
5b9f8cd3 3438static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
3439 &dev_attr_flags.attr,
3440 &dev_attr_filter_flags.attr,
b481de9c 3441 &dev_attr_statistics.attr,
b481de9c 3442 &dev_attr_temperature.attr,
b481de9c 3443 &dev_attr_tx_power.attr,
01abfbb2 3444 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK
3445#ifdef CONFIG_IWLWIFI_DEBUG
3446 &dev_attr_debug_level.attr,
3447#endif
b481de9c
ZY
3448 NULL
3449};
3450
5b9f8cd3 3451static struct attribute_group iwl_attribute_group = {
b481de9c 3452 .name = NULL, /* put in device directory */
5b9f8cd3 3453 .attrs = iwl_sysfs_entries,
b481de9c
ZY
3454};
3455
5b9f8cd3
EG
3456static struct ieee80211_ops iwl_hw_ops = {
3457 .tx = iwl_mac_tx,
3458 .start = iwl_mac_start,
3459 .stop = iwl_mac_stop,
3460 .add_interface = iwl_mac_add_interface,
3461 .remove_interface = iwl_mac_remove_interface,
3462 .config = iwl_mac_config,
5b9f8cd3
EG
3463 .configure_filter = iwl_configure_filter,
3464 .set_key = iwl_mac_set_key,
3465 .update_tkip_key = iwl_mac_update_tkip_key,
3466 .get_stats = iwl_mac_get_stats,
5b9f8cd3
EG
3467 .conf_tx = iwl_mac_conf_tx,
3468 .reset_tsf = iwl_mac_reset_tsf,
3469 .bss_info_changed = iwl_bss_info_changed,
3470 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB
3471 .hw_scan = iwl_mac_hw_scan,
3472 .sta_notify = iwl_mac_sta_notify,
b481de9c
ZY
3473};
3474
5b9f8cd3 3475static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3476{
3477 int err = 0;
c79dd5b5 3478 struct iwl_priv *priv;
b481de9c 3479 struct ieee80211_hw *hw;
82b9a121 3480 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3481 unsigned long flags;
6cd0b1cb 3482 u16 pci_cmd;
b481de9c 3483
316c30d9
AK
3484 /************************
3485 * 1. Allocating HW data
3486 ************************/
3487
6440adb5
BC
3488 /* Disabling hardware scan means that mac80211 will perform scans
3489 * "the hard way", rather than using device's scan. */
1ea87396 3490 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3491 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
3492 dev_printk(KERN_DEBUG, &(pdev->dev),
3493 "Disabling hw_scan\n");
5b9f8cd3 3494 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3495 }
3496
5b9f8cd3 3497 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3498 if (!hw) {
b481de9c
ZY
3499 err = -ENOMEM;
3500 goto out;
3501 }
1d0a082d
AK
3502 priv = hw->priv;
3503 /* At this point both hw and priv are allocated. */
3504
b481de9c
ZY
3505 SET_IEEE80211_DEV(hw, &pdev->dev);
3506
e1623446 3507 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3508 priv->cfg = cfg;
b481de9c 3509 priv->pci_dev = pdev;
40cefda9 3510 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3511
0a6857e7 3512#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3513 atomic_set(&priv->restrict_refcnt, 0);
3514#endif
20594eb0
WYG
3515 if (iwl_alloc_traffic_mem(priv))
3516 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3517
316c30d9
AK
3518 /**************************
3519 * 2. Initializing PCI bus
3520 **************************/
3521 if (pci_enable_device(pdev)) {
3522 err = -ENODEV;
3523 goto out_ieee80211_free_hw;
3524 }
3525
3526 pci_set_master(pdev);
3527
093d874c 3528 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3529 if (!err)
093d874c 3530 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3531 if (err) {
093d874c 3532 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3533 if (!err)
093d874c 3534 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3535 /* both attempts failed: */
316c30d9 3536 if (err) {
978785a3 3537 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3538 goto out_pci_disable_device;
cc2a8ea8 3539 }
316c30d9
AK
3540 }
3541
3542 err = pci_request_regions(pdev, DRV_NAME);
3543 if (err)
3544 goto out_pci_disable_device;
3545
3546 pci_set_drvdata(pdev, priv);
3547
316c30d9
AK
3548
3549 /***********************
3550 * 3. Read REV register
3551 ***********************/
3552 priv->hw_base = pci_iomap(pdev, 0, 0);
3553 if (!priv->hw_base) {
3554 err = -ENODEV;
3555 goto out_pci_release_regions;
3556 }
3557
e1623446 3558 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3559 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3560 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3561
731a29b7 3562 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA
3563 * we should init now
3564 */
3565 spin_lock_init(&priv->reg_lock);
731a29b7 3566 spin_lock_init(&priv->lock);
4843b5a7
RC
3567
3568 /*
3569 * stop and reset the on-board processor just in case it is in a
3570 * strange state ... like being left stranded by a primary kernel
3571 * and this is now the kdump kernel trying to start up
3572 */
3573 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3574
b661c819 3575 iwl_hw_detect(priv);
978785a3 3576 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 3577 priv->cfg->name, priv->hw_rev);
316c30d9 3578
e7b63581
TW
3579 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3580 * PCI Tx retries from interfering with C3 CPU state */
3581 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3582
086ed117
MA
3583 iwl_prepare_card_hw(priv);
3584 if (!priv->hw_ready) {
3585 IWL_WARN(priv, "Failed, HW not ready\n");
3586 goto out_iounmap;
3587 }
3588
91238714
TW
3589 /*****************
3590 * 4. Read EEPROM
3591 *****************/
316c30d9
AK
3592 /* Read the EEPROM */
3593 err = iwl_eeprom_init(priv);
3594 if (err) {
15b1687c 3595 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3596 goto out_iounmap;
3597 }
8614f360
TW
3598 err = iwl_eeprom_check_version(priv);
3599 if (err)
c8f16138 3600 goto out_free_eeprom;
8614f360 3601
02883017 3602 /* extract MAC Address */
316c30d9 3603 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3604 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3605 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3606
3607 /************************
3608 * 5. Setup HW constants
3609 ************************/
da154e30 3610 if (iwl_set_hw_params(priv)) {
15b1687c 3611 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3612 goto out_free_eeprom;
316c30d9
AK
3613 }
3614
3615 /*******************
6ba87956 3616 * 6. Setup priv
316c30d9 3617 *******************/
b481de9c 3618
6ba87956 3619 err = iwl_init_drv(priv);
bf85ea4f 3620 if (err)
399f4900 3621 goto out_free_eeprom;
bf85ea4f 3622 /* At this point both hw and priv are initialized. */
316c30d9 3623
316c30d9 3624 /********************
09f9bf79 3625 * 7. Setup services
316c30d9 3626 ********************/
0359facc 3627 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3628 iwl_disable_interrupts(priv);
0359facc 3629 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3630
6cd0b1cb
HS
3631 pci_enable_msi(priv->pci_dev);
3632
ef850d7c
MA
3633 iwl_alloc_isr_ict(priv);
3634 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3635 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3636 if (err) {
3637 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3638 goto out_disable_msi;
3639 }
5b9f8cd3 3640 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3641 if (err) {
15b1687c 3642 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3643 goto out_free_irq;
316c30d9
AK
3644 }
3645
4e39317d 3646 iwl_setup_deferred_work(priv);
653fa4a0 3647 iwl_setup_rx_handlers(priv);
316c30d9 3648
158bea07
JB
3649 /*********************************************
3650 * 8. Enable interrupts and read RFKILL state
3651 *********************************************/
6ba87956 3652
6cd0b1cb
HS
3653 /* enable interrupts if needed: hw bug w/a */
3654 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3655 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3656 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3657 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3658 }
3659
3660 iwl_enable_interrupts(priv);
3661
6cd0b1cb
HS
3662 /* If platform's RF_KILL switch is NOT set to KILL */
3663 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3664 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3665 else
3666 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3667
a60e77e5
JB
3668 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3669 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3670
58d0f361 3671 iwl_power_initialize(priv);
39b73fb1 3672 iwl_tt_initialize(priv);
158bea07 3673
b08dfd04 3674 err = iwl_request_firmware(priv, true);
158bea07
JB
3675 if (err)
3676 goto out_remove_sysfs;
3677
b481de9c
ZY
3678 return 0;
3679
316c30d9 3680 out_remove_sysfs:
c8f16138
RC
3681 destroy_workqueue(priv->workqueue);
3682 priv->workqueue = NULL;
5b9f8cd3 3683 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3684 out_free_irq:
3685 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3686 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3687 out_disable_msi:
3688 pci_disable_msi(priv->pci_dev);
6ba87956 3689 iwl_uninit_drv(priv);
073d3f5f
TW
3690 out_free_eeprom:
3691 iwl_eeprom_free(priv);
b481de9c
ZY
3692 out_iounmap:
3693 pci_iounmap(pdev, priv->hw_base);
3694 out_pci_release_regions:
316c30d9 3695 pci_set_drvdata(pdev, NULL);
623d563e 3696 pci_release_regions(pdev);
b481de9c
ZY
3697 out_pci_disable_device:
3698 pci_disable_device(pdev);
b481de9c 3699 out_ieee80211_free_hw:
20594eb0 3700 iwl_free_traffic_mem(priv);
d7c76f4c 3701 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3702 out:
3703 return err;
3704}
3705
5b9f8cd3 3706static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3707{
c79dd5b5 3708 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3709 unsigned long flags;
b481de9c
ZY
3710
3711 if (!priv)
3712 return;
3713
e1623446 3714 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3715
67249625 3716 iwl_dbgfs_unregister(priv);
5b9f8cd3 3717 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3718
5b9f8cd3
EG
3719 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3720 * to be called and iwl_down since we are removing the device
0b124c31
GG
3721 * we need to set STATUS_EXIT_PENDING bit.
3722 */
3723 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3724 if (priv->mac80211_registered) {
3725 ieee80211_unregister_hw(priv->hw);
3726 priv->mac80211_registered = 0;
0b124c31 3727 } else {
5b9f8cd3 3728 iwl_down(priv);
c4f55232
RR
3729 }
3730
c166b25a
BC
3731 /*
3732 * Make sure device is reset to low power before unloading driver.
3733 * This may be redundant with iwl_down(), but there are paths to
3734 * run iwl_down() without calling apm_ops.stop(), and there are
3735 * paths to avoid running iwl_down() at all before leaving driver.
3736 * This (inexpensive) call *makes sure* device is reset.
3737 */
3738 priv->cfg->ops->lib->apm_ops.stop(priv);
3739
39b73fb1
WYG
3740 iwl_tt_exit(priv);
3741
0359facc
MA
3742 /* make sure we flush any pending irq or
3743 * tasklet for the driver
3744 */
3745 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3746 iwl_disable_interrupts(priv);
0359facc
MA
3747 spin_unlock_irqrestore(&priv->lock, flags);
3748
3749 iwl_synchronize_irq(priv);
3750
5b9f8cd3 3751 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3752
3753 if (priv->rxq.bd)
a55360e4 3754 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3755 iwl_hw_txq_ctx_free(priv);
b481de9c 3756
c587de0b 3757 iwl_clear_stations_table(priv);
073d3f5f 3758 iwl_eeprom_free(priv);
b481de9c 3759
b481de9c 3760
948c171c
MA
3761 /*netif_stop_queue(dev); */
3762 flush_workqueue(priv->workqueue);
3763
5b9f8cd3 3764 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3765 * priv->workqueue... so we can't take down the workqueue
3766 * until now... */
3767 destroy_workqueue(priv->workqueue);
3768 priv->workqueue = NULL;
20594eb0 3769 iwl_free_traffic_mem(priv);
b481de9c 3770
6cd0b1cb
HS
3771 free_irq(priv->pci_dev->irq, priv);
3772 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3773 pci_iounmap(pdev, priv->hw_base);
3774 pci_release_regions(pdev);
3775 pci_disable_device(pdev);
3776 pci_set_drvdata(pdev, NULL);
3777
6ba87956 3778 iwl_uninit_drv(priv);
b481de9c 3779
ef850d7c
MA
3780 iwl_free_isr_ict(priv);
3781
b481de9c
ZY
3782 if (priv->ibss_beacon)
3783 dev_kfree_skb(priv->ibss_beacon);
3784
3785 ieee80211_free_hw(priv->hw);
3786}
3787
b481de9c
ZY
3788
3789/*****************************************************************************
3790 *
3791 * driver and module entry point
3792 *
3793 *****************************************************************************/
3794
fed9017e 3795/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 3796static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 3797#ifdef CONFIG_IWL4965
fed9017e
RR
3798 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3799 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3800#endif /* CONFIG_IWL4965 */
5a6a256e 3801#ifdef CONFIG_IWL5000
ac592574
WYG
3802/* 5100 Series WiFi */
3803 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3804 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3805 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3806 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3807 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3808 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3809 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3810 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3811 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3812 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3813 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3814 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3815 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3816 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3817 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3818 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3819 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3820 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3821 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3822 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3823 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3824 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3825 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3826 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3827
3828/* 5300 Series WiFi */
3829 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3830 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3831 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3832 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3833 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3834 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3835 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3836 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3837 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3838 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3839 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3840 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3841
3842/* 5350 Series WiFi/WiMax */
3843 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3844 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3845 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3846
3847/* 5150 Series Wifi/WiMax */
3848 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3849 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3850 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3851 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3852 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3853 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3854
3855 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3856 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3857 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3858 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG
3859
3860/* 6x00 Series */
5953a62e
WYG
3861 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3862 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3863 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3864 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3865 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3866 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3867 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3868 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3869 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3870 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3871
3872/* 6x50 WiFi/WiMax Series */
5953a62e
WYG
3873 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3874 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3875 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3876 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG
3877 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3878 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3879
77dcb6a9 3880/* 1000 Series WiFi */
4bd0914f
WYG
3881 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3882 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3883 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3884 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3885 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3886 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3887 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3888 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3889 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3890 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3891 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3892 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 3893#endif /* CONFIG_IWL5000 */
7100e924 3894
fed9017e
RR
3895 {0}
3896};
3897MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3898
3899static struct pci_driver iwl_driver = {
b481de9c 3900 .name = DRV_NAME,
fed9017e 3901 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3902 .probe = iwl_pci_probe,
3903 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3904#ifdef CONFIG_PM
5b9f8cd3
EG
3905 .suspend = iwl_pci_suspend,
3906 .resume = iwl_pci_resume,
b481de9c
ZY
3907#endif
3908};
3909
5b9f8cd3 3910static int __init iwl_init(void)
b481de9c
ZY
3911{
3912
3913 int ret;
3914 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3915 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3916
e227ceac 3917 ret = iwlagn_rate_control_register();
897e1cf2 3918 if (ret) {
a3139c59
SO
3919 printk(KERN_ERR DRV_NAME
3920 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3921 return ret;
3922 }
3923
fed9017e 3924 ret = pci_register_driver(&iwl_driver);
b481de9c 3925 if (ret) {
a3139c59 3926 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3927 goto error_register;
b481de9c 3928 }
b481de9c
ZY
3929
3930 return ret;
897e1cf2 3931
897e1cf2 3932error_register:
e227ceac 3933 iwlagn_rate_control_unregister();
897e1cf2 3934 return ret;
b481de9c
ZY
3935}
3936
5b9f8cd3 3937static void __exit iwl_exit(void)
b481de9c 3938{
fed9017e 3939 pci_unregister_driver(&iwl_driver);
e227ceac 3940 iwlagn_rate_control_unregister();
b481de9c
ZY
3941}
3942
5b9f8cd3
EG
3943module_exit(iwl_exit);
3944module_init(iwl_init);
a562a9dd
RC
3945
3946#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3947module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 3948MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 3949module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
3950MODULE_PARM_DESC(debug, "debug output mask");
3951#endif
3952