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[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
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43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO
47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
b481de9c
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
b481de9c
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64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
80bc5393 75#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
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92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
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101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
e0158e61 105int iwl_commit_rxon(struct iwl_priv *priv)
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106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
b481de9c
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115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
a326a5d0
EG
118 /* allow CTS-to-self if possible. this is relevant only for
119 * 5000, but will not damage 4965 */
120 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
b481de9c 121
8ccde88a 122 ret = iwl_check_rxon_cmd(priv);
43d59b32 123 if (ret) {
15b1687c 124 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
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125 return -EINVAL;
126 }
127
128 /* If we don't need to send a full RXON, we can use
5b9f8cd3 129 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 130 * and other flags for the current radio configuration. */
54559703 131 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
132 ret = iwl_send_rxon_assoc(priv);
133 if (ret) {
15b1687c 134 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 135 return ret;
b481de9c
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136 }
137
138 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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139 return 0;
140 }
141
142 /* station table will be cleared */
143 priv->assoc_station_added = 0;
144
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145 /* If we are currently associated and the new config requires
146 * an RXON_ASSOC and the new config wants the associated mask enabled,
147 * we must clear the associated from the active configuration
148 * before we apply the new config */
43d59b32 149 if (iwl_is_associated(priv) && new_assoc) {
e1623446 150 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
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151 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
152
43d59b32 153 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 154 sizeof(struct iwl_rxon_cmd),
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155 &priv->active_rxon);
156
157 /* If the mask clearing failed then we set
158 * active_rxon back to what it was previously */
43d59b32 159 if (ret) {
b481de9c 160 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 161 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 162 return ret;
b481de9c 163 }
b481de9c
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164 }
165
e1623446 166 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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167 "* with%s RXON_FILTER_ASSOC_MSK\n"
168 "* channel = %d\n"
e174961c 169 "* bssid = %pM\n",
43d59b32 170 (new_assoc ? "" : "out"),
b481de9c 171 le16_to_cpu(priv->staging_rxon.channel),
e174961c 172 priv->staging_rxon.bssid_addr);
b481de9c 173
90e8e424 174 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
175
176 /* Apply the new configuration
177 * RXON unassoc clears the station table in uCode, send it before
178 * we add the bcast station. If assoc bit is set, we will send RXON
179 * after having added the bcast and bssid station.
180 */
181 if (!new_assoc) {
182 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 183 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 184 if (ret) {
15b1687c 185 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
186 return ret;
187 }
188 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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189 }
190
c587de0b 191 iwl_clear_stations_table(priv);
556f8db7 192
19cc1087 193 priv->start_calib = 0;
b481de9c 194
b481de9c 195 /* Add the broadcast address so we can send broadcast frames */
4f40e4d9 196 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
43d59b32 197 IWL_INVALID_STATION) {
15b1687c 198 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
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199 return -EIO;
200 }
201
202 /* If we have set the ASSOC_MSK and we are in BSS mode then
203 * add the IWL_AP_ID to the station rate table */
9185159d 204 if (new_assoc) {
05c914fe 205 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
206 ret = iwl_rxon_add_station(priv,
207 priv->active_rxon.bssid_addr, 1);
208 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
209 IWL_ERR(priv,
210 "Error adding AP address for TX.\n");
9185159d
TW
211 return -EIO;
212 }
213 priv->assoc_station_added = 1;
214 if (priv->default_wep_key &&
215 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
216 IWL_ERR(priv,
217 "Could not send WEP static key.\n");
b481de9c 218 }
43d59b32
EG
219
220 /* Apply the new configuration
221 * RXON assoc doesn't clear the station table in uCode,
222 */
223 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
224 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
225 if (ret) {
15b1687c 226 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
227 return ret;
228 }
229 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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230 }
231
36da7d70
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232 iwl_init_sensitivity(priv);
233
234 /* If we issue a new RXON command which required a tune then we must
235 * send a new TXPOWER command or we won't be able to Tx any frames */
236 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
237 if (ret) {
15b1687c 238 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY
239 return ret;
240 }
241
b481de9c
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242 return 0;
243}
244
5b9f8cd3 245void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
246{
247
45823531
AK
248 if (priv->cfg->ops->hcmd->set_rxon_chain)
249 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 250 iwlcore_commit_rxon(priv);
5da4b55f
MA
251}
252
fcab423d 253static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
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254{
255 struct list_head *element;
256
e1623446 257 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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258 priv->frames_count);
259
260 while (!list_empty(&priv->free_frames)) {
261 element = priv->free_frames.next;
262 list_del(element);
fcab423d 263 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
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264 priv->frames_count--;
265 }
266
267 if (priv->frames_count) {
39aadf8c 268 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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269 priv->frames_count);
270 priv->frames_count = 0;
271 }
272}
273
fcab423d 274static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 275{
fcab423d 276 struct iwl_frame *frame;
b481de9c
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277 struct list_head *element;
278 if (list_empty(&priv->free_frames)) {
279 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
280 if (!frame) {
15b1687c 281 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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282 return NULL;
283 }
284
285 priv->frames_count++;
286 return frame;
287 }
288
289 element = priv->free_frames.next;
290 list_del(element);
fcab423d 291 return list_entry(element, struct iwl_frame, list);
b481de9c
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292}
293
fcab423d 294static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
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295{
296 memset(frame, 0, sizeof(*frame));
297 list_add(&frame->list, &priv->free_frames);
298}
299
4bf64efd
TW
300static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
301 struct ieee80211_hdr *hdr,
73ec1cc2 302 int left)
b481de9c 303{
3109ece1 304 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
305 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
306 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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307 return 0;
308
309 if (priv->ibss_beacon->len > left)
310 return 0;
311
312 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
313
314 return priv->ibss_beacon->len;
315}
316
5b9f8cd3 317static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
4bf64efd
TW
318 struct iwl_frame *frame, u8 rate)
319{
320 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
321 unsigned int frame_size;
322
323 tx_beacon_cmd = &frame->u.beacon;
324 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
325
326 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
327 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
328
329 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd
TW
330 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
331
332 BUG_ON(frame_size > MAX_MPDU_SIZE);
333 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
334
335 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
336 tx_beacon_cmd->tx.rate_n_flags =
337 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
338 else
339 tx_beacon_cmd->tx.rate_n_flags =
340 iwl_hw_set_rate_n_flags(rate, 0);
341
342 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
343 TX_CMD_FLG_TSF_MSK |
344 TX_CMD_FLG_STA_RATE_MSK;
345
346 return sizeof(*tx_beacon_cmd) + frame_size;
347}
5b9f8cd3 348static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 349{
fcab423d 350 struct iwl_frame *frame;
b481de9c
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351 unsigned int frame_size;
352 int rc;
353 u8 rate;
354
fcab423d 355 frame = iwl_get_free_frame(priv);
b481de9c
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356
357 if (!frame) {
15b1687c 358 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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359 "command.\n");
360 return -ENOMEM;
361 }
362
5b9f8cd3 363 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 364
5b9f8cd3 365 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 366
857485c0 367 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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368 &frame->u.cmd[0]);
369
fcab423d 370 iwl_free_frame(priv, frame);
b481de9c
ZY
371
372 return rc;
373}
374
7aaa1d79
SO
375static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
376{
377 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
378
379 dma_addr_t addr = get_unaligned_le32(&tb->lo);
380 if (sizeof(dma_addr_t) > sizeof(u32))
381 addr |=
382 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
383
384 return addr;
385}
386
387static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
388{
389 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
390
391 return le16_to_cpu(tb->hi_n_len) >> 4;
392}
393
394static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
395 dma_addr_t addr, u16 len)
396{
397 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
398 u16 hi_n_len = len << 4;
399
400 put_unaligned_le32(addr, &tb->lo);
401 if (sizeof(dma_addr_t) > sizeof(u32))
402 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
403
404 tb->hi_n_len = cpu_to_le16(hi_n_len);
405
406 tfd->num_tbs = idx + 1;
407}
408
409static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
410{
411 return tfd->num_tbs & 0x1f;
412}
413
414/**
415 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
416 * @priv - driver private data
417 * @txq - tx queue
418 *
419 * Does NOT advance any TFD circular buffer read/write indexes
420 * Does NOT free the TFD itself (which is within circular buffer)
421 */
422void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
423{
59606ffa 424 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
425 struct iwl_tfd *tfd;
426 struct pci_dev *dev = priv->pci_dev;
427 int index = txq->q.read_ptr;
428 int i;
429 int num_tbs;
430
431 tfd = &tfd_tmp[index];
432
433 /* Sanity check on number of chunks */
434 num_tbs = iwl_tfd_get_num_tbs(tfd);
435
436 if (num_tbs >= IWL_NUM_OF_TBS) {
437 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
438 /* @todo issue fatal error, it is quite serious situation */
439 return;
440 }
441
442 /* Unmap tx_cmd */
443 if (num_tbs)
444 pci_unmap_single(dev,
c2acea8e
JB
445 pci_unmap_addr(&txq->meta[index], mapping),
446 pci_unmap_len(&txq->meta[index], len),
96891cee 447 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
448
449 /* Unmap chunks, if any. */
450 for (i = 1; i < num_tbs; i++) {
451 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
452 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
453
454 if (txq->txb) {
455 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
456 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
457 }
458 }
459}
460
461int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
462 struct iwl_tx_queue *txq,
463 dma_addr_t addr, u16 len,
464 u8 reset, u8 pad)
465{
466 struct iwl_queue *q;
59606ffa 467 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
468 u32 num_tbs;
469
470 q = &txq->q;
59606ffa
SO
471 tfd_tmp = (struct iwl_tfd *)txq->tfds;
472 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
473
474 if (reset)
475 memset(tfd, 0, sizeof(*tfd));
476
477 num_tbs = iwl_tfd_get_num_tbs(tfd);
478
479 /* Each TFD can point to a maximum 20 Tx buffers */
480 if (num_tbs >= IWL_NUM_OF_TBS) {
481 IWL_ERR(priv, "Error can not send more than %d chunks\n",
482 IWL_NUM_OF_TBS);
483 return -EINVAL;
484 }
485
486 BUG_ON(addr & ~DMA_BIT_MASK(36));
487 if (unlikely(addr & ~IWL_TX_DMA_MASK))
488 IWL_ERR(priv, "Unaligned address = %llx\n",
489 (unsigned long long)addr);
490
491 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
492
493 return 0;
494}
495
a8e74e27
SO
496/*
497 * Tell nic where to find circular buffer of Tx Frame Descriptors for
498 * given Tx queue, and enable the DMA channel used for that queue.
499 *
500 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
501 * channels supported in hardware.
502 */
503int iwl_hw_tx_queue_init(struct iwl_priv *priv,
504 struct iwl_tx_queue *txq)
505{
a8e74e27
SO
506 int txq_id = txq->q.id;
507
a8e74e27
SO
508 /* Circular buffer (TFD queue in DRAM) physical base address */
509 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
510 txq->q.dma_addr >> 8);
511
a8e74e27
SO
512 return 0;
513}
514
b481de9c
ZY
515/******************************************************************************
516 *
517 * Generic RX handler implementations
518 *
519 ******************************************************************************/
885ba202
TW
520static void iwl_rx_reply_alive(struct iwl_priv *priv,
521 struct iwl_rx_mem_buffer *rxb)
b481de9c 522{
db11d634 523 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
885ba202 524 struct iwl_alive_resp *palive;
b481de9c
ZY
525 struct delayed_work *pwork;
526
527 palive = &pkt->u.alive_frame;
528
e1623446 529 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
530 "0x%01X 0x%01X\n",
531 palive->is_valid, palive->ver_type,
532 palive->ver_subtype);
533
534 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 535 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
536 memcpy(&priv->card_alive_init,
537 &pkt->u.alive_frame,
885ba202 538 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
539 pwork = &priv->init_alive_start;
540 } else {
e1623446 541 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 542 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 543 sizeof(struct iwl_alive_resp));
b481de9c
ZY
544 pwork = &priv->alive_start;
545 }
546
547 /* We delay the ALIVE response by 5ms to
548 * give the HW RF Kill time to activate... */
549 if (palive->is_valid == UCODE_VALID_OK)
550 queue_delayed_work(priv->workqueue, pwork,
551 msecs_to_jiffies(5));
552 else
39aadf8c 553 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
554}
555
5b9f8cd3 556static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 557{
c79dd5b5
TW
558 struct iwl_priv *priv =
559 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
560 struct sk_buff *beacon;
561
562 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 563 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
564
565 if (!beacon) {
15b1687c 566 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
567 return;
568 }
569
570 mutex_lock(&priv->mutex);
571 /* new beacon skb is allocated every time; dispose previous.*/
572 if (priv->ibss_beacon)
573 dev_kfree_skb(priv->ibss_beacon);
574
575 priv->ibss_beacon = beacon;
576 mutex_unlock(&priv->mutex);
577
5b9f8cd3 578 iwl_send_beacon_cmd(priv);
b481de9c
ZY
579}
580
4e39317d 581/**
5b9f8cd3 582 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
583 *
584 * This callback is provided in order to send a statistics request.
585 *
586 * This timer function is continually reset to execute within
587 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
588 * was received. We need to ensure we receive the statistics in order
589 * to update the temperature used for calibrating the TXPOWER.
590 */
5b9f8cd3 591static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
592{
593 struct iwl_priv *priv = (struct iwl_priv *)data;
594
595 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
596 return;
597
61780ee3
MA
598 /* dont send host command if rf-kill is on */
599 if (!iwl_is_ready_rf(priv))
600 return;
601
4e39317d
EG
602 iwl_send_statistics_request(priv, CMD_ASYNC);
603}
604
5b9f8cd3 605static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 606 struct iwl_rx_mem_buffer *rxb)
b481de9c 607{
0a6857e7 608#ifdef CONFIG_IWLWIFI_DEBUG
db11d634 609 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2aa6ab86
TW
610 struct iwl4965_beacon_notif *beacon =
611 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 612 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 613
e1623446 614 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 615 "tsf %d %d rate %d\n",
25a6572c 616 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
617 beacon->beacon_notify_hdr.failure_frame,
618 le32_to_cpu(beacon->ibss_mgr_status),
619 le32_to_cpu(beacon->high_tsf),
620 le32_to_cpu(beacon->low_tsf), rate);
621#endif
622
05c914fe 623 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
624 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
625 queue_work(priv->workqueue, &priv->beacon_update);
626}
627
b481de9c
ZY
628/* Handle notification from uCode that card's power state is changing
629 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 630static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 631 struct iwl_rx_mem_buffer *rxb)
b481de9c 632{
db11d634 633 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
634 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
635 unsigned long status = priv->status;
636
e1623446 637 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
638 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
639 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
640
641 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
642 RF_CARD_DISABLED)) {
643
3395f6e9 644 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
645 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
646
a8b50a0a
MA
647 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
648 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
649
650 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 651 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 652 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 653 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 654 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 655 }
39b73fb1
WYG
656 if (flags & RF_CARD_DISABLED)
657 iwl_tt_enter_ct_kill(priv);
b481de9c 658 }
39b73fb1
WYG
659 if (!(flags & RF_CARD_DISABLED))
660 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
661
662 if (flags & HW_CARD_DISABLED)
663 set_bit(STATUS_RF_KILL_HW, &priv->status);
664 else
665 clear_bit(STATUS_RF_KILL_HW, &priv->status);
666
667
b481de9c 668 if (!(flags & RXON_CARD_DISABLED))
2a421b91 669 iwl_scan_cancel(priv);
b481de9c
ZY
670
671 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
672 test_bit(STATUS_RF_KILL_HW, &priv->status)))
673 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
674 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
675 else
676 wake_up_interruptible(&priv->wait_command_queue);
677}
678
5b9f8cd3 679int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 680{
e2e3c57b 681 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 682 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
683 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
684 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
685 ~APMG_PS_CTRL_MSK_PWR_SRC);
686 } else {
687 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
688 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
689 ~APMG_PS_CTRL_MSK_PWR_SRC);
690 }
691
a8b50a0a 692 return 0;
e2e3c57b
TW
693}
694
b481de9c 695/**
5b9f8cd3 696 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
697 *
698 * Setup the RX handlers for each of the reply types sent from the uCode
699 * to the host.
700 *
701 * This function chains into the hardware specific files for them to setup
702 * any hardware specific handlers as well.
703 */
653fa4a0 704static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 705{
885ba202 706 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
707 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
708 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 709 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 710 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
711 iwl_rx_pm_debug_statistics_notif;
712 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 713
9fbab516
BC
714 /*
715 * The same handler is used for both the REPLY to a discrete
716 * statistics request from the host as well as for the periodic
717 * statistics notifications (after received beacons) from the uCode.
b481de9c 718 */
8f91aecb
EG
719 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
720 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 721
21c339bf 722 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
723 iwl_setup_rx_scan_handlers(priv);
724
37a44211 725 /* status change handler */
5b9f8cd3 726 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 727
c1354754
TW
728 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
729 iwl_rx_missed_beacon_notif;
37a44211 730 /* Rx handlers */
1781a07f
EG
731 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
732 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
733 /* block ack */
734 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 735 /* Set up hardware specific Rx handlers */
d4789efe 736 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
737}
738
b481de9c 739/**
a55360e4 740 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
741 *
742 * Uses the priv->rx_handlers callback function array to invoke
743 * the appropriate handlers, including command responses,
744 * frame-received notifications, and other notifications.
745 */
a55360e4 746void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 747{
a55360e4 748 struct iwl_rx_mem_buffer *rxb;
db11d634 749 struct iwl_rx_packet *pkt;
a55360e4 750 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
751 u32 r, i;
752 int reclaim;
753 unsigned long flags;
5c0eef96 754 u8 fill_rx = 0;
d68ab680 755 u32 count = 8;
4752c93c 756 int total_empty;
b481de9c 757
6440adb5
BC
758 /* uCode's read index (stored in shared DRAM) indicates the last Rx
759 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 760 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
761 i = rxq->read;
762
763 /* Rx interrupt, but nothing sent from uCode */
764 if (i == r)
e1623446 765 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 766
4752c93c
MA
767 /* calculate total frames need to be restock after handling RX */
768 total_empty = r - priv->rxq.write_actual;
769 if (total_empty < 0)
770 total_empty += RX_QUEUE_SIZE;
771
772 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
773 fill_rx = 1;
774
b481de9c
ZY
775 while (i != r) {
776 rxb = rxq->queue[i];
777
9fbab516 778 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
779 * then a bug has been introduced in the queue refilling
780 * routines -- catch it here */
781 BUG_ON(rxb == NULL);
782
783 rxq->queue[i] = NULL;
784
df833b1d
RC
785 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
786 priv->hw_params.rx_buf_size + 256,
787 PCI_DMA_FROMDEVICE);
db11d634 788 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
789
790 /* Reclaim a command buffer only if this packet is a response
791 * to a (driver-originated) command.
792 * If the packet (e.g. Rx frame) originated from uCode,
793 * there is no command buffer to reclaim.
794 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
795 * but apparently a few don't get set; catch them here. */
796 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
797 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 798 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 799 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 800 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
801 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
802 (pkt->hdr.cmd != REPLY_TX);
803
804 /* Based on type of command response or notification,
805 * handle those that need handling via function in
5b9f8cd3 806 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 807 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 808 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 809 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
b481de9c 810 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
a83b9141 811 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
b481de9c
ZY
812 } else {
813 /* No handling needed */
e1623446 814 IWL_DEBUG_RX(priv,
b481de9c
ZY
815 "r %d i %d No handler needed for %s, 0x%02x\n",
816 r, i, get_cmd_string(pkt->hdr.cmd),
817 pkt->hdr.cmd);
818 }
819
820 if (reclaim) {
9fbab516 821 /* Invoke any callbacks, transfer the skb to caller, and
857485c0 822 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY
823 * as we reclaim the driver command queue */
824 if (rxb && rxb->skb)
17b88929 825 iwl_tx_cmd_complete(priv, rxb);
b481de9c 826 else
39aadf8c 827 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
828 }
829
830 /* For now we just don't re-use anything. We can tweak this
831 * later to try and re-use notification packets and SKBs that
832 * fail to Rx correctly */
833 if (rxb->skb != NULL) {
834 priv->alloc_rxb_skb--;
835 dev_kfree_skb_any(rxb->skb);
836 rxb->skb = NULL;
837 }
838
b481de9c
ZY
839 spin_lock_irqsave(&rxq->lock, flags);
840 list_add_tail(&rxb->list, &priv->rxq.rx_used);
841 spin_unlock_irqrestore(&rxq->lock, flags);
842 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
843 /* If there are a lot of unused frames,
844 * restock the Rx queue so ucode wont assert. */
845 if (fill_rx) {
846 count++;
847 if (count >= 8) {
848 priv->rxq.read = i;
4752c93c 849 iwl_rx_replenish_now(priv);
5c0eef96
MA
850 count = 0;
851 }
852 }
b481de9c
ZY
853 }
854
855 /* Backtrack one entry */
856 priv->rxq.read = i;
4752c93c
MA
857 if (fill_rx)
858 iwl_rx_replenish_now(priv);
859 else
860 iwl_rx_queue_restock(priv);
a55360e4 861}
a55360e4 862
0359facc
MA
863/* call this function to flush any scheduled tasklet */
864static inline void iwl_synchronize_irq(struct iwl_priv *priv)
865{
a96a27f9 866 /* wait to make sure we flush pending tasklet*/
0359facc
MA
867 synchronize_irq(priv->pci_dev->irq);
868 tasklet_kill(&priv->irq_tasklet);
869}
870
ef850d7c 871static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
872{
873 u32 inta, handled = 0;
874 u32 inta_fh;
875 unsigned long flags;
0a6857e7 876#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
877 u32 inta_mask;
878#endif
879
880 spin_lock_irqsave(&priv->lock, flags);
881
882 /* Ack/clear/reset pending uCode interrupts.
883 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
884 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
885 inta = iwl_read32(priv, CSR_INT);
886 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
887
888 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
889 * Any new interrupts that happen after this, either while we're
890 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
891 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
892 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 893
0a6857e7 894#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 895 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 896 /* just for debug */
3395f6e9 897 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 898 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
899 inta, inta_mask, inta_fh);
900 }
901#endif
902
903 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
904 * atomic, make sure that inta covers all the interrupts that
905 * we've discovered, even if FH interrupt came in just after
906 * reading CSR_INT. */
6f83eaa1 907 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 908 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 909 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
910 inta |= CSR_INT_BIT_FH_TX;
911
912 /* Now service all interrupt bits discovered above. */
913 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 914 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
915
916 /* Tell the device to stop sending interrupts */
5b9f8cd3 917 iwl_disable_interrupts(priv);
b481de9c 918
a83b9141 919 priv->isr_stats.hw++;
5b9f8cd3 920 iwl_irq_handle_error(priv);
b481de9c
ZY
921
922 handled |= CSR_INT_BIT_HW_ERR;
923
924 spin_unlock_irqrestore(&priv->lock, flags);
925
926 return;
927 }
928
0a6857e7 929#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 930 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 931 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 932 if (inta & CSR_INT_BIT_SCD) {
e1623446 933 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 934 "the frame/frames.\n");
a83b9141
WYG
935 priv->isr_stats.sch++;
936 }
b481de9c
ZY
937
938 /* Alive notification via Rx interrupt will do the real work */
a83b9141 939 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 940 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
941 priv->isr_stats.alive++;
942 }
b481de9c
ZY
943 }
944#endif
945 /* Safely ignore these bits for debug checks below */
25c03d8e 946 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 947
9fbab516 948 /* HW RF KILL switch toggled */
b481de9c
ZY
949 if (inta & CSR_INT_BIT_RF_KILL) {
950 int hw_rf_kill = 0;
3395f6e9 951 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
952 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
953 hw_rf_kill = 1;
954
4c423a2b 955 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 956 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 957
a83b9141
WYG
958 priv->isr_stats.rfkill++;
959
a9efa652 960 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
961 * the driver allows loading the ucode even if the radio
962 * is killed. Hence update the killswitch state here. The
963 * rfkill handler will care about restarting if needed.
a9efa652 964 */
6cd0b1cb
HS
965 if (!test_bit(STATUS_ALIVE, &priv->status)) {
966 if (hw_rf_kill)
967 set_bit(STATUS_RF_KILL_HW, &priv->status);
968 else
969 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 970 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 971 }
b481de9c
ZY
972
973 handled |= CSR_INT_BIT_RF_KILL;
974 }
975
9fbab516 976 /* Chip got too hot and stopped itself */
b481de9c 977 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 978 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 979 priv->isr_stats.ctkill++;
b481de9c
ZY
980 handled |= CSR_INT_BIT_CT_KILL;
981 }
982
983 /* Error detected by uCode */
984 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
985 IWL_ERR(priv, "Microcode SW error detected. "
986 " Restarting 0x%X.\n", inta);
a83b9141
WYG
987 priv->isr_stats.sw++;
988 priv->isr_stats.sw_err = inta;
5b9f8cd3 989 iwl_irq_handle_error(priv);
b481de9c
ZY
990 handled |= CSR_INT_BIT_SW_ERR;
991 }
992
993 /* uCode wakes up after power-down sleep */
994 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 995 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 996 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
babcebfa
TW
997 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
998 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
999 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1000 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1001 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1002 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1003
a83b9141
WYG
1004 priv->isr_stats.wakeup++;
1005
b481de9c
ZY
1006 handled |= CSR_INT_BIT_WAKEUP;
1007 }
1008
1009 /* All uCode command responses, including Tx command responses,
1010 * Rx "responses" (frame-received notification), and other
1011 * notifications from uCode come through here*/
1012 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1013 iwl_rx_handle(priv);
a83b9141 1014 priv->isr_stats.rx++;
b481de9c
ZY
1015 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1016 }
1017
1018 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1019 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
a83b9141 1020 priv->isr_stats.tx++;
b481de9c 1021 handled |= CSR_INT_BIT_FH_TX;
dbb983b7
RR
1022 /* FH finished to write, send event */
1023 priv->ucode_write_complete = 1;
1024 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1025 }
1026
a83b9141 1027 if (inta & ~handled) {
15b1687c 1028 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1029 priv->isr_stats.unhandled++;
1030 }
b481de9c 1031
40cefda9 1032 if (inta & ~(priv->inta_mask)) {
39aadf8c 1033 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1034 inta & ~priv->inta_mask);
39aadf8c 1035 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1036 }
1037
1038 /* Re-enable all interrupts */
0359facc
MA
1039 /* only Re-enable if diabled by irq */
1040 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1041 iwl_enable_interrupts(priv);
b481de9c 1042
0a6857e7 1043#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1044 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1045 inta = iwl_read32(priv, CSR_INT);
1046 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1047 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1048 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1049 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1050 }
1051#endif
1052 spin_unlock_irqrestore(&priv->lock, flags);
1053}
1054
ef850d7c
MA
1055/* tasklet for iwlagn interrupt */
1056static void iwl_irq_tasklet(struct iwl_priv *priv)
1057{
1058 u32 inta = 0;
1059 u32 handled = 0;
1060 unsigned long flags;
1061#ifdef CONFIG_IWLWIFI_DEBUG
1062 u32 inta_mask;
1063#endif
1064
1065 spin_lock_irqsave(&priv->lock, flags);
1066
1067 /* Ack/clear/reset pending uCode interrupts.
1068 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1069 */
1070 iwl_write32(priv, CSR_INT, priv->inta);
1071
1072 inta = priv->inta;
1073
1074#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1075 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1076 /* just for debug */
1077 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1078 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1079 inta, inta_mask);
1080 }
1081#endif
1082 /* saved interrupt in inta variable now we can reset priv->inta */
1083 priv->inta = 0;
1084
1085 /* Now service all interrupt bits discovered above. */
1086 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1087 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1088
1089 /* Tell the device to stop sending interrupts */
1090 iwl_disable_interrupts(priv);
1091
1092 priv->isr_stats.hw++;
1093 iwl_irq_handle_error(priv);
1094
1095 handled |= CSR_INT_BIT_HW_ERR;
1096
1097 spin_unlock_irqrestore(&priv->lock, flags);
1098
1099 return;
1100 }
1101
1102#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1103 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1104 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1105 if (inta & CSR_INT_BIT_SCD) {
1106 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1107 "the frame/frames.\n");
1108 priv->isr_stats.sch++;
1109 }
1110
1111 /* Alive notification via Rx interrupt will do the real work */
1112 if (inta & CSR_INT_BIT_ALIVE) {
1113 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1114 priv->isr_stats.alive++;
1115 }
1116 }
1117#endif
1118 /* Safely ignore these bits for debug checks below */
1119 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1120
1121 /* HW RF KILL switch toggled */
1122 if (inta & CSR_INT_BIT_RF_KILL) {
1123 int hw_rf_kill = 0;
1124 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1125 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1126 hw_rf_kill = 1;
1127
4c423a2b 1128 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1129 hw_rf_kill ? "disable radio" : "enable radio");
1130
1131 priv->isr_stats.rfkill++;
1132
1133 /* driver only loads ucode once setting the interface up.
1134 * the driver allows loading the ucode even if the radio
1135 * is killed. Hence update the killswitch state here. The
1136 * rfkill handler will care about restarting if needed.
1137 */
1138 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1139 if (hw_rf_kill)
1140 set_bit(STATUS_RF_KILL_HW, &priv->status);
1141 else
1142 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1143 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1144 }
1145
1146 handled |= CSR_INT_BIT_RF_KILL;
1147 }
1148
1149 /* Chip got too hot and stopped itself */
1150 if (inta & CSR_INT_BIT_CT_KILL) {
1151 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1152 priv->isr_stats.ctkill++;
1153 handled |= CSR_INT_BIT_CT_KILL;
1154 }
1155
1156 /* Error detected by uCode */
1157 if (inta & CSR_INT_BIT_SW_ERR) {
1158 IWL_ERR(priv, "Microcode SW error detected. "
1159 " Restarting 0x%X.\n", inta);
1160 priv->isr_stats.sw++;
1161 priv->isr_stats.sw_err = inta;
1162 iwl_irq_handle_error(priv);
1163 handled |= CSR_INT_BIT_SW_ERR;
1164 }
1165
1166 /* uCode wakes up after power-down sleep */
1167 if (inta & CSR_INT_BIT_WAKEUP) {
1168 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1169 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1170 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1171 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1172 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1173 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1174 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1175 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1176
1177 priv->isr_stats.wakeup++;
1178
1179 handled |= CSR_INT_BIT_WAKEUP;
1180 }
1181
1182 /* All uCode command responses, including Tx command responses,
1183 * Rx "responses" (frame-received notification), and other
1184 * notifications from uCode come through here*/
40cefda9
MA
1185 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1186 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1187 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1188 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1189 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1190 iwl_write32(priv, CSR_FH_INT_STATUS,
1191 CSR49_FH_INT_RX_MASK);
1192 }
1193 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1194 handled |= CSR_INT_BIT_RX_PERIODIC;
1195 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1196 }
1197 /* Sending RX interrupt require many steps to be done in the
1198 * the device:
1199 * 1- write interrupt to current index in ICT table.
1200 * 2- dma RX frame.
1201 * 3- update RX shared data to indicate last write index.
1202 * 4- send interrupt.
1203 * This could lead to RX race, driver could receive RX interrupt
1204 * but the shared data changes does not reflect this.
1205 * this could lead to RX race, RX periodic will solve this race
1206 */
1207 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1208 CSR_INT_PERIODIC_DIS);
ef850d7c 1209 iwl_rx_handle(priv);
40cefda9
MA
1210 /* Only set RX periodic if real RX is received. */
1211 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1212 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1213 CSR_INT_PERIODIC_ENA);
1214
ef850d7c 1215 priv->isr_stats.rx++;
ef850d7c
MA
1216 }
1217
1218 if (inta & CSR_INT_BIT_FH_TX) {
1219 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1220 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
1221 priv->isr_stats.tx++;
1222 handled |= CSR_INT_BIT_FH_TX;
1223 /* FH finished to write, send event */
1224 priv->ucode_write_complete = 1;
1225 wake_up_interruptible(&priv->wait_command_queue);
1226 }
1227
1228 if (inta & ~handled) {
1229 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1230 priv->isr_stats.unhandled++;
1231 }
1232
40cefda9 1233 if (inta & ~(priv->inta_mask)) {
ef850d7c 1234 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1235 inta & ~priv->inta_mask);
ef850d7c
MA
1236 }
1237
1238
1239 /* Re-enable all interrupts */
1240 /* only Re-enable if diabled by irq */
1241 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1242 iwl_enable_interrupts(priv);
1243
1244 spin_unlock_irqrestore(&priv->lock, flags);
1245
1246}
1247
a83b9141 1248
b481de9c
ZY
1249/******************************************************************************
1250 *
1251 * uCode download functions
1252 *
1253 ******************************************************************************/
1254
5b9f8cd3 1255static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1256{
98c92211
TW
1257 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1258 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1259 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1260 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1261 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1262 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1263}
1264
5b9f8cd3 1265static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1266{
1267 /* Remove all resets to allow NIC to operate */
1268 iwl_write32(priv, CSR_RESET, 0);
1269}
1270
1271
b481de9c 1272/**
5b9f8cd3 1273 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1274 *
1275 * Copy into buffers for card to fetch via bus-mastering
1276 */
5b9f8cd3 1277static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1278{
cc0f555d 1279 struct iwl_ucode_header *ucode;
a0987a8d 1280 int ret = -EINVAL, index;
b481de9c 1281 const struct firmware *ucode_raw;
a0987a8d
RC
1282 const char *name_pre = priv->cfg->fw_name_pre;
1283 const unsigned int api_max = priv->cfg->ucode_api_max;
1284 const unsigned int api_min = priv->cfg->ucode_api_min;
1285 char buf[25];
b481de9c
ZY
1286 u8 *src;
1287 size_t len;
cc0f555d
JS
1288 u32 api_ver, build;
1289 u32 inst_size, data_size, init_size, init_data_size, boot_size;
abdc2d62 1290 u16 eeprom_ver;
b481de9c
ZY
1291
1292 /* Ask kernel firmware_class module to get the boot firmware off disk.
1293 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1294 for (index = api_max; index >= api_min; index--) {
1295 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1296 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1297 if (ret < 0) {
15b1687c 1298 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1299 buf, ret);
1300 if (ret == -ENOENT)
1301 continue;
1302 else
1303 goto error;
1304 } else {
1305 if (index < api_max)
15b1687c
WT
1306 IWL_ERR(priv, "Loaded firmware %s, "
1307 "which is deprecated. "
1308 "Please use API v%u instead.\n",
a0987a8d 1309 buf, api_max);
15b1687c 1310
e1623446 1311 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1312 buf, ucode_raw->size);
1313 break;
1314 }
b481de9c
ZY
1315 }
1316
a0987a8d
RC
1317 if (ret < 0)
1318 goto error;
b481de9c 1319
cc0f555d
JS
1320 /* Make sure that we got at least the v1 header! */
1321 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1322 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1323 ret = -EINVAL;
b481de9c
ZY
1324 goto err_release;
1325 }
1326
1327 /* Data from ucode file: header followed by uCode images */
cc0f555d 1328 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1329
c02b3acd 1330 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1331 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1332 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1333 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1334 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1335 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1336 init_data_size =
1337 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1338 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1339 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1340
a0987a8d
RC
1341 /* api_ver should match the api version forming part of the
1342 * firmware filename ... but we don't check for that and only rely
877d0310 1343 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1344
1345 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1346 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1347 "Driver supports v%u, firmware is v%u.\n",
1348 api_max, api_ver);
1349 priv->ucode_ver = 0;
1350 ret = -EINVAL;
1351 goto err_release;
1352 }
1353 if (api_ver != api_max)
978785a3 1354 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1355 "got v%u. New firmware can be obtained "
1356 "from http://www.intellinuxwireless.org.\n",
1357 api_max, api_ver);
1358
978785a3
TW
1359 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1360 IWL_UCODE_MAJOR(priv->ucode_ver),
1361 IWL_UCODE_MINOR(priv->ucode_ver),
1362 IWL_UCODE_API(priv->ucode_ver),
1363 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1364
cc0f555d
JS
1365 if (build)
1366 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1367
abdc2d62
JS
1368 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1369 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1370 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1371 ? "OTP" : "EEPROM", eeprom_ver);
1372
e1623446 1373 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1374 priv->ucode_ver);
e1623446 1375 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1376 inst_size);
e1623446 1377 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1378 data_size);
e1623446 1379 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1380 init_size);
e1623446 1381 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1382 init_data_size);
e1623446 1383 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1384 boot_size);
1385
1386 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1387 if (ucode_raw->size !=
1388 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1389 inst_size + data_size + init_size +
1390 init_data_size + boot_size) {
1391
cc0f555d
JS
1392 IWL_DEBUG_INFO(priv,
1393 "uCode file size %d does not match expected size\n",
1394 (int)ucode_raw->size);
90e759d1 1395 ret = -EINVAL;
b481de9c
ZY
1396 goto err_release;
1397 }
1398
1399 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1400 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1401 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1402 inst_size);
1403 ret = -EINVAL;
b481de9c
ZY
1404 goto err_release;
1405 }
1406
099b40b7 1407 if (data_size > priv->hw_params.max_data_size) {
e1623446 1408 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1409 data_size);
1410 ret = -EINVAL;
b481de9c
ZY
1411 goto err_release;
1412 }
099b40b7 1413 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1414 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1415 init_size);
90e759d1 1416 ret = -EINVAL;
b481de9c
ZY
1417 goto err_release;
1418 }
099b40b7 1419 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1420 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1421 init_data_size);
1422 ret = -EINVAL;
b481de9c
ZY
1423 goto err_release;
1424 }
099b40b7 1425 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1426 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1427 boot_size);
90e759d1 1428 ret = -EINVAL;
b481de9c
ZY
1429 goto err_release;
1430 }
1431
1432 /* Allocate ucode buffers for card's bus-master loading ... */
1433
1434 /* Runtime instructions and 2 copies of data:
1435 * 1) unmodified from disk
1436 * 2) backup cache for save/restore during power-downs */
1437 priv->ucode_code.len = inst_size;
98c92211 1438 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1439
1440 priv->ucode_data.len = data_size;
98c92211 1441 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1442
1443 priv->ucode_data_backup.len = data_size;
98c92211 1444 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1445
1f304e4e
ZY
1446 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1447 !priv->ucode_data_backup.v_addr)
1448 goto err_pci_alloc;
1449
b481de9c 1450 /* Initialization instructions and data */
90e759d1
TW
1451 if (init_size && init_data_size) {
1452 priv->ucode_init.len = init_size;
98c92211 1453 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1454
1455 priv->ucode_init_data.len = init_data_size;
98c92211 1456 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1457
1458 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1459 goto err_pci_alloc;
1460 }
b481de9c
ZY
1461
1462 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1463 if (boot_size) {
1464 priv->ucode_boot.len = boot_size;
98c92211 1465 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1466
90e759d1
TW
1467 if (!priv->ucode_boot.v_addr)
1468 goto err_pci_alloc;
1469 }
b481de9c
ZY
1470
1471 /* Copy images into buffers for card's bus-master reads ... */
1472
1473 /* Runtime instructions (first block of data in file) */
cc0f555d 1474 len = inst_size;
e1623446 1475 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1476 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1477 src += len;
1478
e1623446 1479 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1480 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1481
1482 /* Runtime data (2nd block)
5b9f8cd3 1483 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1484 len = data_size;
e1623446 1485 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1486 memcpy(priv->ucode_data.v_addr, src, len);
1487 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1488 src += len;
b481de9c
ZY
1489
1490 /* Initialization instructions (3rd block) */
1491 if (init_size) {
cc0f555d 1492 len = init_size;
e1623446 1493 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1494 len);
b481de9c 1495 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1496 src += len;
b481de9c
ZY
1497 }
1498
1499 /* Initialization data (4th block) */
1500 if (init_data_size) {
cc0f555d 1501 len = init_data_size;
e1623446 1502 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1503 len);
b481de9c 1504 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1505 src += len;
b481de9c
ZY
1506 }
1507
1508 /* Bootstrap instructions (5th block) */
cc0f555d 1509 len = boot_size;
e1623446 1510 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1511 memcpy(priv->ucode_boot.v_addr, src, len);
1512
1513 /* We have our copies now, allow OS release its copies */
1514 release_firmware(ucode_raw);
1515 return 0;
1516
1517 err_pci_alloc:
15b1687c 1518 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1519 ret = -ENOMEM;
5b9f8cd3 1520 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1521
1522 err_release:
1523 release_firmware(ucode_raw);
1524
1525 error:
90e759d1 1526 return ret;
b481de9c
ZY
1527}
1528
b7a79404
RC
1529#ifdef CONFIG_IWLWIFI_DEBUG
1530static const char *desc_lookup_text[] = {
1531 "OK",
1532 "FAIL",
1533 "BAD_PARAM",
1534 "BAD_CHECKSUM",
1535 "NMI_INTERRUPT_WDG",
1536 "SYSASSERT",
1537 "FATAL_ERROR",
1538 "BAD_COMMAND",
1539 "HW_ERROR_TUNE_LOCK",
1540 "HW_ERROR_TEMPERATURE",
1541 "ILLEGAL_CHAN_FREQ",
1542 "VCC_NOT_STABLE",
1543 "FH_ERROR",
1544 "NMI_INTERRUPT_HOST",
1545 "NMI_INTERRUPT_ACTION_PT",
1546 "NMI_INTERRUPT_UNKNOWN",
1547 "UCODE_VERSION_MISMATCH",
1548 "HW_ERROR_ABS_LOCK",
1549 "HW_ERROR_CAL_LOCK_FAIL",
1550 "NMI_INTERRUPT_INST_ACTION_PT",
1551 "NMI_INTERRUPT_DATA_ACTION_PT",
1552 "NMI_TRM_HW_ER",
1553 "NMI_INTERRUPT_TRM",
1554 "NMI_INTERRUPT_BREAK_POINT"
1555 "DEBUG_0",
1556 "DEBUG_1",
1557 "DEBUG_2",
1558 "DEBUG_3",
1559 "UNKNOWN"
1560};
1561
1562static const char *desc_lookup(int i)
1563{
1564 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1565
1566 if (i < 0 || i > max)
1567 i = max;
1568
1569 return desc_lookup_text[i];
1570}
1571
1572#define ERROR_START_OFFSET (1 * sizeof(u32))
1573#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1574
1575void iwl_dump_nic_error_log(struct iwl_priv *priv)
1576{
1577 u32 data2, line;
1578 u32 desc, time, count, base, data1;
1579 u32 blink1, blink2, ilink1, ilink2;
1580
1581 if (priv->ucode_type == UCODE_INIT)
1582 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1583 else
1584 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1585
1586 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1587 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1588 return;
1589 }
1590
1591 count = iwl_read_targ_mem(priv, base);
1592
1593 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1594 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1595 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1596 priv->status, count);
1597 }
1598
1599 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1600 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1601 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1602 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1603 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1604 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1605 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1606 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1607 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1608
1609 IWL_ERR(priv, "Desc Time "
1610 "data1 data2 line\n");
1611 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1612 desc_lookup(desc), desc, time, data1, data2, line);
1613 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1614 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1615 ilink1, ilink2);
1616
1617}
1618
1619#define EVENT_START_OFFSET (4 * sizeof(u32))
1620
1621/**
1622 * iwl_print_event_log - Dump error event log to syslog
1623 *
1624 */
1625static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1626 u32 num_events, u32 mode)
1627{
1628 u32 i;
1629 u32 base; /* SRAM byte address of event log header */
1630 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1631 u32 ptr; /* SRAM byte address of log data */
1632 u32 ev, time, data; /* event log data */
1633
1634 if (num_events == 0)
1635 return;
1636 if (priv->ucode_type == UCODE_INIT)
1637 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1638 else
1639 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1640
1641 if (mode == 0)
1642 event_size = 2 * sizeof(u32);
1643 else
1644 event_size = 3 * sizeof(u32);
1645
1646 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1647
1648 /* "time" is actually "data" for mode 0 (no timestamp).
1649 * place event id # at far right for easier visual parsing. */
1650 for (i = 0; i < num_events; i++) {
1651 ev = iwl_read_targ_mem(priv, ptr);
1652 ptr += sizeof(u32);
1653 time = iwl_read_targ_mem(priv, ptr);
1654 ptr += sizeof(u32);
1655 if (mode == 0) {
1656 /* data, ev */
1657 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1658 } else {
1659 data = iwl_read_targ_mem(priv, ptr);
1660 ptr += sizeof(u32);
1661 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1662 time, data, ev);
1663 }
1664 }
1665}
1666
1667void iwl_dump_nic_event_log(struct iwl_priv *priv)
1668{
1669 u32 base; /* SRAM byte address of event log header */
1670 u32 capacity; /* event log capacity in # entries */
1671 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1672 u32 num_wraps; /* # times uCode wrapped to top of log */
1673 u32 next_entry; /* index of next entry to be written by uCode */
1674 u32 size; /* # entries that we'll print */
1675
1676 if (priv->ucode_type == UCODE_INIT)
1677 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1678 else
1679 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1680
1681 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1682 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1683 return;
1684 }
1685
1686 /* event log header */
1687 capacity = iwl_read_targ_mem(priv, base);
1688 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1689 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1690 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1691
1692 size = num_wraps ? capacity : next_entry;
1693
1694 /* bail out if nothing in log */
1695 if (size == 0) {
1696 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1697 return;
1698 }
1699
1700 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1701 size, num_wraps);
1702
1703 /* if uCode has wrapped back to top of log, start at the oldest entry,
1704 * i.e the next one that uCode would fill. */
1705 if (num_wraps)
1706 iwl_print_event_log(priv, next_entry,
1707 capacity - next_entry, mode);
1708 /* (then/else) start at top of log */
1709 iwl_print_event_log(priv, 0, next_entry, mode);
1710
1711}
1712#endif
1713
b481de9c 1714/**
4a4a9e81 1715 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1716 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1717 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1718 */
4a4a9e81 1719static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1720{
57aab75a 1721 int ret = 0;
b481de9c 1722
e1623446 1723 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1724
1725 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1726 /* We had an error bringing up the hardware, so take it
1727 * all the way back down so we can try again */
e1623446 1728 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1729 goto restart;
1730 }
1731
1732 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1733 * This is a paranoid check, because we would not have gotten the
1734 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1735 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1736 /* Runtime instruction load was bad;
1737 * take it all the way back down so we can try again */
e1623446 1738 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1739 goto restart;
1740 }
1741
c587de0b 1742 iwl_clear_stations_table(priv);
57aab75a
TW
1743 ret = priv->cfg->ops->lib->alive_notify(priv);
1744 if (ret) {
39aadf8c
WT
1745 IWL_WARN(priv,
1746 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1747 goto restart;
1748 }
1749
5b9f8cd3 1750 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1751 set_bit(STATUS_ALIVE, &priv->status);
1752
fee1247a 1753 if (iwl_is_rfkill(priv))
b481de9c
ZY
1754 return;
1755
36d6825b 1756 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1757
1758 priv->active_rate = priv->rates_mask;
1759 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1760
3109ece1 1761 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1762 struct iwl_rxon_cmd *active_rxon =
1763 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1764 /* apply any changes in staging */
1765 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1766 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1767 } else {
1768 /* Initialize our rx_config data */
5b9f8cd3 1769 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
1770
1771 if (priv->cfg->ops->hcmd->set_rxon_chain)
1772 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1773
b481de9c
ZY
1774 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1775 }
1776
9fbab516 1777 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1778 iwl_send_bt_config(priv);
b481de9c 1779
4a4a9e81
TW
1780 iwl_reset_run_time_calib(priv);
1781
b481de9c 1782 /* Configure the adapter for unassociated operation */
e0158e61 1783 iwlcore_commit_rxon(priv);
b481de9c
ZY
1784
1785 /* At this point, the NIC is initialized and operational */
47f4a587 1786 iwl_rf_kill_ct_config(priv);
5a66926a 1787
fe00b5a5
RC
1788 iwl_leds_register(priv);
1789
e1623446 1790 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1791 set_bit(STATUS_READY, &priv->status);
5a66926a 1792 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1793
e312c24c 1794 iwl_power_update_mode(priv, true);
c46fbefa 1795
ada17513
MA
1796 /* reassociate for ADHOC mode */
1797 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1798 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1799 priv->vif);
1800 if (beacon)
1801 iwl_mac_beacon_update(priv->hw, beacon);
1802 }
1803
1804
c46fbefa 1805 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1806 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1807
b481de9c
ZY
1808 return;
1809
1810 restart:
1811 queue_work(priv->workqueue, &priv->restart);
1812}
1813
4e39317d 1814static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1815
5b9f8cd3 1816static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1817{
1818 unsigned long flags;
1819 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1820
e1623446 1821 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1822
b481de9c
ZY
1823 if (!exit_pending)
1824 set_bit(STATUS_EXIT_PENDING, &priv->status);
1825
ab53d8af
MA
1826 iwl_leds_unregister(priv);
1827
c587de0b 1828 iwl_clear_stations_table(priv);
b481de9c
ZY
1829
1830 /* Unblock any waiting calls */
1831 wake_up_interruptible_all(&priv->wait_command_queue);
1832
b481de9c
ZY
1833 /* Wipe out the EXIT_PENDING status bit if we are not actually
1834 * exiting the module */
1835 if (!exit_pending)
1836 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1837
1838 /* stop and reset the on-board processor */
3395f6e9 1839 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
1840
1841 /* tell the device to stop sending interrupts */
0359facc 1842 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1843 iwl_disable_interrupts(priv);
0359facc
MA
1844 spin_unlock_irqrestore(&priv->lock, flags);
1845 iwl_synchronize_irq(priv);
b481de9c
ZY
1846
1847 if (priv->mac80211_registered)
1848 ieee80211_stop_queues(priv->hw);
1849
5b9f8cd3 1850 /* If we have not previously called iwl_init() then
a60e77e5 1851 * clear all bits but the RF Kill bit and return */
fee1247a 1852 if (!iwl_is_init(priv)) {
b481de9c
ZY
1853 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1854 STATUS_RF_KILL_HW |
9788864e
RC
1855 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1856 STATUS_GEO_CONFIGURED |
052ec3f1
MA
1857 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1858 STATUS_EXIT_PENDING;
b481de9c
ZY
1859 goto exit;
1860 }
1861
6da3a13e 1862 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 1863 * bit and continue taking the NIC down. */
b481de9c
ZY
1864 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1865 STATUS_RF_KILL_HW |
9788864e
RC
1866 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1867 STATUS_GEO_CONFIGURED |
b481de9c 1868 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
1869 STATUS_FW_ERROR |
1870 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1871 STATUS_EXIT_PENDING;
b481de9c 1872
ef850d7c
MA
1873 /* device going down, Stop using ICT table */
1874 iwl_disable_ict(priv);
b481de9c 1875 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1876 iwl_clear_bit(priv, CSR_GP_CNTRL,
9fbab516 1877 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
1878 spin_unlock_irqrestore(&priv->lock, flags);
1879
da1bc453 1880 iwl_txq_ctx_stop(priv);
b3bbacb7 1881 iwl_rxq_stop(priv);
b481de9c 1882
a8b50a0a
MA
1883 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1884 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
1885
1886 udelay(5);
1887
7f066108 1888 /* FIXME: apm_ops.suspend(priv) */
6da3a13e 1889 if (exit_pending)
d535311e
GG
1890 priv->cfg->ops->lib->apm_ops.stop(priv);
1891 else
1892 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 1893 exit:
885ba202 1894 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
1895
1896 if (priv->ibss_beacon)
1897 dev_kfree_skb(priv->ibss_beacon);
1898 priv->ibss_beacon = NULL;
1899
1900 /* clear out any free frames */
fcab423d 1901 iwl_clear_free_frames(priv);
b481de9c
ZY
1902}
1903
5b9f8cd3 1904static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1905{
1906 mutex_lock(&priv->mutex);
5b9f8cd3 1907 __iwl_down(priv);
b481de9c 1908 mutex_unlock(&priv->mutex);
b24d22b1 1909
4e39317d 1910 iwl_cancel_deferred_work(priv);
b481de9c
ZY
1911}
1912
086ed117
MA
1913#define HW_READY_TIMEOUT (50)
1914
1915static int iwl_set_hw_ready(struct iwl_priv *priv)
1916{
1917 int ret = 0;
1918
1919 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1920 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1921
1922 /* See if we got it */
1923 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1924 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1925 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1926 HW_READY_TIMEOUT);
1927 if (ret != -ETIMEDOUT)
1928 priv->hw_ready = true;
1929 else
1930 priv->hw_ready = false;
1931
1932 IWL_DEBUG_INFO(priv, "hardware %s\n",
1933 (priv->hw_ready == 1) ? "ready" : "not ready");
1934 return ret;
1935}
1936
1937static int iwl_prepare_card_hw(struct iwl_priv *priv)
1938{
1939 int ret = 0;
1940
1941 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
1942
3354a0f6
MA
1943 ret = iwl_set_hw_ready(priv);
1944 if (priv->hw_ready)
1945 return ret;
1946
1947 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
1948 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1949 CSR_HW_IF_CONFIG_REG_PREPARE);
1950
1951 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1952 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
1953 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
1954
3354a0f6 1955 /* HW should be ready by now, check again. */
086ed117
MA
1956 if (ret != -ETIMEDOUT)
1957 iwl_set_hw_ready(priv);
1958
1959 return ret;
1960}
1961
b481de9c
ZY
1962#define MAX_HW_RESTARTS 5
1963
5b9f8cd3 1964static int __iwl_up(struct iwl_priv *priv)
b481de9c 1965{
57aab75a
TW
1966 int i;
1967 int ret;
b481de9c
ZY
1968
1969 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 1970 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
1971 return -EIO;
1972 }
1973
e903fbd4 1974 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 1975 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
1976 return -EIO;
1977 }
1978
086ed117
MA
1979 iwl_prepare_card_hw(priv);
1980
1981 if (!priv->hw_ready) {
1982 IWL_WARN(priv, "Exit HW not ready\n");
1983 return -EIO;
1984 }
1985
e655b9f0 1986 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 1987 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 1988 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1989 else
e655b9f0 1990 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1991
c1842d61 1992 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
1993 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
1994
5b9f8cd3 1995 iwl_enable_interrupts(priv);
a60e77e5 1996 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 1997 return 0;
b481de9c
ZY
1998 }
1999
3395f6e9 2000 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2001
1053d35f 2002 ret = iwl_hw_nic_init(priv);
57aab75a 2003 if (ret) {
15b1687c 2004 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2005 return ret;
b481de9c
ZY
2006 }
2007
2008 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2009 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2010 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2011 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2012
2013 /* clear (again), then enable host interrupts */
3395f6e9 2014 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2015 iwl_enable_interrupts(priv);
b481de9c
ZY
2016
2017 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2018 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2019 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2020
2021 /* Copy original ucode data image from disk into backup cache.
2022 * This will be used to initialize the on-board processor's
2023 * data SRAM for a clean start when the runtime program first loads. */
2024 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2025 priv->ucode_data.len);
b481de9c 2026
b481de9c
ZY
2027 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2028
c587de0b 2029 iwl_clear_stations_table(priv);
b481de9c
ZY
2030
2031 /* load bootstrap state machine,
2032 * load bootstrap program into processor's memory,
2033 * prepare to load the "initialize" uCode */
57aab75a 2034 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2035
57aab75a 2036 if (ret) {
15b1687c
WT
2037 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2038 ret);
b481de9c
ZY
2039 continue;
2040 }
2041
2042 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2043 iwl_nic_start(priv);
b481de9c 2044
e1623446 2045 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2046
2047 return 0;
2048 }
2049
2050 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2051 __iwl_down(priv);
64e72c3e 2052 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2053
2054 /* tried to restart and config the device for as long as our
2055 * patience could withstand */
15b1687c 2056 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2057 return -EIO;
2058}
2059
2060
2061/*****************************************************************************
2062 *
2063 * Workqueue callbacks
2064 *
2065 *****************************************************************************/
2066
4a4a9e81 2067static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2068{
c79dd5b5
TW
2069 struct iwl_priv *priv =
2070 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2071
2072 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2073 return;
2074
2075 mutex_lock(&priv->mutex);
f3ccc08c 2076 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2077 mutex_unlock(&priv->mutex);
2078}
2079
4a4a9e81 2080static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2081{
c79dd5b5
TW
2082 struct iwl_priv *priv =
2083 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2084
2085 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2086 return;
2087
258c44a0
MA
2088 /* enable dram interrupt */
2089 iwl_reset_ict(priv);
2090
b481de9c 2091 mutex_lock(&priv->mutex);
4a4a9e81 2092 iwl_alive_start(priv);
b481de9c
ZY
2093 mutex_unlock(&priv->mutex);
2094}
2095
16e727e8
EG
2096static void iwl_bg_run_time_calib_work(struct work_struct *work)
2097{
2098 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2099 run_time_calib_work);
2100
2101 mutex_lock(&priv->mutex);
2102
2103 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2104 test_bit(STATUS_SCANNING, &priv->status)) {
2105 mutex_unlock(&priv->mutex);
2106 return;
2107 }
2108
2109 if (priv->start_calib) {
2110 iwl_chain_noise_calibration(priv, &priv->statistics);
2111
2112 iwl_sensitivity_calibration(priv, &priv->statistics);
2113 }
2114
2115 mutex_unlock(&priv->mutex);
2116 return;
2117}
2118
5b9f8cd3 2119static void iwl_bg_up(struct work_struct *data)
b481de9c 2120{
c79dd5b5 2121 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2122
2123 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2124 return;
2125
2126 mutex_lock(&priv->mutex);
5b9f8cd3 2127 __iwl_up(priv);
b481de9c
ZY
2128 mutex_unlock(&priv->mutex);
2129}
2130
5b9f8cd3 2131static void iwl_bg_restart(struct work_struct *data)
b481de9c 2132{
c79dd5b5 2133 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2134
2135 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2136 return;
2137
19cc1087
JB
2138 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2139 mutex_lock(&priv->mutex);
2140 priv->vif = NULL;
2141 priv->is_open = 0;
2142 mutex_unlock(&priv->mutex);
2143 iwl_down(priv);
2144 ieee80211_restart_hw(priv->hw);
2145 } else {
2146 iwl_down(priv);
2147 queue_work(priv->workqueue, &priv->up);
2148 }
b481de9c
ZY
2149}
2150
5b9f8cd3 2151static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2152{
c79dd5b5
TW
2153 struct iwl_priv *priv =
2154 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2155
2156 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2157 return;
2158
2159 mutex_lock(&priv->mutex);
a55360e4 2160 iwl_rx_replenish(priv);
b481de9c
ZY
2161 mutex_unlock(&priv->mutex);
2162}
2163
7878a5a4
MA
2164#define IWL_DELAY_NEXT_SCAN (HZ*2)
2165
5bbe233b 2166void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2167{
b481de9c 2168 struct ieee80211_conf *conf = NULL;
857485c0 2169 int ret = 0;
1ff50bda 2170 unsigned long flags;
b481de9c 2171
05c914fe 2172 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2173 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2174 return;
2175 }
2176
e1623446 2177 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2178 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2179
2180
2181 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2182 return;
2183
b481de9c 2184
508e32e1 2185 if (!priv->vif || !priv->is_open)
948c171c 2186 return;
508e32e1 2187
2a421b91 2188 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2189
b481de9c
ZY
2190 conf = ieee80211_get_hw_conf(priv->hw);
2191
2192 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2193 iwlcore_commit_rxon(priv);
b481de9c 2194
3195c1f3 2195 iwl_setup_rxon_timing(priv);
857485c0 2196 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2197 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2198 if (ret)
39aadf8c 2199 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2200 "Attempting to continue.\n");
2201
2202 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2203
42eb7c64 2204 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2205
45823531
AK
2206 if (priv->cfg->ops->hcmd->set_rxon_chain)
2207 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2208
b481de9c
ZY
2209 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2210
e1623446 2211 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2212 priv->assoc_id, priv->beacon_int);
2213
2214 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2215 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2216 else
2217 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2218
2219 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2220 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2221 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2222 else
2223 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2224
05c914fe 2225 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2226 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2227
2228 }
2229
e0158e61 2230 iwlcore_commit_rxon(priv);
b481de9c
ZY
2231
2232 switch (priv->iw_mode) {
05c914fe 2233 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2234 break;
2235
05c914fe 2236 case NL80211_IFTYPE_ADHOC:
b481de9c 2237
c46fbefa
AK
2238 /* assume default assoc id */
2239 priv->assoc_id = 1;
b481de9c 2240
4f40e4d9 2241 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2242 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2243
2244 break;
2245
2246 default:
15b1687c 2247 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2248 __func__, priv->iw_mode);
b481de9c
ZY
2249 break;
2250 }
2251
05c914fe 2252 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2253 priv->assoc_station_added = 1;
2254
1ff50bda
EG
2255 spin_lock_irqsave(&priv->lock, flags);
2256 iwl_activate_qos(priv, 0);
2257 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2258
04816448
GE
2259 /* the chain noise calibration will enabled PM upon completion
2260 * If chain noise has already been run, then we need to enable
2261 * power management here */
2262 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2263 iwl_power_update_mode(priv, false);
c90a74ba
EG
2264
2265 /* Enable Rx differential gain and sensitivity calibrations */
2266 iwl_chain_noise_reset(priv);
2267 priv->start_calib = 1;
2268
508e32e1
RC
2269}
2270
b481de9c
ZY
2271/*****************************************************************************
2272 *
2273 * mac80211 entry point functions
2274 *
2275 *****************************************************************************/
2276
154b25ce 2277#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2278
5b9f8cd3 2279static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2280{
c79dd5b5 2281 struct iwl_priv *priv = hw->priv;
5a66926a 2282 int ret;
b481de9c 2283
e1623446 2284 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2285
2286 /* we should be verifying the device is ready to be opened */
2287 mutex_lock(&priv->mutex);
2288
5a66926a
ZY
2289 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2290 * ucode filename and max sizes are card-specific. */
b481de9c 2291
5a66926a 2292 if (!priv->ucode_code.len) {
5b9f8cd3 2293 ret = iwl_read_ucode(priv);
5a66926a 2294 if (ret) {
15b1687c 2295 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2296 mutex_unlock(&priv->mutex);
6cd0b1cb 2297 return ret;
5a66926a
ZY
2298 }
2299 }
b481de9c 2300
5b9f8cd3 2301 ret = __iwl_up(priv);
5a66926a 2302
b481de9c 2303 mutex_unlock(&priv->mutex);
5a66926a 2304
e655b9f0 2305 if (ret)
6cd0b1cb 2306 return ret;
e655b9f0 2307
c1842d61
TW
2308 if (iwl_is_rfkill(priv))
2309 goto out;
2310
e1623446 2311 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2312
fe9b6b72 2313 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2314 * mac80211 will not be run successfully. */
154b25ce
EG
2315 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2316 test_bit(STATUS_READY, &priv->status),
2317 UCODE_READY_TIMEOUT);
2318 if (!ret) {
2319 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2320 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2321 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2322 return -ETIMEDOUT;
5a66926a 2323 }
fe9b6b72 2324 }
0a078ffa 2325
c1842d61 2326out:
0a078ffa 2327 priv->is_open = 1;
e1623446 2328 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2329 return 0;
2330}
2331
5b9f8cd3 2332static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2333{
c79dd5b5 2334 struct iwl_priv *priv = hw->priv;
b481de9c 2335
e1623446 2336 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2337
19cc1087 2338 if (!priv->is_open)
e655b9f0 2339 return;
e655b9f0 2340
b481de9c 2341 priv->is_open = 0;
5a66926a 2342
5bddf549 2343 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2344 /* stop mac, cancel any scan request and clear
2345 * RXON_FILTER_ASSOC_MSK BIT
2346 */
5a66926a 2347 mutex_lock(&priv->mutex);
2a421b91 2348 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2349 mutex_unlock(&priv->mutex);
fde3571f
MA
2350 }
2351
5b9f8cd3 2352 iwl_down(priv);
5a66926a
ZY
2353
2354 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2355
2356 /* enable interrupts again in order to receive rfkill changes */
2357 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2358 iwl_enable_interrupts(priv);
948c171c 2359
e1623446 2360 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2361}
2362
5b9f8cd3 2363static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2364{
c79dd5b5 2365 struct iwl_priv *priv = hw->priv;
b481de9c 2366
e1623446 2367 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2368
e1623446 2369 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2370 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2371
e039fa4a 2372 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2373 dev_kfree_skb_any(skb);
2374
e1623446 2375 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2376 return NETDEV_TX_OK;
b481de9c
ZY
2377}
2378
60690a6a 2379void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2380{
857485c0 2381 int ret = 0;
1ff50bda 2382 unsigned long flags;
b481de9c 2383
d986bcd1 2384 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2385 return;
2386
2387 /* The following should be done only at AP bring up */
3195c1f3 2388 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2389
2390 /* RXON - unassoc (to set timing command) */
2391 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2392 iwlcore_commit_rxon(priv);
b481de9c
ZY
2393
2394 /* RXON Timing */
3195c1f3 2395 iwl_setup_rxon_timing(priv);
857485c0 2396 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2397 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2398 if (ret)
39aadf8c 2399 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2400 "Attempting to continue.\n");
2401
45823531
AK
2402 if (priv->cfg->ops->hcmd->set_rxon_chain)
2403 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2404
2405 /* FIXME: what should be the assoc_id for AP? */
2406 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2407 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2408 priv->staging_rxon.flags |=
2409 RXON_FLG_SHORT_PREAMBLE_MSK;
2410 else
2411 priv->staging_rxon.flags &=
2412 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2413
2414 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2415 if (priv->assoc_capability &
2416 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2417 priv->staging_rxon.flags |=
2418 RXON_FLG_SHORT_SLOT_MSK;
2419 else
2420 priv->staging_rxon.flags &=
2421 ~RXON_FLG_SHORT_SLOT_MSK;
2422
05c914fe 2423 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2424 priv->staging_rxon.flags &=
2425 ~RXON_FLG_SHORT_SLOT_MSK;
2426 }
2427 /* restore RXON assoc */
2428 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2429 iwlcore_commit_rxon(priv);
1ff50bda
EG
2430 spin_lock_irqsave(&priv->lock, flags);
2431 iwl_activate_qos(priv, 1);
2432 spin_unlock_irqrestore(&priv->lock, flags);
4f40e4d9 2433 iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
e1493deb 2434 }
5b9f8cd3 2435 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2436
2437 /* FIXME - we need to add code here to detect a totally new
2438 * configuration, reset the AP, unassoc, rxon timing, assoc,
2439 * clear sta table, add BCAST sta... */
2440}
2441
5b9f8cd3 2442static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2443 struct ieee80211_key_conf *keyconf, const u8 *addr,
2444 u32 iv32, u16 *phase1key)
2445{
ab885f8c 2446
9f58671e 2447 struct iwl_priv *priv = hw->priv;
e1623446 2448 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2449
9f58671e 2450 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2451
e1623446 2452 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2453}
2454
5b9f8cd3 2455static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2456 struct ieee80211_vif *vif,
2457 struct ieee80211_sta *sta,
b481de9c
ZY
2458 struct ieee80211_key_conf *key)
2459{
c79dd5b5 2460 struct iwl_priv *priv = hw->priv;
42986796
WT
2461 const u8 *addr;
2462 int ret;
2463 u8 sta_id;
2464 bool is_default_wep_key = false;
b481de9c 2465
e1623446 2466 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2467
90e8e424 2468 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2469 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2470 return -EOPNOTSUPP;
2471 }
42986796 2472 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2473 sta_id = iwl_find_station(priv, addr);
6974e363 2474 if (sta_id == IWL_INVALID_STATION) {
e1623446 2475 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2476 addr);
6974e363 2477 return -EINVAL;
b481de9c 2478
deb09c43 2479 }
b481de9c 2480
6974e363 2481 mutex_lock(&priv->mutex);
2a421b91 2482 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2483 mutex_unlock(&priv->mutex);
2484
2485 /* If we are getting WEP group key and we didn't receive any key mapping
2486 * so far, we are in legacy wep mode (group key only), otherwise we are
2487 * in 1X mode.
2488 * In legacy wep mode, we use another host command to the uCode */
5425e490 2489 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2490 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2491 if (cmd == SET_KEY)
2492 is_default_wep_key = !priv->key_mapping_key;
2493 else
ccc038ab
EG
2494 is_default_wep_key =
2495 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2496 }
052c4b9f 2497
b481de9c 2498 switch (cmd) {
deb09c43 2499 case SET_KEY:
6974e363
EG
2500 if (is_default_wep_key)
2501 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2502 else
7480513f 2503 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2504
e1623446 2505 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2506 break;
2507 case DISABLE_KEY:
6974e363
EG
2508 if (is_default_wep_key)
2509 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2510 else
3ec47732 2511 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2512
e1623446 2513 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2514 break;
2515 default:
deb09c43 2516 ret = -EINVAL;
b481de9c
ZY
2517 }
2518
e1623446 2519 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2520
deb09c43 2521 return ret;
b481de9c
ZY
2522}
2523
5b9f8cd3 2524static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
d783b061 2525 enum ieee80211_ampdu_mlme_action action,
17741cdc 2526 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2527{
2528 struct iwl_priv *priv = hw->priv;
5c2207c6 2529 int ret;
d783b061 2530
e1623446 2531 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2532 sta->addr, tid);
d783b061
TW
2533
2534 if (!(priv->cfg->sku & IWL_SKU_N))
2535 return -EACCES;
2536
2537 switch (action) {
2538 case IEEE80211_AMPDU_RX_START:
e1623446 2539 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2540 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2541 case IEEE80211_AMPDU_RX_STOP:
e1623446 2542 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2543 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2544 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2545 return 0;
2546 else
2547 return ret;
d783b061 2548 case IEEE80211_AMPDU_TX_START:
e1623446 2549 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2550 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2551 case IEEE80211_AMPDU_TX_STOP:
e1623446 2552 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2553 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2554 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2555 return 0;
2556 else
2557 return ret;
d783b061 2558 default:
e1623446 2559 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2560 return -EINVAL;
2561 break;
2562 }
2563 return 0;
2564}
9f58671e 2565
5b9f8cd3 2566static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2567 struct ieee80211_low_level_stats *stats)
2568{
bf403db8
EK
2569 struct iwl_priv *priv = hw->priv;
2570
2571 priv = hw->priv;
e1623446
TW
2572 IWL_DEBUG_MAC80211(priv, "enter\n");
2573 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2574
2575 return 0;
2576}
2577
b481de9c
ZY
2578/*****************************************************************************
2579 *
2580 * sysfs attributes
2581 *
2582 *****************************************************************************/
2583
0a6857e7 2584#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2585
2586/*
2587 * The following adds a new attribute to the sysfs representation
c3a739fa 2588 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2589 * used for controlling the debug level.
2590 *
2591 * See the level definitions in iwl for details.
a562a9dd 2592 *
3d816c77
RC
2593 * The debug_level being managed using sysfs below is a per device debug
2594 * level that is used instead of the global debug level if it (the per
2595 * device debug level) is set.
b481de9c 2596 */
8cf769c6
EK
2597static ssize_t show_debug_level(struct device *d,
2598 struct device_attribute *attr, char *buf)
b481de9c 2599{
3d816c77
RC
2600 struct iwl_priv *priv = dev_get_drvdata(d);
2601 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 2602}
8cf769c6
EK
2603static ssize_t store_debug_level(struct device *d,
2604 struct device_attribute *attr,
b481de9c
ZY
2605 const char *buf, size_t count)
2606{
928841b1 2607 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2608 unsigned long val;
2609 int ret;
b481de9c 2610
9257746f
TW
2611 ret = strict_strtoul(buf, 0, &val);
2612 if (ret)
978785a3 2613 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 2614 else {
3d816c77 2615 priv->debug_level = val;
20594eb0
WYG
2616 if (iwl_alloc_traffic_mem(priv))
2617 IWL_ERR(priv,
2618 "Not enough memory to generate traffic log\n");
2619 }
b481de9c
ZY
2620 return strnlen(buf, count);
2621}
2622
8cf769c6
EK
2623static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2624 show_debug_level, store_debug_level);
2625
b481de9c 2626
0a6857e7 2627#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2628
b481de9c
ZY
2629
2630static ssize_t show_temperature(struct device *d,
2631 struct device_attribute *attr, char *buf)
2632{
928841b1 2633 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 2634
fee1247a 2635 if (!iwl_is_alive(priv))
b481de9c
ZY
2636 return -EAGAIN;
2637
91dbc5bd 2638 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2639}
2640
2641static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2642
b481de9c
ZY
2643static ssize_t show_tx_power(struct device *d,
2644 struct device_attribute *attr, char *buf)
2645{
928841b1 2646 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
2647
2648 if (!iwl_is_ready_rf(priv))
2649 return sprintf(buf, "off\n");
2650 else
2651 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2652}
2653
2654static ssize_t store_tx_power(struct device *d,
2655 struct device_attribute *attr,
2656 const char *buf, size_t count)
2657{
928841b1 2658 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2659 unsigned long val;
2660 int ret;
b481de9c 2661
9257746f
TW
2662 ret = strict_strtoul(buf, 10, &val);
2663 if (ret)
978785a3 2664 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
2665 else {
2666 ret = iwl_set_tx_power(priv, val, false);
2667 if (ret)
2668 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
2669 ret);
2670 else
2671 ret = count;
2672 }
2673 return ret;
b481de9c
ZY
2674}
2675
2676static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2677
2678static ssize_t show_flags(struct device *d,
2679 struct device_attribute *attr, char *buf)
2680{
928841b1 2681 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2682
2683 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2684}
2685
2686static ssize_t store_flags(struct device *d,
2687 struct device_attribute *attr,
2688 const char *buf, size_t count)
2689{
928841b1 2690 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2691 unsigned long val;
2692 u32 flags;
2693 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2694 if (ret)
9257746f
TW
2695 return ret;
2696 flags = (u32)val;
b481de9c
ZY
2697
2698 mutex_lock(&priv->mutex);
2699 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2700 /* Cancel any currently running scans... */
2a421b91 2701 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2702 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2703 else {
e1623446 2704 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2705 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2706 iwlcore_commit_rxon(priv);
b481de9c
ZY
2707 }
2708 }
2709 mutex_unlock(&priv->mutex);
2710
2711 return count;
2712}
2713
2714static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2715
2716static ssize_t show_filter_flags(struct device *d,
2717 struct device_attribute *attr, char *buf)
2718{
928841b1 2719 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2720
2721 return sprintf(buf, "0x%04X\n",
2722 le32_to_cpu(priv->active_rxon.filter_flags));
2723}
2724
2725static ssize_t store_filter_flags(struct device *d,
2726 struct device_attribute *attr,
2727 const char *buf, size_t count)
2728{
928841b1 2729 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2730 unsigned long val;
2731 u32 filter_flags;
2732 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2733 if (ret)
9257746f
TW
2734 return ret;
2735 filter_flags = (u32)val;
b481de9c
ZY
2736
2737 mutex_lock(&priv->mutex);
2738 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2739 /* Cancel any currently running scans... */
2a421b91 2740 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2741 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2742 else {
e1623446 2743 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
2744 "0x%04X\n", filter_flags);
2745 priv->staging_rxon.filter_flags =
2746 cpu_to_le32(filter_flags);
e0158e61 2747 iwlcore_commit_rxon(priv);
b481de9c
ZY
2748 }
2749 }
2750 mutex_unlock(&priv->mutex);
2751
2752 return count;
2753}
2754
2755static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2756 store_filter_flags);
2757
b481de9c
ZY
2758
2759static ssize_t show_statistics(struct device *d,
2760 struct device_attribute *attr, char *buf)
2761{
c79dd5b5 2762 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 2763 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 2764 u32 len = 0, ofs = 0;
3ac7f146 2765 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
2766 int rc = 0;
2767
fee1247a 2768 if (!iwl_is_alive(priv))
b481de9c
ZY
2769 return -EAGAIN;
2770
2771 mutex_lock(&priv->mutex);
49ea8596 2772 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
2773 mutex_unlock(&priv->mutex);
2774
2775 if (rc) {
2776 len = sprintf(buf,
2777 "Error sending statistics request: 0x%08X\n", rc);
2778 return len;
2779 }
2780
2781 while (size && (PAGE_SIZE - len)) {
2782 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2783 PAGE_SIZE - len, 1);
2784 len = strlen(buf);
2785 if (PAGE_SIZE - len)
2786 buf[len++] = '\n';
2787
2788 ofs += 16;
2789 size -= min(size, 16U);
2790 }
2791
2792 return len;
2793}
2794
2795static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2796
b481de9c 2797
b481de9c
ZY
2798/*****************************************************************************
2799 *
2800 * driver setup and teardown
2801 *
2802 *****************************************************************************/
2803
4e39317d 2804static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2805{
d21050c7 2806 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
2807
2808 init_waitqueue_head(&priv->wait_command_queue);
2809
5b9f8cd3
EG
2810 INIT_WORK(&priv->up, iwl_bg_up);
2811 INIT_WORK(&priv->restart, iwl_bg_restart);
2812 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 2813 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 2814 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
2815 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2816 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 2817
2a421b91 2818 iwl_setup_scan_deferred_work(priv);
bb8c093b 2819
4e39317d
EG
2820 if (priv->cfg->ops->lib->setup_deferred_work)
2821 priv->cfg->ops->lib->setup_deferred_work(priv);
2822
2823 init_timer(&priv->statistics_periodic);
2824 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 2825 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 2826
ef850d7c
MA
2827 if (!priv->cfg->use_isr_legacy)
2828 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2829 iwl_irq_tasklet, (unsigned long)priv);
2830 else
2831 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2832 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
2833}
2834
4e39317d 2835static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2836{
4e39317d
EG
2837 if (priv->cfg->ops->lib->cancel_deferred_work)
2838 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 2839
3ae6a054 2840 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
2841 cancel_delayed_work(&priv->scan_check);
2842 cancel_delayed_work(&priv->alive_start);
b481de9c 2843 cancel_work_sync(&priv->beacon_update);
4e39317d 2844 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
2845}
2846
5b9f8cd3 2847static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
2848 &dev_attr_flags.attr,
2849 &dev_attr_filter_flags.attr,
b481de9c 2850 &dev_attr_statistics.attr,
b481de9c 2851 &dev_attr_temperature.attr,
b481de9c 2852 &dev_attr_tx_power.attr,
8cf769c6
EK
2853#ifdef CONFIG_IWLWIFI_DEBUG
2854 &dev_attr_debug_level.attr,
2855#endif
b481de9c
ZY
2856 NULL
2857};
2858
5b9f8cd3 2859static struct attribute_group iwl_attribute_group = {
b481de9c 2860 .name = NULL, /* put in device directory */
5b9f8cd3 2861 .attrs = iwl_sysfs_entries,
b481de9c
ZY
2862};
2863
5b9f8cd3
EG
2864static struct ieee80211_ops iwl_hw_ops = {
2865 .tx = iwl_mac_tx,
2866 .start = iwl_mac_start,
2867 .stop = iwl_mac_stop,
2868 .add_interface = iwl_mac_add_interface,
2869 .remove_interface = iwl_mac_remove_interface,
2870 .config = iwl_mac_config,
5b9f8cd3
EG
2871 .configure_filter = iwl_configure_filter,
2872 .set_key = iwl_mac_set_key,
2873 .update_tkip_key = iwl_mac_update_tkip_key,
2874 .get_stats = iwl_mac_get_stats,
2875 .get_tx_stats = iwl_mac_get_tx_stats,
2876 .conf_tx = iwl_mac_conf_tx,
2877 .reset_tsf = iwl_mac_reset_tsf,
2878 .bss_info_changed = iwl_bss_info_changed,
2879 .ampdu_action = iwl_mac_ampdu_action,
cb43dc25 2880 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
2881};
2882
5b9f8cd3 2883static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
2884{
2885 int err = 0;
c79dd5b5 2886 struct iwl_priv *priv;
b481de9c 2887 struct ieee80211_hw *hw;
82b9a121 2888 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 2889 unsigned long flags;
6cd0b1cb 2890 u16 pci_cmd;
b481de9c 2891
316c30d9
AK
2892 /************************
2893 * 1. Allocating HW data
2894 ************************/
2895
6440adb5
BC
2896 /* Disabling hardware scan means that mac80211 will perform scans
2897 * "the hard way", rather than using device's scan. */
1ea87396 2898 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 2899 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
2900 dev_printk(KERN_DEBUG, &(pdev->dev),
2901 "Disabling hw_scan\n");
5b9f8cd3 2902 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
2903 }
2904
5b9f8cd3 2905 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 2906 if (!hw) {
b481de9c
ZY
2907 err = -ENOMEM;
2908 goto out;
2909 }
1d0a082d
AK
2910 priv = hw->priv;
2911 /* At this point both hw and priv are allocated. */
2912
b481de9c
ZY
2913 SET_IEEE80211_DEV(hw, &pdev->dev);
2914
e1623446 2915 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 2916 priv->cfg = cfg;
b481de9c 2917 priv->pci_dev = pdev;
40cefda9 2918 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 2919
0a6857e7 2920#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2921 atomic_set(&priv->restrict_refcnt, 0);
2922#endif
20594eb0
WYG
2923 if (iwl_alloc_traffic_mem(priv))
2924 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 2925
316c30d9
AK
2926 /**************************
2927 * 2. Initializing PCI bus
2928 **************************/
2929 if (pci_enable_device(pdev)) {
2930 err = -ENODEV;
2931 goto out_ieee80211_free_hw;
2932 }
2933
2934 pci_set_master(pdev);
2935
093d874c 2936 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 2937 if (!err)
093d874c 2938 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 2939 if (err) {
093d874c 2940 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 2941 if (!err)
093d874c 2942 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 2943 /* both attempts failed: */
316c30d9 2944 if (err) {
978785a3 2945 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 2946 goto out_pci_disable_device;
cc2a8ea8 2947 }
316c30d9
AK
2948 }
2949
2950 err = pci_request_regions(pdev, DRV_NAME);
2951 if (err)
2952 goto out_pci_disable_device;
2953
2954 pci_set_drvdata(pdev, priv);
2955
316c30d9
AK
2956
2957 /***********************
2958 * 3. Read REV register
2959 ***********************/
2960 priv->hw_base = pci_iomap(pdev, 0, 0);
2961 if (!priv->hw_base) {
2962 err = -ENODEV;
2963 goto out_pci_release_regions;
2964 }
2965
e1623446 2966 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 2967 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 2968 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 2969
a8b50a0a
MA
2970 /* this spin lock will be used in apm_ops.init and EEPROM access
2971 * we should init now
2972 */
2973 spin_lock_init(&priv->reg_lock);
b661c819 2974 iwl_hw_detect(priv);
978785a3 2975 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 2976 priv->cfg->name, priv->hw_rev);
316c30d9 2977
e7b63581
TW
2978 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2979 * PCI Tx retries from interfering with C3 CPU state */
2980 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2981
086ed117
MA
2982 iwl_prepare_card_hw(priv);
2983 if (!priv->hw_ready) {
2984 IWL_WARN(priv, "Failed, HW not ready\n");
2985 goto out_iounmap;
2986 }
2987
91238714
TW
2988 /* amp init */
2989 err = priv->cfg->ops->lib->apm_ops.init(priv);
316c30d9 2990 if (err < 0) {
808ff697 2991 IWL_ERR(priv, "Failed to init APMG\n");
316c30d9
AK
2992 goto out_iounmap;
2993 }
91238714
TW
2994 /*****************
2995 * 4. Read EEPROM
2996 *****************/
316c30d9
AK
2997 /* Read the EEPROM */
2998 err = iwl_eeprom_init(priv);
2999 if (err) {
15b1687c 3000 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3001 goto out_iounmap;
3002 }
8614f360
TW
3003 err = iwl_eeprom_check_version(priv);
3004 if (err)
c8f16138 3005 goto out_free_eeprom;
8614f360 3006
02883017 3007 /* extract MAC Address */
316c30d9 3008 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3009 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3010 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3011
3012 /************************
3013 * 5. Setup HW constants
3014 ************************/
da154e30 3015 if (iwl_set_hw_params(priv)) {
15b1687c 3016 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3017 goto out_free_eeprom;
316c30d9
AK
3018 }
3019
3020 /*******************
6ba87956 3021 * 6. Setup priv
316c30d9 3022 *******************/
b481de9c 3023
6ba87956 3024 err = iwl_init_drv(priv);
bf85ea4f 3025 if (err)
399f4900 3026 goto out_free_eeprom;
bf85ea4f 3027 /* At this point both hw and priv are initialized. */
316c30d9 3028
316c30d9 3029 /********************
09f9bf79 3030 * 7. Setup services
316c30d9 3031 ********************/
0359facc 3032 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3033 iwl_disable_interrupts(priv);
0359facc 3034 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3035
6cd0b1cb
HS
3036 pci_enable_msi(priv->pci_dev);
3037
ef850d7c
MA
3038 iwl_alloc_isr_ict(priv);
3039 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3040 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3041 if (err) {
3042 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3043 goto out_disable_msi;
3044 }
5b9f8cd3 3045 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3046 if (err) {
15b1687c 3047 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3048 goto out_free_irq;
316c30d9
AK
3049 }
3050
4e39317d 3051 iwl_setup_deferred_work(priv);
653fa4a0 3052 iwl_setup_rx_handlers(priv);
316c30d9 3053
6ba87956 3054 /**********************************
09f9bf79 3055 * 8. Setup and register mac80211
6ba87956
TW
3056 **********************************/
3057
6cd0b1cb
HS
3058 /* enable interrupts if needed: hw bug w/a */
3059 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3060 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3061 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3062 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3063 }
3064
3065 iwl_enable_interrupts(priv);
3066
6ba87956
TW
3067 err = iwl_setup_mac(priv);
3068 if (err)
3069 goto out_remove_sysfs;
3070
3071 err = iwl_dbgfs_register(priv, DRV_NAME);
3072 if (err)
a75fbe8d 3073 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
6ba87956 3074
6cd0b1cb
HS
3075 /* If platform's RF_KILL switch is NOT set to KILL */
3076 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3077 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3078 else
3079 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3080
a60e77e5
JB
3081 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3082 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3083
58d0f361 3084 iwl_power_initialize(priv);
39b73fb1 3085 iwl_tt_initialize(priv);
b481de9c
ZY
3086 return 0;
3087
316c30d9 3088 out_remove_sysfs:
c8f16138
RC
3089 destroy_workqueue(priv->workqueue);
3090 priv->workqueue = NULL;
5b9f8cd3 3091 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3092 out_free_irq:
3093 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3094 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3095 out_disable_msi:
3096 pci_disable_msi(priv->pci_dev);
6ba87956 3097 iwl_uninit_drv(priv);
073d3f5f
TW
3098 out_free_eeprom:
3099 iwl_eeprom_free(priv);
b481de9c
ZY
3100 out_iounmap:
3101 pci_iounmap(pdev, priv->hw_base);
3102 out_pci_release_regions:
316c30d9 3103 pci_set_drvdata(pdev, NULL);
623d563e 3104 pci_release_regions(pdev);
b481de9c
ZY
3105 out_pci_disable_device:
3106 pci_disable_device(pdev);
b481de9c
ZY
3107 out_ieee80211_free_hw:
3108 ieee80211_free_hw(priv->hw);
20594eb0 3109 iwl_free_traffic_mem(priv);
b481de9c
ZY
3110 out:
3111 return err;
3112}
3113
5b9f8cd3 3114static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3115{
c79dd5b5 3116 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3117 unsigned long flags;
b481de9c
ZY
3118
3119 if (!priv)
3120 return;
3121
e1623446 3122 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3123
67249625 3124 iwl_dbgfs_unregister(priv);
5b9f8cd3 3125 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3126
5b9f8cd3
EG
3127 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3128 * to be called and iwl_down since we are removing the device
0b124c31
GG
3129 * we need to set STATUS_EXIT_PENDING bit.
3130 */
3131 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3132 if (priv->mac80211_registered) {
3133 ieee80211_unregister_hw(priv->hw);
3134 priv->mac80211_registered = 0;
0b124c31 3135 } else {
5b9f8cd3 3136 iwl_down(priv);
c4f55232
RR
3137 }
3138
39b73fb1
WYG
3139 iwl_tt_exit(priv);
3140
0359facc
MA
3141 /* make sure we flush any pending irq or
3142 * tasklet for the driver
3143 */
3144 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3145 iwl_disable_interrupts(priv);
0359facc
MA
3146 spin_unlock_irqrestore(&priv->lock, flags);
3147
3148 iwl_synchronize_irq(priv);
3149
5b9f8cd3 3150 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3151
3152 if (priv->rxq.bd)
a55360e4 3153 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3154 iwl_hw_txq_ctx_free(priv);
b481de9c 3155
c587de0b 3156 iwl_clear_stations_table(priv);
073d3f5f 3157 iwl_eeprom_free(priv);
b481de9c 3158
b481de9c 3159
948c171c
MA
3160 /*netif_stop_queue(dev); */
3161 flush_workqueue(priv->workqueue);
3162
5b9f8cd3 3163 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3164 * priv->workqueue... so we can't take down the workqueue
3165 * until now... */
3166 destroy_workqueue(priv->workqueue);
3167 priv->workqueue = NULL;
20594eb0 3168 iwl_free_traffic_mem(priv);
b481de9c 3169
6cd0b1cb
HS
3170 free_irq(priv->pci_dev->irq, priv);
3171 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3172 pci_iounmap(pdev, priv->hw_base);
3173 pci_release_regions(pdev);
3174 pci_disable_device(pdev);
3175 pci_set_drvdata(pdev, NULL);
3176
6ba87956 3177 iwl_uninit_drv(priv);
b481de9c 3178
ef850d7c
MA
3179 iwl_free_isr_ict(priv);
3180
b481de9c
ZY
3181 if (priv->ibss_beacon)
3182 dev_kfree_skb(priv->ibss_beacon);
3183
3184 ieee80211_free_hw(priv->hw);
3185}
3186
b481de9c
ZY
3187
3188/*****************************************************************************
3189 *
3190 * driver and module entry point
3191 *
3192 *****************************************************************************/
3193
fed9017e
RR
3194/* Hardware specific file defines the PCI IDs table for that hardware module */
3195static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3196#ifdef CONFIG_IWL4965
fed9017e
RR
3197 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3198 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3199#endif /* CONFIG_IWL4965 */
5a6a256e 3200#ifdef CONFIG_IWL5000
47408639
EK
3201 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3202 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3203 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3204 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3205 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3206 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3207 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK
3208 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3209 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3210 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW
3211/* 5350 WiFi/WiMax */
3212 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3213 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3214 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW
3215/* 5150 Wifi/WiMax */
3216 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3217 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
e1228374 3218/* 6000/6050 Series */
65b7998a
WYG
3219 {IWL_PCI_DEVICE(0x008D, PCI_ANY_ID, iwl6000h_2agn_cfg)},
3220 {IWL_PCI_DEVICE(0x008E, PCI_ANY_ID, iwl6000h_2agn_cfg)},
e1228374 3221 {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
65b7998a 3222 {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000i_2agn_cfg)},
e1228374 3223 {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
65b7998a 3224 {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000i_2agn_cfg)},
e1228374
JS
3225 {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
3226 {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
3227 {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
3228 {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
77dcb6a9
JS
3229/* 1000 Series WiFi */
3230 {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
3231 {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
5a6a256e 3232#endif /* CONFIG_IWL5000 */
7100e924 3233
fed9017e
RR
3234 {0}
3235};
3236MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3237
3238static struct pci_driver iwl_driver = {
b481de9c 3239 .name = DRV_NAME,
fed9017e 3240 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3241 .probe = iwl_pci_probe,
3242 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3243#ifdef CONFIG_PM
5b9f8cd3
EG
3244 .suspend = iwl_pci_suspend,
3245 .resume = iwl_pci_resume,
b481de9c
ZY
3246#endif
3247};
3248
5b9f8cd3 3249static int __init iwl_init(void)
b481de9c
ZY
3250{
3251
3252 int ret;
3253 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3254 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3255
e227ceac 3256 ret = iwlagn_rate_control_register();
897e1cf2 3257 if (ret) {
a3139c59
SO
3258 printk(KERN_ERR DRV_NAME
3259 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3260 return ret;
3261 }
3262
fed9017e 3263 ret = pci_register_driver(&iwl_driver);
b481de9c 3264 if (ret) {
a3139c59 3265 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3266 goto error_register;
b481de9c 3267 }
b481de9c
ZY
3268
3269 return ret;
897e1cf2 3270
897e1cf2 3271error_register:
e227ceac 3272 iwlagn_rate_control_unregister();
897e1cf2 3273 return ret;
b481de9c
ZY
3274}
3275
5b9f8cd3 3276static void __exit iwl_exit(void)
b481de9c 3277{
fed9017e 3278 pci_unregister_driver(&iwl_driver);
e227ceac 3279 iwlagn_rate_control_unregister();
b481de9c
ZY
3280}
3281
5b9f8cd3
EG
3282module_exit(iwl_exit);
3283module_init(iwl_init);
a562a9dd
RC
3284
3285#ifdef CONFIG_IWLWIFI_DEBUG
3286module_param_named(debug50, iwl_debug_level, uint, 0444);
3287MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
3288module_param_named(debug, iwl_debug_level, uint, 0644);
3289MODULE_PARM_DESC(debug, "debug output mask");
3290#endif
3291