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CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
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43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO
47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
b481de9c
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
b481de9c
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64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
80bc5393 75#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
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92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
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101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
e0158e61 105int iwl_commit_rxon(struct iwl_priv *priv)
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106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
b481de9c
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115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
118
8ccde88a 119 ret = iwl_check_rxon_cmd(priv);
43d59b32 120 if (ret) {
15b1687c 121 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
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122 return -EINVAL;
123 }
124
0924e519
WYG
125 /*
126 * receive commit_rxon request
127 * abort any previous channel switch if still in process
128 */
129 if (priv->switch_rxon.switch_in_progress &&
130 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
131 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
132 le16_to_cpu(priv->switch_rxon.channel));
133 priv->switch_rxon.switch_in_progress = false;
134 }
135
b481de9c 136 /* If we don't need to send a full RXON, we can use
5b9f8cd3 137 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 138 * and other flags for the current radio configuration. */
54559703 139 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
140 ret = iwl_send_rxon_assoc(priv);
141 if (ret) {
15b1687c 142 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 143 return ret;
b481de9c
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144 }
145
146 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 147 iwl_print_rx_config_cmd(priv);
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148 return 0;
149 }
150
151 /* station table will be cleared */
152 priv->assoc_station_added = 0;
153
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154 /* If we are currently associated and the new config requires
155 * an RXON_ASSOC and the new config wants the associated mask enabled,
156 * we must clear the associated from the active configuration
157 * before we apply the new config */
43d59b32 158 if (iwl_is_associated(priv) && new_assoc) {
e1623446 159 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
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160 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
161
43d59b32 162 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 163 sizeof(struct iwl_rxon_cmd),
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164 &priv->active_rxon);
165
166 /* If the mask clearing failed then we set
167 * active_rxon back to what it was previously */
43d59b32 168 if (ret) {
b481de9c 169 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 170 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 171 return ret;
b481de9c 172 }
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173 }
174
e1623446 175 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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176 "* with%s RXON_FILTER_ASSOC_MSK\n"
177 "* channel = %d\n"
e174961c 178 "* bssid = %pM\n",
43d59b32 179 (new_assoc ? "" : "out"),
b481de9c 180 le16_to_cpu(priv->staging_rxon.channel),
e174961c 181 priv->staging_rxon.bssid_addr);
b481de9c 182
90e8e424 183 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
184
185 /* Apply the new configuration
186 * RXON unassoc clears the station table in uCode, send it before
187 * we add the bcast station. If assoc bit is set, we will send RXON
188 * after having added the bcast and bssid station.
189 */
190 if (!new_assoc) {
191 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 192 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 193 if (ret) {
15b1687c 194 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
195 return ret;
196 }
197 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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198 }
199
c587de0b 200 iwl_clear_stations_table(priv);
556f8db7 201
19cc1087 202 priv->start_calib = 0;
b481de9c 203
b481de9c 204 /* Add the broadcast address so we can send broadcast frames */
9a9ca65f 205 iwl_add_bcast_station(priv);
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206
207 /* If we have set the ASSOC_MSK and we are in BSS mode then
208 * add the IWL_AP_ID to the station rate table */
9185159d 209 if (new_assoc) {
05c914fe 210 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
211 ret = iwl_rxon_add_station(priv,
212 priv->active_rxon.bssid_addr, 1);
213 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
214 IWL_ERR(priv,
215 "Error adding AP address for TX.\n");
9185159d
TW
216 return -EIO;
217 }
218 priv->assoc_station_added = 1;
219 if (priv->default_wep_key &&
220 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
221 IWL_ERR(priv,
222 "Could not send WEP static key.\n");
b481de9c 223 }
43d59b32 224
47eef9bd
WYG
225 /*
226 * allow CTS-to-self if possible for new association.
227 * this is relevant only for 5000 series and up,
228 * but will not damage 4965
229 */
230 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
231
43d59b32
EG
232 /* Apply the new configuration
233 * RXON assoc doesn't clear the station table in uCode,
234 */
235 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
236 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
237 if (ret) {
15b1687c 238 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
239 return ret;
240 }
241 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 242 }
a643565e 243 iwl_print_rx_config_cmd(priv);
b481de9c 244
36da7d70
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245 iwl_init_sensitivity(priv);
246
247 /* If we issue a new RXON command which required a tune then we must
248 * send a new TXPOWER command or we won't be able to Tx any frames */
249 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
250 if (ret) {
15b1687c 251 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY
252 return ret;
253 }
254
b481de9c
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255 return 0;
256}
257
5b9f8cd3 258void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
259{
260
45823531
AK
261 if (priv->cfg->ops->hcmd->set_rxon_chain)
262 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 263 iwlcore_commit_rxon(priv);
5da4b55f
MA
264}
265
fcab423d 266static void iwl_clear_free_frames(struct iwl_priv *priv)
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267{
268 struct list_head *element;
269
e1623446 270 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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271 priv->frames_count);
272
273 while (!list_empty(&priv->free_frames)) {
274 element = priv->free_frames.next;
275 list_del(element);
fcab423d 276 kfree(list_entry(element, struct iwl_frame, list));
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277 priv->frames_count--;
278 }
279
280 if (priv->frames_count) {
39aadf8c 281 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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282 priv->frames_count);
283 priv->frames_count = 0;
284 }
285}
286
fcab423d 287static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 288{
fcab423d 289 struct iwl_frame *frame;
b481de9c
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290 struct list_head *element;
291 if (list_empty(&priv->free_frames)) {
292 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
293 if (!frame) {
15b1687c 294 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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295 return NULL;
296 }
297
298 priv->frames_count++;
299 return frame;
300 }
301
302 element = priv->free_frames.next;
303 list_del(element);
fcab423d 304 return list_entry(element, struct iwl_frame, list);
b481de9c
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305}
306
fcab423d 307static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
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308{
309 memset(frame, 0, sizeof(*frame));
310 list_add(&frame->list, &priv->free_frames);
311}
312
47ff65c4 313static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 314 struct ieee80211_hdr *hdr,
73ec1cc2 315 int left)
b481de9c 316{
3109ece1 317 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
318 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
319 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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320 return 0;
321
322 if (priv->ibss_beacon->len > left)
323 return 0;
324
325 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
326
327 return priv->ibss_beacon->len;
328}
329
47ff65c4
DH
330/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
331static void iwl_set_beacon_tim(struct iwl_priv *priv,
332 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
333 u8 *beacon, u32 frame_size)
334{
335 u16 tim_idx;
336 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
337
338 /*
339 * The index is relative to frame start but we start looking at the
340 * variable-length part of the beacon.
341 */
342 tim_idx = mgmt->u.beacon.variable - beacon;
343
344 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
345 while ((tim_idx < (frame_size - 2)) &&
346 (beacon[tim_idx] != WLAN_EID_TIM))
347 tim_idx += beacon[tim_idx+1] + 2;
348
349 /* If TIM field was found, set variables */
350 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
351 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
352 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
353 } else
354 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
355}
356
5b9f8cd3 357static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 358 struct iwl_frame *frame)
4bf64efd
TW
359{
360 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH
361 u32 frame_size;
362 u32 rate_flags;
363 u32 rate;
364 /*
365 * We have to set up the TX command, the TX Beacon command, and the
366 * beacon contents.
367 */
4bf64efd 368
47ff65c4 369 /* Initialize memory */
4bf64efd
TW
370 tx_beacon_cmd = &frame->u.beacon;
371 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
372
47ff65c4 373 /* Set up TX beacon contents */
4bf64efd 374 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 375 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH
376 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
377 return 0;
4bf64efd 378
47ff65c4 379 /* Set up TX command fields */
4bf64efd 380 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH
381 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
382 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
383 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
384 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 385
47ff65c4
DH
386 /* Set up TX beacon command fields */
387 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
388 frame_size);
4bf64efd 389
47ff65c4
DH
390 /* Set up packet rate and flags */
391 rate = iwl_rate_get_lowest_plcp(priv);
392 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
393 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
394 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
395 rate_flags |= RATE_MCS_CCK_MSK;
396 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
397 rate_flags);
4bf64efd
TW
398
399 return sizeof(*tx_beacon_cmd) + frame_size;
400}
5b9f8cd3 401static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 402{
fcab423d 403 struct iwl_frame *frame;
b481de9c
ZY
404 unsigned int frame_size;
405 int rc;
b481de9c 406
fcab423d 407 frame = iwl_get_free_frame(priv);
b481de9c 408 if (!frame) {
15b1687c 409 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
410 "command.\n");
411 return -ENOMEM;
412 }
413
47ff65c4
DH
414 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
415 if (!frame_size) {
416 IWL_ERR(priv, "Error configuring the beacon command\n");
417 iwl_free_frame(priv, frame);
418 return -EINVAL;
419 }
b481de9c 420
857485c0 421 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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422 &frame->u.cmd[0]);
423
fcab423d 424 iwl_free_frame(priv, frame);
b481de9c
ZY
425
426 return rc;
427}
428
7aaa1d79
SO
429static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
430{
431 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
432
433 dma_addr_t addr = get_unaligned_le32(&tb->lo);
434 if (sizeof(dma_addr_t) > sizeof(u32))
435 addr |=
436 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
437
438 return addr;
439}
440
441static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
442{
443 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
444
445 return le16_to_cpu(tb->hi_n_len) >> 4;
446}
447
448static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
449 dma_addr_t addr, u16 len)
450{
451 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
452 u16 hi_n_len = len << 4;
453
454 put_unaligned_le32(addr, &tb->lo);
455 if (sizeof(dma_addr_t) > sizeof(u32))
456 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
457
458 tb->hi_n_len = cpu_to_le16(hi_n_len);
459
460 tfd->num_tbs = idx + 1;
461}
462
463static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
464{
465 return tfd->num_tbs & 0x1f;
466}
467
468/**
469 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
470 * @priv - driver private data
471 * @txq - tx queue
472 *
473 * Does NOT advance any TFD circular buffer read/write indexes
474 * Does NOT free the TFD itself (which is within circular buffer)
475 */
476void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
477{
59606ffa 478 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
479 struct iwl_tfd *tfd;
480 struct pci_dev *dev = priv->pci_dev;
481 int index = txq->q.read_ptr;
482 int i;
483 int num_tbs;
484
485 tfd = &tfd_tmp[index];
486
487 /* Sanity check on number of chunks */
488 num_tbs = iwl_tfd_get_num_tbs(tfd);
489
490 if (num_tbs >= IWL_NUM_OF_TBS) {
491 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
492 /* @todo issue fatal error, it is quite serious situation */
493 return;
494 }
495
496 /* Unmap tx_cmd */
497 if (num_tbs)
498 pci_unmap_single(dev,
c2acea8e
JB
499 pci_unmap_addr(&txq->meta[index], mapping),
500 pci_unmap_len(&txq->meta[index], len),
96891cee 501 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
502
503 /* Unmap chunks, if any. */
504 for (i = 1; i < num_tbs; i++) {
505 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
506 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
507
508 if (txq->txb) {
509 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
510 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
511 }
512 }
513}
514
515int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
516 struct iwl_tx_queue *txq,
517 dma_addr_t addr, u16 len,
518 u8 reset, u8 pad)
519{
520 struct iwl_queue *q;
59606ffa 521 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
522 u32 num_tbs;
523
524 q = &txq->q;
59606ffa
SO
525 tfd_tmp = (struct iwl_tfd *)txq->tfds;
526 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
527
528 if (reset)
529 memset(tfd, 0, sizeof(*tfd));
530
531 num_tbs = iwl_tfd_get_num_tbs(tfd);
532
533 /* Each TFD can point to a maximum 20 Tx buffers */
534 if (num_tbs >= IWL_NUM_OF_TBS) {
535 IWL_ERR(priv, "Error can not send more than %d chunks\n",
536 IWL_NUM_OF_TBS);
537 return -EINVAL;
538 }
539
540 BUG_ON(addr & ~DMA_BIT_MASK(36));
541 if (unlikely(addr & ~IWL_TX_DMA_MASK))
542 IWL_ERR(priv, "Unaligned address = %llx\n",
543 (unsigned long long)addr);
544
545 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
546
547 return 0;
548}
549
a8e74e27
SO
550/*
551 * Tell nic where to find circular buffer of Tx Frame Descriptors for
552 * given Tx queue, and enable the DMA channel used for that queue.
553 *
554 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
555 * channels supported in hardware.
556 */
557int iwl_hw_tx_queue_init(struct iwl_priv *priv,
558 struct iwl_tx_queue *txq)
559{
a8e74e27
SO
560 int txq_id = txq->q.id;
561
a8e74e27
SO
562 /* Circular buffer (TFD queue in DRAM) physical base address */
563 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
564 txq->q.dma_addr >> 8);
565
a8e74e27
SO
566 return 0;
567}
568
b481de9c
ZY
569/******************************************************************************
570 *
571 * Generic RX handler implementations
572 *
573 ******************************************************************************/
885ba202
TW
574static void iwl_rx_reply_alive(struct iwl_priv *priv,
575 struct iwl_rx_mem_buffer *rxb)
b481de9c 576{
2f301227 577 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 578 struct iwl_alive_resp *palive;
b481de9c
ZY
579 struct delayed_work *pwork;
580
581 palive = &pkt->u.alive_frame;
582
e1623446 583 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
584 "0x%01X 0x%01X\n",
585 palive->is_valid, palive->ver_type,
586 palive->ver_subtype);
587
588 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 589 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
590 memcpy(&priv->card_alive_init,
591 &pkt->u.alive_frame,
885ba202 592 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
593 pwork = &priv->init_alive_start;
594 } else {
e1623446 595 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 596 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 597 sizeof(struct iwl_alive_resp));
b481de9c
ZY
598 pwork = &priv->alive_start;
599 }
600
601 /* We delay the ALIVE response by 5ms to
602 * give the HW RF Kill time to activate... */
603 if (palive->is_valid == UCODE_VALID_OK)
604 queue_delayed_work(priv->workqueue, pwork,
605 msecs_to_jiffies(5));
606 else
39aadf8c 607 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
608}
609
5b9f8cd3 610static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 611{
c79dd5b5
TW
612 struct iwl_priv *priv =
613 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
614 struct sk_buff *beacon;
615
616 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 617 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
618
619 if (!beacon) {
15b1687c 620 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
621 return;
622 }
623
624 mutex_lock(&priv->mutex);
625 /* new beacon skb is allocated every time; dispose previous.*/
626 if (priv->ibss_beacon)
627 dev_kfree_skb(priv->ibss_beacon);
628
629 priv->ibss_beacon = beacon;
630 mutex_unlock(&priv->mutex);
631
5b9f8cd3 632 iwl_send_beacon_cmd(priv);
b481de9c
ZY
633}
634
4e39317d 635/**
5b9f8cd3 636 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
637 *
638 * This callback is provided in order to send a statistics request.
639 *
640 * This timer function is continually reset to execute within
641 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
642 * was received. We need to ensure we receive the statistics in order
643 * to update the temperature used for calibrating the TXPOWER.
644 */
5b9f8cd3 645static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
646{
647 struct iwl_priv *priv = (struct iwl_priv *)data;
648
649 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
650 return;
651
61780ee3
MA
652 /* dont send host command if rf-kill is on */
653 if (!iwl_is_ready_rf(priv))
654 return;
655
ef8d5529 656 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG
657}
658
5b9f8cd3 659static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 660 struct iwl_rx_mem_buffer *rxb)
b481de9c 661{
0a6857e7 662#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 663 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW
664 struct iwl4965_beacon_notif *beacon =
665 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 666 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 667
e1623446 668 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 669 "tsf %d %d rate %d\n",
25a6572c 670 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
671 beacon->beacon_notify_hdr.failure_frame,
672 le32_to_cpu(beacon->ibss_mgr_status),
673 le32_to_cpu(beacon->high_tsf),
674 le32_to_cpu(beacon->low_tsf), rate);
675#endif
676
05c914fe 677 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
678 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
679 queue_work(priv->workqueue, &priv->beacon_update);
680}
681
b481de9c
ZY
682/* Handle notification from uCode that card's power state is changing
683 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 684static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 685 struct iwl_rx_mem_buffer *rxb)
b481de9c 686{
2f301227 687 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
688 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
689 unsigned long status = priv->status;
690
e1623446 691 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
692 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
693 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
694
695 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
696 RF_CARD_DISABLED)) {
697
3395f6e9 698 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
699 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
700
a8b50a0a
MA
701 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
702 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
703
704 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 705 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 706 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 707 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 708 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 709 }
39b73fb1
WYG
710 if (flags & RF_CARD_DISABLED)
711 iwl_tt_enter_ct_kill(priv);
b481de9c 712 }
39b73fb1
WYG
713 if (!(flags & RF_CARD_DISABLED))
714 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
715
716 if (flags & HW_CARD_DISABLED)
717 set_bit(STATUS_RF_KILL_HW, &priv->status);
718 else
719 clear_bit(STATUS_RF_KILL_HW, &priv->status);
720
721
b481de9c 722 if (!(flags & RXON_CARD_DISABLED))
2a421b91 723 iwl_scan_cancel(priv);
b481de9c
ZY
724
725 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
726 test_bit(STATUS_RF_KILL_HW, &priv->status)))
727 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
728 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
729 else
730 wake_up_interruptible(&priv->wait_command_queue);
731}
732
5b9f8cd3 733int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 734{
e2e3c57b 735 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 736 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
737 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
738 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
739 ~APMG_PS_CTRL_MSK_PWR_SRC);
740 } else {
741 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
742 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
743 ~APMG_PS_CTRL_MSK_PWR_SRC);
744 }
745
a8b50a0a 746 return 0;
e2e3c57b
TW
747}
748
b481de9c 749/**
5b9f8cd3 750 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
751 *
752 * Setup the RX handlers for each of the reply types sent from the uCode
753 * to the host.
754 *
755 * This function chains into the hardware specific files for them to setup
756 * any hardware specific handlers as well.
757 */
653fa4a0 758static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 759{
885ba202 760 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
761 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
762 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 763 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 764 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
765 iwl_rx_pm_debug_statistics_notif;
766 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 767
9fbab516
BC
768 /*
769 * The same handler is used for both the REPLY to a discrete
770 * statistics request from the host as well as for the periodic
771 * statistics notifications (after received beacons) from the uCode.
b481de9c 772 */
ef8d5529 773 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 774 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 775
21c339bf 776 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
777 iwl_setup_rx_scan_handlers(priv);
778
37a44211 779 /* status change handler */
5b9f8cd3 780 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 781
c1354754
TW
782 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
783 iwl_rx_missed_beacon_notif;
37a44211 784 /* Rx handlers */
1781a07f
EG
785 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
786 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
787 /* block ack */
788 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 789 /* Set up hardware specific Rx handlers */
d4789efe 790 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
791}
792
b481de9c 793/**
a55360e4 794 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
795 *
796 * Uses the priv->rx_handlers callback function array to invoke
797 * the appropriate handlers, including command responses,
798 * frame-received notifications, and other notifications.
799 */
a55360e4 800void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 801{
a55360e4 802 struct iwl_rx_mem_buffer *rxb;
db11d634 803 struct iwl_rx_packet *pkt;
a55360e4 804 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
805 u32 r, i;
806 int reclaim;
807 unsigned long flags;
5c0eef96 808 u8 fill_rx = 0;
d68ab680 809 u32 count = 8;
4752c93c 810 int total_empty;
b481de9c 811
6440adb5
BC
812 /* uCode's read index (stored in shared DRAM) indicates the last Rx
813 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 814 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
815 i = rxq->read;
816
817 /* Rx interrupt, but nothing sent from uCode */
818 if (i == r)
e1623446 819 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 820
4752c93c 821 /* calculate total frames need to be restock after handling RX */
7300515d 822 total_empty = r - rxq->write_actual;
4752c93c
MA
823 if (total_empty < 0)
824 total_empty += RX_QUEUE_SIZE;
825
826 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
827 fill_rx = 1;
828
b481de9c
ZY
829 while (i != r) {
830 rxb = rxq->queue[i];
831
9fbab516 832 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
833 * then a bug has been introduced in the queue refilling
834 * routines -- catch it here */
835 BUG_ON(rxb == NULL);
836
837 rxq->queue[i] = NULL;
838
2f301227
ZY
839 pci_unmap_page(priv->pci_dev, rxb->page_dma,
840 PAGE_SIZE << priv->hw_params.rx_page_order,
841 PCI_DMA_FROMDEVICE);
842 pkt = rxb_addr(rxb);
b481de9c 843
be1a71a1
JB
844 trace_iwlwifi_dev_rx(priv, pkt,
845 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
846
b481de9c
ZY
847 /* Reclaim a command buffer only if this packet is a response
848 * to a (driver-originated) command.
849 * If the packet (e.g. Rx frame) originated from uCode,
850 * there is no command buffer to reclaim.
851 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
852 * but apparently a few don't get set; catch them here. */
853 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
854 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 855 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 856 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 857 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
858 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
859 (pkt->hdr.cmd != REPLY_TX);
860
861 /* Based on type of command response or notification,
862 * handle those that need handling via function in
5b9f8cd3 863 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 864 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 865 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 866 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 867 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 868 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
869 } else {
870 /* No handling needed */
e1623446 871 IWL_DEBUG_RX(priv,
b481de9c
ZY
872 "r %d i %d No handler needed for %s, 0x%02x\n",
873 r, i, get_cmd_string(pkt->hdr.cmd),
874 pkt->hdr.cmd);
875 }
876
29b1b268
ZY
877 /*
878 * XXX: After here, we should always check rxb->page
879 * against NULL before touching it or its virtual
880 * memory (pkt). Because some rx_handler might have
881 * already taken or freed the pages.
882 */
883
b481de9c 884 if (reclaim) {
2f301227
ZY
885 /* Invoke any callbacks, transfer the buffer to caller,
886 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 887 * as we reclaim the driver command queue */
29b1b268 888 if (rxb->page)
17b88929 889 iwl_tx_cmd_complete(priv, rxb);
b481de9c 890 else
39aadf8c 891 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
892 }
893
7300515d
ZY
894 /* Reuse the page if possible. For notification packets and
895 * SKBs that fail to Rx correctly, add them back into the
896 * rx_free list for reuse later. */
897 spin_lock_irqsave(&rxq->lock, flags);
2f301227 898 if (rxb->page != NULL) {
7300515d
ZY
899 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
900 0, PAGE_SIZE << priv->hw_params.rx_page_order,
901 PCI_DMA_FROMDEVICE);
902 list_add_tail(&rxb->list, &rxq->rx_free);
903 rxq->free_count++;
904 } else
905 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 906
b481de9c 907 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 908
b481de9c 909 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
910 /* If there are a lot of unused frames,
911 * restock the Rx queue so ucode wont assert. */
912 if (fill_rx) {
913 count++;
914 if (count >= 8) {
7300515d 915 rxq->read = i;
4752c93c 916 iwl_rx_replenish_now(priv);
5c0eef96
MA
917 count = 0;
918 }
919 }
b481de9c
ZY
920 }
921
922 /* Backtrack one entry */
7300515d 923 rxq->read = i;
4752c93c
MA
924 if (fill_rx)
925 iwl_rx_replenish_now(priv);
926 else
927 iwl_rx_queue_restock(priv);
a55360e4 928}
a55360e4 929
0359facc
MA
930/* call this function to flush any scheduled tasklet */
931static inline void iwl_synchronize_irq(struct iwl_priv *priv)
932{
a96a27f9 933 /* wait to make sure we flush pending tasklet*/
0359facc
MA
934 synchronize_irq(priv->pci_dev->irq);
935 tasklet_kill(&priv->irq_tasklet);
936}
937
ef850d7c 938static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
939{
940 u32 inta, handled = 0;
941 u32 inta_fh;
942 unsigned long flags;
c2e61da2 943 u32 i;
0a6857e7 944#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
945 u32 inta_mask;
946#endif
947
948 spin_lock_irqsave(&priv->lock, flags);
949
950 /* Ack/clear/reset pending uCode interrupts.
951 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
952 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
953 inta = iwl_read32(priv, CSR_INT);
954 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
955
956 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
957 * Any new interrupts that happen after this, either while we're
958 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
959 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
960 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 961
0a6857e7 962#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 963 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 964 /* just for debug */
3395f6e9 965 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 966 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
967 inta, inta_mask, inta_fh);
968 }
969#endif
970
2f301227
ZY
971 spin_unlock_irqrestore(&priv->lock, flags);
972
b481de9c
ZY
973 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
974 * atomic, make sure that inta covers all the interrupts that
975 * we've discovered, even if FH interrupt came in just after
976 * reading CSR_INT. */
6f83eaa1 977 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 978 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 979 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
980 inta |= CSR_INT_BIT_FH_TX;
981
982 /* Now service all interrupt bits discovered above. */
983 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 984 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
985
986 /* Tell the device to stop sending interrupts */
5b9f8cd3 987 iwl_disable_interrupts(priv);
b481de9c 988
a83b9141 989 priv->isr_stats.hw++;
5b9f8cd3 990 iwl_irq_handle_error(priv);
b481de9c
ZY
991
992 handled |= CSR_INT_BIT_HW_ERR;
993
b481de9c
ZY
994 return;
995 }
996
0a6857e7 997#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 998 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 999 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1000 if (inta & CSR_INT_BIT_SCD) {
e1623446 1001 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1002 "the frame/frames.\n");
a83b9141
WYG
1003 priv->isr_stats.sch++;
1004 }
b481de9c
ZY
1005
1006 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1007 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1008 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
1009 priv->isr_stats.alive++;
1010 }
b481de9c
ZY
1011 }
1012#endif
1013 /* Safely ignore these bits for debug checks below */
25c03d8e 1014 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1015
9fbab516 1016 /* HW RF KILL switch toggled */
b481de9c
ZY
1017 if (inta & CSR_INT_BIT_RF_KILL) {
1018 int hw_rf_kill = 0;
3395f6e9 1019 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
1020 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1021 hw_rf_kill = 1;
1022
4c423a2b 1023 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1024 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1025
a83b9141
WYG
1026 priv->isr_stats.rfkill++;
1027
a9efa652 1028 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
1029 * the driver allows loading the ucode even if the radio
1030 * is killed. Hence update the killswitch state here. The
1031 * rfkill handler will care about restarting if needed.
a9efa652 1032 */
6cd0b1cb
HS
1033 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1034 if (hw_rf_kill)
1035 set_bit(STATUS_RF_KILL_HW, &priv->status);
1036 else
1037 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1038 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1039 }
b481de9c
ZY
1040
1041 handled |= CSR_INT_BIT_RF_KILL;
1042 }
1043
9fbab516 1044 /* Chip got too hot and stopped itself */
b481de9c 1045 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1046 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1047 priv->isr_stats.ctkill++;
b481de9c
ZY
1048 handled |= CSR_INT_BIT_CT_KILL;
1049 }
1050
1051 /* Error detected by uCode */
1052 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1053 IWL_ERR(priv, "Microcode SW error detected. "
1054 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1055 priv->isr_stats.sw++;
1056 priv->isr_stats.sw_err = inta;
5b9f8cd3 1057 iwl_irq_handle_error(priv);
b481de9c
ZY
1058 handled |= CSR_INT_BIT_SW_ERR;
1059 }
1060
c2e61da2
BC
1061 /*
1062 * uCode wakes up after power-down sleep.
1063 * Tell device about any new tx or host commands enqueued,
1064 * and about any Rx buffers made available while asleep.
1065 */
b481de9c 1066 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1067 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1068 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC
1069 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1070 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1071 priv->isr_stats.wakeup++;
b481de9c
ZY
1072 handled |= CSR_INT_BIT_WAKEUP;
1073 }
1074
1075 /* All uCode command responses, including Tx command responses,
1076 * Rx "responses" (frame-received notification), and other
1077 * notifications from uCode come through here*/
1078 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1079 iwl_rx_handle(priv);
a83b9141 1080 priv->isr_stats.rx++;
1ed2a3d2 1081 iwl_leds_background(priv);
b481de9c
ZY
1082 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1083 }
1084
c72cd19f 1085 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1086 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1087 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1088 priv->isr_stats.tx++;
b481de9c 1089 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1090 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR
1091 priv->ucode_write_complete = 1;
1092 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1093 }
1094
a83b9141 1095 if (inta & ~handled) {
15b1687c 1096 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1097 priv->isr_stats.unhandled++;
1098 }
b481de9c 1099
40cefda9 1100 if (inta & ~(priv->inta_mask)) {
39aadf8c 1101 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1102 inta & ~priv->inta_mask);
39aadf8c 1103 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1104 }
1105
1106 /* Re-enable all interrupts */
0359facc
MA
1107 /* only Re-enable if diabled by irq */
1108 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1109 iwl_enable_interrupts(priv);
b481de9c 1110
0a6857e7 1111#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1112 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1113 inta = iwl_read32(priv, CSR_INT);
1114 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1115 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1116 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1117 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1118 }
1119#endif
b481de9c
ZY
1120}
1121
ef850d7c
MA
1122/* tasklet for iwlagn interrupt */
1123static void iwl_irq_tasklet(struct iwl_priv *priv)
1124{
1125 u32 inta = 0;
1126 u32 handled = 0;
1127 unsigned long flags;
8756990f 1128 u32 i;
ef850d7c
MA
1129#ifdef CONFIG_IWLWIFI_DEBUG
1130 u32 inta_mask;
1131#endif
1132
1133 spin_lock_irqsave(&priv->lock, flags);
1134
1135 /* Ack/clear/reset pending uCode interrupts.
1136 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1137 */
1138 iwl_write32(priv, CSR_INT, priv->inta);
1139
1140 inta = priv->inta;
1141
1142#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1143 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1144 /* just for debug */
1145 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1146 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1147 inta, inta_mask);
1148 }
1149#endif
2f301227
ZY
1150
1151 spin_unlock_irqrestore(&priv->lock, flags);
1152
ef850d7c
MA
1153 /* saved interrupt in inta variable now we can reset priv->inta */
1154 priv->inta = 0;
1155
1156 /* Now service all interrupt bits discovered above. */
1157 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1158 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1159
1160 /* Tell the device to stop sending interrupts */
1161 iwl_disable_interrupts(priv);
1162
1163 priv->isr_stats.hw++;
1164 iwl_irq_handle_error(priv);
1165
1166 handled |= CSR_INT_BIT_HW_ERR;
1167
ef850d7c
MA
1168 return;
1169 }
1170
1171#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1172 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1173 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1174 if (inta & CSR_INT_BIT_SCD) {
1175 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1176 "the frame/frames.\n");
1177 priv->isr_stats.sch++;
1178 }
1179
1180 /* Alive notification via Rx interrupt will do the real work */
1181 if (inta & CSR_INT_BIT_ALIVE) {
1182 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1183 priv->isr_stats.alive++;
1184 }
1185 }
1186#endif
1187 /* Safely ignore these bits for debug checks below */
1188 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1189
1190 /* HW RF KILL switch toggled */
1191 if (inta & CSR_INT_BIT_RF_KILL) {
1192 int hw_rf_kill = 0;
1193 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1194 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1195 hw_rf_kill = 1;
1196
4c423a2b 1197 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1198 hw_rf_kill ? "disable radio" : "enable radio");
1199
1200 priv->isr_stats.rfkill++;
1201
1202 /* driver only loads ucode once setting the interface up.
1203 * the driver allows loading the ucode even if the radio
1204 * is killed. Hence update the killswitch state here. The
1205 * rfkill handler will care about restarting if needed.
1206 */
1207 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1208 if (hw_rf_kill)
1209 set_bit(STATUS_RF_KILL_HW, &priv->status);
1210 else
1211 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1212 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1213 }
1214
1215 handled |= CSR_INT_BIT_RF_KILL;
1216 }
1217
1218 /* Chip got too hot and stopped itself */
1219 if (inta & CSR_INT_BIT_CT_KILL) {
1220 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1221 priv->isr_stats.ctkill++;
1222 handled |= CSR_INT_BIT_CT_KILL;
1223 }
1224
1225 /* Error detected by uCode */
1226 if (inta & CSR_INT_BIT_SW_ERR) {
1227 IWL_ERR(priv, "Microcode SW error detected. "
1228 " Restarting 0x%X.\n", inta);
1229 priv->isr_stats.sw++;
1230 priv->isr_stats.sw_err = inta;
1231 iwl_irq_handle_error(priv);
1232 handled |= CSR_INT_BIT_SW_ERR;
1233 }
1234
1235 /* uCode wakes up after power-down sleep */
1236 if (inta & CSR_INT_BIT_WAKEUP) {
1237 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1238 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC
1239 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1240 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA
1241
1242 priv->isr_stats.wakeup++;
1243
1244 handled |= CSR_INT_BIT_WAKEUP;
1245 }
1246
1247 /* All uCode command responses, including Tx command responses,
1248 * Rx "responses" (frame-received notification), and other
1249 * notifications from uCode come through here*/
40cefda9
MA
1250 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1251 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1252 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1253 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1254 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1255 iwl_write32(priv, CSR_FH_INT_STATUS,
1256 CSR49_FH_INT_RX_MASK);
1257 }
1258 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1259 handled |= CSR_INT_BIT_RX_PERIODIC;
1260 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1261 }
1262 /* Sending RX interrupt require many steps to be done in the
1263 * the device:
1264 * 1- write interrupt to current index in ICT table.
1265 * 2- dma RX frame.
1266 * 3- update RX shared data to indicate last write index.
1267 * 4- send interrupt.
1268 * This could lead to RX race, driver could receive RX interrupt
1269 * but the shared data changes does not reflect this.
1270 * this could lead to RX race, RX periodic will solve this race
1271 */
1272 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1273 CSR_INT_PERIODIC_DIS);
ef850d7c 1274 iwl_rx_handle(priv);
40cefda9
MA
1275 /* Only set RX periodic if real RX is received. */
1276 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1277 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1278 CSR_INT_PERIODIC_ENA);
1279
ef850d7c 1280 priv->isr_stats.rx++;
1ed2a3d2 1281 iwl_leds_background(priv);
ef850d7c
MA
1282 }
1283
c72cd19f 1284 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA
1285 if (inta & CSR_INT_BIT_FH_TX) {
1286 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1287 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA
1288 priv->isr_stats.tx++;
1289 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1290 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA
1291 priv->ucode_write_complete = 1;
1292 wake_up_interruptible(&priv->wait_command_queue);
1293 }
1294
1295 if (inta & ~handled) {
1296 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1297 priv->isr_stats.unhandled++;
1298 }
1299
40cefda9 1300 if (inta & ~(priv->inta_mask)) {
ef850d7c 1301 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1302 inta & ~priv->inta_mask);
ef850d7c
MA
1303 }
1304
ef850d7c
MA
1305 /* Re-enable all interrupts */
1306 /* only Re-enable if diabled by irq */
1307 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1308 iwl_enable_interrupts(priv);
ef850d7c
MA
1309}
1310
a83b9141 1311
b481de9c
ZY
1312/******************************************************************************
1313 *
1314 * uCode download functions
1315 *
1316 ******************************************************************************/
1317
5b9f8cd3 1318static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1319{
98c92211
TW
1320 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1321 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1322 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1323 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1324 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1325 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1326}
1327
5b9f8cd3 1328static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1329{
1330 /* Remove all resets to allow NIC to operate */
1331 iwl_write32(priv, CSR_RESET, 0);
1332}
1333
1334
b481de9c 1335/**
5b9f8cd3 1336 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1337 *
1338 * Copy into buffers for card to fetch via bus-mastering
1339 */
5b9f8cd3 1340static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1341{
cc0f555d 1342 struct iwl_ucode_header *ucode;
a0987a8d 1343 int ret = -EINVAL, index;
b481de9c 1344 const struct firmware *ucode_raw;
a0987a8d
RC
1345 const char *name_pre = priv->cfg->fw_name_pre;
1346 const unsigned int api_max = priv->cfg->ucode_api_max;
1347 const unsigned int api_min = priv->cfg->ucode_api_min;
1348 char buf[25];
b481de9c
ZY
1349 u8 *src;
1350 size_t len;
cc0f555d
JS
1351 u32 api_ver, build;
1352 u32 inst_size, data_size, init_size, init_data_size, boot_size;
abdc2d62 1353 u16 eeprom_ver;
b481de9c
ZY
1354
1355 /* Ask kernel firmware_class module to get the boot firmware off disk.
1356 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1357 for (index = api_max; index >= api_min; index--) {
1358 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1359 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1360 if (ret < 0) {
15b1687c 1361 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1362 buf, ret);
1363 if (ret == -ENOENT)
1364 continue;
1365 else
1366 goto error;
1367 } else {
1368 if (index < api_max)
15b1687c
WT
1369 IWL_ERR(priv, "Loaded firmware %s, "
1370 "which is deprecated. "
1371 "Please use API v%u instead.\n",
a0987a8d 1372 buf, api_max);
15b1687c 1373
e1623446 1374 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1375 buf, ucode_raw->size);
1376 break;
1377 }
b481de9c
ZY
1378 }
1379
a0987a8d
RC
1380 if (ret < 0)
1381 goto error;
b481de9c 1382
cc0f555d
JS
1383 /* Make sure that we got at least the v1 header! */
1384 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1385 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1386 ret = -EINVAL;
b481de9c
ZY
1387 goto err_release;
1388 }
1389
1390 /* Data from ucode file: header followed by uCode images */
cc0f555d 1391 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1392
c02b3acd 1393 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1394 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1395 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1396 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1397 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1398 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1399 init_data_size =
1400 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1401 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1402 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1403
a0987a8d
RC
1404 /* api_ver should match the api version forming part of the
1405 * firmware filename ... but we don't check for that and only rely
877d0310 1406 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1407
1408 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1409 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1410 "Driver supports v%u, firmware is v%u.\n",
1411 api_max, api_ver);
1412 priv->ucode_ver = 0;
1413 ret = -EINVAL;
1414 goto err_release;
1415 }
1416 if (api_ver != api_max)
978785a3 1417 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1418 "got v%u. New firmware can be obtained "
1419 "from http://www.intellinuxwireless.org.\n",
1420 api_max, api_ver);
1421
978785a3
TW
1422 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1423 IWL_UCODE_MAJOR(priv->ucode_ver),
1424 IWL_UCODE_MINOR(priv->ucode_ver),
1425 IWL_UCODE_API(priv->ucode_ver),
1426 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1427
5ebeb5a6
RC
1428 snprintf(priv->hw->wiphy->fw_version,
1429 sizeof(priv->hw->wiphy->fw_version),
1430 "%u.%u.%u.%u",
1431 IWL_UCODE_MAJOR(priv->ucode_ver),
1432 IWL_UCODE_MINOR(priv->ucode_ver),
1433 IWL_UCODE_API(priv->ucode_ver),
1434 IWL_UCODE_SERIAL(priv->ucode_ver));
1435
cc0f555d
JS
1436 if (build)
1437 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1438
abdc2d62
JS
1439 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1440 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1441 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1442 ? "OTP" : "EEPROM", eeprom_ver);
1443
e1623446 1444 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1445 priv->ucode_ver);
e1623446 1446 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1447 inst_size);
e1623446 1448 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1449 data_size);
e1623446 1450 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1451 init_size);
e1623446 1452 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1453 init_data_size);
e1623446 1454 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1455 boot_size);
1456
1457 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1458 if (ucode_raw->size !=
1459 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1460 inst_size + data_size + init_size +
1461 init_data_size + boot_size) {
1462
cc0f555d
JS
1463 IWL_DEBUG_INFO(priv,
1464 "uCode file size %d does not match expected size\n",
1465 (int)ucode_raw->size);
90e759d1 1466 ret = -EINVAL;
b481de9c
ZY
1467 goto err_release;
1468 }
1469
1470 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1471 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1472 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1473 inst_size);
1474 ret = -EINVAL;
b481de9c
ZY
1475 goto err_release;
1476 }
1477
099b40b7 1478 if (data_size > priv->hw_params.max_data_size) {
e1623446 1479 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1480 data_size);
1481 ret = -EINVAL;
b481de9c
ZY
1482 goto err_release;
1483 }
099b40b7 1484 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1485 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1486 init_size);
90e759d1 1487 ret = -EINVAL;
b481de9c
ZY
1488 goto err_release;
1489 }
099b40b7 1490 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1491 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1492 init_data_size);
1493 ret = -EINVAL;
b481de9c
ZY
1494 goto err_release;
1495 }
099b40b7 1496 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1497 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1498 boot_size);
90e759d1 1499 ret = -EINVAL;
b481de9c
ZY
1500 goto err_release;
1501 }
1502
1503 /* Allocate ucode buffers for card's bus-master loading ... */
1504
1505 /* Runtime instructions and 2 copies of data:
1506 * 1) unmodified from disk
1507 * 2) backup cache for save/restore during power-downs */
1508 priv->ucode_code.len = inst_size;
98c92211 1509 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1510
1511 priv->ucode_data.len = data_size;
98c92211 1512 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1513
1514 priv->ucode_data_backup.len = data_size;
98c92211 1515 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1516
1f304e4e
ZY
1517 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1518 !priv->ucode_data_backup.v_addr)
1519 goto err_pci_alloc;
1520
b481de9c 1521 /* Initialization instructions and data */
90e759d1
TW
1522 if (init_size && init_data_size) {
1523 priv->ucode_init.len = init_size;
98c92211 1524 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1525
1526 priv->ucode_init_data.len = init_data_size;
98c92211 1527 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1528
1529 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1530 goto err_pci_alloc;
1531 }
b481de9c
ZY
1532
1533 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1534 if (boot_size) {
1535 priv->ucode_boot.len = boot_size;
98c92211 1536 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1537
90e759d1
TW
1538 if (!priv->ucode_boot.v_addr)
1539 goto err_pci_alloc;
1540 }
b481de9c
ZY
1541
1542 /* Copy images into buffers for card's bus-master reads ... */
1543
1544 /* Runtime instructions (first block of data in file) */
cc0f555d 1545 len = inst_size;
e1623446 1546 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1547 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1548 src += len;
1549
e1623446 1550 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1551 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1552
1553 /* Runtime data (2nd block)
5b9f8cd3 1554 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1555 len = data_size;
e1623446 1556 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1557 memcpy(priv->ucode_data.v_addr, src, len);
1558 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1559 src += len;
b481de9c
ZY
1560
1561 /* Initialization instructions (3rd block) */
1562 if (init_size) {
cc0f555d 1563 len = init_size;
e1623446 1564 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1565 len);
b481de9c 1566 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1567 src += len;
b481de9c
ZY
1568 }
1569
1570 /* Initialization data (4th block) */
1571 if (init_data_size) {
cc0f555d 1572 len = init_data_size;
e1623446 1573 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1574 len);
b481de9c 1575 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1576 src += len;
b481de9c
ZY
1577 }
1578
1579 /* Bootstrap instructions (5th block) */
cc0f555d 1580 len = boot_size;
e1623446 1581 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1582 memcpy(priv->ucode_boot.v_addr, src, len);
1583
1584 /* We have our copies now, allow OS release its copies */
1585 release_firmware(ucode_raw);
1586 return 0;
1587
1588 err_pci_alloc:
15b1687c 1589 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1590 ret = -ENOMEM;
5b9f8cd3 1591 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1592
1593 err_release:
1594 release_firmware(ucode_raw);
1595
1596 error:
90e759d1 1597 return ret;
b481de9c
ZY
1598}
1599
b7a79404
RC
1600#ifdef CONFIG_IWLWIFI_DEBUG
1601static const char *desc_lookup_text[] = {
1602 "OK",
1603 "FAIL",
1604 "BAD_PARAM",
1605 "BAD_CHECKSUM",
1606 "NMI_INTERRUPT_WDG",
1607 "SYSASSERT",
1608 "FATAL_ERROR",
1609 "BAD_COMMAND",
1610 "HW_ERROR_TUNE_LOCK",
1611 "HW_ERROR_TEMPERATURE",
1612 "ILLEGAL_CHAN_FREQ",
1613 "VCC_NOT_STABLE",
1614 "FH_ERROR",
1615 "NMI_INTERRUPT_HOST",
1616 "NMI_INTERRUPT_ACTION_PT",
1617 "NMI_INTERRUPT_UNKNOWN",
1618 "UCODE_VERSION_MISMATCH",
1619 "HW_ERROR_ABS_LOCK",
1620 "HW_ERROR_CAL_LOCK_FAIL",
1621 "NMI_INTERRUPT_INST_ACTION_PT",
1622 "NMI_INTERRUPT_DATA_ACTION_PT",
1623 "NMI_TRM_HW_ER",
1624 "NMI_INTERRUPT_TRM",
1625 "NMI_INTERRUPT_BREAK_POINT"
1626 "DEBUG_0",
1627 "DEBUG_1",
1628 "DEBUG_2",
1629 "DEBUG_3",
1630 "UNKNOWN"
1631};
1632
1633static const char *desc_lookup(int i)
1634{
1635 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1636
1637 if (i < 0 || i > max)
1638 i = max;
1639
1640 return desc_lookup_text[i];
1641}
1642
1643#define ERROR_START_OFFSET (1 * sizeof(u32))
1644#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1645
1646void iwl_dump_nic_error_log(struct iwl_priv *priv)
1647{
1648 u32 data2, line;
1649 u32 desc, time, count, base, data1;
1650 u32 blink1, blink2, ilink1, ilink2;
1651
1652 if (priv->ucode_type == UCODE_INIT)
1653 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1654 else
1655 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1656
1657 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1658 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1659 return;
1660 }
1661
1662 count = iwl_read_targ_mem(priv, base);
1663
1664 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1665 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1666 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1667 priv->status, count);
1668 }
1669
1670 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1671 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1672 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1673 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1674 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1675 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1676 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1677 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1678 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1679
be1a71a1
JB
1680 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1681 blink1, blink2, ilink1, ilink2);
1682
b7a79404
RC
1683 IWL_ERR(priv, "Desc Time "
1684 "data1 data2 line\n");
1685 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1686 desc_lookup(desc), desc, time, data1, data2, line);
1687 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1688 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1689 ilink1, ilink2);
1690
1691}
1692
1693#define EVENT_START_OFFSET (4 * sizeof(u32))
1694
1695/**
1696 * iwl_print_event_log - Dump error event log to syslog
1697 *
1698 */
1699static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1700 u32 num_events, u32 mode)
1701{
1702 u32 i;
1703 u32 base; /* SRAM byte address of event log header */
1704 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1705 u32 ptr; /* SRAM byte address of log data */
1706 u32 ev, time, data; /* event log data */
e5854471 1707 unsigned long reg_flags;
b7a79404
RC
1708
1709 if (num_events == 0)
1710 return;
1711 if (priv->ucode_type == UCODE_INIT)
1712 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1713 else
1714 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1715
1716 if (mode == 0)
1717 event_size = 2 * sizeof(u32);
1718 else
1719 event_size = 3 * sizeof(u32);
1720
1721 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1722
e5854471
BC
1723 /* Make sure device is powered up for SRAM reads */
1724 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1725 iwl_grab_nic_access(priv);
1726
1727 /* Set starting address; reads will auto-increment */
1728 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1729 rmb();
1730
b7a79404
RC
1731 /* "time" is actually "data" for mode 0 (no timestamp).
1732 * place event id # at far right for easier visual parsing. */
1733 for (i = 0; i < num_events; i++) {
e5854471
BC
1734 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1735 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1736 if (mode == 0) {
1737 /* data, ev */
be1a71a1 1738 trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
b7a79404
RC
1739 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1740 } else {
e5854471 1741 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1742 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1743 time, data, ev);
be1a71a1 1744 trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
b7a79404
RC
1745 }
1746 }
e5854471
BC
1747
1748 /* Allow device to power down */
1749 iwl_release_nic_access(priv);
1750 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b7a79404
RC
1751}
1752
84c40692
BC
1753/* For sanity check only. Actual size is determined by uCode, typ. 512 */
1754#define MAX_EVENT_LOG_SIZE (512)
1755
b7a79404
RC
1756void iwl_dump_nic_event_log(struct iwl_priv *priv)
1757{
1758 u32 base; /* SRAM byte address of event log header */
1759 u32 capacity; /* event log capacity in # entries */
1760 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1761 u32 num_wraps; /* # times uCode wrapped to top of log */
1762 u32 next_entry; /* index of next entry to be written by uCode */
1763 u32 size; /* # entries that we'll print */
1764
1765 if (priv->ucode_type == UCODE_INIT)
1766 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1767 else
1768 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1769
1770 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1771 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1772 return;
1773 }
1774
1775 /* event log header */
1776 capacity = iwl_read_targ_mem(priv, base);
1777 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1778 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1779 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1780
84c40692
BC
1781 if (capacity > MAX_EVENT_LOG_SIZE) {
1782 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1783 capacity, MAX_EVENT_LOG_SIZE);
1784 capacity = MAX_EVENT_LOG_SIZE;
1785 }
1786
1787 if (next_entry > MAX_EVENT_LOG_SIZE) {
1788 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1789 next_entry, MAX_EVENT_LOG_SIZE);
1790 next_entry = MAX_EVENT_LOG_SIZE;
1791 }
1792
b7a79404
RC
1793 size = num_wraps ? capacity : next_entry;
1794
1795 /* bail out if nothing in log */
1796 if (size == 0) {
1797 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1798 return;
1799 }
1800
1801 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1802 size, num_wraps);
1803
1804 /* if uCode has wrapped back to top of log, start at the oldest entry,
1805 * i.e the next one that uCode would fill. */
1806 if (num_wraps)
1807 iwl_print_event_log(priv, next_entry,
1808 capacity - next_entry, mode);
1809 /* (then/else) start at top of log */
1810 iwl_print_event_log(priv, 0, next_entry, mode);
1811
1812}
1813#endif
1814
b481de9c 1815/**
4a4a9e81 1816 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1817 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1818 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1819 */
4a4a9e81 1820static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1821{
57aab75a 1822 int ret = 0;
b481de9c 1823
e1623446 1824 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1825
1826 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1827 /* We had an error bringing up the hardware, so take it
1828 * all the way back down so we can try again */
e1623446 1829 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1830 goto restart;
1831 }
1832
1833 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1834 * This is a paranoid check, because we would not have gotten the
1835 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1836 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1837 /* Runtime instruction load was bad;
1838 * take it all the way back down so we can try again */
e1623446 1839 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1840 goto restart;
1841 }
1842
c587de0b 1843 iwl_clear_stations_table(priv);
57aab75a
TW
1844 ret = priv->cfg->ops->lib->alive_notify(priv);
1845 if (ret) {
39aadf8c
WT
1846 IWL_WARN(priv,
1847 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1848 goto restart;
1849 }
1850
5b9f8cd3 1851 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1852 set_bit(STATUS_ALIVE, &priv->status);
1853
fee1247a 1854 if (iwl_is_rfkill(priv))
b481de9c
ZY
1855 return;
1856
36d6825b 1857 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1858
1859 priv->active_rate = priv->rates_mask;
1860 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1861
2f748dec
WYG
1862 /* Configure Tx antenna selection based on H/W config */
1863 if (priv->cfg->ops->hcmd->set_tx_ant)
1864 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
1865
3109ece1 1866 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1867 struct iwl_rxon_cmd *active_rxon =
1868 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1869 /* apply any changes in staging */
1870 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1871 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1872 } else {
1873 /* Initialize our rx_config data */
5b9f8cd3 1874 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
1875
1876 if (priv->cfg->ops->hcmd->set_rxon_chain)
1877 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1878
b481de9c
ZY
1879 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1880 }
1881
9fbab516 1882 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1883 iwl_send_bt_config(priv);
b481de9c 1884
4a4a9e81
TW
1885 iwl_reset_run_time_calib(priv);
1886
b481de9c 1887 /* Configure the adapter for unassociated operation */
e0158e61 1888 iwlcore_commit_rxon(priv);
b481de9c
ZY
1889
1890 /* At this point, the NIC is initialized and operational */
47f4a587 1891 iwl_rf_kill_ct_config(priv);
5a66926a 1892
e932a609 1893 iwl_leds_init(priv);
fe00b5a5 1894
e1623446 1895 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1896 set_bit(STATUS_READY, &priv->status);
5a66926a 1897 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1898
e312c24c 1899 iwl_power_update_mode(priv, true);
c46fbefa 1900
ada17513
MA
1901 /* reassociate for ADHOC mode */
1902 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1903 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1904 priv->vif);
1905 if (beacon)
1906 iwl_mac_beacon_update(priv->hw, beacon);
1907 }
1908
1909
c46fbefa 1910 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1911 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1912
b481de9c
ZY
1913 return;
1914
1915 restart:
1916 queue_work(priv->workqueue, &priv->restart);
1917}
1918
4e39317d 1919static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1920
5b9f8cd3 1921static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1922{
1923 unsigned long flags;
1924 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1925
e1623446 1926 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1927
b481de9c
ZY
1928 if (!exit_pending)
1929 set_bit(STATUS_EXIT_PENDING, &priv->status);
1930
c587de0b 1931 iwl_clear_stations_table(priv);
b481de9c
ZY
1932
1933 /* Unblock any waiting calls */
1934 wake_up_interruptible_all(&priv->wait_command_queue);
1935
b481de9c
ZY
1936 /* Wipe out the EXIT_PENDING status bit if we are not actually
1937 * exiting the module */
1938 if (!exit_pending)
1939 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1940
1941 /* stop and reset the on-board processor */
3395f6e9 1942 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
1943
1944 /* tell the device to stop sending interrupts */
0359facc 1945 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1946 iwl_disable_interrupts(priv);
0359facc
MA
1947 spin_unlock_irqrestore(&priv->lock, flags);
1948 iwl_synchronize_irq(priv);
b481de9c
ZY
1949
1950 if (priv->mac80211_registered)
1951 ieee80211_stop_queues(priv->hw);
1952
5b9f8cd3 1953 /* If we have not previously called iwl_init() then
a60e77e5 1954 * clear all bits but the RF Kill bit and return */
fee1247a 1955 if (!iwl_is_init(priv)) {
b481de9c
ZY
1956 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1957 STATUS_RF_KILL_HW |
9788864e
RC
1958 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1959 STATUS_GEO_CONFIGURED |
052ec3f1
MA
1960 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1961 STATUS_EXIT_PENDING;
b481de9c
ZY
1962 goto exit;
1963 }
1964
6da3a13e 1965 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 1966 * bit and continue taking the NIC down. */
b481de9c
ZY
1967 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1968 STATUS_RF_KILL_HW |
9788864e
RC
1969 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1970 STATUS_GEO_CONFIGURED |
b481de9c 1971 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
1972 STATUS_FW_ERROR |
1973 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1974 STATUS_EXIT_PENDING;
b481de9c 1975
ef850d7c
MA
1976 /* device going down, Stop using ICT table */
1977 iwl_disable_ict(priv);
b481de9c 1978
da1bc453 1979 iwl_txq_ctx_stop(priv);
b3bbacb7 1980 iwl_rxq_stop(priv);
b481de9c 1981
309e731a
BC
1982 /* Power-down device's busmaster DMA clocks */
1983 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
1984 udelay(5);
1985
309e731a
BC
1986 /* Make sure (redundant) we've released our request to stay awake */
1987 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1988
4d2ccdb9
BC
1989 /* Stop the device, and put it in low power state */
1990 priv->cfg->ops->lib->apm_ops.stop(priv);
1991
b481de9c 1992 exit:
885ba202 1993 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
1994
1995 if (priv->ibss_beacon)
1996 dev_kfree_skb(priv->ibss_beacon);
1997 priv->ibss_beacon = NULL;
1998
1999 /* clear out any free frames */
fcab423d 2000 iwl_clear_free_frames(priv);
b481de9c
ZY
2001}
2002
5b9f8cd3 2003static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2004{
2005 mutex_lock(&priv->mutex);
5b9f8cd3 2006 __iwl_down(priv);
b481de9c 2007 mutex_unlock(&priv->mutex);
b24d22b1 2008
4e39317d 2009 iwl_cancel_deferred_work(priv);
b481de9c
ZY
2010}
2011
086ed117
MA
2012#define HW_READY_TIMEOUT (50)
2013
2014static int iwl_set_hw_ready(struct iwl_priv *priv)
2015{
2016 int ret = 0;
2017
2018 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2019 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2020
2021 /* See if we got it */
2022 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2023 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2024 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2025 HW_READY_TIMEOUT);
2026 if (ret != -ETIMEDOUT)
2027 priv->hw_ready = true;
2028 else
2029 priv->hw_ready = false;
2030
2031 IWL_DEBUG_INFO(priv, "hardware %s\n",
2032 (priv->hw_ready == 1) ? "ready" : "not ready");
2033 return ret;
2034}
2035
2036static int iwl_prepare_card_hw(struct iwl_priv *priv)
2037{
2038 int ret = 0;
2039
2040 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
2041
3354a0f6
MA
2042 ret = iwl_set_hw_ready(priv);
2043 if (priv->hw_ready)
2044 return ret;
2045
2046 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
2047 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2048 CSR_HW_IF_CONFIG_REG_PREPARE);
2049
2050 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2051 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2052 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2053
3354a0f6 2054 /* HW should be ready by now, check again. */
086ed117
MA
2055 if (ret != -ETIMEDOUT)
2056 iwl_set_hw_ready(priv);
2057
2058 return ret;
2059}
2060
b481de9c
ZY
2061#define MAX_HW_RESTARTS 5
2062
5b9f8cd3 2063static int __iwl_up(struct iwl_priv *priv)
b481de9c 2064{
57aab75a
TW
2065 int i;
2066 int ret;
b481de9c
ZY
2067
2068 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2069 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2070 return -EIO;
2071 }
2072
e903fbd4 2073 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2074 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
2075 return -EIO;
2076 }
2077
086ed117
MA
2078 iwl_prepare_card_hw(priv);
2079
2080 if (!priv->hw_ready) {
2081 IWL_WARN(priv, "Exit HW not ready\n");
2082 return -EIO;
2083 }
2084
e655b9f0 2085 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2086 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2087 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2088 else
e655b9f0 2089 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2090
c1842d61 2091 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
2092 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2093
5b9f8cd3 2094 iwl_enable_interrupts(priv);
a60e77e5 2095 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2096 return 0;
b481de9c
ZY
2097 }
2098
3395f6e9 2099 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2100
1053d35f 2101 ret = iwl_hw_nic_init(priv);
57aab75a 2102 if (ret) {
15b1687c 2103 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2104 return ret;
b481de9c
ZY
2105 }
2106
2107 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2108 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2109 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2110 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2111
2112 /* clear (again), then enable host interrupts */
3395f6e9 2113 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2114 iwl_enable_interrupts(priv);
b481de9c
ZY
2115
2116 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2117 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2118 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2119
2120 /* Copy original ucode data image from disk into backup cache.
2121 * This will be used to initialize the on-board processor's
2122 * data SRAM for a clean start when the runtime program first loads. */
2123 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2124 priv->ucode_data.len);
b481de9c 2125
b481de9c
ZY
2126 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2127
c587de0b 2128 iwl_clear_stations_table(priv);
b481de9c
ZY
2129
2130 /* load bootstrap state machine,
2131 * load bootstrap program into processor's memory,
2132 * prepare to load the "initialize" uCode */
57aab75a 2133 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2134
57aab75a 2135 if (ret) {
15b1687c
WT
2136 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2137 ret);
b481de9c
ZY
2138 continue;
2139 }
2140
2141 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2142 iwl_nic_start(priv);
b481de9c 2143
e1623446 2144 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2145
2146 return 0;
2147 }
2148
2149 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2150 __iwl_down(priv);
64e72c3e 2151 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2152
2153 /* tried to restart and config the device for as long as our
2154 * patience could withstand */
15b1687c 2155 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2156 return -EIO;
2157}
2158
2159
2160/*****************************************************************************
2161 *
2162 * Workqueue callbacks
2163 *
2164 *****************************************************************************/
2165
4a4a9e81 2166static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2167{
c79dd5b5
TW
2168 struct iwl_priv *priv =
2169 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2170
2171 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2172 return;
2173
2174 mutex_lock(&priv->mutex);
f3ccc08c 2175 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2176 mutex_unlock(&priv->mutex);
2177}
2178
4a4a9e81 2179static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2180{
c79dd5b5
TW
2181 struct iwl_priv *priv =
2182 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2183
2184 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2185 return;
2186
258c44a0
MA
2187 /* enable dram interrupt */
2188 iwl_reset_ict(priv);
2189
b481de9c 2190 mutex_lock(&priv->mutex);
4a4a9e81 2191 iwl_alive_start(priv);
b481de9c
ZY
2192 mutex_unlock(&priv->mutex);
2193}
2194
16e727e8
EG
2195static void iwl_bg_run_time_calib_work(struct work_struct *work)
2196{
2197 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2198 run_time_calib_work);
2199
2200 mutex_lock(&priv->mutex);
2201
2202 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2203 test_bit(STATUS_SCANNING, &priv->status)) {
2204 mutex_unlock(&priv->mutex);
2205 return;
2206 }
2207
2208 if (priv->start_calib) {
2209 iwl_chain_noise_calibration(priv, &priv->statistics);
2210
2211 iwl_sensitivity_calibration(priv, &priv->statistics);
2212 }
2213
2214 mutex_unlock(&priv->mutex);
2215 return;
2216}
2217
5b9f8cd3 2218static void iwl_bg_up(struct work_struct *data)
b481de9c 2219{
c79dd5b5 2220 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2221
2222 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2223 return;
2224
2225 mutex_lock(&priv->mutex);
5b9f8cd3 2226 __iwl_up(priv);
b481de9c
ZY
2227 mutex_unlock(&priv->mutex);
2228}
2229
5b9f8cd3 2230static void iwl_bg_restart(struct work_struct *data)
b481de9c 2231{
c79dd5b5 2232 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2233
2234 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2235 return;
2236
19cc1087
JB
2237 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2238 mutex_lock(&priv->mutex);
2239 priv->vif = NULL;
2240 priv->is_open = 0;
2241 mutex_unlock(&priv->mutex);
2242 iwl_down(priv);
2243 ieee80211_restart_hw(priv->hw);
2244 } else {
2245 iwl_down(priv);
2246 queue_work(priv->workqueue, &priv->up);
2247 }
b481de9c
ZY
2248}
2249
5b9f8cd3 2250static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2251{
c79dd5b5
TW
2252 struct iwl_priv *priv =
2253 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2254
2255 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2256 return;
2257
2258 mutex_lock(&priv->mutex);
a55360e4 2259 iwl_rx_replenish(priv);
b481de9c
ZY
2260 mutex_unlock(&priv->mutex);
2261}
2262
7878a5a4
MA
2263#define IWL_DELAY_NEXT_SCAN (HZ*2)
2264
5bbe233b 2265void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2266{
b481de9c 2267 struct ieee80211_conf *conf = NULL;
857485c0 2268 int ret = 0;
1ff50bda 2269 unsigned long flags;
b481de9c 2270
05c914fe 2271 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2272 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2273 return;
2274 }
2275
e1623446 2276 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2277 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2278
2279
2280 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2281 return;
2282
b481de9c 2283
508e32e1 2284 if (!priv->vif || !priv->is_open)
948c171c 2285 return;
508e32e1 2286
2a421b91 2287 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2288
b481de9c
ZY
2289 conf = ieee80211_get_hw_conf(priv->hw);
2290
2291 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2292 iwlcore_commit_rxon(priv);
b481de9c 2293
3195c1f3 2294 iwl_setup_rxon_timing(priv);
857485c0 2295 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2296 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2297 if (ret)
39aadf8c 2298 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2299 "Attempting to continue.\n");
2300
2301 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2302
42eb7c64 2303 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2304
45823531
AK
2305 if (priv->cfg->ops->hcmd->set_rxon_chain)
2306 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2307
b481de9c
ZY
2308 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2309
e1623446 2310 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2311 priv->assoc_id, priv->beacon_int);
2312
2313 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2314 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2315 else
2316 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2317
2318 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2319 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2320 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2321 else
2322 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2323
05c914fe 2324 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2325 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2326
2327 }
2328
e0158e61 2329 iwlcore_commit_rxon(priv);
b481de9c
ZY
2330
2331 switch (priv->iw_mode) {
05c914fe 2332 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2333 break;
2334
05c914fe 2335 case NL80211_IFTYPE_ADHOC:
b481de9c 2336
c46fbefa
AK
2337 /* assume default assoc id */
2338 priv->assoc_id = 1;
b481de9c 2339
4f40e4d9 2340 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2341 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2342
2343 break;
2344
2345 default:
15b1687c 2346 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2347 __func__, priv->iw_mode);
b481de9c
ZY
2348 break;
2349 }
2350
05c914fe 2351 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2352 priv->assoc_station_added = 1;
2353
1ff50bda
EG
2354 spin_lock_irqsave(&priv->lock, flags);
2355 iwl_activate_qos(priv, 0);
2356 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2357
04816448
GE
2358 /* the chain noise calibration will enabled PM upon completion
2359 * If chain noise has already been run, then we need to enable
2360 * power management here */
2361 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2362 iwl_power_update_mode(priv, false);
c90a74ba
EG
2363
2364 /* Enable Rx differential gain and sensitivity calibrations */
2365 iwl_chain_noise_reset(priv);
2366 priv->start_calib = 1;
2367
508e32e1
RC
2368}
2369
b481de9c
ZY
2370/*****************************************************************************
2371 *
2372 * mac80211 entry point functions
2373 *
2374 *****************************************************************************/
2375
154b25ce 2376#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2377
f0b6e2e8
RC
2378/*
2379 * Not a mac80211 entry point function, but it fits in with all the
2380 * other mac80211 functions grouped here.
2381 */
2382static int iwl_setup_mac(struct iwl_priv *priv)
2383{
2384 int ret;
2385 struct ieee80211_hw *hw = priv->hw;
2386 hw->rate_control_algorithm = "iwl-agn-rs";
2387
2388 /* Tell mac80211 our characteristics */
2389 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2390 IEEE80211_HW_NOISE_DBM |
2391 IEEE80211_HW_AMPDU_AGGREGATION |
2392 IEEE80211_HW_SPECTRUM_MGMT;
2393
2394 if (!priv->cfg->broken_powersave)
2395 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2396 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2397
8d9698b3 2398 hw->sta_data_size = sizeof(struct iwl_station_priv);
f0b6e2e8
RC
2399 hw->wiphy->interface_modes =
2400 BIT(NL80211_IFTYPE_STATION) |
2401 BIT(NL80211_IFTYPE_ADHOC);
2402
5be83de5
JB
2403 hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
2404 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC
2405
2406 /*
2407 * For now, disable PS by default because it affects
2408 * RX performance significantly.
2409 */
5be83de5 2410 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8
RC
2411
2412 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2413 /* we create the 802.11 header and a zero-length SSID element */
2414 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2415
2416 /* Default value; 4 EDCA QOS priorities */
2417 hw->queues = 4;
2418
2419 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2420
2421 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2422 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2423 &priv->bands[IEEE80211_BAND_2GHZ];
2424 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2425 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2426 &priv->bands[IEEE80211_BAND_5GHZ];
2427
2428 ret = ieee80211_register_hw(priv->hw);
2429 if (ret) {
2430 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2431 return ret;
2432 }
2433 priv->mac80211_registered = 1;
2434
2435 return 0;
2436}
2437
2438
5b9f8cd3 2439static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2440{
c79dd5b5 2441 struct iwl_priv *priv = hw->priv;
5a66926a 2442 int ret;
b481de9c 2443
e1623446 2444 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2445
2446 /* we should be verifying the device is ready to be opened */
2447 mutex_lock(&priv->mutex);
2448
5a66926a
ZY
2449 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2450 * ucode filename and max sizes are card-specific. */
b481de9c 2451
5a66926a 2452 if (!priv->ucode_code.len) {
5b9f8cd3 2453 ret = iwl_read_ucode(priv);
5a66926a 2454 if (ret) {
15b1687c 2455 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2456 mutex_unlock(&priv->mutex);
6cd0b1cb 2457 return ret;
5a66926a
ZY
2458 }
2459 }
b481de9c 2460
5b9f8cd3 2461 ret = __iwl_up(priv);
5a66926a 2462
b481de9c 2463 mutex_unlock(&priv->mutex);
5a66926a 2464
e655b9f0 2465 if (ret)
6cd0b1cb 2466 return ret;
e655b9f0 2467
c1842d61
TW
2468 if (iwl_is_rfkill(priv))
2469 goto out;
2470
e1623446 2471 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2472
fe9b6b72 2473 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2474 * mac80211 will not be run successfully. */
154b25ce
EG
2475 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2476 test_bit(STATUS_READY, &priv->status),
2477 UCODE_READY_TIMEOUT);
2478 if (!ret) {
2479 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2480 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2481 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2482 return -ETIMEDOUT;
5a66926a 2483 }
fe9b6b72 2484 }
0a078ffa 2485
e932a609
JB
2486 iwl_led_start(priv);
2487
c1842d61 2488out:
0a078ffa 2489 priv->is_open = 1;
e1623446 2490 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2491 return 0;
2492}
2493
5b9f8cd3 2494static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2495{
c79dd5b5 2496 struct iwl_priv *priv = hw->priv;
b481de9c 2497
e1623446 2498 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2499
19cc1087 2500 if (!priv->is_open)
e655b9f0 2501 return;
e655b9f0 2502
b481de9c 2503 priv->is_open = 0;
5a66926a 2504
5bddf549 2505 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2506 /* stop mac, cancel any scan request and clear
2507 * RXON_FILTER_ASSOC_MSK BIT
2508 */
5a66926a 2509 mutex_lock(&priv->mutex);
2a421b91 2510 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2511 mutex_unlock(&priv->mutex);
fde3571f
MA
2512 }
2513
5b9f8cd3 2514 iwl_down(priv);
5a66926a
ZY
2515
2516 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2517
2518 /* enable interrupts again in order to receive rfkill changes */
2519 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2520 iwl_enable_interrupts(priv);
948c171c 2521
e1623446 2522 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2523}
2524
5b9f8cd3 2525static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2526{
c79dd5b5 2527 struct iwl_priv *priv = hw->priv;
b481de9c 2528
e1623446 2529 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2530
e1623446 2531 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2532 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2533
e039fa4a 2534 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2535 dev_kfree_skb_any(skb);
2536
e1623446 2537 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2538 return NETDEV_TX_OK;
b481de9c
ZY
2539}
2540
60690a6a 2541void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2542{
857485c0 2543 int ret = 0;
1ff50bda 2544 unsigned long flags;
b481de9c 2545
d986bcd1 2546 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2547 return;
2548
2549 /* The following should be done only at AP bring up */
3195c1f3 2550 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2551
2552 /* RXON - unassoc (to set timing command) */
2553 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2554 iwlcore_commit_rxon(priv);
b481de9c
ZY
2555
2556 /* RXON Timing */
3195c1f3 2557 iwl_setup_rxon_timing(priv);
857485c0 2558 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2559 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2560 if (ret)
39aadf8c 2561 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2562 "Attempting to continue.\n");
2563
f513dfff
DH
2564 /* AP has all antennas */
2565 priv->chain_noise_data.active_chains =
2566 priv->hw_params.valid_rx_ant;
2567 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK
2568 if (priv->cfg->ops->hcmd->set_rxon_chain)
2569 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2570
2571 /* FIXME: what should be the assoc_id for AP? */
2572 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2573 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2574 priv->staging_rxon.flags |=
2575 RXON_FLG_SHORT_PREAMBLE_MSK;
2576 else
2577 priv->staging_rxon.flags &=
2578 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2579
2580 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2581 if (priv->assoc_capability &
2582 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2583 priv->staging_rxon.flags |=
2584 RXON_FLG_SHORT_SLOT_MSK;
2585 else
2586 priv->staging_rxon.flags &=
2587 ~RXON_FLG_SHORT_SLOT_MSK;
2588
05c914fe 2589 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2590 priv->staging_rxon.flags &=
2591 ~RXON_FLG_SHORT_SLOT_MSK;
2592 }
2593 /* restore RXON assoc */
2594 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2595 iwlcore_commit_rxon(priv);
f513dfff 2596 iwl_reset_qos(priv);
1ff50bda
EG
2597 spin_lock_irqsave(&priv->lock, flags);
2598 iwl_activate_qos(priv, 1);
2599 spin_unlock_irqrestore(&priv->lock, flags);
9a9ca65f 2600 iwl_add_bcast_station(priv);
e1493deb 2601 }
5b9f8cd3 2602 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2603
2604 /* FIXME - we need to add code here to detect a totally new
2605 * configuration, reset the AP, unassoc, rxon timing, assoc,
2606 * clear sta table, add BCAST sta... */
2607}
2608
5b9f8cd3 2609static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2610 struct ieee80211_key_conf *keyconf, const u8 *addr,
2611 u32 iv32, u16 *phase1key)
2612{
ab885f8c 2613
9f58671e 2614 struct iwl_priv *priv = hw->priv;
e1623446 2615 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2616
9f58671e 2617 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2618
e1623446 2619 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2620}
2621
5b9f8cd3 2622static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2623 struct ieee80211_vif *vif,
2624 struct ieee80211_sta *sta,
b481de9c
ZY
2625 struct ieee80211_key_conf *key)
2626{
c79dd5b5 2627 struct iwl_priv *priv = hw->priv;
42986796
WT
2628 const u8 *addr;
2629 int ret;
2630 u8 sta_id;
2631 bool is_default_wep_key = false;
b481de9c 2632
e1623446 2633 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2634
90e8e424 2635 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2636 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2637 return -EOPNOTSUPP;
2638 }
42986796 2639 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2640 sta_id = iwl_find_station(priv, addr);
6974e363 2641 if (sta_id == IWL_INVALID_STATION) {
e1623446 2642 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2643 addr);
6974e363 2644 return -EINVAL;
b481de9c 2645
deb09c43 2646 }
b481de9c 2647
6974e363 2648 mutex_lock(&priv->mutex);
2a421b91 2649 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2650 mutex_unlock(&priv->mutex);
2651
2652 /* If we are getting WEP group key and we didn't receive any key mapping
2653 * so far, we are in legacy wep mode (group key only), otherwise we are
2654 * in 1X mode.
2655 * In legacy wep mode, we use another host command to the uCode */
5425e490 2656 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2657 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2658 if (cmd == SET_KEY)
2659 is_default_wep_key = !priv->key_mapping_key;
2660 else
ccc038ab
EG
2661 is_default_wep_key =
2662 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2663 }
052c4b9f 2664
b481de9c 2665 switch (cmd) {
deb09c43 2666 case SET_KEY:
6974e363
EG
2667 if (is_default_wep_key)
2668 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2669 else
7480513f 2670 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2671
e1623446 2672 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2673 break;
2674 case DISABLE_KEY:
6974e363
EG
2675 if (is_default_wep_key)
2676 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2677 else
3ec47732 2678 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2679
e1623446 2680 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2681 break;
2682 default:
deb09c43 2683 ret = -EINVAL;
b481de9c
ZY
2684 }
2685
e1623446 2686 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2687
deb09c43 2688 return ret;
b481de9c
ZY
2689}
2690
5b9f8cd3 2691static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2692 struct ieee80211_vif *vif,
d783b061 2693 enum ieee80211_ampdu_mlme_action action,
17741cdc 2694 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2695{
2696 struct iwl_priv *priv = hw->priv;
5c2207c6 2697 int ret;
d783b061 2698
e1623446 2699 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2700 sta->addr, tid);
d783b061
TW
2701
2702 if (!(priv->cfg->sku & IWL_SKU_N))
2703 return -EACCES;
2704
2705 switch (action) {
2706 case IEEE80211_AMPDU_RX_START:
e1623446 2707 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2708 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2709 case IEEE80211_AMPDU_RX_STOP:
e1623446 2710 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2711 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2712 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2713 return 0;
2714 else
2715 return ret;
d783b061 2716 case IEEE80211_AMPDU_TX_START:
e1623446 2717 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2718 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2719 case IEEE80211_AMPDU_TX_STOP:
e1623446 2720 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2721 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2722 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2723 return 0;
2724 else
2725 return ret;
d783b061 2726 default:
e1623446 2727 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2728 return -EINVAL;
2729 break;
2730 }
2731 return 0;
2732}
9f58671e 2733
5b9f8cd3 2734static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2735 struct ieee80211_low_level_stats *stats)
2736{
bf403db8
EK
2737 struct iwl_priv *priv = hw->priv;
2738
2739 priv = hw->priv;
e1623446
TW
2740 IWL_DEBUG_MAC80211(priv, "enter\n");
2741 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2742
2743 return 0;
2744}
2745
6ab10ff8
JB
2746static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
2747 struct ieee80211_vif *vif,
2748 enum sta_notify_cmd cmd,
2749 struct ieee80211_sta *sta)
2750{
2751 struct iwl_priv *priv = hw->priv;
2752 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
2753 int sta_id;
2754
2755 /*
2756 * TODO: We really should use this callback to
2757 * actually maintain the station table in
2758 * the device.
2759 */
2760
2761 switch (cmd) {
2762 case STA_NOTIFY_ADD:
2763 atomic_set(&sta_priv->pending_frames, 0);
2764 if (vif->type == NL80211_IFTYPE_AP)
2765 sta_priv->client = true;
2766 break;
2767 case STA_NOTIFY_SLEEP:
2768 WARN_ON(!sta_priv->client);
2769 sta_priv->asleep = true;
2770 if (atomic_read(&sta_priv->pending_frames) > 0)
2771 ieee80211_sta_block_awake(hw, sta, true);
2772 break;
2773 case STA_NOTIFY_AWAKE:
2774 WARN_ON(!sta_priv->client);
2775 sta_priv->asleep = false;
2776 sta_id = iwl_find_station(priv, sta->addr);
2777 if (sta_id != IWL_INVALID_STATION)
2778 iwl_sta_modify_ps_wake(priv, sta_id);
2779 break;
2780 default:
2781 break;
2782 }
2783}
2784
b481de9c
ZY
2785/*****************************************************************************
2786 *
2787 * sysfs attributes
2788 *
2789 *****************************************************************************/
2790
0a6857e7 2791#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2792
2793/*
2794 * The following adds a new attribute to the sysfs representation
c3a739fa 2795 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2796 * used for controlling the debug level.
2797 *
2798 * See the level definitions in iwl for details.
a562a9dd 2799 *
3d816c77
RC
2800 * The debug_level being managed using sysfs below is a per device debug
2801 * level that is used instead of the global debug level if it (the per
2802 * device debug level) is set.
b481de9c 2803 */
8cf769c6
EK
2804static ssize_t show_debug_level(struct device *d,
2805 struct device_attribute *attr, char *buf)
b481de9c 2806{
3d816c77
RC
2807 struct iwl_priv *priv = dev_get_drvdata(d);
2808 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 2809}
8cf769c6
EK
2810static ssize_t store_debug_level(struct device *d,
2811 struct device_attribute *attr,
b481de9c
ZY
2812 const char *buf, size_t count)
2813{
928841b1 2814 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2815 unsigned long val;
2816 int ret;
b481de9c 2817
9257746f
TW
2818 ret = strict_strtoul(buf, 0, &val);
2819 if (ret)
978785a3 2820 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 2821 else {
3d816c77 2822 priv->debug_level = val;
20594eb0
WYG
2823 if (iwl_alloc_traffic_mem(priv))
2824 IWL_ERR(priv,
2825 "Not enough memory to generate traffic log\n");
2826 }
b481de9c
ZY
2827 return strnlen(buf, count);
2828}
2829
8cf769c6
EK
2830static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2831 show_debug_level, store_debug_level);
2832
b481de9c 2833
0a6857e7 2834#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2835
b481de9c
ZY
2836
2837static ssize_t show_temperature(struct device *d,
2838 struct device_attribute *attr, char *buf)
2839{
928841b1 2840 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 2841
fee1247a 2842 if (!iwl_is_alive(priv))
b481de9c
ZY
2843 return -EAGAIN;
2844
91dbc5bd 2845 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2846}
2847
2848static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2849
b481de9c
ZY
2850static ssize_t show_tx_power(struct device *d,
2851 struct device_attribute *attr, char *buf)
2852{
928841b1 2853 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
2854
2855 if (!iwl_is_ready_rf(priv))
2856 return sprintf(buf, "off\n");
2857 else
2858 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2859}
2860
2861static ssize_t store_tx_power(struct device *d,
2862 struct device_attribute *attr,
2863 const char *buf, size_t count)
2864{
928841b1 2865 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2866 unsigned long val;
2867 int ret;
b481de9c 2868
9257746f
TW
2869 ret = strict_strtoul(buf, 10, &val);
2870 if (ret)
978785a3 2871 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
2872 else {
2873 ret = iwl_set_tx_power(priv, val, false);
2874 if (ret)
2875 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
2876 ret);
2877 else
2878 ret = count;
2879 }
2880 return ret;
b481de9c
ZY
2881}
2882
2883static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2884
2885static ssize_t show_flags(struct device *d,
2886 struct device_attribute *attr, char *buf)
2887{
928841b1 2888 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2889
2890 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2891}
2892
2893static ssize_t store_flags(struct device *d,
2894 struct device_attribute *attr,
2895 const char *buf, size_t count)
2896{
928841b1 2897 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2898 unsigned long val;
2899 u32 flags;
2900 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2901 if (ret)
9257746f
TW
2902 return ret;
2903 flags = (u32)val;
b481de9c
ZY
2904
2905 mutex_lock(&priv->mutex);
2906 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2907 /* Cancel any currently running scans... */
2a421b91 2908 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2909 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2910 else {
e1623446 2911 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2912 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2913 iwlcore_commit_rxon(priv);
b481de9c
ZY
2914 }
2915 }
2916 mutex_unlock(&priv->mutex);
2917
2918 return count;
2919}
2920
2921static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2922
2923static ssize_t show_filter_flags(struct device *d,
2924 struct device_attribute *attr, char *buf)
2925{
928841b1 2926 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2927
2928 return sprintf(buf, "0x%04X\n",
2929 le32_to_cpu(priv->active_rxon.filter_flags));
2930}
2931
2932static ssize_t store_filter_flags(struct device *d,
2933 struct device_attribute *attr,
2934 const char *buf, size_t count)
2935{
928841b1 2936 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2937 unsigned long val;
2938 u32 filter_flags;
2939 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2940 if (ret)
9257746f
TW
2941 return ret;
2942 filter_flags = (u32)val;
b481de9c
ZY
2943
2944 mutex_lock(&priv->mutex);
2945 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2946 /* Cancel any currently running scans... */
2a421b91 2947 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2948 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2949 else {
e1623446 2950 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
2951 "0x%04X\n", filter_flags);
2952 priv->staging_rxon.filter_flags =
2953 cpu_to_le32(filter_flags);
e0158e61 2954 iwlcore_commit_rxon(priv);
b481de9c
ZY
2955 }
2956 }
2957 mutex_unlock(&priv->mutex);
2958
2959 return count;
2960}
2961
2962static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2963 store_filter_flags);
2964
b481de9c
ZY
2965
2966static ssize_t show_statistics(struct device *d,
2967 struct device_attribute *attr, char *buf)
2968{
c79dd5b5 2969 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 2970 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 2971 u32 len = 0, ofs = 0;
3ac7f146 2972 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
2973 int rc = 0;
2974
fee1247a 2975 if (!iwl_is_alive(priv))
b481de9c
ZY
2976 return -EAGAIN;
2977
2978 mutex_lock(&priv->mutex);
ef8d5529 2979 rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
b481de9c
ZY
2980 mutex_unlock(&priv->mutex);
2981
2982 if (rc) {
2983 len = sprintf(buf,
2984 "Error sending statistics request: 0x%08X\n", rc);
2985 return len;
2986 }
2987
2988 while (size && (PAGE_SIZE - len)) {
2989 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2990 PAGE_SIZE - len, 1);
2991 len = strlen(buf);
2992 if (PAGE_SIZE - len)
2993 buf[len++] = '\n';
2994
2995 ofs += 16;
2996 size -= min(size, 16U);
2997 }
2998
2999 return len;
3000}
3001
3002static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3003
01abfbb2
WYG
3004static ssize_t show_rts_ht_protection(struct device *d,
3005 struct device_attribute *attr, char *buf)
3006{
3007 struct iwl_priv *priv = dev_get_drvdata(d);
3008
3009 return sprintf(buf, "%s\n",
3010 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3011}
3012
3013static ssize_t store_rts_ht_protection(struct device *d,
3014 struct device_attribute *attr,
3015 const char *buf, size_t count)
3016{
3017 struct iwl_priv *priv = dev_get_drvdata(d);
3018 unsigned long val;
3019 int ret;
3020
3021 ret = strict_strtoul(buf, 10, &val);
3022 if (ret)
3023 IWL_INFO(priv, "Input is not in decimal form.\n");
3024 else {
3025 if (!iwl_is_associated(priv))
3026 priv->cfg->use_rts_for_ht = val ? true : false;
3027 else
3028 IWL_ERR(priv, "Sta associated with AP - "
3029 "Change protection mechanism is not allowed\n");
3030 ret = count;
3031 }
3032 return ret;
3033}
3034
3035static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3036 show_rts_ht_protection, store_rts_ht_protection);
3037
b481de9c 3038
b481de9c
ZY
3039/*****************************************************************************
3040 *
3041 * driver setup and teardown
3042 *
3043 *****************************************************************************/
3044
4e39317d 3045static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3046{
d21050c7 3047 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3048
3049 init_waitqueue_head(&priv->wait_command_queue);
3050
5b9f8cd3
EG
3051 INIT_WORK(&priv->up, iwl_bg_up);
3052 INIT_WORK(&priv->restart, iwl_bg_restart);
3053 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3054 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3055 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
3056 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3057 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3058
2a421b91 3059 iwl_setup_scan_deferred_work(priv);
bb8c093b 3060
4e39317d
EG
3061 if (priv->cfg->ops->lib->setup_deferred_work)
3062 priv->cfg->ops->lib->setup_deferred_work(priv);
3063
3064 init_timer(&priv->statistics_periodic);
3065 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3066 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3067
ef850d7c
MA
3068 if (!priv->cfg->use_isr_legacy)
3069 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3070 iwl_irq_tasklet, (unsigned long)priv);
3071 else
3072 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3073 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
3074}
3075
4e39317d 3076static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3077{
4e39317d
EG
3078 if (priv->cfg->ops->lib->cancel_deferred_work)
3079 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3080
3ae6a054 3081 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3082 cancel_delayed_work(&priv->scan_check);
3083 cancel_delayed_work(&priv->alive_start);
b481de9c 3084 cancel_work_sync(&priv->beacon_update);
4e39317d 3085 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
3086}
3087
89f186a8
RC
3088static void iwl_init_hw_rates(struct iwl_priv *priv,
3089 struct ieee80211_rate *rates)
3090{
3091 int i;
3092
3093 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3094 rates[i].bitrate = iwl_rates[i].ieee * 5;
3095 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3096 rates[i].hw_value_short = i;
3097 rates[i].flags = 0;
3098 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3099 /*
3100 * If CCK != 1M then set short preamble rate flag.
3101 */
3102 rates[i].flags |=
3103 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3104 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3105 }
3106 }
3107}
3108
3109static int iwl_init_drv(struct iwl_priv *priv)
3110{
3111 int ret;
3112
3113 priv->ibss_beacon = NULL;
3114
3115 spin_lock_init(&priv->lock);
3116 spin_lock_init(&priv->sta_lock);
3117 spin_lock_init(&priv->hcmd_lock);
3118
3119 INIT_LIST_HEAD(&priv->free_frames);
3120
3121 mutex_init(&priv->mutex);
3122
3123 /* Clear the driver's (not device's) station table */
3124 iwl_clear_stations_table(priv);
3125
3126 priv->ieee_channels = NULL;
3127 priv->ieee_rates = NULL;
3128 priv->band = IEEE80211_BAND_2GHZ;
3129
3130 priv->iw_mode = NL80211_IFTYPE_STATION;
3f3e0376
WYG
3131 if (priv->cfg->support_sm_ps)
3132 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DYNAMIC;
3133 else
3134 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
89f186a8
RC
3135
3136 /* Choose which receivers/antennas to use */
3137 if (priv->cfg->ops->hcmd->set_rxon_chain)
3138 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3139
3140 iwl_init_scan_params(priv);
3141
3142 iwl_reset_qos(priv);
3143
3144 priv->qos_data.qos_active = 0;
3145 priv->qos_data.qos_cap.val = 0;
3146
3147 priv->rates_mask = IWL_RATES_MASK;
3148 /* Set the tx_power_user_lmt to the lowest power level
3149 * this value will get overwritten by channel max power avg
3150 * from eeprom */
3151 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
3152
3153 ret = iwl_init_channel_map(priv);
3154 if (ret) {
3155 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3156 goto err;
3157 }
3158
3159 ret = iwlcore_init_geos(priv);
3160 if (ret) {
3161 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3162 goto err_free_channel_map;
3163 }
3164 iwl_init_hw_rates(priv, priv->ieee_rates);
3165
3166 return 0;
3167
3168err_free_channel_map:
3169 iwl_free_channel_map(priv);
3170err:
3171 return ret;
3172}
3173
3174static void iwl_uninit_drv(struct iwl_priv *priv)
3175{
3176 iwl_calib_free_results(priv);
3177 iwlcore_free_geos(priv);
3178 iwl_free_channel_map(priv);
3179 kfree(priv->scan);
3180}
3181
5b9f8cd3 3182static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
3183 &dev_attr_flags.attr,
3184 &dev_attr_filter_flags.attr,
b481de9c 3185 &dev_attr_statistics.attr,
b481de9c 3186 &dev_attr_temperature.attr,
b481de9c 3187 &dev_attr_tx_power.attr,
01abfbb2 3188 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK
3189#ifdef CONFIG_IWLWIFI_DEBUG
3190 &dev_attr_debug_level.attr,
3191#endif
b481de9c
ZY
3192 NULL
3193};
3194
5b9f8cd3 3195static struct attribute_group iwl_attribute_group = {
b481de9c 3196 .name = NULL, /* put in device directory */
5b9f8cd3 3197 .attrs = iwl_sysfs_entries,
b481de9c
ZY
3198};
3199
5b9f8cd3
EG
3200static struct ieee80211_ops iwl_hw_ops = {
3201 .tx = iwl_mac_tx,
3202 .start = iwl_mac_start,
3203 .stop = iwl_mac_stop,
3204 .add_interface = iwl_mac_add_interface,
3205 .remove_interface = iwl_mac_remove_interface,
3206 .config = iwl_mac_config,
5b9f8cd3
EG
3207 .configure_filter = iwl_configure_filter,
3208 .set_key = iwl_mac_set_key,
3209 .update_tkip_key = iwl_mac_update_tkip_key,
3210 .get_stats = iwl_mac_get_stats,
3211 .get_tx_stats = iwl_mac_get_tx_stats,
3212 .conf_tx = iwl_mac_conf_tx,
3213 .reset_tsf = iwl_mac_reset_tsf,
3214 .bss_info_changed = iwl_bss_info_changed,
3215 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB
3216 .hw_scan = iwl_mac_hw_scan,
3217 .sta_notify = iwl_mac_sta_notify,
b481de9c
ZY
3218};
3219
5b9f8cd3 3220static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3221{
3222 int err = 0;
c79dd5b5 3223 struct iwl_priv *priv;
b481de9c 3224 struct ieee80211_hw *hw;
82b9a121 3225 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3226 unsigned long flags;
6cd0b1cb 3227 u16 pci_cmd;
b481de9c 3228
316c30d9
AK
3229 /************************
3230 * 1. Allocating HW data
3231 ************************/
3232
6440adb5
BC
3233 /* Disabling hardware scan means that mac80211 will perform scans
3234 * "the hard way", rather than using device's scan. */
1ea87396 3235 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3236 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
3237 dev_printk(KERN_DEBUG, &(pdev->dev),
3238 "Disabling hw_scan\n");
5b9f8cd3 3239 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3240 }
3241
5b9f8cd3 3242 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3243 if (!hw) {
b481de9c
ZY
3244 err = -ENOMEM;
3245 goto out;
3246 }
1d0a082d
AK
3247 priv = hw->priv;
3248 /* At this point both hw and priv are allocated. */
3249
b481de9c
ZY
3250 SET_IEEE80211_DEV(hw, &pdev->dev);
3251
e1623446 3252 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3253 priv->cfg = cfg;
b481de9c 3254 priv->pci_dev = pdev;
40cefda9 3255 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3256
0a6857e7 3257#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3258 atomic_set(&priv->restrict_refcnt, 0);
3259#endif
20594eb0
WYG
3260 if (iwl_alloc_traffic_mem(priv))
3261 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3262
316c30d9
AK
3263 /**************************
3264 * 2. Initializing PCI bus
3265 **************************/
3266 if (pci_enable_device(pdev)) {
3267 err = -ENODEV;
3268 goto out_ieee80211_free_hw;
3269 }
3270
3271 pci_set_master(pdev);
3272
093d874c 3273 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3274 if (!err)
093d874c 3275 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3276 if (err) {
093d874c 3277 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3278 if (!err)
093d874c 3279 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3280 /* both attempts failed: */
316c30d9 3281 if (err) {
978785a3 3282 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3283 goto out_pci_disable_device;
cc2a8ea8 3284 }
316c30d9
AK
3285 }
3286
3287 err = pci_request_regions(pdev, DRV_NAME);
3288 if (err)
3289 goto out_pci_disable_device;
3290
3291 pci_set_drvdata(pdev, priv);
3292
316c30d9
AK
3293
3294 /***********************
3295 * 3. Read REV register
3296 ***********************/
3297 priv->hw_base = pci_iomap(pdev, 0, 0);
3298 if (!priv->hw_base) {
3299 err = -ENODEV;
3300 goto out_pci_release_regions;
3301 }
3302
e1623446 3303 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3304 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3305 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3306
a8b50a0a
MA
3307 /* this spin lock will be used in apm_ops.init and EEPROM access
3308 * we should init now
3309 */
3310 spin_lock_init(&priv->reg_lock);
b661c819 3311 iwl_hw_detect(priv);
978785a3 3312 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 3313 priv->cfg->name, priv->hw_rev);
316c30d9 3314
e7b63581
TW
3315 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3316 * PCI Tx retries from interfering with C3 CPU state */
3317 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3318
086ed117
MA
3319 iwl_prepare_card_hw(priv);
3320 if (!priv->hw_ready) {
3321 IWL_WARN(priv, "Failed, HW not ready\n");
3322 goto out_iounmap;
3323 }
3324
91238714
TW
3325 /*****************
3326 * 4. Read EEPROM
3327 *****************/
316c30d9
AK
3328 /* Read the EEPROM */
3329 err = iwl_eeprom_init(priv);
3330 if (err) {
15b1687c 3331 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3332 goto out_iounmap;
3333 }
8614f360
TW
3334 err = iwl_eeprom_check_version(priv);
3335 if (err)
c8f16138 3336 goto out_free_eeprom;
8614f360 3337
02883017 3338 /* extract MAC Address */
316c30d9 3339 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3340 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3341 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3342
3343 /************************
3344 * 5. Setup HW constants
3345 ************************/
da154e30 3346 if (iwl_set_hw_params(priv)) {
15b1687c 3347 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3348 goto out_free_eeprom;
316c30d9
AK
3349 }
3350
3351 /*******************
6ba87956 3352 * 6. Setup priv
316c30d9 3353 *******************/
b481de9c 3354
6ba87956 3355 err = iwl_init_drv(priv);
bf85ea4f 3356 if (err)
399f4900 3357 goto out_free_eeprom;
bf85ea4f 3358 /* At this point both hw and priv are initialized. */
316c30d9 3359
316c30d9 3360 /********************
09f9bf79 3361 * 7. Setup services
316c30d9 3362 ********************/
0359facc 3363 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3364 iwl_disable_interrupts(priv);
0359facc 3365 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3366
6cd0b1cb
HS
3367 pci_enable_msi(priv->pci_dev);
3368
ef850d7c
MA
3369 iwl_alloc_isr_ict(priv);
3370 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3371 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3372 if (err) {
3373 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3374 goto out_disable_msi;
3375 }
5b9f8cd3 3376 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3377 if (err) {
15b1687c 3378 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3379 goto out_free_irq;
316c30d9
AK
3380 }
3381
4e39317d 3382 iwl_setup_deferred_work(priv);
653fa4a0 3383 iwl_setup_rx_handlers(priv);
316c30d9 3384
6ba87956 3385 /**********************************
09f9bf79 3386 * 8. Setup and register mac80211
6ba87956
TW
3387 **********************************/
3388
6cd0b1cb
HS
3389 /* enable interrupts if needed: hw bug w/a */
3390 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3391 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3392 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3393 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3394 }
3395
3396 iwl_enable_interrupts(priv);
3397
6ba87956
TW
3398 err = iwl_setup_mac(priv);
3399 if (err)
3400 goto out_remove_sysfs;
3401
3402 err = iwl_dbgfs_register(priv, DRV_NAME);
3403 if (err)
a75fbe8d 3404 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
6ba87956 3405
6cd0b1cb
HS
3406 /* If platform's RF_KILL switch is NOT set to KILL */
3407 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3408 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3409 else
3410 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3411
a60e77e5
JB
3412 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3413 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3414
58d0f361 3415 iwl_power_initialize(priv);
39b73fb1 3416 iwl_tt_initialize(priv);
b481de9c
ZY
3417 return 0;
3418
316c30d9 3419 out_remove_sysfs:
c8f16138
RC
3420 destroy_workqueue(priv->workqueue);
3421 priv->workqueue = NULL;
5b9f8cd3 3422 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3423 out_free_irq:
3424 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3425 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3426 out_disable_msi:
3427 pci_disable_msi(priv->pci_dev);
6ba87956 3428 iwl_uninit_drv(priv);
073d3f5f
TW
3429 out_free_eeprom:
3430 iwl_eeprom_free(priv);
b481de9c
ZY
3431 out_iounmap:
3432 pci_iounmap(pdev, priv->hw_base);
3433 out_pci_release_regions:
316c30d9 3434 pci_set_drvdata(pdev, NULL);
623d563e 3435 pci_release_regions(pdev);
b481de9c
ZY
3436 out_pci_disable_device:
3437 pci_disable_device(pdev);
b481de9c 3438 out_ieee80211_free_hw:
20594eb0 3439 iwl_free_traffic_mem(priv);
d7c76f4c 3440 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3441 out:
3442 return err;
3443}
3444
5b9f8cd3 3445static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3446{
c79dd5b5 3447 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3448 unsigned long flags;
b481de9c
ZY
3449
3450 if (!priv)
3451 return;
3452
e1623446 3453 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3454
67249625 3455 iwl_dbgfs_unregister(priv);
5b9f8cd3 3456 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3457
5b9f8cd3
EG
3458 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3459 * to be called and iwl_down since we are removing the device
0b124c31
GG
3460 * we need to set STATUS_EXIT_PENDING bit.
3461 */
3462 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3463 if (priv->mac80211_registered) {
3464 ieee80211_unregister_hw(priv->hw);
3465 priv->mac80211_registered = 0;
0b124c31 3466 } else {
5b9f8cd3 3467 iwl_down(priv);
c4f55232
RR
3468 }
3469
c166b25a
BC
3470 /*
3471 * Make sure device is reset to low power before unloading driver.
3472 * This may be redundant with iwl_down(), but there are paths to
3473 * run iwl_down() without calling apm_ops.stop(), and there are
3474 * paths to avoid running iwl_down() at all before leaving driver.
3475 * This (inexpensive) call *makes sure* device is reset.
3476 */
3477 priv->cfg->ops->lib->apm_ops.stop(priv);
3478
39b73fb1
WYG
3479 iwl_tt_exit(priv);
3480
0359facc
MA
3481 /* make sure we flush any pending irq or
3482 * tasklet for the driver
3483 */
3484 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3485 iwl_disable_interrupts(priv);
0359facc
MA
3486 spin_unlock_irqrestore(&priv->lock, flags);
3487
3488 iwl_synchronize_irq(priv);
3489
5b9f8cd3 3490 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3491
3492 if (priv->rxq.bd)
a55360e4 3493 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3494 iwl_hw_txq_ctx_free(priv);
b481de9c 3495
c587de0b 3496 iwl_clear_stations_table(priv);
073d3f5f 3497 iwl_eeprom_free(priv);
b481de9c 3498
b481de9c 3499
948c171c
MA
3500 /*netif_stop_queue(dev); */
3501 flush_workqueue(priv->workqueue);
3502
5b9f8cd3 3503 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3504 * priv->workqueue... so we can't take down the workqueue
3505 * until now... */
3506 destroy_workqueue(priv->workqueue);
3507 priv->workqueue = NULL;
20594eb0 3508 iwl_free_traffic_mem(priv);
b481de9c 3509
6cd0b1cb
HS
3510 free_irq(priv->pci_dev->irq, priv);
3511 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3512 pci_iounmap(pdev, priv->hw_base);
3513 pci_release_regions(pdev);
3514 pci_disable_device(pdev);
3515 pci_set_drvdata(pdev, NULL);
3516
6ba87956 3517 iwl_uninit_drv(priv);
b481de9c 3518
ef850d7c
MA
3519 iwl_free_isr_ict(priv);
3520
b481de9c
ZY
3521 if (priv->ibss_beacon)
3522 dev_kfree_skb(priv->ibss_beacon);
3523
3524 ieee80211_free_hw(priv->hw);
3525}
3526
b481de9c
ZY
3527
3528/*****************************************************************************
3529 *
3530 * driver and module entry point
3531 *
3532 *****************************************************************************/
3533
fed9017e
RR
3534/* Hardware specific file defines the PCI IDs table for that hardware module */
3535static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3536#ifdef CONFIG_IWL4965
fed9017e
RR
3537 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3538 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3539#endif /* CONFIG_IWL4965 */
5a6a256e 3540#ifdef CONFIG_IWL5000
47408639
EK
3541 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3542 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3543 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3544 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3545 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3546 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3547 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK
3548 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3549 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3550 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW
3551/* 5350 WiFi/WiMax */
3552 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3553 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3554 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW
3555/* 5150 Wifi/WiMax */
3556 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3557 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
5953a62e
WYG
3558
3559/* 6x00 Series */
5953a62e
WYG
3560 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3561 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3562 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3563 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3564 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3565 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3566 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3567 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3568 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3569 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3570
3571/* 6x50 WiFi/WiMax Series */
5953a62e
WYG
3572 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3573 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3574 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3575 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG
3576 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3577 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3578
77dcb6a9 3579/* 1000 Series WiFi */
4bd0914f
WYG
3580 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3581 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3582 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3583 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3584 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3585 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3586 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3587 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3588 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3589 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3590 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3591 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 3592#endif /* CONFIG_IWL5000 */
7100e924 3593
fed9017e
RR
3594 {0}
3595};
3596MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3597
3598static struct pci_driver iwl_driver = {
b481de9c 3599 .name = DRV_NAME,
fed9017e 3600 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3601 .probe = iwl_pci_probe,
3602 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3603#ifdef CONFIG_PM
5b9f8cd3
EG
3604 .suspend = iwl_pci_suspend,
3605 .resume = iwl_pci_resume,
b481de9c
ZY
3606#endif
3607};
3608
5b9f8cd3 3609static int __init iwl_init(void)
b481de9c
ZY
3610{
3611
3612 int ret;
3613 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3614 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3615
e227ceac 3616 ret = iwlagn_rate_control_register();
897e1cf2 3617 if (ret) {
a3139c59
SO
3618 printk(KERN_ERR DRV_NAME
3619 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3620 return ret;
3621 }
3622
fed9017e 3623 ret = pci_register_driver(&iwl_driver);
b481de9c 3624 if (ret) {
a3139c59 3625 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3626 goto error_register;
b481de9c 3627 }
b481de9c
ZY
3628
3629 return ret;
897e1cf2 3630
897e1cf2 3631error_register:
e227ceac 3632 iwlagn_rate_control_unregister();
897e1cf2 3633 return ret;
b481de9c
ZY
3634}
3635
5b9f8cd3 3636static void __exit iwl_exit(void)
b481de9c 3637{
fed9017e 3638 pci_unregister_driver(&iwl_driver);
e227ceac 3639 iwlagn_rate_control_unregister();
b481de9c
ZY
3640}
3641
5b9f8cd3
EG
3642module_exit(iwl_exit);
3643module_init(iwl_init);
a562a9dd
RC
3644
3645#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3646module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 3647MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 3648module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
3649MODULE_PARM_DESC(debug, "debug output mask");
3650#endif
3651