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iwlwifi: separate IO tracing
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
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43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO
47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
b481de9c
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
b481de9c
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64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
80bc5393 75#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
b481de9c
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
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92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
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101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
e0158e61 105int iwl_commit_rxon(struct iwl_priv *priv)
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106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
b481de9c
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115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
118
8ccde88a 119 ret = iwl_check_rxon_cmd(priv);
43d59b32 120 if (ret) {
15b1687c 121 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
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122 return -EINVAL;
123 }
124
0924e519
WYG
125 /*
126 * receive commit_rxon request
127 * abort any previous channel switch if still in process
128 */
129 if (priv->switch_rxon.switch_in_progress &&
130 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
131 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
132 le16_to_cpu(priv->switch_rxon.channel));
133 priv->switch_rxon.switch_in_progress = false;
134 }
135
b481de9c 136 /* If we don't need to send a full RXON, we can use
5b9f8cd3 137 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 138 * and other flags for the current radio configuration. */
54559703 139 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
140 ret = iwl_send_rxon_assoc(priv);
141 if (ret) {
15b1687c 142 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 143 return ret;
b481de9c
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144 }
145
146 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 147 iwl_print_rx_config_cmd(priv);
b481de9c
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148 return 0;
149 }
150
151 /* station table will be cleared */
152 priv->assoc_station_added = 0;
153
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154 /* If we are currently associated and the new config requires
155 * an RXON_ASSOC and the new config wants the associated mask enabled,
156 * we must clear the associated from the active configuration
157 * before we apply the new config */
43d59b32 158 if (iwl_is_associated(priv) && new_assoc) {
e1623446 159 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
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160 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
161
43d59b32 162 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 163 sizeof(struct iwl_rxon_cmd),
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164 &priv->active_rxon);
165
166 /* If the mask clearing failed then we set
167 * active_rxon back to what it was previously */
43d59b32 168 if (ret) {
b481de9c 169 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 170 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 171 return ret;
b481de9c 172 }
b481de9c
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173 }
174
e1623446 175 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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176 "* with%s RXON_FILTER_ASSOC_MSK\n"
177 "* channel = %d\n"
e174961c 178 "* bssid = %pM\n",
43d59b32 179 (new_assoc ? "" : "out"),
b481de9c 180 le16_to_cpu(priv->staging_rxon.channel),
e174961c 181 priv->staging_rxon.bssid_addr);
b481de9c 182
90e8e424 183 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
184
185 /* Apply the new configuration
186 * RXON unassoc clears the station table in uCode, send it before
187 * we add the bcast station. If assoc bit is set, we will send RXON
188 * after having added the bcast and bssid station.
189 */
190 if (!new_assoc) {
191 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 192 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 193 if (ret) {
15b1687c 194 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
195 return ret;
196 }
197 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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198 }
199
c587de0b 200 iwl_clear_stations_table(priv);
556f8db7 201
19cc1087 202 priv->start_calib = 0;
b481de9c 203
b481de9c 204 /* Add the broadcast address so we can send broadcast frames */
9a9ca65f 205 iwl_add_bcast_station(priv);
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206
207 /* If we have set the ASSOC_MSK and we are in BSS mode then
208 * add the IWL_AP_ID to the station rate table */
9185159d 209 if (new_assoc) {
05c914fe 210 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
211 ret = iwl_rxon_add_station(priv,
212 priv->active_rxon.bssid_addr, 1);
213 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
214 IWL_ERR(priv,
215 "Error adding AP address for TX.\n");
9185159d
TW
216 return -EIO;
217 }
218 priv->assoc_station_added = 1;
219 if (priv->default_wep_key &&
220 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
221 IWL_ERR(priv,
222 "Could not send WEP static key.\n");
b481de9c 223 }
43d59b32 224
47eef9bd
WYG
225 /*
226 * allow CTS-to-self if possible for new association.
227 * this is relevant only for 5000 series and up,
228 * but will not damage 4965
229 */
230 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
231
43d59b32
EG
232 /* Apply the new configuration
233 * RXON assoc doesn't clear the station table in uCode,
234 */
235 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
236 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
237 if (ret) {
15b1687c 238 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
239 return ret;
240 }
241 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 242 }
a643565e 243 iwl_print_rx_config_cmd(priv);
b481de9c 244
36da7d70
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245 iwl_init_sensitivity(priv);
246
247 /* If we issue a new RXON command which required a tune then we must
248 * send a new TXPOWER command or we won't be able to Tx any frames */
249 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
250 if (ret) {
15b1687c 251 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY
252 return ret;
253 }
254
b481de9c
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255 return 0;
256}
257
5b9f8cd3 258void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
259{
260
45823531
AK
261 if (priv->cfg->ops->hcmd->set_rxon_chain)
262 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 263 iwlcore_commit_rxon(priv);
5da4b55f
MA
264}
265
fcab423d 266static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
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267{
268 struct list_head *element;
269
e1623446 270 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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271 priv->frames_count);
272
273 while (!list_empty(&priv->free_frames)) {
274 element = priv->free_frames.next;
275 list_del(element);
fcab423d 276 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
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277 priv->frames_count--;
278 }
279
280 if (priv->frames_count) {
39aadf8c 281 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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282 priv->frames_count);
283 priv->frames_count = 0;
284 }
285}
286
fcab423d 287static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 288{
fcab423d 289 struct iwl_frame *frame;
b481de9c
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290 struct list_head *element;
291 if (list_empty(&priv->free_frames)) {
292 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
293 if (!frame) {
15b1687c 294 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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295 return NULL;
296 }
297
298 priv->frames_count++;
299 return frame;
300 }
301
302 element = priv->free_frames.next;
303 list_del(element);
fcab423d 304 return list_entry(element, struct iwl_frame, list);
b481de9c
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305}
306
fcab423d 307static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
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308{
309 memset(frame, 0, sizeof(*frame));
310 list_add(&frame->list, &priv->free_frames);
311}
312
47ff65c4 313static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 314 struct ieee80211_hdr *hdr,
73ec1cc2 315 int left)
b481de9c 316{
3109ece1 317 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
318 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
319 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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320 return 0;
321
322 if (priv->ibss_beacon->len > left)
323 return 0;
324
325 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
326
327 return priv->ibss_beacon->len;
328}
329
47ff65c4
DH
330/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
331static void iwl_set_beacon_tim(struct iwl_priv *priv,
332 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
333 u8 *beacon, u32 frame_size)
334{
335 u16 tim_idx;
336 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
337
338 /*
339 * The index is relative to frame start but we start looking at the
340 * variable-length part of the beacon.
341 */
342 tim_idx = mgmt->u.beacon.variable - beacon;
343
344 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
345 while ((tim_idx < (frame_size - 2)) &&
346 (beacon[tim_idx] != WLAN_EID_TIM))
347 tim_idx += beacon[tim_idx+1] + 2;
348
349 /* If TIM field was found, set variables */
350 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
351 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
352 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
353 } else
354 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
355}
356
5b9f8cd3 357static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 358 struct iwl_frame *frame)
4bf64efd
TW
359{
360 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH
361 u32 frame_size;
362 u32 rate_flags;
363 u32 rate;
364 /*
365 * We have to set up the TX command, the TX Beacon command, and the
366 * beacon contents.
367 */
4bf64efd 368
47ff65c4 369 /* Initialize memory */
4bf64efd
TW
370 tx_beacon_cmd = &frame->u.beacon;
371 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
372
47ff65c4 373 /* Set up TX beacon contents */
4bf64efd 374 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 375 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH
376 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
377 return 0;
4bf64efd 378
47ff65c4 379 /* Set up TX command fields */
4bf64efd 380 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH
381 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
382 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
383 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
384 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 385
47ff65c4
DH
386 /* Set up TX beacon command fields */
387 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
388 frame_size);
4bf64efd 389
47ff65c4
DH
390 /* Set up packet rate and flags */
391 rate = iwl_rate_get_lowest_plcp(priv);
392 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
393 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
394 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
395 rate_flags |= RATE_MCS_CCK_MSK;
396 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
397 rate_flags);
4bf64efd
TW
398
399 return sizeof(*tx_beacon_cmd) + frame_size;
400}
5b9f8cd3 401static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 402{
fcab423d 403 struct iwl_frame *frame;
b481de9c
ZY
404 unsigned int frame_size;
405 int rc;
b481de9c 406
fcab423d 407 frame = iwl_get_free_frame(priv);
b481de9c 408 if (!frame) {
15b1687c 409 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
410 "command.\n");
411 return -ENOMEM;
412 }
413
47ff65c4
DH
414 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
415 if (!frame_size) {
416 IWL_ERR(priv, "Error configuring the beacon command\n");
417 iwl_free_frame(priv, frame);
418 return -EINVAL;
419 }
b481de9c 420
857485c0 421 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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422 &frame->u.cmd[0]);
423
fcab423d 424 iwl_free_frame(priv, frame);
b481de9c
ZY
425
426 return rc;
427}
428
7aaa1d79
SO
429static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
430{
431 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
432
433 dma_addr_t addr = get_unaligned_le32(&tb->lo);
434 if (sizeof(dma_addr_t) > sizeof(u32))
435 addr |=
436 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
437
438 return addr;
439}
440
441static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
442{
443 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
444
445 return le16_to_cpu(tb->hi_n_len) >> 4;
446}
447
448static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
449 dma_addr_t addr, u16 len)
450{
451 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
452 u16 hi_n_len = len << 4;
453
454 put_unaligned_le32(addr, &tb->lo);
455 if (sizeof(dma_addr_t) > sizeof(u32))
456 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
457
458 tb->hi_n_len = cpu_to_le16(hi_n_len);
459
460 tfd->num_tbs = idx + 1;
461}
462
463static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
464{
465 return tfd->num_tbs & 0x1f;
466}
467
468/**
469 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
470 * @priv - driver private data
471 * @txq - tx queue
472 *
473 * Does NOT advance any TFD circular buffer read/write indexes
474 * Does NOT free the TFD itself (which is within circular buffer)
475 */
476void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
477{
59606ffa 478 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
479 struct iwl_tfd *tfd;
480 struct pci_dev *dev = priv->pci_dev;
481 int index = txq->q.read_ptr;
482 int i;
483 int num_tbs;
484
485 tfd = &tfd_tmp[index];
486
487 /* Sanity check on number of chunks */
488 num_tbs = iwl_tfd_get_num_tbs(tfd);
489
490 if (num_tbs >= IWL_NUM_OF_TBS) {
491 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
492 /* @todo issue fatal error, it is quite serious situation */
493 return;
494 }
495
496 /* Unmap tx_cmd */
497 if (num_tbs)
498 pci_unmap_single(dev,
c2acea8e
JB
499 pci_unmap_addr(&txq->meta[index], mapping),
500 pci_unmap_len(&txq->meta[index], len),
96891cee 501 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
502
503 /* Unmap chunks, if any. */
504 for (i = 1; i < num_tbs; i++) {
505 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
506 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
507
508 if (txq->txb) {
509 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
510 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
511 }
512 }
513}
514
515int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
516 struct iwl_tx_queue *txq,
517 dma_addr_t addr, u16 len,
518 u8 reset, u8 pad)
519{
520 struct iwl_queue *q;
59606ffa 521 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
522 u32 num_tbs;
523
524 q = &txq->q;
59606ffa
SO
525 tfd_tmp = (struct iwl_tfd *)txq->tfds;
526 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
527
528 if (reset)
529 memset(tfd, 0, sizeof(*tfd));
530
531 num_tbs = iwl_tfd_get_num_tbs(tfd);
532
533 /* Each TFD can point to a maximum 20 Tx buffers */
534 if (num_tbs >= IWL_NUM_OF_TBS) {
535 IWL_ERR(priv, "Error can not send more than %d chunks\n",
536 IWL_NUM_OF_TBS);
537 return -EINVAL;
538 }
539
540 BUG_ON(addr & ~DMA_BIT_MASK(36));
541 if (unlikely(addr & ~IWL_TX_DMA_MASK))
542 IWL_ERR(priv, "Unaligned address = %llx\n",
543 (unsigned long long)addr);
544
545 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
546
547 return 0;
548}
549
a8e74e27
SO
550/*
551 * Tell nic where to find circular buffer of Tx Frame Descriptors for
552 * given Tx queue, and enable the DMA channel used for that queue.
553 *
554 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
555 * channels supported in hardware.
556 */
557int iwl_hw_tx_queue_init(struct iwl_priv *priv,
558 struct iwl_tx_queue *txq)
559{
a8e74e27
SO
560 int txq_id = txq->q.id;
561
a8e74e27
SO
562 /* Circular buffer (TFD queue in DRAM) physical base address */
563 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
564 txq->q.dma_addr >> 8);
565
a8e74e27
SO
566 return 0;
567}
568
b481de9c
ZY
569/******************************************************************************
570 *
571 * Generic RX handler implementations
572 *
573 ******************************************************************************/
885ba202
TW
574static void iwl_rx_reply_alive(struct iwl_priv *priv,
575 struct iwl_rx_mem_buffer *rxb)
b481de9c 576{
2f301227 577 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 578 struct iwl_alive_resp *palive;
b481de9c
ZY
579 struct delayed_work *pwork;
580
581 palive = &pkt->u.alive_frame;
582
e1623446 583 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
584 "0x%01X 0x%01X\n",
585 palive->is_valid, palive->ver_type,
586 palive->ver_subtype);
587
588 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 589 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
590 memcpy(&priv->card_alive_init,
591 &pkt->u.alive_frame,
885ba202 592 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
593 pwork = &priv->init_alive_start;
594 } else {
e1623446 595 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 596 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 597 sizeof(struct iwl_alive_resp));
b481de9c
ZY
598 pwork = &priv->alive_start;
599 }
600
601 /* We delay the ALIVE response by 5ms to
602 * give the HW RF Kill time to activate... */
603 if (palive->is_valid == UCODE_VALID_OK)
604 queue_delayed_work(priv->workqueue, pwork,
605 msecs_to_jiffies(5));
606 else
39aadf8c 607 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
608}
609
5b9f8cd3 610static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 611{
c79dd5b5
TW
612 struct iwl_priv *priv =
613 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
614 struct sk_buff *beacon;
615
616 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 617 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
618
619 if (!beacon) {
15b1687c 620 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
621 return;
622 }
623
624 mutex_lock(&priv->mutex);
625 /* new beacon skb is allocated every time; dispose previous.*/
626 if (priv->ibss_beacon)
627 dev_kfree_skb(priv->ibss_beacon);
628
629 priv->ibss_beacon = beacon;
630 mutex_unlock(&priv->mutex);
631
5b9f8cd3 632 iwl_send_beacon_cmd(priv);
b481de9c
ZY
633}
634
4e39317d 635/**
5b9f8cd3 636 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
637 *
638 * This callback is provided in order to send a statistics request.
639 *
640 * This timer function is continually reset to execute within
641 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
642 * was received. We need to ensure we receive the statistics in order
643 * to update the temperature used for calibrating the TXPOWER.
644 */
5b9f8cd3 645static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
646{
647 struct iwl_priv *priv = (struct iwl_priv *)data;
648
649 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
650 return;
651
61780ee3
MA
652 /* dont send host command if rf-kill is on */
653 if (!iwl_is_ready_rf(priv))
654 return;
655
ef8d5529 656 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG
657}
658
5b9f8cd3 659static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 660 struct iwl_rx_mem_buffer *rxb)
b481de9c 661{
0a6857e7 662#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 663 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW
664 struct iwl4965_beacon_notif *beacon =
665 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 666 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 667
e1623446 668 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 669 "tsf %d %d rate %d\n",
25a6572c 670 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
671 beacon->beacon_notify_hdr.failure_frame,
672 le32_to_cpu(beacon->ibss_mgr_status),
673 le32_to_cpu(beacon->high_tsf),
674 le32_to_cpu(beacon->low_tsf), rate);
675#endif
676
05c914fe 677 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
678 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
679 queue_work(priv->workqueue, &priv->beacon_update);
680}
681
b481de9c
ZY
682/* Handle notification from uCode that card's power state is changing
683 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 684static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 685 struct iwl_rx_mem_buffer *rxb)
b481de9c 686{
2f301227 687 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
688 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
689 unsigned long status = priv->status;
690
e1623446 691 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
692 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
693 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
694
695 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
696 RF_CARD_DISABLED)) {
697
3395f6e9 698 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
699 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
700
a8b50a0a
MA
701 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
702 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
703
704 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 705 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 706 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 707 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 708 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 709 }
39b73fb1
WYG
710 if (flags & RF_CARD_DISABLED)
711 iwl_tt_enter_ct_kill(priv);
b481de9c 712 }
39b73fb1
WYG
713 if (!(flags & RF_CARD_DISABLED))
714 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
715
716 if (flags & HW_CARD_DISABLED)
717 set_bit(STATUS_RF_KILL_HW, &priv->status);
718 else
719 clear_bit(STATUS_RF_KILL_HW, &priv->status);
720
721
b481de9c 722 if (!(flags & RXON_CARD_DISABLED))
2a421b91 723 iwl_scan_cancel(priv);
b481de9c
ZY
724
725 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
726 test_bit(STATUS_RF_KILL_HW, &priv->status)))
727 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
728 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
729 else
730 wake_up_interruptible(&priv->wait_command_queue);
731}
732
5b9f8cd3 733int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 734{
e2e3c57b 735 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 736 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
737 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
738 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
739 ~APMG_PS_CTRL_MSK_PWR_SRC);
740 } else {
741 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
742 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
743 ~APMG_PS_CTRL_MSK_PWR_SRC);
744 }
745
a8b50a0a 746 return 0;
e2e3c57b
TW
747}
748
b481de9c 749/**
5b9f8cd3 750 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
751 *
752 * Setup the RX handlers for each of the reply types sent from the uCode
753 * to the host.
754 *
755 * This function chains into the hardware specific files for them to setup
756 * any hardware specific handlers as well.
757 */
653fa4a0 758static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 759{
885ba202 760 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
761 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
762 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 763 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 764 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
765 iwl_rx_pm_debug_statistics_notif;
766 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 767
9fbab516
BC
768 /*
769 * The same handler is used for both the REPLY to a discrete
770 * statistics request from the host as well as for the periodic
771 * statistics notifications (after received beacons) from the uCode.
b481de9c 772 */
ef8d5529 773 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 774 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 775
21c339bf 776 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
777 iwl_setup_rx_scan_handlers(priv);
778
37a44211 779 /* status change handler */
5b9f8cd3 780 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 781
c1354754
TW
782 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
783 iwl_rx_missed_beacon_notif;
37a44211 784 /* Rx handlers */
1781a07f
EG
785 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
786 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
787 /* block ack */
788 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 789 /* Set up hardware specific Rx handlers */
d4789efe 790 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
791}
792
b481de9c 793/**
a55360e4 794 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
795 *
796 * Uses the priv->rx_handlers callback function array to invoke
797 * the appropriate handlers, including command responses,
798 * frame-received notifications, and other notifications.
799 */
a55360e4 800void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 801{
a55360e4 802 struct iwl_rx_mem_buffer *rxb;
db11d634 803 struct iwl_rx_packet *pkt;
a55360e4 804 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
805 u32 r, i;
806 int reclaim;
807 unsigned long flags;
5c0eef96 808 u8 fill_rx = 0;
d68ab680 809 u32 count = 8;
4752c93c 810 int total_empty;
b481de9c 811
6440adb5
BC
812 /* uCode's read index (stored in shared DRAM) indicates the last Rx
813 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 814 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
815 i = rxq->read;
816
817 /* Rx interrupt, but nothing sent from uCode */
818 if (i == r)
e1623446 819 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 820
4752c93c 821 /* calculate total frames need to be restock after handling RX */
7300515d 822 total_empty = r - rxq->write_actual;
4752c93c
MA
823 if (total_empty < 0)
824 total_empty += RX_QUEUE_SIZE;
825
826 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
827 fill_rx = 1;
828
b481de9c
ZY
829 while (i != r) {
830 rxb = rxq->queue[i];
831
9fbab516 832 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
833 * then a bug has been introduced in the queue refilling
834 * routines -- catch it here */
835 BUG_ON(rxb == NULL);
836
837 rxq->queue[i] = NULL;
838
2f301227
ZY
839 pci_unmap_page(priv->pci_dev, rxb->page_dma,
840 PAGE_SIZE << priv->hw_params.rx_page_order,
841 PCI_DMA_FROMDEVICE);
842 pkt = rxb_addr(rxb);
b481de9c 843
be1a71a1
JB
844 trace_iwlwifi_dev_rx(priv, pkt,
845 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
846
b481de9c
ZY
847 /* Reclaim a command buffer only if this packet is a response
848 * to a (driver-originated) command.
849 * If the packet (e.g. Rx frame) originated from uCode,
850 * there is no command buffer to reclaim.
851 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
852 * but apparently a few don't get set; catch them here. */
853 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
854 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 855 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 856 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 857 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
858 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
859 (pkt->hdr.cmd != REPLY_TX);
860
861 /* Based on type of command response or notification,
862 * handle those that need handling via function in
5b9f8cd3 863 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 864 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 865 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 866 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 867 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 868 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
869 } else {
870 /* No handling needed */
e1623446 871 IWL_DEBUG_RX(priv,
b481de9c
ZY
872 "r %d i %d No handler needed for %s, 0x%02x\n",
873 r, i, get_cmd_string(pkt->hdr.cmd),
874 pkt->hdr.cmd);
875 }
876
29b1b268
ZY
877 /*
878 * XXX: After here, we should always check rxb->page
879 * against NULL before touching it or its virtual
880 * memory (pkt). Because some rx_handler might have
881 * already taken or freed the pages.
882 */
883
b481de9c 884 if (reclaim) {
2f301227
ZY
885 /* Invoke any callbacks, transfer the buffer to caller,
886 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 887 * as we reclaim the driver command queue */
29b1b268 888 if (rxb->page)
17b88929 889 iwl_tx_cmd_complete(priv, rxb);
b481de9c 890 else
39aadf8c 891 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
892 }
893
7300515d
ZY
894 /* Reuse the page if possible. For notification packets and
895 * SKBs that fail to Rx correctly, add them back into the
896 * rx_free list for reuse later. */
897 spin_lock_irqsave(&rxq->lock, flags);
2f301227 898 if (rxb->page != NULL) {
7300515d
ZY
899 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
900 0, PAGE_SIZE << priv->hw_params.rx_page_order,
901 PCI_DMA_FROMDEVICE);
902 list_add_tail(&rxb->list, &rxq->rx_free);
903 rxq->free_count++;
904 } else
905 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 906
b481de9c 907 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 908
b481de9c 909 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
910 /* If there are a lot of unused frames,
911 * restock the Rx queue so ucode wont assert. */
912 if (fill_rx) {
913 count++;
914 if (count >= 8) {
7300515d 915 rxq->read = i;
4752c93c 916 iwl_rx_replenish_now(priv);
5c0eef96
MA
917 count = 0;
918 }
919 }
b481de9c
ZY
920 }
921
922 /* Backtrack one entry */
7300515d 923 rxq->read = i;
4752c93c
MA
924 if (fill_rx)
925 iwl_rx_replenish_now(priv);
926 else
927 iwl_rx_queue_restock(priv);
a55360e4 928}
a55360e4 929
0359facc
MA
930/* call this function to flush any scheduled tasklet */
931static inline void iwl_synchronize_irq(struct iwl_priv *priv)
932{
a96a27f9 933 /* wait to make sure we flush pending tasklet*/
0359facc
MA
934 synchronize_irq(priv->pci_dev->irq);
935 tasklet_kill(&priv->irq_tasklet);
936}
937
ef850d7c 938static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
939{
940 u32 inta, handled = 0;
941 u32 inta_fh;
942 unsigned long flags;
c2e61da2 943 u32 i;
0a6857e7 944#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
945 u32 inta_mask;
946#endif
947
948 spin_lock_irqsave(&priv->lock, flags);
949
950 /* Ack/clear/reset pending uCode interrupts.
951 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
952 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
953 inta = iwl_read32(priv, CSR_INT);
954 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
955
956 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
957 * Any new interrupts that happen after this, either while we're
958 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
959 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
960 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 961
0a6857e7 962#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 963 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 964 /* just for debug */
3395f6e9 965 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 966 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
967 inta, inta_mask, inta_fh);
968 }
969#endif
970
2f301227
ZY
971 spin_unlock_irqrestore(&priv->lock, flags);
972
b481de9c
ZY
973 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
974 * atomic, make sure that inta covers all the interrupts that
975 * we've discovered, even if FH interrupt came in just after
976 * reading CSR_INT. */
6f83eaa1 977 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 978 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 979 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
980 inta |= CSR_INT_BIT_FH_TX;
981
982 /* Now service all interrupt bits discovered above. */
983 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 984 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
985
986 /* Tell the device to stop sending interrupts */
5b9f8cd3 987 iwl_disable_interrupts(priv);
b481de9c 988
a83b9141 989 priv->isr_stats.hw++;
5b9f8cd3 990 iwl_irq_handle_error(priv);
b481de9c
ZY
991
992 handled |= CSR_INT_BIT_HW_ERR;
993
b481de9c
ZY
994 return;
995 }
996
0a6857e7 997#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 998 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 999 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1000 if (inta & CSR_INT_BIT_SCD) {
e1623446 1001 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1002 "the frame/frames.\n");
a83b9141
WYG
1003 priv->isr_stats.sch++;
1004 }
b481de9c
ZY
1005
1006 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1007 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1008 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
1009 priv->isr_stats.alive++;
1010 }
b481de9c
ZY
1011 }
1012#endif
1013 /* Safely ignore these bits for debug checks below */
25c03d8e 1014 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1015
9fbab516 1016 /* HW RF KILL switch toggled */
b481de9c
ZY
1017 if (inta & CSR_INT_BIT_RF_KILL) {
1018 int hw_rf_kill = 0;
3395f6e9 1019 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
1020 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1021 hw_rf_kill = 1;
1022
4c423a2b 1023 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1024 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1025
a83b9141
WYG
1026 priv->isr_stats.rfkill++;
1027
a9efa652 1028 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
1029 * the driver allows loading the ucode even if the radio
1030 * is killed. Hence update the killswitch state here. The
1031 * rfkill handler will care about restarting if needed.
a9efa652 1032 */
6cd0b1cb
HS
1033 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1034 if (hw_rf_kill)
1035 set_bit(STATUS_RF_KILL_HW, &priv->status);
1036 else
1037 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1038 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1039 }
b481de9c
ZY
1040
1041 handled |= CSR_INT_BIT_RF_KILL;
1042 }
1043
9fbab516 1044 /* Chip got too hot and stopped itself */
b481de9c 1045 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1046 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1047 priv->isr_stats.ctkill++;
b481de9c
ZY
1048 handled |= CSR_INT_BIT_CT_KILL;
1049 }
1050
1051 /* Error detected by uCode */
1052 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1053 IWL_ERR(priv, "Microcode SW error detected. "
1054 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1055 priv->isr_stats.sw++;
1056 priv->isr_stats.sw_err = inta;
5b9f8cd3 1057 iwl_irq_handle_error(priv);
b481de9c
ZY
1058 handled |= CSR_INT_BIT_SW_ERR;
1059 }
1060
c2e61da2
BC
1061 /*
1062 * uCode wakes up after power-down sleep.
1063 * Tell device about any new tx or host commands enqueued,
1064 * and about any Rx buffers made available while asleep.
1065 */
b481de9c 1066 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1067 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1068 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC
1069 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1070 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1071 priv->isr_stats.wakeup++;
b481de9c
ZY
1072 handled |= CSR_INT_BIT_WAKEUP;
1073 }
1074
1075 /* All uCode command responses, including Tx command responses,
1076 * Rx "responses" (frame-received notification), and other
1077 * notifications from uCode come through here*/
1078 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1079 iwl_rx_handle(priv);
a83b9141 1080 priv->isr_stats.rx++;
b481de9c
ZY
1081 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1082 }
1083
c72cd19f 1084 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1085 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1086 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1087 priv->isr_stats.tx++;
b481de9c 1088 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1089 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR
1090 priv->ucode_write_complete = 1;
1091 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1092 }
1093
a83b9141 1094 if (inta & ~handled) {
15b1687c 1095 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1096 priv->isr_stats.unhandled++;
1097 }
b481de9c 1098
40cefda9 1099 if (inta & ~(priv->inta_mask)) {
39aadf8c 1100 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1101 inta & ~priv->inta_mask);
39aadf8c 1102 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1103 }
1104
1105 /* Re-enable all interrupts */
0359facc
MA
1106 /* only Re-enable if diabled by irq */
1107 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1108 iwl_enable_interrupts(priv);
b481de9c 1109
0a6857e7 1110#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1111 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1112 inta = iwl_read32(priv, CSR_INT);
1113 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1114 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1115 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1116 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1117 }
1118#endif
b481de9c
ZY
1119}
1120
ef850d7c
MA
1121/* tasklet for iwlagn interrupt */
1122static void iwl_irq_tasklet(struct iwl_priv *priv)
1123{
1124 u32 inta = 0;
1125 u32 handled = 0;
1126 unsigned long flags;
8756990f 1127 u32 i;
ef850d7c
MA
1128#ifdef CONFIG_IWLWIFI_DEBUG
1129 u32 inta_mask;
1130#endif
1131
1132 spin_lock_irqsave(&priv->lock, flags);
1133
1134 /* Ack/clear/reset pending uCode interrupts.
1135 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1136 */
1137 iwl_write32(priv, CSR_INT, priv->inta);
1138
1139 inta = priv->inta;
1140
1141#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1142 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1143 /* just for debug */
1144 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1145 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1146 inta, inta_mask);
1147 }
1148#endif
2f301227
ZY
1149
1150 spin_unlock_irqrestore(&priv->lock, flags);
1151
ef850d7c
MA
1152 /* saved interrupt in inta variable now we can reset priv->inta */
1153 priv->inta = 0;
1154
1155 /* Now service all interrupt bits discovered above. */
1156 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1157 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1158
1159 /* Tell the device to stop sending interrupts */
1160 iwl_disable_interrupts(priv);
1161
1162 priv->isr_stats.hw++;
1163 iwl_irq_handle_error(priv);
1164
1165 handled |= CSR_INT_BIT_HW_ERR;
1166
ef850d7c
MA
1167 return;
1168 }
1169
1170#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1171 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1172 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1173 if (inta & CSR_INT_BIT_SCD) {
1174 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1175 "the frame/frames.\n");
1176 priv->isr_stats.sch++;
1177 }
1178
1179 /* Alive notification via Rx interrupt will do the real work */
1180 if (inta & CSR_INT_BIT_ALIVE) {
1181 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1182 priv->isr_stats.alive++;
1183 }
1184 }
1185#endif
1186 /* Safely ignore these bits for debug checks below */
1187 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1188
1189 /* HW RF KILL switch toggled */
1190 if (inta & CSR_INT_BIT_RF_KILL) {
1191 int hw_rf_kill = 0;
1192 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1193 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1194 hw_rf_kill = 1;
1195
4c423a2b 1196 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1197 hw_rf_kill ? "disable radio" : "enable radio");
1198
1199 priv->isr_stats.rfkill++;
1200
1201 /* driver only loads ucode once setting the interface up.
1202 * the driver allows loading the ucode even if the radio
1203 * is killed. Hence update the killswitch state here. The
1204 * rfkill handler will care about restarting if needed.
1205 */
1206 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1207 if (hw_rf_kill)
1208 set_bit(STATUS_RF_KILL_HW, &priv->status);
1209 else
1210 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1211 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1212 }
1213
1214 handled |= CSR_INT_BIT_RF_KILL;
1215 }
1216
1217 /* Chip got too hot and stopped itself */
1218 if (inta & CSR_INT_BIT_CT_KILL) {
1219 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1220 priv->isr_stats.ctkill++;
1221 handled |= CSR_INT_BIT_CT_KILL;
1222 }
1223
1224 /* Error detected by uCode */
1225 if (inta & CSR_INT_BIT_SW_ERR) {
1226 IWL_ERR(priv, "Microcode SW error detected. "
1227 " Restarting 0x%X.\n", inta);
1228 priv->isr_stats.sw++;
1229 priv->isr_stats.sw_err = inta;
1230 iwl_irq_handle_error(priv);
1231 handled |= CSR_INT_BIT_SW_ERR;
1232 }
1233
1234 /* uCode wakes up after power-down sleep */
1235 if (inta & CSR_INT_BIT_WAKEUP) {
1236 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1237 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC
1238 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1239 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA
1240
1241 priv->isr_stats.wakeup++;
1242
1243 handled |= CSR_INT_BIT_WAKEUP;
1244 }
1245
1246 /* All uCode command responses, including Tx command responses,
1247 * Rx "responses" (frame-received notification), and other
1248 * notifications from uCode come through here*/
40cefda9
MA
1249 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1250 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1251 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1252 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1253 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1254 iwl_write32(priv, CSR_FH_INT_STATUS,
1255 CSR49_FH_INT_RX_MASK);
1256 }
1257 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1258 handled |= CSR_INT_BIT_RX_PERIODIC;
1259 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1260 }
1261 /* Sending RX interrupt require many steps to be done in the
1262 * the device:
1263 * 1- write interrupt to current index in ICT table.
1264 * 2- dma RX frame.
1265 * 3- update RX shared data to indicate last write index.
1266 * 4- send interrupt.
1267 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC
1268 * but the shared data changes does not reflect this;
1269 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1270 */
74ba67ed
BC
1271
1272 /* Disable periodic interrupt; we use it as just a one-shot. */
1273 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1274 CSR_INT_PERIODIC_DIS);
ef850d7c 1275 iwl_rx_handle(priv);
74ba67ed
BC
1276
1277 /*
1278 * Enable periodic interrupt in 8 msec only if we received
1279 * real RX interrupt (instead of just periodic int), to catch
1280 * any dangling Rx interrupt. If it was just the periodic
1281 * interrupt, there was no dangling Rx activity, and no need
1282 * to extend the periodic interrupt; one-shot is enough.
1283 */
40cefda9 1284 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1285 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA
1286 CSR_INT_PERIODIC_ENA);
1287
ef850d7c 1288 priv->isr_stats.rx++;
ef850d7c
MA
1289 }
1290
c72cd19f 1291 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA
1292 if (inta & CSR_INT_BIT_FH_TX) {
1293 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1294 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA
1295 priv->isr_stats.tx++;
1296 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1297 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA
1298 priv->ucode_write_complete = 1;
1299 wake_up_interruptible(&priv->wait_command_queue);
1300 }
1301
1302 if (inta & ~handled) {
1303 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1304 priv->isr_stats.unhandled++;
1305 }
1306
40cefda9 1307 if (inta & ~(priv->inta_mask)) {
ef850d7c 1308 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1309 inta & ~priv->inta_mask);
ef850d7c
MA
1310 }
1311
ef850d7c
MA
1312 /* Re-enable all interrupts */
1313 /* only Re-enable if diabled by irq */
1314 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1315 iwl_enable_interrupts(priv);
ef850d7c
MA
1316}
1317
a83b9141 1318
b481de9c
ZY
1319/******************************************************************************
1320 *
1321 * uCode download functions
1322 *
1323 ******************************************************************************/
1324
5b9f8cd3 1325static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1326{
98c92211
TW
1327 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1328 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1329 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1330 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1331 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1332 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1333}
1334
5b9f8cd3 1335static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1336{
1337 /* Remove all resets to allow NIC to operate */
1338 iwl_write32(priv, CSR_RESET, 0);
1339}
1340
1341
b481de9c 1342/**
5b9f8cd3 1343 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1344 *
1345 * Copy into buffers for card to fetch via bus-mastering
1346 */
5b9f8cd3 1347static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1348{
cc0f555d 1349 struct iwl_ucode_header *ucode;
a0987a8d 1350 int ret = -EINVAL, index;
b481de9c 1351 const struct firmware *ucode_raw;
a0987a8d
RC
1352 const char *name_pre = priv->cfg->fw_name_pre;
1353 const unsigned int api_max = priv->cfg->ucode_api_max;
1354 const unsigned int api_min = priv->cfg->ucode_api_min;
1355 char buf[25];
b481de9c
ZY
1356 u8 *src;
1357 size_t len;
cc0f555d
JS
1358 u32 api_ver, build;
1359 u32 inst_size, data_size, init_size, init_data_size, boot_size;
abdc2d62 1360 u16 eeprom_ver;
b481de9c
ZY
1361
1362 /* Ask kernel firmware_class module to get the boot firmware off disk.
1363 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1364 for (index = api_max; index >= api_min; index--) {
1365 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1366 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1367 if (ret < 0) {
15b1687c 1368 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1369 buf, ret);
1370 if (ret == -ENOENT)
1371 continue;
1372 else
1373 goto error;
1374 } else {
1375 if (index < api_max)
15b1687c
WT
1376 IWL_ERR(priv, "Loaded firmware %s, "
1377 "which is deprecated. "
1378 "Please use API v%u instead.\n",
a0987a8d 1379 buf, api_max);
15b1687c 1380
e1623446 1381 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1382 buf, ucode_raw->size);
1383 break;
1384 }
b481de9c
ZY
1385 }
1386
a0987a8d
RC
1387 if (ret < 0)
1388 goto error;
b481de9c 1389
cc0f555d
JS
1390 /* Make sure that we got at least the v1 header! */
1391 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1392 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1393 ret = -EINVAL;
b481de9c
ZY
1394 goto err_release;
1395 }
1396
1397 /* Data from ucode file: header followed by uCode images */
cc0f555d 1398 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1399
c02b3acd 1400 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1401 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1402 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1403 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1404 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1405 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1406 init_data_size =
1407 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1408 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1409 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1410
a0987a8d
RC
1411 /* api_ver should match the api version forming part of the
1412 * firmware filename ... but we don't check for that and only rely
877d0310 1413 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1414
1415 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1416 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1417 "Driver supports v%u, firmware is v%u.\n",
1418 api_max, api_ver);
1419 priv->ucode_ver = 0;
1420 ret = -EINVAL;
1421 goto err_release;
1422 }
1423 if (api_ver != api_max)
978785a3 1424 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1425 "got v%u. New firmware can be obtained "
1426 "from http://www.intellinuxwireless.org.\n",
1427 api_max, api_ver);
1428
978785a3
TW
1429 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1430 IWL_UCODE_MAJOR(priv->ucode_ver),
1431 IWL_UCODE_MINOR(priv->ucode_ver),
1432 IWL_UCODE_API(priv->ucode_ver),
1433 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1434
5ebeb5a6
RC
1435 snprintf(priv->hw->wiphy->fw_version,
1436 sizeof(priv->hw->wiphy->fw_version),
1437 "%u.%u.%u.%u",
1438 IWL_UCODE_MAJOR(priv->ucode_ver),
1439 IWL_UCODE_MINOR(priv->ucode_ver),
1440 IWL_UCODE_API(priv->ucode_ver),
1441 IWL_UCODE_SERIAL(priv->ucode_ver));
1442
cc0f555d
JS
1443 if (build)
1444 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1445
abdc2d62
JS
1446 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1447 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1448 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1449 ? "OTP" : "EEPROM", eeprom_ver);
1450
e1623446 1451 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1452 priv->ucode_ver);
e1623446 1453 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1454 inst_size);
e1623446 1455 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1456 data_size);
e1623446 1457 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1458 init_size);
e1623446 1459 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1460 init_data_size);
e1623446 1461 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1462 boot_size);
1463
1464 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1465 if (ucode_raw->size !=
1466 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1467 inst_size + data_size + init_size +
1468 init_data_size + boot_size) {
1469
cc0f555d
JS
1470 IWL_DEBUG_INFO(priv,
1471 "uCode file size %d does not match expected size\n",
1472 (int)ucode_raw->size);
90e759d1 1473 ret = -EINVAL;
b481de9c
ZY
1474 goto err_release;
1475 }
1476
1477 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1478 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1479 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1480 inst_size);
1481 ret = -EINVAL;
b481de9c
ZY
1482 goto err_release;
1483 }
1484
099b40b7 1485 if (data_size > priv->hw_params.max_data_size) {
e1623446 1486 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1487 data_size);
1488 ret = -EINVAL;
b481de9c
ZY
1489 goto err_release;
1490 }
099b40b7 1491 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1492 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1493 init_size);
90e759d1 1494 ret = -EINVAL;
b481de9c
ZY
1495 goto err_release;
1496 }
099b40b7 1497 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1498 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1499 init_data_size);
1500 ret = -EINVAL;
b481de9c
ZY
1501 goto err_release;
1502 }
099b40b7 1503 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1504 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1505 boot_size);
90e759d1 1506 ret = -EINVAL;
b481de9c
ZY
1507 goto err_release;
1508 }
1509
1510 /* Allocate ucode buffers for card's bus-master loading ... */
1511
1512 /* Runtime instructions and 2 copies of data:
1513 * 1) unmodified from disk
1514 * 2) backup cache for save/restore during power-downs */
1515 priv->ucode_code.len = inst_size;
98c92211 1516 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1517
1518 priv->ucode_data.len = data_size;
98c92211 1519 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1520
1521 priv->ucode_data_backup.len = data_size;
98c92211 1522 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1523
1f304e4e
ZY
1524 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1525 !priv->ucode_data_backup.v_addr)
1526 goto err_pci_alloc;
1527
b481de9c 1528 /* Initialization instructions and data */
90e759d1
TW
1529 if (init_size && init_data_size) {
1530 priv->ucode_init.len = init_size;
98c92211 1531 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1532
1533 priv->ucode_init_data.len = init_data_size;
98c92211 1534 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1535
1536 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1537 goto err_pci_alloc;
1538 }
b481de9c
ZY
1539
1540 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1541 if (boot_size) {
1542 priv->ucode_boot.len = boot_size;
98c92211 1543 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1544
90e759d1
TW
1545 if (!priv->ucode_boot.v_addr)
1546 goto err_pci_alloc;
1547 }
b481de9c
ZY
1548
1549 /* Copy images into buffers for card's bus-master reads ... */
1550
1551 /* Runtime instructions (first block of data in file) */
cc0f555d 1552 len = inst_size;
e1623446 1553 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1554 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1555 src += len;
1556
e1623446 1557 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1558 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1559
1560 /* Runtime data (2nd block)
5b9f8cd3 1561 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1562 len = data_size;
e1623446 1563 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1564 memcpy(priv->ucode_data.v_addr, src, len);
1565 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1566 src += len;
b481de9c
ZY
1567
1568 /* Initialization instructions (3rd block) */
1569 if (init_size) {
cc0f555d 1570 len = init_size;
e1623446 1571 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1572 len);
b481de9c 1573 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1574 src += len;
b481de9c
ZY
1575 }
1576
1577 /* Initialization data (4th block) */
1578 if (init_data_size) {
cc0f555d 1579 len = init_data_size;
e1623446 1580 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1581 len);
b481de9c 1582 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1583 src += len;
b481de9c
ZY
1584 }
1585
1586 /* Bootstrap instructions (5th block) */
cc0f555d 1587 len = boot_size;
e1623446 1588 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1589 memcpy(priv->ucode_boot.v_addr, src, len);
1590
1591 /* We have our copies now, allow OS release its copies */
1592 release_firmware(ucode_raw);
1593 return 0;
1594
1595 err_pci_alloc:
15b1687c 1596 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1597 ret = -ENOMEM;
5b9f8cd3 1598 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1599
1600 err_release:
1601 release_firmware(ucode_raw);
1602
1603 error:
90e759d1 1604 return ret;
b481de9c
ZY
1605}
1606
b7a79404
RC
1607#ifdef CONFIG_IWLWIFI_DEBUG
1608static const char *desc_lookup_text[] = {
1609 "OK",
1610 "FAIL",
1611 "BAD_PARAM",
1612 "BAD_CHECKSUM",
1613 "NMI_INTERRUPT_WDG",
1614 "SYSASSERT",
1615 "FATAL_ERROR",
1616 "BAD_COMMAND",
1617 "HW_ERROR_TUNE_LOCK",
1618 "HW_ERROR_TEMPERATURE",
1619 "ILLEGAL_CHAN_FREQ",
1620 "VCC_NOT_STABLE",
1621 "FH_ERROR",
1622 "NMI_INTERRUPT_HOST",
1623 "NMI_INTERRUPT_ACTION_PT",
1624 "NMI_INTERRUPT_UNKNOWN",
1625 "UCODE_VERSION_MISMATCH",
1626 "HW_ERROR_ABS_LOCK",
1627 "HW_ERROR_CAL_LOCK_FAIL",
1628 "NMI_INTERRUPT_INST_ACTION_PT",
1629 "NMI_INTERRUPT_DATA_ACTION_PT",
1630 "NMI_TRM_HW_ER",
1631 "NMI_INTERRUPT_TRM",
1632 "NMI_INTERRUPT_BREAK_POINT"
1633 "DEBUG_0",
1634 "DEBUG_1",
1635 "DEBUG_2",
1636 "DEBUG_3",
1637 "UNKNOWN"
1638};
1639
1640static const char *desc_lookup(int i)
1641{
1642 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1643
1644 if (i < 0 || i > max)
1645 i = max;
1646
1647 return desc_lookup_text[i];
1648}
1649
1650#define ERROR_START_OFFSET (1 * sizeof(u32))
1651#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1652
1653void iwl_dump_nic_error_log(struct iwl_priv *priv)
1654{
1655 u32 data2, line;
1656 u32 desc, time, count, base, data1;
1657 u32 blink1, blink2, ilink1, ilink2;
1658
1659 if (priv->ucode_type == UCODE_INIT)
1660 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1661 else
1662 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1663
1664 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1665 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1666 return;
1667 }
1668
1669 count = iwl_read_targ_mem(priv, base);
1670
1671 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1672 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1673 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1674 priv->status, count);
1675 }
1676
1677 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1678 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1679 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1680 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1681 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1682 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1683 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1684 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1685 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1686
be1a71a1
JB
1687 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1688 blink1, blink2, ilink1, ilink2);
1689
b7a79404
RC
1690 IWL_ERR(priv, "Desc Time "
1691 "data1 data2 line\n");
1692 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1693 desc_lookup(desc), desc, time, data1, data2, line);
1694 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1695 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1696 ilink1, ilink2);
1697
1698}
1699
1700#define EVENT_START_OFFSET (4 * sizeof(u32))
1701
1702/**
1703 * iwl_print_event_log - Dump error event log to syslog
1704 *
1705 */
1706static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1707 u32 num_events, u32 mode)
1708{
1709 u32 i;
1710 u32 base; /* SRAM byte address of event log header */
1711 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1712 u32 ptr; /* SRAM byte address of log data */
1713 u32 ev, time, data; /* event log data */
e5854471 1714 unsigned long reg_flags;
b7a79404
RC
1715
1716 if (num_events == 0)
1717 return;
1718 if (priv->ucode_type == UCODE_INIT)
1719 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1720 else
1721 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1722
1723 if (mode == 0)
1724 event_size = 2 * sizeof(u32);
1725 else
1726 event_size = 3 * sizeof(u32);
1727
1728 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1729
e5854471
BC
1730 /* Make sure device is powered up for SRAM reads */
1731 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1732 iwl_grab_nic_access(priv);
1733
1734 /* Set starting address; reads will auto-increment */
1735 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1736 rmb();
1737
b7a79404
RC
1738 /* "time" is actually "data" for mode 0 (no timestamp).
1739 * place event id # at far right for easier visual parsing. */
1740 for (i = 0; i < num_events; i++) {
e5854471
BC
1741 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1742 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1743 if (mode == 0) {
1744 /* data, ev */
be1a71a1 1745 trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
b7a79404
RC
1746 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1747 } else {
e5854471 1748 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1749 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1750 time, data, ev);
be1a71a1 1751 trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
b7a79404
RC
1752 }
1753 }
e5854471
BC
1754
1755 /* Allow device to power down */
1756 iwl_release_nic_access(priv);
1757 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b7a79404
RC
1758}
1759
84c40692
BC
1760/* For sanity check only. Actual size is determined by uCode, typ. 512 */
1761#define MAX_EVENT_LOG_SIZE (512)
1762
b7a79404
RC
1763void iwl_dump_nic_event_log(struct iwl_priv *priv)
1764{
1765 u32 base; /* SRAM byte address of event log header */
1766 u32 capacity; /* event log capacity in # entries */
1767 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1768 u32 num_wraps; /* # times uCode wrapped to top of log */
1769 u32 next_entry; /* index of next entry to be written by uCode */
1770 u32 size; /* # entries that we'll print */
1771
1772 if (priv->ucode_type == UCODE_INIT)
1773 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1774 else
1775 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1776
1777 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1778 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1779 return;
1780 }
1781
1782 /* event log header */
1783 capacity = iwl_read_targ_mem(priv, base);
1784 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1785 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1786 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1787
84c40692
BC
1788 if (capacity > MAX_EVENT_LOG_SIZE) {
1789 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1790 capacity, MAX_EVENT_LOG_SIZE);
1791 capacity = MAX_EVENT_LOG_SIZE;
1792 }
1793
1794 if (next_entry > MAX_EVENT_LOG_SIZE) {
1795 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1796 next_entry, MAX_EVENT_LOG_SIZE);
1797 next_entry = MAX_EVENT_LOG_SIZE;
1798 }
1799
b7a79404
RC
1800 size = num_wraps ? capacity : next_entry;
1801
1802 /* bail out if nothing in log */
1803 if (size == 0) {
1804 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1805 return;
1806 }
1807
1808 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1809 size, num_wraps);
1810
1811 /* if uCode has wrapped back to top of log, start at the oldest entry,
1812 * i.e the next one that uCode would fill. */
1813 if (num_wraps)
1814 iwl_print_event_log(priv, next_entry,
1815 capacity - next_entry, mode);
1816 /* (then/else) start at top of log */
1817 iwl_print_event_log(priv, 0, next_entry, mode);
1818
1819}
1820#endif
1821
b481de9c 1822/**
4a4a9e81 1823 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1824 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1825 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1826 */
4a4a9e81 1827static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1828{
57aab75a 1829 int ret = 0;
b481de9c 1830
e1623446 1831 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1832
1833 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1834 /* We had an error bringing up the hardware, so take it
1835 * all the way back down so we can try again */
e1623446 1836 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1837 goto restart;
1838 }
1839
1840 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1841 * This is a paranoid check, because we would not have gotten the
1842 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1843 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1844 /* Runtime instruction load was bad;
1845 * take it all the way back down so we can try again */
e1623446 1846 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1847 goto restart;
1848 }
1849
c587de0b 1850 iwl_clear_stations_table(priv);
57aab75a
TW
1851 ret = priv->cfg->ops->lib->alive_notify(priv);
1852 if (ret) {
39aadf8c
WT
1853 IWL_WARN(priv,
1854 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1855 goto restart;
1856 }
1857
5b9f8cd3 1858 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1859 set_bit(STATUS_ALIVE, &priv->status);
1860
fee1247a 1861 if (iwl_is_rfkill(priv))
b481de9c
ZY
1862 return;
1863
36d6825b 1864 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1865
1866 priv->active_rate = priv->rates_mask;
1867 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1868
2f748dec
WYG
1869 /* Configure Tx antenna selection based on H/W config */
1870 if (priv->cfg->ops->hcmd->set_tx_ant)
1871 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
1872
3109ece1 1873 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1874 struct iwl_rxon_cmd *active_rxon =
1875 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1876 /* apply any changes in staging */
1877 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1878 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1879 } else {
1880 /* Initialize our rx_config data */
5b9f8cd3 1881 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
1882
1883 if (priv->cfg->ops->hcmd->set_rxon_chain)
1884 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1885
b481de9c
ZY
1886 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1887 }
1888
9fbab516 1889 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1890 iwl_send_bt_config(priv);
b481de9c 1891
4a4a9e81
TW
1892 iwl_reset_run_time_calib(priv);
1893
b481de9c 1894 /* Configure the adapter for unassociated operation */
e0158e61 1895 iwlcore_commit_rxon(priv);
b481de9c
ZY
1896
1897 /* At this point, the NIC is initialized and operational */
47f4a587 1898 iwl_rf_kill_ct_config(priv);
5a66926a 1899
e932a609 1900 iwl_leds_init(priv);
fe00b5a5 1901
e1623446 1902 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1903 set_bit(STATUS_READY, &priv->status);
5a66926a 1904 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1905
e312c24c 1906 iwl_power_update_mode(priv, true);
c46fbefa 1907
ada17513
MA
1908 /* reassociate for ADHOC mode */
1909 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1910 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1911 priv->vif);
1912 if (beacon)
1913 iwl_mac_beacon_update(priv->hw, beacon);
1914 }
1915
1916
c46fbefa 1917 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1918 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1919
b481de9c
ZY
1920 return;
1921
1922 restart:
1923 queue_work(priv->workqueue, &priv->restart);
1924}
1925
4e39317d 1926static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1927
5b9f8cd3 1928static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1929{
1930 unsigned long flags;
1931 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1932
e1623446 1933 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1934
b481de9c
ZY
1935 if (!exit_pending)
1936 set_bit(STATUS_EXIT_PENDING, &priv->status);
1937
c587de0b 1938 iwl_clear_stations_table(priv);
b481de9c
ZY
1939
1940 /* Unblock any waiting calls */
1941 wake_up_interruptible_all(&priv->wait_command_queue);
1942
b481de9c
ZY
1943 /* Wipe out the EXIT_PENDING status bit if we are not actually
1944 * exiting the module */
1945 if (!exit_pending)
1946 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1947
1948 /* stop and reset the on-board processor */
3395f6e9 1949 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
1950
1951 /* tell the device to stop sending interrupts */
0359facc 1952 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1953 iwl_disable_interrupts(priv);
0359facc
MA
1954 spin_unlock_irqrestore(&priv->lock, flags);
1955 iwl_synchronize_irq(priv);
b481de9c
ZY
1956
1957 if (priv->mac80211_registered)
1958 ieee80211_stop_queues(priv->hw);
1959
5b9f8cd3 1960 /* If we have not previously called iwl_init() then
a60e77e5 1961 * clear all bits but the RF Kill bit and return */
fee1247a 1962 if (!iwl_is_init(priv)) {
b481de9c
ZY
1963 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1964 STATUS_RF_KILL_HW |
9788864e
RC
1965 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1966 STATUS_GEO_CONFIGURED |
052ec3f1
MA
1967 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1968 STATUS_EXIT_PENDING;
b481de9c
ZY
1969 goto exit;
1970 }
1971
6da3a13e 1972 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 1973 * bit and continue taking the NIC down. */
b481de9c
ZY
1974 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1975 STATUS_RF_KILL_HW |
9788864e
RC
1976 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1977 STATUS_GEO_CONFIGURED |
b481de9c 1978 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
1979 STATUS_FW_ERROR |
1980 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1981 STATUS_EXIT_PENDING;
b481de9c 1982
ef850d7c
MA
1983 /* device going down, Stop using ICT table */
1984 iwl_disable_ict(priv);
b481de9c 1985
da1bc453 1986 iwl_txq_ctx_stop(priv);
b3bbacb7 1987 iwl_rxq_stop(priv);
b481de9c 1988
309e731a
BC
1989 /* Power-down device's busmaster DMA clocks */
1990 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
1991 udelay(5);
1992
309e731a
BC
1993 /* Make sure (redundant) we've released our request to stay awake */
1994 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1995
4d2ccdb9
BC
1996 /* Stop the device, and put it in low power state */
1997 priv->cfg->ops->lib->apm_ops.stop(priv);
1998
b481de9c 1999 exit:
885ba202 2000 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2001
2002 if (priv->ibss_beacon)
2003 dev_kfree_skb(priv->ibss_beacon);
2004 priv->ibss_beacon = NULL;
2005
2006 /* clear out any free frames */
fcab423d 2007 iwl_clear_free_frames(priv);
b481de9c
ZY
2008}
2009
5b9f8cd3 2010static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2011{
2012 mutex_lock(&priv->mutex);
5b9f8cd3 2013 __iwl_down(priv);
b481de9c 2014 mutex_unlock(&priv->mutex);
b24d22b1 2015
4e39317d 2016 iwl_cancel_deferred_work(priv);
b481de9c
ZY
2017}
2018
086ed117
MA
2019#define HW_READY_TIMEOUT (50)
2020
2021static int iwl_set_hw_ready(struct iwl_priv *priv)
2022{
2023 int ret = 0;
2024
2025 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2026 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2027
2028 /* See if we got it */
2029 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2030 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2031 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2032 HW_READY_TIMEOUT);
2033 if (ret != -ETIMEDOUT)
2034 priv->hw_ready = true;
2035 else
2036 priv->hw_ready = false;
2037
2038 IWL_DEBUG_INFO(priv, "hardware %s\n",
2039 (priv->hw_ready == 1) ? "ready" : "not ready");
2040 return ret;
2041}
2042
2043static int iwl_prepare_card_hw(struct iwl_priv *priv)
2044{
2045 int ret = 0;
2046
2047 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
2048
3354a0f6
MA
2049 ret = iwl_set_hw_ready(priv);
2050 if (priv->hw_ready)
2051 return ret;
2052
2053 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
2054 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2055 CSR_HW_IF_CONFIG_REG_PREPARE);
2056
2057 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2058 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2059 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2060
3354a0f6 2061 /* HW should be ready by now, check again. */
086ed117
MA
2062 if (ret != -ETIMEDOUT)
2063 iwl_set_hw_ready(priv);
2064
2065 return ret;
2066}
2067
b481de9c
ZY
2068#define MAX_HW_RESTARTS 5
2069
5b9f8cd3 2070static int __iwl_up(struct iwl_priv *priv)
b481de9c 2071{
57aab75a
TW
2072 int i;
2073 int ret;
b481de9c
ZY
2074
2075 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2076 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2077 return -EIO;
2078 }
2079
e903fbd4 2080 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2081 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
2082 return -EIO;
2083 }
2084
086ed117
MA
2085 iwl_prepare_card_hw(priv);
2086
2087 if (!priv->hw_ready) {
2088 IWL_WARN(priv, "Exit HW not ready\n");
2089 return -EIO;
2090 }
2091
e655b9f0 2092 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2093 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2094 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2095 else
e655b9f0 2096 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2097
c1842d61 2098 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
2099 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2100
5b9f8cd3 2101 iwl_enable_interrupts(priv);
a60e77e5 2102 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2103 return 0;
b481de9c
ZY
2104 }
2105
3395f6e9 2106 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2107
1053d35f 2108 ret = iwl_hw_nic_init(priv);
57aab75a 2109 if (ret) {
15b1687c 2110 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2111 return ret;
b481de9c
ZY
2112 }
2113
2114 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2115 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2116 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2117 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2118
2119 /* clear (again), then enable host interrupts */
3395f6e9 2120 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2121 iwl_enable_interrupts(priv);
b481de9c
ZY
2122
2123 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2124 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2125 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2126
2127 /* Copy original ucode data image from disk into backup cache.
2128 * This will be used to initialize the on-board processor's
2129 * data SRAM for a clean start when the runtime program first loads. */
2130 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2131 priv->ucode_data.len);
b481de9c 2132
b481de9c
ZY
2133 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2134
c587de0b 2135 iwl_clear_stations_table(priv);
b481de9c
ZY
2136
2137 /* load bootstrap state machine,
2138 * load bootstrap program into processor's memory,
2139 * prepare to load the "initialize" uCode */
57aab75a 2140 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2141
57aab75a 2142 if (ret) {
15b1687c
WT
2143 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2144 ret);
b481de9c
ZY
2145 continue;
2146 }
2147
2148 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2149 iwl_nic_start(priv);
b481de9c 2150
e1623446 2151 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2152
2153 return 0;
2154 }
2155
2156 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2157 __iwl_down(priv);
64e72c3e 2158 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2159
2160 /* tried to restart and config the device for as long as our
2161 * patience could withstand */
15b1687c 2162 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2163 return -EIO;
2164}
2165
2166
2167/*****************************************************************************
2168 *
2169 * Workqueue callbacks
2170 *
2171 *****************************************************************************/
2172
4a4a9e81 2173static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2174{
c79dd5b5
TW
2175 struct iwl_priv *priv =
2176 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2177
2178 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2179 return;
2180
2181 mutex_lock(&priv->mutex);
f3ccc08c 2182 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2183 mutex_unlock(&priv->mutex);
2184}
2185
4a4a9e81 2186static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2187{
c79dd5b5
TW
2188 struct iwl_priv *priv =
2189 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2190
2191 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2192 return;
2193
258c44a0
MA
2194 /* enable dram interrupt */
2195 iwl_reset_ict(priv);
2196
b481de9c 2197 mutex_lock(&priv->mutex);
4a4a9e81 2198 iwl_alive_start(priv);
b481de9c
ZY
2199 mutex_unlock(&priv->mutex);
2200}
2201
16e727e8
EG
2202static void iwl_bg_run_time_calib_work(struct work_struct *work)
2203{
2204 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2205 run_time_calib_work);
2206
2207 mutex_lock(&priv->mutex);
2208
2209 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2210 test_bit(STATUS_SCANNING, &priv->status)) {
2211 mutex_unlock(&priv->mutex);
2212 return;
2213 }
2214
2215 if (priv->start_calib) {
2216 iwl_chain_noise_calibration(priv, &priv->statistics);
2217
2218 iwl_sensitivity_calibration(priv, &priv->statistics);
2219 }
2220
2221 mutex_unlock(&priv->mutex);
2222 return;
2223}
2224
5b9f8cd3 2225static void iwl_bg_up(struct work_struct *data)
b481de9c 2226{
c79dd5b5 2227 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2228
2229 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2230 return;
2231
2232 mutex_lock(&priv->mutex);
5b9f8cd3 2233 __iwl_up(priv);
b481de9c
ZY
2234 mutex_unlock(&priv->mutex);
2235}
2236
5b9f8cd3 2237static void iwl_bg_restart(struct work_struct *data)
b481de9c 2238{
c79dd5b5 2239 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2240
2241 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2242 return;
2243
19cc1087
JB
2244 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2245 mutex_lock(&priv->mutex);
2246 priv->vif = NULL;
2247 priv->is_open = 0;
2248 mutex_unlock(&priv->mutex);
2249 iwl_down(priv);
2250 ieee80211_restart_hw(priv->hw);
2251 } else {
2252 iwl_down(priv);
2253 queue_work(priv->workqueue, &priv->up);
2254 }
b481de9c
ZY
2255}
2256
5b9f8cd3 2257static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2258{
c79dd5b5
TW
2259 struct iwl_priv *priv =
2260 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2261
2262 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2263 return;
2264
2265 mutex_lock(&priv->mutex);
a55360e4 2266 iwl_rx_replenish(priv);
b481de9c
ZY
2267 mutex_unlock(&priv->mutex);
2268}
2269
7878a5a4
MA
2270#define IWL_DELAY_NEXT_SCAN (HZ*2)
2271
5bbe233b 2272void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2273{
b481de9c 2274 struct ieee80211_conf *conf = NULL;
857485c0 2275 int ret = 0;
1ff50bda 2276 unsigned long flags;
b481de9c 2277
05c914fe 2278 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2279 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2280 return;
2281 }
2282
e1623446 2283 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2284 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2285
2286
2287 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2288 return;
2289
b481de9c 2290
508e32e1 2291 if (!priv->vif || !priv->is_open)
948c171c 2292 return;
508e32e1 2293
2a421b91 2294 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2295
b481de9c
ZY
2296 conf = ieee80211_get_hw_conf(priv->hw);
2297
2298 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2299 iwlcore_commit_rxon(priv);
b481de9c 2300
3195c1f3 2301 iwl_setup_rxon_timing(priv);
857485c0 2302 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2303 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2304 if (ret)
39aadf8c 2305 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2306 "Attempting to continue.\n");
2307
2308 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2309
42eb7c64 2310 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2311
45823531
AK
2312 if (priv->cfg->ops->hcmd->set_rxon_chain)
2313 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2314
b481de9c
ZY
2315 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2316
e1623446 2317 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2318 priv->assoc_id, priv->beacon_int);
2319
2320 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2321 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2322 else
2323 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2324
2325 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2326 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2327 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2328 else
2329 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2330
05c914fe 2331 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2332 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2333
2334 }
2335
e0158e61 2336 iwlcore_commit_rxon(priv);
b481de9c
ZY
2337
2338 switch (priv->iw_mode) {
05c914fe 2339 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2340 break;
2341
05c914fe 2342 case NL80211_IFTYPE_ADHOC:
b481de9c 2343
c46fbefa
AK
2344 /* assume default assoc id */
2345 priv->assoc_id = 1;
b481de9c 2346
4f40e4d9 2347 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2348 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2349
2350 break;
2351
2352 default:
15b1687c 2353 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2354 __func__, priv->iw_mode);
b481de9c
ZY
2355 break;
2356 }
2357
05c914fe 2358 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2359 priv->assoc_station_added = 1;
2360
1ff50bda
EG
2361 spin_lock_irqsave(&priv->lock, flags);
2362 iwl_activate_qos(priv, 0);
2363 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2364
04816448
GE
2365 /* the chain noise calibration will enabled PM upon completion
2366 * If chain noise has already been run, then we need to enable
2367 * power management here */
2368 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2369 iwl_power_update_mode(priv, false);
c90a74ba
EG
2370
2371 /* Enable Rx differential gain and sensitivity calibrations */
2372 iwl_chain_noise_reset(priv);
2373 priv->start_calib = 1;
2374
508e32e1
RC
2375}
2376
b481de9c
ZY
2377/*****************************************************************************
2378 *
2379 * mac80211 entry point functions
2380 *
2381 *****************************************************************************/
2382
154b25ce 2383#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2384
f0b6e2e8
RC
2385/*
2386 * Not a mac80211 entry point function, but it fits in with all the
2387 * other mac80211 functions grouped here.
2388 */
2389static int iwl_setup_mac(struct iwl_priv *priv)
2390{
2391 int ret;
2392 struct ieee80211_hw *hw = priv->hw;
2393 hw->rate_control_algorithm = "iwl-agn-rs";
2394
2395 /* Tell mac80211 our characteristics */
2396 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2397 IEEE80211_HW_NOISE_DBM |
2398 IEEE80211_HW_AMPDU_AGGREGATION |
2399 IEEE80211_HW_SPECTRUM_MGMT;
2400
2401 if (!priv->cfg->broken_powersave)
2402 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2403 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2404
8d9698b3 2405 hw->sta_data_size = sizeof(struct iwl_station_priv);
f0b6e2e8
RC
2406 hw->wiphy->interface_modes =
2407 BIT(NL80211_IFTYPE_STATION) |
2408 BIT(NL80211_IFTYPE_ADHOC);
2409
5be83de5
JB
2410 hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
2411 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC
2412
2413 /*
2414 * For now, disable PS by default because it affects
2415 * RX performance significantly.
2416 */
5be83de5 2417 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8
RC
2418
2419 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2420 /* we create the 802.11 header and a zero-length SSID element */
2421 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2422
2423 /* Default value; 4 EDCA QOS priorities */
2424 hw->queues = 4;
2425
2426 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2427
2428 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2429 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2430 &priv->bands[IEEE80211_BAND_2GHZ];
2431 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2432 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2433 &priv->bands[IEEE80211_BAND_5GHZ];
2434
2435 ret = ieee80211_register_hw(priv->hw);
2436 if (ret) {
2437 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2438 return ret;
2439 }
2440 priv->mac80211_registered = 1;
2441
2442 return 0;
2443}
2444
2445
5b9f8cd3 2446static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2447{
c79dd5b5 2448 struct iwl_priv *priv = hw->priv;
5a66926a 2449 int ret;
b481de9c 2450
e1623446 2451 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2452
2453 /* we should be verifying the device is ready to be opened */
2454 mutex_lock(&priv->mutex);
2455
5a66926a
ZY
2456 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2457 * ucode filename and max sizes are card-specific. */
b481de9c 2458
5a66926a 2459 if (!priv->ucode_code.len) {
5b9f8cd3 2460 ret = iwl_read_ucode(priv);
5a66926a 2461 if (ret) {
15b1687c 2462 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2463 mutex_unlock(&priv->mutex);
6cd0b1cb 2464 return ret;
5a66926a
ZY
2465 }
2466 }
b481de9c 2467
5b9f8cd3 2468 ret = __iwl_up(priv);
5a66926a 2469
b481de9c 2470 mutex_unlock(&priv->mutex);
5a66926a 2471
e655b9f0 2472 if (ret)
6cd0b1cb 2473 return ret;
e655b9f0 2474
c1842d61
TW
2475 if (iwl_is_rfkill(priv))
2476 goto out;
2477
e1623446 2478 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2479
fe9b6b72 2480 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2481 * mac80211 will not be run successfully. */
154b25ce
EG
2482 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2483 test_bit(STATUS_READY, &priv->status),
2484 UCODE_READY_TIMEOUT);
2485 if (!ret) {
2486 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2487 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2488 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2489 return -ETIMEDOUT;
5a66926a 2490 }
fe9b6b72 2491 }
0a078ffa 2492
e932a609
JB
2493 iwl_led_start(priv);
2494
c1842d61 2495out:
0a078ffa 2496 priv->is_open = 1;
e1623446 2497 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2498 return 0;
2499}
2500
5b9f8cd3 2501static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2502{
c79dd5b5 2503 struct iwl_priv *priv = hw->priv;
b481de9c 2504
e1623446 2505 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2506
19cc1087 2507 if (!priv->is_open)
e655b9f0 2508 return;
e655b9f0 2509
b481de9c 2510 priv->is_open = 0;
5a66926a 2511
5bddf549 2512 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2513 /* stop mac, cancel any scan request and clear
2514 * RXON_FILTER_ASSOC_MSK BIT
2515 */
5a66926a 2516 mutex_lock(&priv->mutex);
2a421b91 2517 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2518 mutex_unlock(&priv->mutex);
fde3571f
MA
2519 }
2520
5b9f8cd3 2521 iwl_down(priv);
5a66926a
ZY
2522
2523 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2524
2525 /* enable interrupts again in order to receive rfkill changes */
2526 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2527 iwl_enable_interrupts(priv);
948c171c 2528
e1623446 2529 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2530}
2531
5b9f8cd3 2532static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2533{
c79dd5b5 2534 struct iwl_priv *priv = hw->priv;
b481de9c 2535
e1623446 2536 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2537
e1623446 2538 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2539 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2540
e039fa4a 2541 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2542 dev_kfree_skb_any(skb);
2543
e1623446 2544 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2545 return NETDEV_TX_OK;
b481de9c
ZY
2546}
2547
60690a6a 2548void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2549{
857485c0 2550 int ret = 0;
1ff50bda 2551 unsigned long flags;
b481de9c 2552
d986bcd1 2553 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2554 return;
2555
2556 /* The following should be done only at AP bring up */
3195c1f3 2557 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2558
2559 /* RXON - unassoc (to set timing command) */
2560 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2561 iwlcore_commit_rxon(priv);
b481de9c
ZY
2562
2563 /* RXON Timing */
3195c1f3 2564 iwl_setup_rxon_timing(priv);
857485c0 2565 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2566 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2567 if (ret)
39aadf8c 2568 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2569 "Attempting to continue.\n");
2570
f513dfff
DH
2571 /* AP has all antennas */
2572 priv->chain_noise_data.active_chains =
2573 priv->hw_params.valid_rx_ant;
2574 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK
2575 if (priv->cfg->ops->hcmd->set_rxon_chain)
2576 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2577
2578 /* FIXME: what should be the assoc_id for AP? */
2579 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2580 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2581 priv->staging_rxon.flags |=
2582 RXON_FLG_SHORT_PREAMBLE_MSK;
2583 else
2584 priv->staging_rxon.flags &=
2585 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2586
2587 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2588 if (priv->assoc_capability &
2589 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2590 priv->staging_rxon.flags |=
2591 RXON_FLG_SHORT_SLOT_MSK;
2592 else
2593 priv->staging_rxon.flags &=
2594 ~RXON_FLG_SHORT_SLOT_MSK;
2595
05c914fe 2596 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2597 priv->staging_rxon.flags &=
2598 ~RXON_FLG_SHORT_SLOT_MSK;
2599 }
2600 /* restore RXON assoc */
2601 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2602 iwlcore_commit_rxon(priv);
f513dfff 2603 iwl_reset_qos(priv);
1ff50bda
EG
2604 spin_lock_irqsave(&priv->lock, flags);
2605 iwl_activate_qos(priv, 1);
2606 spin_unlock_irqrestore(&priv->lock, flags);
9a9ca65f 2607 iwl_add_bcast_station(priv);
e1493deb 2608 }
5b9f8cd3 2609 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2610
2611 /* FIXME - we need to add code here to detect a totally new
2612 * configuration, reset the AP, unassoc, rxon timing, assoc,
2613 * clear sta table, add BCAST sta... */
2614}
2615
5b9f8cd3 2616static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2617 struct ieee80211_key_conf *keyconf, const u8 *addr,
2618 u32 iv32, u16 *phase1key)
2619{
ab885f8c 2620
9f58671e 2621 struct iwl_priv *priv = hw->priv;
e1623446 2622 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2623
9f58671e 2624 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2625
e1623446 2626 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2627}
2628
5b9f8cd3 2629static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2630 struct ieee80211_vif *vif,
2631 struct ieee80211_sta *sta,
b481de9c
ZY
2632 struct ieee80211_key_conf *key)
2633{
c79dd5b5 2634 struct iwl_priv *priv = hw->priv;
42986796
WT
2635 const u8 *addr;
2636 int ret;
2637 u8 sta_id;
2638 bool is_default_wep_key = false;
b481de9c 2639
e1623446 2640 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2641
90e8e424 2642 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2643 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2644 return -EOPNOTSUPP;
2645 }
42986796 2646 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2647 sta_id = iwl_find_station(priv, addr);
6974e363 2648 if (sta_id == IWL_INVALID_STATION) {
e1623446 2649 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2650 addr);
6974e363 2651 return -EINVAL;
b481de9c 2652
deb09c43 2653 }
b481de9c 2654
6974e363 2655 mutex_lock(&priv->mutex);
2a421b91 2656 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2657 mutex_unlock(&priv->mutex);
2658
2659 /* If we are getting WEP group key and we didn't receive any key mapping
2660 * so far, we are in legacy wep mode (group key only), otherwise we are
2661 * in 1X mode.
2662 * In legacy wep mode, we use another host command to the uCode */
5425e490 2663 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2664 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2665 if (cmd == SET_KEY)
2666 is_default_wep_key = !priv->key_mapping_key;
2667 else
ccc038ab
EG
2668 is_default_wep_key =
2669 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2670 }
052c4b9f 2671
b481de9c 2672 switch (cmd) {
deb09c43 2673 case SET_KEY:
6974e363
EG
2674 if (is_default_wep_key)
2675 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2676 else
7480513f 2677 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2678
e1623446 2679 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2680 break;
2681 case DISABLE_KEY:
6974e363
EG
2682 if (is_default_wep_key)
2683 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2684 else
3ec47732 2685 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2686
e1623446 2687 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2688 break;
2689 default:
deb09c43 2690 ret = -EINVAL;
b481de9c
ZY
2691 }
2692
e1623446 2693 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2694
deb09c43 2695 return ret;
b481de9c
ZY
2696}
2697
5b9f8cd3 2698static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2699 struct ieee80211_vif *vif,
d783b061 2700 enum ieee80211_ampdu_mlme_action action,
17741cdc 2701 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2702{
2703 struct iwl_priv *priv = hw->priv;
5c2207c6 2704 int ret;
d783b061 2705
e1623446 2706 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2707 sta->addr, tid);
d783b061
TW
2708
2709 if (!(priv->cfg->sku & IWL_SKU_N))
2710 return -EACCES;
2711
2712 switch (action) {
2713 case IEEE80211_AMPDU_RX_START:
e1623446 2714 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2715 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2716 case IEEE80211_AMPDU_RX_STOP:
e1623446 2717 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2718 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2719 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2720 return 0;
2721 else
2722 return ret;
d783b061 2723 case IEEE80211_AMPDU_TX_START:
e1623446 2724 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2725 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2726 case IEEE80211_AMPDU_TX_STOP:
e1623446 2727 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2728 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2729 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2730 return 0;
2731 else
2732 return ret;
d783b061 2733 default:
e1623446 2734 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2735 return -EINVAL;
2736 break;
2737 }
2738 return 0;
2739}
9f58671e 2740
5b9f8cd3 2741static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2742 struct ieee80211_low_level_stats *stats)
2743{
bf403db8
EK
2744 struct iwl_priv *priv = hw->priv;
2745
2746 priv = hw->priv;
e1623446
TW
2747 IWL_DEBUG_MAC80211(priv, "enter\n");
2748 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2749
2750 return 0;
2751}
2752
6ab10ff8
JB
2753static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
2754 struct ieee80211_vif *vif,
2755 enum sta_notify_cmd cmd,
2756 struct ieee80211_sta *sta)
2757{
2758 struct iwl_priv *priv = hw->priv;
2759 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
2760 int sta_id;
2761
2762 /*
2763 * TODO: We really should use this callback to
2764 * actually maintain the station table in
2765 * the device.
2766 */
2767
2768 switch (cmd) {
2769 case STA_NOTIFY_ADD:
2770 atomic_set(&sta_priv->pending_frames, 0);
2771 if (vif->type == NL80211_IFTYPE_AP)
2772 sta_priv->client = true;
2773 break;
2774 case STA_NOTIFY_SLEEP:
2775 WARN_ON(!sta_priv->client);
2776 sta_priv->asleep = true;
2777 if (atomic_read(&sta_priv->pending_frames) > 0)
2778 ieee80211_sta_block_awake(hw, sta, true);
2779 break;
2780 case STA_NOTIFY_AWAKE:
2781 WARN_ON(!sta_priv->client);
2782 sta_priv->asleep = false;
2783 sta_id = iwl_find_station(priv, sta->addr);
2784 if (sta_id != IWL_INVALID_STATION)
2785 iwl_sta_modify_ps_wake(priv, sta_id);
2786 break;
2787 default:
2788 break;
2789 }
2790}
2791
b481de9c
ZY
2792/*****************************************************************************
2793 *
2794 * sysfs attributes
2795 *
2796 *****************************************************************************/
2797
0a6857e7 2798#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2799
2800/*
2801 * The following adds a new attribute to the sysfs representation
c3a739fa 2802 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2803 * used for controlling the debug level.
2804 *
2805 * See the level definitions in iwl for details.
a562a9dd 2806 *
3d816c77
RC
2807 * The debug_level being managed using sysfs below is a per device debug
2808 * level that is used instead of the global debug level if it (the per
2809 * device debug level) is set.
b481de9c 2810 */
8cf769c6
EK
2811static ssize_t show_debug_level(struct device *d,
2812 struct device_attribute *attr, char *buf)
b481de9c 2813{
3d816c77
RC
2814 struct iwl_priv *priv = dev_get_drvdata(d);
2815 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 2816}
8cf769c6
EK
2817static ssize_t store_debug_level(struct device *d,
2818 struct device_attribute *attr,
b481de9c
ZY
2819 const char *buf, size_t count)
2820{
928841b1 2821 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2822 unsigned long val;
2823 int ret;
b481de9c 2824
9257746f
TW
2825 ret = strict_strtoul(buf, 0, &val);
2826 if (ret)
978785a3 2827 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 2828 else {
3d816c77 2829 priv->debug_level = val;
20594eb0
WYG
2830 if (iwl_alloc_traffic_mem(priv))
2831 IWL_ERR(priv,
2832 "Not enough memory to generate traffic log\n");
2833 }
b481de9c
ZY
2834 return strnlen(buf, count);
2835}
2836
8cf769c6
EK
2837static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2838 show_debug_level, store_debug_level);
2839
b481de9c 2840
0a6857e7 2841#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2842
b481de9c
ZY
2843
2844static ssize_t show_temperature(struct device *d,
2845 struct device_attribute *attr, char *buf)
2846{
928841b1 2847 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 2848
fee1247a 2849 if (!iwl_is_alive(priv))
b481de9c
ZY
2850 return -EAGAIN;
2851
91dbc5bd 2852 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2853}
2854
2855static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2856
b481de9c
ZY
2857static ssize_t show_tx_power(struct device *d,
2858 struct device_attribute *attr, char *buf)
2859{
928841b1 2860 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
2861
2862 if (!iwl_is_ready_rf(priv))
2863 return sprintf(buf, "off\n");
2864 else
2865 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2866}
2867
2868static ssize_t store_tx_power(struct device *d,
2869 struct device_attribute *attr,
2870 const char *buf, size_t count)
2871{
928841b1 2872 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2873 unsigned long val;
2874 int ret;
b481de9c 2875
9257746f
TW
2876 ret = strict_strtoul(buf, 10, &val);
2877 if (ret)
978785a3 2878 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
2879 else {
2880 ret = iwl_set_tx_power(priv, val, false);
2881 if (ret)
2882 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
2883 ret);
2884 else
2885 ret = count;
2886 }
2887 return ret;
b481de9c
ZY
2888}
2889
2890static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2891
2892static ssize_t show_flags(struct device *d,
2893 struct device_attribute *attr, char *buf)
2894{
928841b1 2895 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2896
2897 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2898}
2899
2900static ssize_t store_flags(struct device *d,
2901 struct device_attribute *attr,
2902 const char *buf, size_t count)
2903{
928841b1 2904 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2905 unsigned long val;
2906 u32 flags;
2907 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2908 if (ret)
9257746f
TW
2909 return ret;
2910 flags = (u32)val;
b481de9c
ZY
2911
2912 mutex_lock(&priv->mutex);
2913 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2914 /* Cancel any currently running scans... */
2a421b91 2915 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2916 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2917 else {
e1623446 2918 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2919 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2920 iwlcore_commit_rxon(priv);
b481de9c
ZY
2921 }
2922 }
2923 mutex_unlock(&priv->mutex);
2924
2925 return count;
2926}
2927
2928static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2929
2930static ssize_t show_filter_flags(struct device *d,
2931 struct device_attribute *attr, char *buf)
2932{
928841b1 2933 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2934
2935 return sprintf(buf, "0x%04X\n",
2936 le32_to_cpu(priv->active_rxon.filter_flags));
2937}
2938
2939static ssize_t store_filter_flags(struct device *d,
2940 struct device_attribute *attr,
2941 const char *buf, size_t count)
2942{
928841b1 2943 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2944 unsigned long val;
2945 u32 filter_flags;
2946 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2947 if (ret)
9257746f
TW
2948 return ret;
2949 filter_flags = (u32)val;
b481de9c
ZY
2950
2951 mutex_lock(&priv->mutex);
2952 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2953 /* Cancel any currently running scans... */
2a421b91 2954 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2955 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2956 else {
e1623446 2957 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
2958 "0x%04X\n", filter_flags);
2959 priv->staging_rxon.filter_flags =
2960 cpu_to_le32(filter_flags);
e0158e61 2961 iwlcore_commit_rxon(priv);
b481de9c
ZY
2962 }
2963 }
2964 mutex_unlock(&priv->mutex);
2965
2966 return count;
2967}
2968
2969static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2970 store_filter_flags);
2971
b481de9c
ZY
2972
2973static ssize_t show_statistics(struct device *d,
2974 struct device_attribute *attr, char *buf)
2975{
c79dd5b5 2976 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 2977 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 2978 u32 len = 0, ofs = 0;
3ac7f146 2979 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
2980 int rc = 0;
2981
fee1247a 2982 if (!iwl_is_alive(priv))
b481de9c
ZY
2983 return -EAGAIN;
2984
2985 mutex_lock(&priv->mutex);
ef8d5529 2986 rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
b481de9c
ZY
2987 mutex_unlock(&priv->mutex);
2988
2989 if (rc) {
2990 len = sprintf(buf,
2991 "Error sending statistics request: 0x%08X\n", rc);
2992 return len;
2993 }
2994
2995 while (size && (PAGE_SIZE - len)) {
2996 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2997 PAGE_SIZE - len, 1);
2998 len = strlen(buf);
2999 if (PAGE_SIZE - len)
3000 buf[len++] = '\n';
3001
3002 ofs += 16;
3003 size -= min(size, 16U);
3004 }
3005
3006 return len;
3007}
3008
3009static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3010
01abfbb2
WYG
3011static ssize_t show_rts_ht_protection(struct device *d,
3012 struct device_attribute *attr, char *buf)
3013{
3014 struct iwl_priv *priv = dev_get_drvdata(d);
3015
3016 return sprintf(buf, "%s\n",
3017 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3018}
3019
3020static ssize_t store_rts_ht_protection(struct device *d,
3021 struct device_attribute *attr,
3022 const char *buf, size_t count)
3023{
3024 struct iwl_priv *priv = dev_get_drvdata(d);
3025 unsigned long val;
3026 int ret;
3027
3028 ret = strict_strtoul(buf, 10, &val);
3029 if (ret)
3030 IWL_INFO(priv, "Input is not in decimal form.\n");
3031 else {
3032 if (!iwl_is_associated(priv))
3033 priv->cfg->use_rts_for_ht = val ? true : false;
3034 else
3035 IWL_ERR(priv, "Sta associated with AP - "
3036 "Change protection mechanism is not allowed\n");
3037 ret = count;
3038 }
3039 return ret;
3040}
3041
3042static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3043 show_rts_ht_protection, store_rts_ht_protection);
3044
b481de9c 3045
b481de9c
ZY
3046/*****************************************************************************
3047 *
3048 * driver setup and teardown
3049 *
3050 *****************************************************************************/
3051
4e39317d 3052static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3053{
d21050c7 3054 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3055
3056 init_waitqueue_head(&priv->wait_command_queue);
3057
5b9f8cd3
EG
3058 INIT_WORK(&priv->up, iwl_bg_up);
3059 INIT_WORK(&priv->restart, iwl_bg_restart);
3060 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3061 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3062 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
3063 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3064 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3065
2a421b91 3066 iwl_setup_scan_deferred_work(priv);
bb8c093b 3067
4e39317d
EG
3068 if (priv->cfg->ops->lib->setup_deferred_work)
3069 priv->cfg->ops->lib->setup_deferred_work(priv);
3070
3071 init_timer(&priv->statistics_periodic);
3072 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3073 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3074
ef850d7c
MA
3075 if (!priv->cfg->use_isr_legacy)
3076 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3077 iwl_irq_tasklet, (unsigned long)priv);
3078 else
3079 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3080 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
3081}
3082
4e39317d 3083static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3084{
4e39317d
EG
3085 if (priv->cfg->ops->lib->cancel_deferred_work)
3086 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3087
3ae6a054 3088 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3089 cancel_delayed_work(&priv->scan_check);
3090 cancel_delayed_work(&priv->alive_start);
b481de9c 3091 cancel_work_sync(&priv->beacon_update);
4e39317d 3092 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
3093}
3094
89f186a8
RC
3095static void iwl_init_hw_rates(struct iwl_priv *priv,
3096 struct ieee80211_rate *rates)
3097{
3098 int i;
3099
3100 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3101 rates[i].bitrate = iwl_rates[i].ieee * 5;
3102 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3103 rates[i].hw_value_short = i;
3104 rates[i].flags = 0;
3105 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3106 /*
3107 * If CCK != 1M then set short preamble rate flag.
3108 */
3109 rates[i].flags |=
3110 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3111 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3112 }
3113 }
3114}
3115
3116static int iwl_init_drv(struct iwl_priv *priv)
3117{
3118 int ret;
3119
3120 priv->ibss_beacon = NULL;
3121
3122 spin_lock_init(&priv->lock);
3123 spin_lock_init(&priv->sta_lock);
3124 spin_lock_init(&priv->hcmd_lock);
3125
3126 INIT_LIST_HEAD(&priv->free_frames);
3127
3128 mutex_init(&priv->mutex);
3129
3130 /* Clear the driver's (not device's) station table */
3131 iwl_clear_stations_table(priv);
3132
3133 priv->ieee_channels = NULL;
3134 priv->ieee_rates = NULL;
3135 priv->band = IEEE80211_BAND_2GHZ;
3136
3137 priv->iw_mode = NL80211_IFTYPE_STATION;
3138
3139 /* Choose which receivers/antennas to use */
3140 if (priv->cfg->ops->hcmd->set_rxon_chain)
3141 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3142
3143 iwl_init_scan_params(priv);
3144
3145 iwl_reset_qos(priv);
3146
3147 priv->qos_data.qos_active = 0;
3148 priv->qos_data.qos_cap.val = 0;
3149
3150 priv->rates_mask = IWL_RATES_MASK;
3151 /* Set the tx_power_user_lmt to the lowest power level
3152 * this value will get overwritten by channel max power avg
3153 * from eeprom */
3154 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
3155
3156 ret = iwl_init_channel_map(priv);
3157 if (ret) {
3158 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3159 goto err;
3160 }
3161
3162 ret = iwlcore_init_geos(priv);
3163 if (ret) {
3164 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3165 goto err_free_channel_map;
3166 }
3167 iwl_init_hw_rates(priv, priv->ieee_rates);
3168
3169 return 0;
3170
3171err_free_channel_map:
3172 iwl_free_channel_map(priv);
3173err:
3174 return ret;
3175}
3176
3177static void iwl_uninit_drv(struct iwl_priv *priv)
3178{
3179 iwl_calib_free_results(priv);
3180 iwlcore_free_geos(priv);
3181 iwl_free_channel_map(priv);
3182 kfree(priv->scan);
3183}
3184
5b9f8cd3 3185static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
3186 &dev_attr_flags.attr,
3187 &dev_attr_filter_flags.attr,
b481de9c 3188 &dev_attr_statistics.attr,
b481de9c 3189 &dev_attr_temperature.attr,
b481de9c 3190 &dev_attr_tx_power.attr,
01abfbb2 3191 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK
3192#ifdef CONFIG_IWLWIFI_DEBUG
3193 &dev_attr_debug_level.attr,
3194#endif
b481de9c
ZY
3195 NULL
3196};
3197
5b9f8cd3 3198static struct attribute_group iwl_attribute_group = {
b481de9c 3199 .name = NULL, /* put in device directory */
5b9f8cd3 3200 .attrs = iwl_sysfs_entries,
b481de9c
ZY
3201};
3202
5b9f8cd3
EG
3203static struct ieee80211_ops iwl_hw_ops = {
3204 .tx = iwl_mac_tx,
3205 .start = iwl_mac_start,
3206 .stop = iwl_mac_stop,
3207 .add_interface = iwl_mac_add_interface,
3208 .remove_interface = iwl_mac_remove_interface,
3209 .config = iwl_mac_config,
5b9f8cd3
EG
3210 .configure_filter = iwl_configure_filter,
3211 .set_key = iwl_mac_set_key,
3212 .update_tkip_key = iwl_mac_update_tkip_key,
3213 .get_stats = iwl_mac_get_stats,
3214 .get_tx_stats = iwl_mac_get_tx_stats,
3215 .conf_tx = iwl_mac_conf_tx,
3216 .reset_tsf = iwl_mac_reset_tsf,
3217 .bss_info_changed = iwl_bss_info_changed,
3218 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB
3219 .hw_scan = iwl_mac_hw_scan,
3220 .sta_notify = iwl_mac_sta_notify,
b481de9c
ZY
3221};
3222
5b9f8cd3 3223static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3224{
3225 int err = 0;
c79dd5b5 3226 struct iwl_priv *priv;
b481de9c 3227 struct ieee80211_hw *hw;
82b9a121 3228 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3229 unsigned long flags;
6cd0b1cb 3230 u16 pci_cmd;
b481de9c 3231
316c30d9
AK
3232 /************************
3233 * 1. Allocating HW data
3234 ************************/
3235
6440adb5
BC
3236 /* Disabling hardware scan means that mac80211 will perform scans
3237 * "the hard way", rather than using device's scan. */
1ea87396 3238 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3239 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
3240 dev_printk(KERN_DEBUG, &(pdev->dev),
3241 "Disabling hw_scan\n");
5b9f8cd3 3242 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3243 }
3244
5b9f8cd3 3245 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3246 if (!hw) {
b481de9c
ZY
3247 err = -ENOMEM;
3248 goto out;
3249 }
1d0a082d
AK
3250 priv = hw->priv;
3251 /* At this point both hw and priv are allocated. */
3252
b481de9c
ZY
3253 SET_IEEE80211_DEV(hw, &pdev->dev);
3254
e1623446 3255 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3256 priv->cfg = cfg;
b481de9c 3257 priv->pci_dev = pdev;
40cefda9 3258 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3259
0a6857e7 3260#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3261 atomic_set(&priv->restrict_refcnt, 0);
3262#endif
20594eb0
WYG
3263 if (iwl_alloc_traffic_mem(priv))
3264 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3265
316c30d9
AK
3266 /**************************
3267 * 2. Initializing PCI bus
3268 **************************/
3269 if (pci_enable_device(pdev)) {
3270 err = -ENODEV;
3271 goto out_ieee80211_free_hw;
3272 }
3273
3274 pci_set_master(pdev);
3275
093d874c 3276 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3277 if (!err)
093d874c 3278 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3279 if (err) {
093d874c 3280 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3281 if (!err)
093d874c 3282 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3283 /* both attempts failed: */
316c30d9 3284 if (err) {
978785a3 3285 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3286 goto out_pci_disable_device;
cc2a8ea8 3287 }
316c30d9
AK
3288 }
3289
3290 err = pci_request_regions(pdev, DRV_NAME);
3291 if (err)
3292 goto out_pci_disable_device;
3293
3294 pci_set_drvdata(pdev, priv);
3295
316c30d9
AK
3296
3297 /***********************
3298 * 3. Read REV register
3299 ***********************/
3300 priv->hw_base = pci_iomap(pdev, 0, 0);
3301 if (!priv->hw_base) {
3302 err = -ENODEV;
3303 goto out_pci_release_regions;
3304 }
3305
e1623446 3306 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3307 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3308 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3309
a8b50a0a
MA
3310 /* this spin lock will be used in apm_ops.init and EEPROM access
3311 * we should init now
3312 */
3313 spin_lock_init(&priv->reg_lock);
b661c819 3314 iwl_hw_detect(priv);
978785a3 3315 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 3316 priv->cfg->name, priv->hw_rev);
316c30d9 3317
e7b63581
TW
3318 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3319 * PCI Tx retries from interfering with C3 CPU state */
3320 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3321
086ed117
MA
3322 iwl_prepare_card_hw(priv);
3323 if (!priv->hw_ready) {
3324 IWL_WARN(priv, "Failed, HW not ready\n");
3325 goto out_iounmap;
3326 }
3327
91238714
TW
3328 /*****************
3329 * 4. Read EEPROM
3330 *****************/
316c30d9
AK
3331 /* Read the EEPROM */
3332 err = iwl_eeprom_init(priv);
3333 if (err) {
15b1687c 3334 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3335 goto out_iounmap;
3336 }
8614f360
TW
3337 err = iwl_eeprom_check_version(priv);
3338 if (err)
c8f16138 3339 goto out_free_eeprom;
8614f360 3340
02883017 3341 /* extract MAC Address */
316c30d9 3342 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3343 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3344 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3345
3346 /************************
3347 * 5. Setup HW constants
3348 ************************/
da154e30 3349 if (iwl_set_hw_params(priv)) {
15b1687c 3350 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3351 goto out_free_eeprom;
316c30d9
AK
3352 }
3353
3354 /*******************
6ba87956 3355 * 6. Setup priv
316c30d9 3356 *******************/
b481de9c 3357
6ba87956 3358 err = iwl_init_drv(priv);
bf85ea4f 3359 if (err)
399f4900 3360 goto out_free_eeprom;
bf85ea4f 3361 /* At this point both hw and priv are initialized. */
316c30d9 3362
316c30d9 3363 /********************
09f9bf79 3364 * 7. Setup services
316c30d9 3365 ********************/
0359facc 3366 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3367 iwl_disable_interrupts(priv);
0359facc 3368 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3369
6cd0b1cb
HS
3370 pci_enable_msi(priv->pci_dev);
3371
ef850d7c
MA
3372 iwl_alloc_isr_ict(priv);
3373 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3374 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3375 if (err) {
3376 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3377 goto out_disable_msi;
3378 }
5b9f8cd3 3379 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3380 if (err) {
15b1687c 3381 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3382 goto out_free_irq;
316c30d9
AK
3383 }
3384
4e39317d 3385 iwl_setup_deferred_work(priv);
653fa4a0 3386 iwl_setup_rx_handlers(priv);
316c30d9 3387
6ba87956 3388 /**********************************
09f9bf79 3389 * 8. Setup and register mac80211
6ba87956
TW
3390 **********************************/
3391
6cd0b1cb
HS
3392 /* enable interrupts if needed: hw bug w/a */
3393 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3394 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3395 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3396 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3397 }
3398
3399 iwl_enable_interrupts(priv);
3400
6ba87956
TW
3401 err = iwl_setup_mac(priv);
3402 if (err)
3403 goto out_remove_sysfs;
3404
3405 err = iwl_dbgfs_register(priv, DRV_NAME);
3406 if (err)
a75fbe8d 3407 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
6ba87956 3408
6cd0b1cb
HS
3409 /* If platform's RF_KILL switch is NOT set to KILL */
3410 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3411 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3412 else
3413 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3414
a60e77e5
JB
3415 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3416 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3417
58d0f361 3418 iwl_power_initialize(priv);
39b73fb1 3419 iwl_tt_initialize(priv);
b481de9c
ZY
3420 return 0;
3421
316c30d9 3422 out_remove_sysfs:
c8f16138
RC
3423 destroy_workqueue(priv->workqueue);
3424 priv->workqueue = NULL;
5b9f8cd3 3425 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3426 out_free_irq:
3427 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3428 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3429 out_disable_msi:
3430 pci_disable_msi(priv->pci_dev);
6ba87956 3431 iwl_uninit_drv(priv);
073d3f5f
TW
3432 out_free_eeprom:
3433 iwl_eeprom_free(priv);
b481de9c
ZY
3434 out_iounmap:
3435 pci_iounmap(pdev, priv->hw_base);
3436 out_pci_release_regions:
316c30d9 3437 pci_set_drvdata(pdev, NULL);
623d563e 3438 pci_release_regions(pdev);
b481de9c
ZY
3439 out_pci_disable_device:
3440 pci_disable_device(pdev);
b481de9c 3441 out_ieee80211_free_hw:
20594eb0 3442 iwl_free_traffic_mem(priv);
d7c76f4c 3443 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3444 out:
3445 return err;
3446}
3447
5b9f8cd3 3448static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3449{
c79dd5b5 3450 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3451 unsigned long flags;
b481de9c
ZY
3452
3453 if (!priv)
3454 return;
3455
e1623446 3456 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3457
67249625 3458 iwl_dbgfs_unregister(priv);
5b9f8cd3 3459 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3460
5b9f8cd3
EG
3461 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3462 * to be called and iwl_down since we are removing the device
0b124c31
GG
3463 * we need to set STATUS_EXIT_PENDING bit.
3464 */
3465 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3466 if (priv->mac80211_registered) {
3467 ieee80211_unregister_hw(priv->hw);
3468 priv->mac80211_registered = 0;
0b124c31 3469 } else {
5b9f8cd3 3470 iwl_down(priv);
c4f55232
RR
3471 }
3472
c166b25a
BC
3473 /*
3474 * Make sure device is reset to low power before unloading driver.
3475 * This may be redundant with iwl_down(), but there are paths to
3476 * run iwl_down() without calling apm_ops.stop(), and there are
3477 * paths to avoid running iwl_down() at all before leaving driver.
3478 * This (inexpensive) call *makes sure* device is reset.
3479 */
3480 priv->cfg->ops->lib->apm_ops.stop(priv);
3481
39b73fb1
WYG
3482 iwl_tt_exit(priv);
3483
0359facc
MA
3484 /* make sure we flush any pending irq or
3485 * tasklet for the driver
3486 */
3487 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3488 iwl_disable_interrupts(priv);
0359facc
MA
3489 spin_unlock_irqrestore(&priv->lock, flags);
3490
3491 iwl_synchronize_irq(priv);
3492
5b9f8cd3 3493 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3494
3495 if (priv->rxq.bd)
a55360e4 3496 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3497 iwl_hw_txq_ctx_free(priv);
b481de9c 3498
c587de0b 3499 iwl_clear_stations_table(priv);
073d3f5f 3500 iwl_eeprom_free(priv);
b481de9c 3501
b481de9c 3502
948c171c
MA
3503 /*netif_stop_queue(dev); */
3504 flush_workqueue(priv->workqueue);
3505
5b9f8cd3 3506 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3507 * priv->workqueue... so we can't take down the workqueue
3508 * until now... */
3509 destroy_workqueue(priv->workqueue);
3510 priv->workqueue = NULL;
20594eb0 3511 iwl_free_traffic_mem(priv);
b481de9c 3512
6cd0b1cb
HS
3513 free_irq(priv->pci_dev->irq, priv);
3514 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3515 pci_iounmap(pdev, priv->hw_base);
3516 pci_release_regions(pdev);
3517 pci_disable_device(pdev);
3518 pci_set_drvdata(pdev, NULL);
3519
6ba87956 3520 iwl_uninit_drv(priv);
b481de9c 3521
ef850d7c
MA
3522 iwl_free_isr_ict(priv);
3523
b481de9c
ZY
3524 if (priv->ibss_beacon)
3525 dev_kfree_skb(priv->ibss_beacon);
3526
3527 ieee80211_free_hw(priv->hw);
3528}
3529
b481de9c
ZY
3530
3531/*****************************************************************************
3532 *
3533 * driver and module entry point
3534 *
3535 *****************************************************************************/
3536
fed9017e
RR
3537/* Hardware specific file defines the PCI IDs table for that hardware module */
3538static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3539#ifdef CONFIG_IWL4965
fed9017e
RR
3540 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3541 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3542#endif /* CONFIG_IWL4965 */
5a6a256e 3543#ifdef CONFIG_IWL5000
47408639
EK
3544 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3545 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3546 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3547 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3548 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3549 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3550 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK
3551 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3552 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3553 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW
3554/* 5350 WiFi/WiMax */
3555 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3556 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3557 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW
3558/* 5150 Wifi/WiMax */
3559 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3560 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
5953a62e
WYG
3561
3562/* 6x00 Series */
5953a62e
WYG
3563 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3564 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3565 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3566 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3567 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3568 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3569 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3570 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3571 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3572 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3573
3574/* 6x50 WiFi/WiMax Series */
5953a62e
WYG
3575 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3576 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3577 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3578 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG
3579 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3580 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3581
77dcb6a9 3582/* 1000 Series WiFi */
4bd0914f
WYG
3583 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3584 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3585 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3586 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3587 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3588 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3589 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3590 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3591 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3592 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3593 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3594 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 3595#endif /* CONFIG_IWL5000 */
7100e924 3596
fed9017e
RR
3597 {0}
3598};
3599MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3600
3601static struct pci_driver iwl_driver = {
b481de9c 3602 .name = DRV_NAME,
fed9017e 3603 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3604 .probe = iwl_pci_probe,
3605 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3606#ifdef CONFIG_PM
5b9f8cd3
EG
3607 .suspend = iwl_pci_suspend,
3608 .resume = iwl_pci_resume,
b481de9c
ZY
3609#endif
3610};
3611
5b9f8cd3 3612static int __init iwl_init(void)
b481de9c
ZY
3613{
3614
3615 int ret;
3616 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3617 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3618
e227ceac 3619 ret = iwlagn_rate_control_register();
897e1cf2 3620 if (ret) {
a3139c59
SO
3621 printk(KERN_ERR DRV_NAME
3622 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3623 return ret;
3624 }
3625
fed9017e 3626 ret = pci_register_driver(&iwl_driver);
b481de9c 3627 if (ret) {
a3139c59 3628 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3629 goto error_register;
b481de9c 3630 }
b481de9c
ZY
3631
3632 return ret;
897e1cf2 3633
897e1cf2 3634error_register:
e227ceac 3635 iwlagn_rate_control_unregister();
897e1cf2 3636 return ret;
b481de9c
ZY
3637}
3638
5b9f8cd3 3639static void __exit iwl_exit(void)
b481de9c 3640{
fed9017e 3641 pci_unregister_driver(&iwl_driver);
e227ceac 3642 iwlagn_rate_control_unregister();
b481de9c
ZY
3643}
3644
5b9f8cd3
EG
3645module_exit(iwl_exit);
3646module_init(iwl_init);
a562a9dd
RC
3647
3648#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3649module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 3650MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 3651module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
3652MODULE_PARM_DESC(debug, "debug output mask");
3653#endif
3654