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cfg80211: fix Kconfig for users of cfg80211
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
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43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO
47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
b481de9c
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64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
80bc5393 75#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
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92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
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101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
e0158e61 105int iwl_commit_rxon(struct iwl_priv *priv)
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106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
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115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
a326a5d0
EG
118 /* allow CTS-to-self if possible. this is relevant only for
119 * 5000, but will not damage 4965 */
120 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
b481de9c 121
8ccde88a 122 ret = iwl_check_rxon_cmd(priv);
43d59b32 123 if (ret) {
15b1687c 124 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
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125 return -EINVAL;
126 }
127
128 /* If we don't need to send a full RXON, we can use
5b9f8cd3 129 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 130 * and other flags for the current radio configuration. */
54559703 131 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
132 ret = iwl_send_rxon_assoc(priv);
133 if (ret) {
15b1687c 134 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 135 return ret;
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136 }
137
138 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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139 return 0;
140 }
141
142 /* station table will be cleared */
143 priv->assoc_station_added = 0;
144
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145 /* If we are currently associated and the new config requires
146 * an RXON_ASSOC and the new config wants the associated mask enabled,
147 * we must clear the associated from the active configuration
148 * before we apply the new config */
43d59b32 149 if (iwl_is_associated(priv) && new_assoc) {
e1623446 150 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
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151 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
152
43d59b32 153 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 154 sizeof(struct iwl_rxon_cmd),
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155 &priv->active_rxon);
156
157 /* If the mask clearing failed then we set
158 * active_rxon back to what it was previously */
43d59b32 159 if (ret) {
b481de9c 160 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 161 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 162 return ret;
b481de9c 163 }
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164 }
165
e1623446 166 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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167 "* with%s RXON_FILTER_ASSOC_MSK\n"
168 "* channel = %d\n"
e174961c 169 "* bssid = %pM\n",
43d59b32 170 (new_assoc ? "" : "out"),
b481de9c 171 le16_to_cpu(priv->staging_rxon.channel),
e174961c 172 priv->staging_rxon.bssid_addr);
b481de9c 173
5b9f8cd3 174 iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
43d59b32
EG
175
176 /* Apply the new configuration
177 * RXON unassoc clears the station table in uCode, send it before
178 * we add the bcast station. If assoc bit is set, we will send RXON
179 * after having added the bcast and bssid station.
180 */
181 if (!new_assoc) {
182 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 183 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 184 if (ret) {
15b1687c 185 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
186 return ret;
187 }
188 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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189 }
190
e11bc028 191 priv->cfg->ops->smgmt->clear_station_table(priv);
556f8db7 192
19cc1087 193 priv->start_calib = 0;
b481de9c 194
b481de9c 195 /* Add the broadcast address so we can send broadcast frames */
4f40e4d9 196 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
43d59b32 197 IWL_INVALID_STATION) {
15b1687c 198 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
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199 return -EIO;
200 }
201
202 /* If we have set the ASSOC_MSK and we are in BSS mode then
203 * add the IWL_AP_ID to the station rate table */
9185159d 204 if (new_assoc) {
05c914fe 205 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
206 ret = iwl_rxon_add_station(priv,
207 priv->active_rxon.bssid_addr, 1);
208 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
209 IWL_ERR(priv,
210 "Error adding AP address for TX.\n");
9185159d
TW
211 return -EIO;
212 }
213 priv->assoc_station_added = 1;
214 if (priv->default_wep_key &&
215 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
216 IWL_ERR(priv,
217 "Could not send WEP static key.\n");
b481de9c 218 }
43d59b32
EG
219
220 /* Apply the new configuration
221 * RXON assoc doesn't clear the station table in uCode,
222 */
223 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
224 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
225 if (ret) {
15b1687c 226 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
227 return ret;
228 }
229 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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230 }
231
36da7d70
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232 iwl_init_sensitivity(priv);
233
234 /* If we issue a new RXON command which required a tune then we must
235 * send a new TXPOWER command or we won't be able to Tx any frames */
236 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
237 if (ret) {
15b1687c 238 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
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239 return ret;
240 }
241
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242 return 0;
243}
244
5b9f8cd3 245void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
246{
247
45823531
AK
248 if (priv->cfg->ops->hcmd->set_rxon_chain)
249 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 250 iwlcore_commit_rxon(priv);
5da4b55f
MA
251}
252
fcab423d 253static void iwl_clear_free_frames(struct iwl_priv *priv)
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254{
255 struct list_head *element;
256
e1623446 257 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
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258 priv->frames_count);
259
260 while (!list_empty(&priv->free_frames)) {
261 element = priv->free_frames.next;
262 list_del(element);
fcab423d 263 kfree(list_entry(element, struct iwl_frame, list));
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264 priv->frames_count--;
265 }
266
267 if (priv->frames_count) {
39aadf8c 268 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
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269 priv->frames_count);
270 priv->frames_count = 0;
271 }
272}
273
fcab423d 274static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 275{
fcab423d 276 struct iwl_frame *frame;
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277 struct list_head *element;
278 if (list_empty(&priv->free_frames)) {
279 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
280 if (!frame) {
15b1687c 281 IWL_ERR(priv, "Could not allocate frame!\n");
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282 return NULL;
283 }
284
285 priv->frames_count++;
286 return frame;
287 }
288
289 element = priv->free_frames.next;
290 list_del(element);
fcab423d 291 return list_entry(element, struct iwl_frame, list);
b481de9c
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292}
293
fcab423d 294static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
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295{
296 memset(frame, 0, sizeof(*frame));
297 list_add(&frame->list, &priv->free_frames);
298}
299
4bf64efd
TW
300static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
301 struct ieee80211_hdr *hdr,
73ec1cc2 302 int left)
b481de9c 303{
3109ece1 304 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
305 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
306 (priv->iw_mode != NL80211_IFTYPE_AP)))
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307 return 0;
308
309 if (priv->ibss_beacon->len > left)
310 return 0;
311
312 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
313
314 return priv->ibss_beacon->len;
315}
316
5b9f8cd3 317static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
4bf64efd
TW
318 struct iwl_frame *frame, u8 rate)
319{
320 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
321 unsigned int frame_size;
322
323 tx_beacon_cmd = &frame->u.beacon;
324 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
325
326 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
327 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
328
329 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd
TW
330 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
331
332 BUG_ON(frame_size > MAX_MPDU_SIZE);
333 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
334
335 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
336 tx_beacon_cmd->tx.rate_n_flags =
337 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
338 else
339 tx_beacon_cmd->tx.rate_n_flags =
340 iwl_hw_set_rate_n_flags(rate, 0);
341
342 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
343 TX_CMD_FLG_TSF_MSK |
344 TX_CMD_FLG_STA_RATE_MSK;
345
346 return sizeof(*tx_beacon_cmd) + frame_size;
347}
5b9f8cd3 348static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 349{
fcab423d 350 struct iwl_frame *frame;
b481de9c
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351 unsigned int frame_size;
352 int rc;
353 u8 rate;
354
fcab423d 355 frame = iwl_get_free_frame(priv);
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356
357 if (!frame) {
15b1687c 358 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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359 "command.\n");
360 return -ENOMEM;
361 }
362
5b9f8cd3 363 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 364
5b9f8cd3 365 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 366
857485c0 367 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
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368 &frame->u.cmd[0]);
369
fcab423d 370 iwl_free_frame(priv, frame);
b481de9c
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371
372 return rc;
373}
374
7aaa1d79
SO
375static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
376{
377 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
378
379 dma_addr_t addr = get_unaligned_le32(&tb->lo);
380 if (sizeof(dma_addr_t) > sizeof(u32))
381 addr |=
382 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
383
384 return addr;
385}
386
387static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
388{
389 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
390
391 return le16_to_cpu(tb->hi_n_len) >> 4;
392}
393
394static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
395 dma_addr_t addr, u16 len)
396{
397 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
398 u16 hi_n_len = len << 4;
399
400 put_unaligned_le32(addr, &tb->lo);
401 if (sizeof(dma_addr_t) > sizeof(u32))
402 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
403
404 tb->hi_n_len = cpu_to_le16(hi_n_len);
405
406 tfd->num_tbs = idx + 1;
407}
408
409static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
410{
411 return tfd->num_tbs & 0x1f;
412}
413
414/**
415 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
416 * @priv - driver private data
417 * @txq - tx queue
418 *
419 * Does NOT advance any TFD circular buffer read/write indexes
420 * Does NOT free the TFD itself (which is within circular buffer)
421 */
422void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
423{
59606ffa 424 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
425 struct iwl_tfd *tfd;
426 struct pci_dev *dev = priv->pci_dev;
427 int index = txq->q.read_ptr;
428 int i;
429 int num_tbs;
430
431 tfd = &tfd_tmp[index];
432
433 /* Sanity check on number of chunks */
434 num_tbs = iwl_tfd_get_num_tbs(tfd);
435
436 if (num_tbs >= IWL_NUM_OF_TBS) {
437 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
438 /* @todo issue fatal error, it is quite serious situation */
439 return;
440 }
441
442 /* Unmap tx_cmd */
443 if (num_tbs)
444 pci_unmap_single(dev,
445 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
446 pci_unmap_len(&txq->cmd[index]->meta, len),
96891cee 447 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
448
449 /* Unmap chunks, if any. */
450 for (i = 1; i < num_tbs; i++) {
451 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
452 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
453
454 if (txq->txb) {
455 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
456 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
457 }
458 }
459}
460
461int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
462 struct iwl_tx_queue *txq,
463 dma_addr_t addr, u16 len,
464 u8 reset, u8 pad)
465{
466 struct iwl_queue *q;
59606ffa 467 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
468 u32 num_tbs;
469
470 q = &txq->q;
59606ffa
SO
471 tfd_tmp = (struct iwl_tfd *)txq->tfds;
472 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
473
474 if (reset)
475 memset(tfd, 0, sizeof(*tfd));
476
477 num_tbs = iwl_tfd_get_num_tbs(tfd);
478
479 /* Each TFD can point to a maximum 20 Tx buffers */
480 if (num_tbs >= IWL_NUM_OF_TBS) {
481 IWL_ERR(priv, "Error can not send more than %d chunks\n",
482 IWL_NUM_OF_TBS);
483 return -EINVAL;
484 }
485
486 BUG_ON(addr & ~DMA_BIT_MASK(36));
487 if (unlikely(addr & ~IWL_TX_DMA_MASK))
488 IWL_ERR(priv, "Unaligned address = %llx\n",
489 (unsigned long long)addr);
490
491 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
492
493 return 0;
494}
495
a8e74e27
SO
496/*
497 * Tell nic where to find circular buffer of Tx Frame Descriptors for
498 * given Tx queue, and enable the DMA channel used for that queue.
499 *
500 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
501 * channels supported in hardware.
502 */
503int iwl_hw_tx_queue_init(struct iwl_priv *priv,
504 struct iwl_tx_queue *txq)
505{
a8e74e27
SO
506 int txq_id = txq->q.id;
507
a8e74e27
SO
508 /* Circular buffer (TFD queue in DRAM) physical base address */
509 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
510 txq->q.dma_addr >> 8);
511
a8e74e27
SO
512 return 0;
513}
514
515
b481de9c
ZY
516/******************************************************************************
517 *
518 * Misc. internal state and helper functions
519 *
520 ******************************************************************************/
b481de9c 521
b481de9c 522#define MAX_UCODE_BEACON_INTERVAL 4096
b481de9c 523
3195c1f3 524static u16 iwl_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY
525{
526 u16 new_val = 0;
527 u16 beacon_factor = 0;
528
3195c1f3
TW
529 beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL)
530 / MAX_UCODE_BEACON_INTERVAL;
b481de9c
ZY
531 new_val = beacon_val / beacon_factor;
532
41d2f291
JL
533 if (!new_val)
534 new_val = MAX_UCODE_BEACON_INTERVAL;
535
3195c1f3 536 return new_val;
b481de9c
ZY
537}
538
3195c1f3 539static void iwl_setup_rxon_timing(struct iwl_priv *priv)
b481de9c 540{
3195c1f3
TW
541 u64 tsf;
542 s32 interval_tm, rem;
b481de9c
ZY
543 unsigned long flags;
544 struct ieee80211_conf *conf = NULL;
545 u16 beacon_int = 0;
546
547 conf = ieee80211_get_hw_conf(priv->hw);
548
549 spin_lock_irqsave(&priv->lock, flags);
3195c1f3 550 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
b5d7be5e 551 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
b481de9c 552
05c914fe 553 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
3195c1f3 554 beacon_int = iwl_adjust_beacon_interval(priv->beacon_int);
b481de9c
ZY
555 priv->rxon_timing.atim_window = 0;
556 } else {
57c4d7b4
JB
557 beacon_int = iwl_adjust_beacon_interval(
558 priv->vif->bss_conf.beacon_int);
3195c1f3 559
b481de9c
ZY
560 /* TODO: we need to get atim_window from upper stack
561 * for now we set to 0 */
562 priv->rxon_timing.atim_window = 0;
563 }
564
3195c1f3 565 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
b481de9c 566
3195c1f3
TW
567 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
568 interval_tm = beacon_int * 1024;
569 rem = do_div(tsf, interval_tm);
570 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
571
572 spin_unlock_irqrestore(&priv->lock, flags);
e1623446 573 IWL_DEBUG_ASSOC(priv, "beacon interval %d beacon timer %d beacon tim %d\n",
3195c1f3
TW
574 le16_to_cpu(priv->rxon_timing.beacon_interval),
575 le32_to_cpu(priv->rxon_timing.beacon_init_val),
576 le16_to_cpu(priv->rxon_timing.atim_window));
b481de9c
ZY
577}
578
b481de9c
ZY
579/******************************************************************************
580 *
581 * Generic RX handler implementations
582 *
583 ******************************************************************************/
885ba202
TW
584static void iwl_rx_reply_alive(struct iwl_priv *priv,
585 struct iwl_rx_mem_buffer *rxb)
b481de9c 586{
db11d634 587 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
885ba202 588 struct iwl_alive_resp *palive;
b481de9c
ZY
589 struct delayed_work *pwork;
590
591 palive = &pkt->u.alive_frame;
592
e1623446 593 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
594 "0x%01X 0x%01X\n",
595 palive->is_valid, palive->ver_type,
596 palive->ver_subtype);
597
598 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 599 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
600 memcpy(&priv->card_alive_init,
601 &pkt->u.alive_frame,
885ba202 602 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
603 pwork = &priv->init_alive_start;
604 } else {
e1623446 605 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 606 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 607 sizeof(struct iwl_alive_resp));
b481de9c
ZY
608 pwork = &priv->alive_start;
609 }
610
611 /* We delay the ALIVE response by 5ms to
612 * give the HW RF Kill time to activate... */
613 if (palive->is_valid == UCODE_VALID_OK)
614 queue_delayed_work(priv->workqueue, pwork,
615 msecs_to_jiffies(5));
616 else
39aadf8c 617 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
618}
619
5b9f8cd3 620static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 621{
c79dd5b5
TW
622 struct iwl_priv *priv =
623 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
624 struct sk_buff *beacon;
625
626 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 627 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
628
629 if (!beacon) {
15b1687c 630 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
631 return;
632 }
633
634 mutex_lock(&priv->mutex);
635 /* new beacon skb is allocated every time; dispose previous.*/
636 if (priv->ibss_beacon)
637 dev_kfree_skb(priv->ibss_beacon);
638
639 priv->ibss_beacon = beacon;
640 mutex_unlock(&priv->mutex);
641
5b9f8cd3 642 iwl_send_beacon_cmd(priv);
b481de9c
ZY
643}
644
4e39317d 645/**
5b9f8cd3 646 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
647 *
648 * This callback is provided in order to send a statistics request.
649 *
650 * This timer function is continually reset to execute within
651 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
652 * was received. We need to ensure we receive the statistics in order
653 * to update the temperature used for calibrating the TXPOWER.
654 */
5b9f8cd3 655static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
656{
657 struct iwl_priv *priv = (struct iwl_priv *)data;
658
659 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
660 return;
661
61780ee3
MA
662 /* dont send host command if rf-kill is on */
663 if (!iwl_is_ready_rf(priv))
664 return;
665
4e39317d
EG
666 iwl_send_statistics_request(priv, CMD_ASYNC);
667}
668
5b9f8cd3 669static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 670 struct iwl_rx_mem_buffer *rxb)
b481de9c 671{
0a6857e7 672#ifdef CONFIG_IWLWIFI_DEBUG
db11d634 673 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2aa6ab86
TW
674 struct iwl4965_beacon_notif *beacon =
675 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 676 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 677
e1623446 678 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 679 "tsf %d %d rate %d\n",
25a6572c 680 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
681 beacon->beacon_notify_hdr.failure_frame,
682 le32_to_cpu(beacon->ibss_mgr_status),
683 le32_to_cpu(beacon->high_tsf),
684 le32_to_cpu(beacon->low_tsf), rate);
685#endif
686
05c914fe 687 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
688 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
689 queue_work(priv->workqueue, &priv->beacon_update);
690}
691
b481de9c
ZY
692/* Handle notification from uCode that card's power state is changing
693 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 694static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 695 struct iwl_rx_mem_buffer *rxb)
b481de9c 696{
db11d634 697 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
698 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
699 unsigned long status = priv->status;
a8b50a0a 700 unsigned long reg_flags;
b481de9c 701
e1623446 702 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
703 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
704 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
705
706 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
707 RF_CARD_DISABLED)) {
708
3395f6e9 709 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
710 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
711
a8b50a0a
MA
712 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
713 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
714
715 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 716 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 717 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 718 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c
ZY
719 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
720
b481de9c
ZY
721 }
722
723 if (flags & RF_CARD_DISABLED) {
3395f6e9 724 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c 725 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
3395f6e9 726 iwl_read32(priv, CSR_UCODE_DRV_GP1);
a8b50a0a 727 spin_lock_irqsave(&priv->reg_lock, reg_flags);
3395f6e9
TW
728 if (!iwl_grab_nic_access(priv))
729 iwl_release_nic_access(priv);
a8b50a0a 730 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b481de9c
ZY
731 }
732 }
733
734 if (flags & HW_CARD_DISABLED)
735 set_bit(STATUS_RF_KILL_HW, &priv->status);
736 else
737 clear_bit(STATUS_RF_KILL_HW, &priv->status);
738
739
740 if (flags & SW_CARD_DISABLED)
741 set_bit(STATUS_RF_KILL_SW, &priv->status);
742 else
743 clear_bit(STATUS_RF_KILL_SW, &priv->status);
744
745 if (!(flags & RXON_CARD_DISABLED))
2a421b91 746 iwl_scan_cancel(priv);
b481de9c
ZY
747
748 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
749 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
750 (test_bit(STATUS_RF_KILL_SW, &status) !=
751 test_bit(STATUS_RF_KILL_SW, &priv->status)))
752 queue_work(priv->workqueue, &priv->rf_kill);
753 else
754 wake_up_interruptible(&priv->wait_command_queue);
755}
756
5b9f8cd3 757int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 758{
e2e3c57b 759 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 760 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
761 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
762 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
763 ~APMG_PS_CTRL_MSK_PWR_SRC);
764 } else {
765 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
766 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
767 ~APMG_PS_CTRL_MSK_PWR_SRC);
768 }
769
a8b50a0a 770 return 0;
e2e3c57b
TW
771}
772
b481de9c 773/**
5b9f8cd3 774 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
775 *
776 * Setup the RX handlers for each of the reply types sent from the uCode
777 * to the host.
778 *
779 * This function chains into the hardware specific files for them to setup
780 * any hardware specific handlers as well.
781 */
653fa4a0 782static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 783{
885ba202 784 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
785 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
786 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 787 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 788 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
789 iwl_rx_pm_debug_statistics_notif;
790 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 791
9fbab516
BC
792 /*
793 * The same handler is used for both the REPLY to a discrete
794 * statistics request from the host as well as for the periodic
795 * statistics notifications (after received beacons) from the uCode.
b481de9c 796 */
8f91aecb
EG
797 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
798 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 799
21c339bf 800 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
801 iwl_setup_rx_scan_handlers(priv);
802
37a44211 803 /* status change handler */
5b9f8cd3 804 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 805
c1354754
TW
806 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
807 iwl_rx_missed_beacon_notif;
37a44211 808 /* Rx handlers */
1781a07f
EG
809 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
810 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
811 /* block ack */
812 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 813 /* Set up hardware specific Rx handlers */
d4789efe 814 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
815}
816
b481de9c 817/**
a55360e4 818 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
819 *
820 * Uses the priv->rx_handlers callback function array to invoke
821 * the appropriate handlers, including command responses,
822 * frame-received notifications, and other notifications.
823 */
a55360e4 824void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 825{
a55360e4 826 struct iwl_rx_mem_buffer *rxb;
db11d634 827 struct iwl_rx_packet *pkt;
a55360e4 828 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
829 u32 r, i;
830 int reclaim;
831 unsigned long flags;
5c0eef96 832 u8 fill_rx = 0;
d68ab680 833 u32 count = 8;
4752c93c 834 int total_empty;
b481de9c 835
6440adb5
BC
836 /* uCode's read index (stored in shared DRAM) indicates the last Rx
837 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 838 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
839 i = rxq->read;
840
841 /* Rx interrupt, but nothing sent from uCode */
842 if (i == r)
e1623446 843 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 844
4752c93c
MA
845 /* calculate total frames need to be restock after handling RX */
846 total_empty = r - priv->rxq.write_actual;
847 if (total_empty < 0)
848 total_empty += RX_QUEUE_SIZE;
849
850 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
851 fill_rx = 1;
852
b481de9c
ZY
853 while (i != r) {
854 rxb = rxq->queue[i];
855
9fbab516 856 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
857 * then a bug has been introduced in the queue refilling
858 * routines -- catch it here */
859 BUG_ON(rxb == NULL);
860
861 rxq->queue[i] = NULL;
862
df833b1d
RC
863 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
864 priv->hw_params.rx_buf_size + 256,
865 PCI_DMA_FROMDEVICE);
db11d634 866 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
867
868 /* Reclaim a command buffer only if this packet is a response
869 * to a (driver-originated) command.
870 * If the packet (e.g. Rx frame) originated from uCode,
871 * there is no command buffer to reclaim.
872 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
873 * but apparently a few don't get set; catch them here. */
874 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
875 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 876 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 877 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 878 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
879 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
880 (pkt->hdr.cmd != REPLY_TX);
881
882 /* Based on type of command response or notification,
883 * handle those that need handling via function in
5b9f8cd3 884 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 885 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 886 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 887 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
b481de9c 888 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
a83b9141 889 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
b481de9c
ZY
890 } else {
891 /* No handling needed */
e1623446 892 IWL_DEBUG_RX(priv,
b481de9c
ZY
893 "r %d i %d No handler needed for %s, 0x%02x\n",
894 r, i, get_cmd_string(pkt->hdr.cmd),
895 pkt->hdr.cmd);
896 }
897
898 if (reclaim) {
9fbab516 899 /* Invoke any callbacks, transfer the skb to caller, and
857485c0 900 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY
901 * as we reclaim the driver command queue */
902 if (rxb && rxb->skb)
17b88929 903 iwl_tx_cmd_complete(priv, rxb);
b481de9c 904 else
39aadf8c 905 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
906 }
907
908 /* For now we just don't re-use anything. We can tweak this
909 * later to try and re-use notification packets and SKBs that
910 * fail to Rx correctly */
911 if (rxb->skb != NULL) {
912 priv->alloc_rxb_skb--;
913 dev_kfree_skb_any(rxb->skb);
914 rxb->skb = NULL;
915 }
916
b481de9c
ZY
917 spin_lock_irqsave(&rxq->lock, flags);
918 list_add_tail(&rxb->list, &priv->rxq.rx_used);
919 spin_unlock_irqrestore(&rxq->lock, flags);
920 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
921 /* If there are a lot of unused frames,
922 * restock the Rx queue so ucode wont assert. */
923 if (fill_rx) {
924 count++;
925 if (count >= 8) {
926 priv->rxq.read = i;
4752c93c 927 iwl_rx_replenish_now(priv);
5c0eef96
MA
928 count = 0;
929 }
930 }
b481de9c
ZY
931 }
932
933 /* Backtrack one entry */
934 priv->rxq.read = i;
4752c93c
MA
935 if (fill_rx)
936 iwl_rx_replenish_now(priv);
937 else
938 iwl_rx_queue_restock(priv);
a55360e4 939}
a55360e4 940
0359facc
MA
941/* call this function to flush any scheduled tasklet */
942static inline void iwl_synchronize_irq(struct iwl_priv *priv)
943{
a96a27f9 944 /* wait to make sure we flush pending tasklet*/
0359facc
MA
945 synchronize_irq(priv->pci_dev->irq);
946 tasklet_kill(&priv->irq_tasklet);
947}
948
ef850d7c 949static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
950{
951 u32 inta, handled = 0;
952 u32 inta_fh;
953 unsigned long flags;
0a6857e7 954#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
955 u32 inta_mask;
956#endif
957
958 spin_lock_irqsave(&priv->lock, flags);
959
960 /* Ack/clear/reset pending uCode interrupts.
961 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
962 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
963 inta = iwl_read32(priv, CSR_INT);
964 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
965
966 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
967 * Any new interrupts that happen after this, either while we're
968 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
969 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
970 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 971
0a6857e7 972#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 973 if (priv->debug_level & IWL_DL_ISR) {
9fbab516 974 /* just for debug */
3395f6e9 975 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 976 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
977 inta, inta_mask, inta_fh);
978 }
979#endif
980
981 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
982 * atomic, make sure that inta covers all the interrupts that
983 * we've discovered, even if FH interrupt came in just after
984 * reading CSR_INT. */
6f83eaa1 985 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 986 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 987 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
988 inta |= CSR_INT_BIT_FH_TX;
989
990 /* Now service all interrupt bits discovered above. */
991 if (inta & CSR_INT_BIT_HW_ERR) {
15b1687c 992 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
b481de9c
ZY
993
994 /* Tell the device to stop sending interrupts */
5b9f8cd3 995 iwl_disable_interrupts(priv);
b481de9c 996
a83b9141 997 priv->isr_stats.hw++;
5b9f8cd3 998 iwl_irq_handle_error(priv);
b481de9c
ZY
999
1000 handled |= CSR_INT_BIT_HW_ERR;
1001
1002 spin_unlock_irqrestore(&priv->lock, flags);
1003
1004 return;
1005 }
1006
0a6857e7 1007#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 1008 if (priv->debug_level & (IWL_DL_ISR)) {
b481de9c 1009 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1010 if (inta & CSR_INT_BIT_SCD) {
e1623446 1011 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1012 "the frame/frames.\n");
a83b9141
WYG
1013 priv->isr_stats.sch++;
1014 }
b481de9c
ZY
1015
1016 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1017 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1018 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
1019 priv->isr_stats.alive++;
1020 }
b481de9c
ZY
1021 }
1022#endif
1023 /* Safely ignore these bits for debug checks below */
25c03d8e 1024 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1025
9fbab516 1026 /* HW RF KILL switch toggled */
b481de9c
ZY
1027 if (inta & CSR_INT_BIT_RF_KILL) {
1028 int hw_rf_kill = 0;
3395f6e9 1029 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
1030 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1031 hw_rf_kill = 1;
1032
e1623446 1033 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1034 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1035
a83b9141
WYG
1036 priv->isr_stats.rfkill++;
1037
a9efa652 1038 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
1039 * the driver allows loading the ucode even if the radio
1040 * is killed. Hence update the killswitch state here. The
1041 * rfkill handler will care about restarting if needed.
a9efa652 1042 */
6cd0b1cb
HS
1043 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1044 if (hw_rf_kill)
1045 set_bit(STATUS_RF_KILL_HW, &priv->status);
1046 else
1047 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1048 queue_work(priv->workqueue, &priv->rf_kill);
edb34228 1049 }
b481de9c
ZY
1050
1051 handled |= CSR_INT_BIT_RF_KILL;
1052 }
1053
9fbab516 1054 /* Chip got too hot and stopped itself */
b481de9c 1055 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1056 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1057 priv->isr_stats.ctkill++;
b481de9c
ZY
1058 handled |= CSR_INT_BIT_CT_KILL;
1059 }
1060
1061 /* Error detected by uCode */
1062 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1063 IWL_ERR(priv, "Microcode SW error detected. "
1064 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1065 priv->isr_stats.sw++;
1066 priv->isr_stats.sw_err = inta;
5b9f8cd3 1067 iwl_irq_handle_error(priv);
b481de9c
ZY
1068 handled |= CSR_INT_BIT_SW_ERR;
1069 }
1070
1071 /* uCode wakes up after power-down sleep */
1072 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1073 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1074 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
babcebfa
TW
1075 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1076 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1077 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1078 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1079 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1080 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1081
a83b9141
WYG
1082 priv->isr_stats.wakeup++;
1083
b481de9c
ZY
1084 handled |= CSR_INT_BIT_WAKEUP;
1085 }
1086
1087 /* All uCode command responses, including Tx command responses,
1088 * Rx "responses" (frame-received notification), and other
1089 * notifications from uCode come through here*/
1090 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1091 iwl_rx_handle(priv);
a83b9141 1092 priv->isr_stats.rx++;
b481de9c
ZY
1093 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1094 }
1095
1096 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1097 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
a83b9141 1098 priv->isr_stats.tx++;
b481de9c 1099 handled |= CSR_INT_BIT_FH_TX;
dbb983b7
RR
1100 /* FH finished to write, send event */
1101 priv->ucode_write_complete = 1;
1102 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1103 }
1104
a83b9141 1105 if (inta & ~handled) {
15b1687c 1106 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1107 priv->isr_stats.unhandled++;
1108 }
b481de9c 1109
40cefda9 1110 if (inta & ~(priv->inta_mask)) {
39aadf8c 1111 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1112 inta & ~priv->inta_mask);
39aadf8c 1113 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1114 }
1115
1116 /* Re-enable all interrupts */
0359facc
MA
1117 /* only Re-enable if diabled by irq */
1118 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1119 iwl_enable_interrupts(priv);
b481de9c 1120
0a6857e7 1121#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 1122 if (priv->debug_level & (IWL_DL_ISR)) {
3395f6e9
TW
1123 inta = iwl_read32(priv, CSR_INT);
1124 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1125 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1126 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1127 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1128 }
1129#endif
1130 spin_unlock_irqrestore(&priv->lock, flags);
1131}
1132
ef850d7c
MA
1133/* tasklet for iwlagn interrupt */
1134static void iwl_irq_tasklet(struct iwl_priv *priv)
1135{
1136 u32 inta = 0;
1137 u32 handled = 0;
1138 unsigned long flags;
1139#ifdef CONFIG_IWLWIFI_DEBUG
1140 u32 inta_mask;
1141#endif
1142
1143 spin_lock_irqsave(&priv->lock, flags);
1144
1145 /* Ack/clear/reset pending uCode interrupts.
1146 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1147 */
1148 iwl_write32(priv, CSR_INT, priv->inta);
1149
1150 inta = priv->inta;
1151
1152#ifdef CONFIG_IWLWIFI_DEBUG
1153 if (priv->debug_level & IWL_DL_ISR) {
1154 /* just for debug */
1155 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1156 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1157 inta, inta_mask);
1158 }
1159#endif
1160 /* saved interrupt in inta variable now we can reset priv->inta */
1161 priv->inta = 0;
1162
1163 /* Now service all interrupt bits discovered above. */
1164 if (inta & CSR_INT_BIT_HW_ERR) {
1165 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
1166
1167 /* Tell the device to stop sending interrupts */
1168 iwl_disable_interrupts(priv);
1169
1170 priv->isr_stats.hw++;
1171 iwl_irq_handle_error(priv);
1172
1173 handled |= CSR_INT_BIT_HW_ERR;
1174
1175 spin_unlock_irqrestore(&priv->lock, flags);
1176
1177 return;
1178 }
1179
1180#ifdef CONFIG_IWLWIFI_DEBUG
1181 if (priv->debug_level & (IWL_DL_ISR)) {
1182 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1183 if (inta & CSR_INT_BIT_SCD) {
1184 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1185 "the frame/frames.\n");
1186 priv->isr_stats.sch++;
1187 }
1188
1189 /* Alive notification via Rx interrupt will do the real work */
1190 if (inta & CSR_INT_BIT_ALIVE) {
1191 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1192 priv->isr_stats.alive++;
1193 }
1194 }
1195#endif
1196 /* Safely ignore these bits for debug checks below */
1197 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1198
1199 /* HW RF KILL switch toggled */
1200 if (inta & CSR_INT_BIT_RF_KILL) {
1201 int hw_rf_kill = 0;
1202 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1203 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1204 hw_rf_kill = 1;
1205
1206 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
1207 hw_rf_kill ? "disable radio" : "enable radio");
1208
1209 priv->isr_stats.rfkill++;
1210
1211 /* driver only loads ucode once setting the interface up.
1212 * the driver allows loading the ucode even if the radio
1213 * is killed. Hence update the killswitch state here. The
1214 * rfkill handler will care about restarting if needed.
1215 */
1216 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1217 if (hw_rf_kill)
1218 set_bit(STATUS_RF_KILL_HW, &priv->status);
1219 else
1220 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1221 queue_work(priv->workqueue, &priv->rf_kill);
1222 }
1223
1224 handled |= CSR_INT_BIT_RF_KILL;
1225 }
1226
1227 /* Chip got too hot and stopped itself */
1228 if (inta & CSR_INT_BIT_CT_KILL) {
1229 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1230 priv->isr_stats.ctkill++;
1231 handled |= CSR_INT_BIT_CT_KILL;
1232 }
1233
1234 /* Error detected by uCode */
1235 if (inta & CSR_INT_BIT_SW_ERR) {
1236 IWL_ERR(priv, "Microcode SW error detected. "
1237 " Restarting 0x%X.\n", inta);
1238 priv->isr_stats.sw++;
1239 priv->isr_stats.sw_err = inta;
1240 iwl_irq_handle_error(priv);
1241 handled |= CSR_INT_BIT_SW_ERR;
1242 }
1243
1244 /* uCode wakes up after power-down sleep */
1245 if (inta & CSR_INT_BIT_WAKEUP) {
1246 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1247 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1248 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1249 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1250 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1251 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1252 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1253 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1254
1255 priv->isr_stats.wakeup++;
1256
1257 handled |= CSR_INT_BIT_WAKEUP;
1258 }
1259
1260 /* All uCode command responses, including Tx command responses,
1261 * Rx "responses" (frame-received notification), and other
1262 * notifications from uCode come through here*/
40cefda9
MA
1263 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1264 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1265 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1266 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1267 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1268 iwl_write32(priv, CSR_FH_INT_STATUS,
1269 CSR49_FH_INT_RX_MASK);
1270 }
1271 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1272 handled |= CSR_INT_BIT_RX_PERIODIC;
1273 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1274 }
1275 /* Sending RX interrupt require many steps to be done in the
1276 * the device:
1277 * 1- write interrupt to current index in ICT table.
1278 * 2- dma RX frame.
1279 * 3- update RX shared data to indicate last write index.
1280 * 4- send interrupt.
1281 * This could lead to RX race, driver could receive RX interrupt
1282 * but the shared data changes does not reflect this.
1283 * this could lead to RX race, RX periodic will solve this race
1284 */
1285 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1286 CSR_INT_PERIODIC_DIS);
ef850d7c 1287 iwl_rx_handle(priv);
40cefda9
MA
1288 /* Only set RX periodic if real RX is received. */
1289 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1290 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1291 CSR_INT_PERIODIC_ENA);
1292
ef850d7c 1293 priv->isr_stats.rx++;
ef850d7c
MA
1294 }
1295
1296 if (inta & CSR_INT_BIT_FH_TX) {
1297 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1298 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
1299 priv->isr_stats.tx++;
1300 handled |= CSR_INT_BIT_FH_TX;
1301 /* FH finished to write, send event */
1302 priv->ucode_write_complete = 1;
1303 wake_up_interruptible(&priv->wait_command_queue);
1304 }
1305
1306 if (inta & ~handled) {
1307 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1308 priv->isr_stats.unhandled++;
1309 }
1310
40cefda9 1311 if (inta & ~(priv->inta_mask)) {
ef850d7c 1312 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1313 inta & ~priv->inta_mask);
ef850d7c
MA
1314 }
1315
1316
1317 /* Re-enable all interrupts */
1318 /* only Re-enable if diabled by irq */
1319 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1320 iwl_enable_interrupts(priv);
1321
1322 spin_unlock_irqrestore(&priv->lock, flags);
1323
1324}
1325
a83b9141 1326
b481de9c
ZY
1327/******************************************************************************
1328 *
1329 * uCode download functions
1330 *
1331 ******************************************************************************/
1332
5b9f8cd3 1333static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1334{
98c92211
TW
1335 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1336 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1337 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1338 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1339 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1340 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1341}
1342
5b9f8cd3 1343static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1344{
1345 /* Remove all resets to allow NIC to operate */
1346 iwl_write32(priv, CSR_RESET, 0);
1347}
1348
1349
b481de9c 1350/**
5b9f8cd3 1351 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1352 *
1353 * Copy into buffers for card to fetch via bus-mastering
1354 */
5b9f8cd3 1355static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1356{
14b3d338 1357 struct iwl_ucode *ucode;
a0987a8d 1358 int ret = -EINVAL, index;
b481de9c 1359 const struct firmware *ucode_raw;
a0987a8d
RC
1360 const char *name_pre = priv->cfg->fw_name_pre;
1361 const unsigned int api_max = priv->cfg->ucode_api_max;
1362 const unsigned int api_min = priv->cfg->ucode_api_min;
1363 char buf[25];
b481de9c
ZY
1364 u8 *src;
1365 size_t len;
a0987a8d 1366 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
1367
1368 /* Ask kernel firmware_class module to get the boot firmware off disk.
1369 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1370 for (index = api_max; index >= api_min; index--) {
1371 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1372 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1373 if (ret < 0) {
15b1687c 1374 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1375 buf, ret);
1376 if (ret == -ENOENT)
1377 continue;
1378 else
1379 goto error;
1380 } else {
1381 if (index < api_max)
15b1687c
WT
1382 IWL_ERR(priv, "Loaded firmware %s, "
1383 "which is deprecated. "
1384 "Please use API v%u instead.\n",
a0987a8d 1385 buf, api_max);
15b1687c 1386
e1623446 1387 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1388 buf, ucode_raw->size);
1389 break;
1390 }
b481de9c
ZY
1391 }
1392
a0987a8d
RC
1393 if (ret < 0)
1394 goto error;
b481de9c
ZY
1395
1396 /* Make sure that we got at least our header! */
1397 if (ucode_raw->size < sizeof(*ucode)) {
15b1687c 1398 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1399 ret = -EINVAL;
b481de9c
ZY
1400 goto err_release;
1401 }
1402
1403 /* Data from ucode file: header followed by uCode images */
1404 ucode = (void *)ucode_raw->data;
1405
c02b3acd 1406 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1407 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY
1408 inst_size = le32_to_cpu(ucode->inst_size);
1409 data_size = le32_to_cpu(ucode->data_size);
1410 init_size = le32_to_cpu(ucode->init_size);
1411 init_data_size = le32_to_cpu(ucode->init_data_size);
1412 boot_size = le32_to_cpu(ucode->boot_size);
1413
a0987a8d
RC
1414 /* api_ver should match the api version forming part of the
1415 * firmware filename ... but we don't check for that and only rely
877d0310 1416 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1417
1418 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1419 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1420 "Driver supports v%u, firmware is v%u.\n",
1421 api_max, api_ver);
1422 priv->ucode_ver = 0;
1423 ret = -EINVAL;
1424 goto err_release;
1425 }
1426 if (api_ver != api_max)
978785a3 1427 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1428 "got v%u. New firmware can be obtained "
1429 "from http://www.intellinuxwireless.org.\n",
1430 api_max, api_ver);
1431
978785a3
TW
1432 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1433 IWL_UCODE_MAJOR(priv->ucode_ver),
1434 IWL_UCODE_MINOR(priv->ucode_ver),
1435 IWL_UCODE_API(priv->ucode_ver),
1436 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1437
e1623446 1438 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1439 priv->ucode_ver);
e1623446 1440 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1441 inst_size);
e1623446 1442 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1443 data_size);
e1623446 1444 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1445 init_size);
e1623446 1446 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1447 init_data_size);
e1623446 1448 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1449 boot_size);
1450
1451 /* Verify size of file vs. image size info in file's header */
1452 if (ucode_raw->size < sizeof(*ucode) +
1453 inst_size + data_size + init_size +
1454 init_data_size + boot_size) {
1455
e1623446 1456 IWL_DEBUG_INFO(priv, "uCode file size %d too small\n",
b481de9c 1457 (int)ucode_raw->size);
90e759d1 1458 ret = -EINVAL;
b481de9c
ZY
1459 goto err_release;
1460 }
1461
1462 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1463 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1464 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1465 inst_size);
1466 ret = -EINVAL;
b481de9c
ZY
1467 goto err_release;
1468 }
1469
099b40b7 1470 if (data_size > priv->hw_params.max_data_size) {
e1623446 1471 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1472 data_size);
1473 ret = -EINVAL;
b481de9c
ZY
1474 goto err_release;
1475 }
099b40b7 1476 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1477 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1478 init_size);
90e759d1 1479 ret = -EINVAL;
b481de9c
ZY
1480 goto err_release;
1481 }
099b40b7 1482 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1483 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1484 init_data_size);
1485 ret = -EINVAL;
b481de9c
ZY
1486 goto err_release;
1487 }
099b40b7 1488 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1489 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1490 boot_size);
90e759d1 1491 ret = -EINVAL;
b481de9c
ZY
1492 goto err_release;
1493 }
1494
1495 /* Allocate ucode buffers for card's bus-master loading ... */
1496
1497 /* Runtime instructions and 2 copies of data:
1498 * 1) unmodified from disk
1499 * 2) backup cache for save/restore during power-downs */
1500 priv->ucode_code.len = inst_size;
98c92211 1501 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1502
1503 priv->ucode_data.len = data_size;
98c92211 1504 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1505
1506 priv->ucode_data_backup.len = data_size;
98c92211 1507 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1508
1f304e4e
ZY
1509 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1510 !priv->ucode_data_backup.v_addr)
1511 goto err_pci_alloc;
1512
b481de9c 1513 /* Initialization instructions and data */
90e759d1
TW
1514 if (init_size && init_data_size) {
1515 priv->ucode_init.len = init_size;
98c92211 1516 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1517
1518 priv->ucode_init_data.len = init_data_size;
98c92211 1519 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1520
1521 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1522 goto err_pci_alloc;
1523 }
b481de9c
ZY
1524
1525 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1526 if (boot_size) {
1527 priv->ucode_boot.len = boot_size;
98c92211 1528 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1529
90e759d1
TW
1530 if (!priv->ucode_boot.v_addr)
1531 goto err_pci_alloc;
1532 }
b481de9c
ZY
1533
1534 /* Copy images into buffers for card's bus-master reads ... */
1535
1536 /* Runtime instructions (first block of data in file) */
1537 src = &ucode->data[0];
1538 len = priv->ucode_code.len;
e1623446 1539 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1540 memcpy(priv->ucode_code.v_addr, src, len);
e1623446 1541 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1542 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1543
1544 /* Runtime data (2nd block)
5b9f8cd3 1545 * NOTE: Copy into backup buffer will be done in iwl_up() */
b481de9c
ZY
1546 src = &ucode->data[inst_size];
1547 len = priv->ucode_data.len;
e1623446 1548 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1549 memcpy(priv->ucode_data.v_addr, src, len);
1550 memcpy(priv->ucode_data_backup.v_addr, src, len);
1551
1552 /* Initialization instructions (3rd block) */
1553 if (init_size) {
1554 src = &ucode->data[inst_size + data_size];
1555 len = priv->ucode_init.len;
e1623446 1556 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1557 len);
b481de9c
ZY
1558 memcpy(priv->ucode_init.v_addr, src, len);
1559 }
1560
1561 /* Initialization data (4th block) */
1562 if (init_data_size) {
1563 src = &ucode->data[inst_size + data_size + init_size];
1564 len = priv->ucode_init_data.len;
e1623446 1565 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1566 len);
b481de9c
ZY
1567 memcpy(priv->ucode_init_data.v_addr, src, len);
1568 }
1569
1570 /* Bootstrap instructions (5th block) */
1571 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
1572 len = priv->ucode_boot.len;
e1623446 1573 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1574 memcpy(priv->ucode_boot.v_addr, src, len);
1575
1576 /* We have our copies now, allow OS release its copies */
1577 release_firmware(ucode_raw);
1578 return 0;
1579
1580 err_pci_alloc:
15b1687c 1581 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1582 ret = -ENOMEM;
5b9f8cd3 1583 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1584
1585 err_release:
1586 release_firmware(ucode_raw);
1587
1588 error:
90e759d1 1589 return ret;
b481de9c
ZY
1590}
1591
b481de9c 1592/**
4a4a9e81 1593 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1594 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1595 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1596 */
4a4a9e81 1597static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1598{
57aab75a 1599 int ret = 0;
b481de9c 1600
e1623446 1601 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1602
1603 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1604 /* We had an error bringing up the hardware, so take it
1605 * all the way back down so we can try again */
e1623446 1606 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1607 goto restart;
1608 }
1609
1610 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1611 * This is a paranoid check, because we would not have gotten the
1612 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1613 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1614 /* Runtime instruction load was bad;
1615 * take it all the way back down so we can try again */
e1623446 1616 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1617 goto restart;
1618 }
1619
e11bc028 1620 priv->cfg->ops->smgmt->clear_station_table(priv);
57aab75a
TW
1621 ret = priv->cfg->ops->lib->alive_notify(priv);
1622 if (ret) {
39aadf8c
WT
1623 IWL_WARN(priv,
1624 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1625 goto restart;
1626 }
1627
5b9f8cd3 1628 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1629 set_bit(STATUS_ALIVE, &priv->status);
1630
fee1247a 1631 if (iwl_is_rfkill(priv))
b481de9c
ZY
1632 return;
1633
36d6825b 1634 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1635
1636 priv->active_rate = priv->rates_mask;
1637 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1638
3109ece1 1639 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1640 struct iwl_rxon_cmd *active_rxon =
1641 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1642 /* apply any changes in staging */
1643 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1644 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1645 } else {
1646 /* Initialize our rx_config data */
5b9f8cd3 1647 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
1648
1649 if (priv->cfg->ops->hcmd->set_rxon_chain)
1650 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1651
b481de9c
ZY
1652 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1653 }
1654
9fbab516 1655 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1656 iwl_send_bt_config(priv);
b481de9c 1657
4a4a9e81
TW
1658 iwl_reset_run_time_calib(priv);
1659
b481de9c 1660 /* Configure the adapter for unassociated operation */
e0158e61 1661 iwlcore_commit_rxon(priv);
b481de9c
ZY
1662
1663 /* At this point, the NIC is initialized and operational */
47f4a587 1664 iwl_rf_kill_ct_config(priv);
5a66926a 1665
fe00b5a5
RC
1666 iwl_leds_register(priv);
1667
e1623446 1668 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1669 set_bit(STATUS_READY, &priv->status);
5a66926a 1670 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1671
58d0f361 1672 iwl_power_update_mode(priv, 1);
c46fbefa 1673
ada17513
MA
1674 /* reassociate for ADHOC mode */
1675 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1676 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1677 priv->vif);
1678 if (beacon)
1679 iwl_mac_beacon_update(priv->hw, beacon);
1680 }
1681
1682
c46fbefa 1683 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1684 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1685
b481de9c
ZY
1686 return;
1687
1688 restart:
1689 queue_work(priv->workqueue, &priv->restart);
1690}
1691
4e39317d 1692static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1693
5b9f8cd3 1694static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1695{
1696 unsigned long flags;
1697 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1698
e1623446 1699 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1700
b481de9c
ZY
1701 if (!exit_pending)
1702 set_bit(STATUS_EXIT_PENDING, &priv->status);
1703
ab53d8af
MA
1704 iwl_leds_unregister(priv);
1705
e11bc028 1706 priv->cfg->ops->smgmt->clear_station_table(priv);
b481de9c
ZY
1707
1708 /* Unblock any waiting calls */
1709 wake_up_interruptible_all(&priv->wait_command_queue);
1710
b481de9c
ZY
1711 /* Wipe out the EXIT_PENDING status bit if we are not actually
1712 * exiting the module */
1713 if (!exit_pending)
1714 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1715
1716 /* stop and reset the on-board processor */
3395f6e9 1717 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
1718
1719 /* tell the device to stop sending interrupts */
0359facc 1720 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1721 iwl_disable_interrupts(priv);
0359facc
MA
1722 spin_unlock_irqrestore(&priv->lock, flags);
1723 iwl_synchronize_irq(priv);
b481de9c
ZY
1724
1725 if (priv->mac80211_registered)
1726 ieee80211_stop_queues(priv->hw);
1727
5b9f8cd3 1728 /* If we have not previously called iwl_init() then
6da3a13e 1729 * clear all bits but the RF Kill bits and return */
fee1247a 1730 if (!iwl_is_init(priv)) {
b481de9c
ZY
1731 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1732 STATUS_RF_KILL_HW |
1733 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
1734 STATUS_RF_KILL_SW |
9788864e
RC
1735 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1736 STATUS_GEO_CONFIGURED |
052ec3f1
MA
1737 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1738 STATUS_EXIT_PENDING;
b481de9c
ZY
1739 goto exit;
1740 }
1741
6da3a13e
WYG
1742 /* ...otherwise clear out all the status bits but the RF Kill
1743 * bits and continue taking the NIC down. */
b481de9c
ZY
1744 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1745 STATUS_RF_KILL_HW |
1746 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
1747 STATUS_RF_KILL_SW |
9788864e
RC
1748 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1749 STATUS_GEO_CONFIGURED |
b481de9c 1750 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
1751 STATUS_FW_ERROR |
1752 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1753 STATUS_EXIT_PENDING;
b481de9c 1754
ef850d7c
MA
1755 /* device going down, Stop using ICT table */
1756 iwl_disable_ict(priv);
b481de9c 1757 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1758 iwl_clear_bit(priv, CSR_GP_CNTRL,
9fbab516 1759 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
1760 spin_unlock_irqrestore(&priv->lock, flags);
1761
da1bc453 1762 iwl_txq_ctx_stop(priv);
b3bbacb7 1763 iwl_rxq_stop(priv);
b481de9c 1764
a8b50a0a
MA
1765 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1766 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
1767
1768 udelay(5);
1769
7f066108 1770 /* FIXME: apm_ops.suspend(priv) */
6da3a13e 1771 if (exit_pending)
d535311e
GG
1772 priv->cfg->ops->lib->apm_ops.stop(priv);
1773 else
1774 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 1775 exit:
885ba202 1776 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
1777
1778 if (priv->ibss_beacon)
1779 dev_kfree_skb(priv->ibss_beacon);
1780 priv->ibss_beacon = NULL;
1781
1782 /* clear out any free frames */
fcab423d 1783 iwl_clear_free_frames(priv);
b481de9c
ZY
1784}
1785
5b9f8cd3 1786static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1787{
1788 mutex_lock(&priv->mutex);
5b9f8cd3 1789 __iwl_down(priv);
b481de9c 1790 mutex_unlock(&priv->mutex);
b24d22b1 1791
4e39317d 1792 iwl_cancel_deferred_work(priv);
b481de9c
ZY
1793}
1794
086ed117
MA
1795#define HW_READY_TIMEOUT (50)
1796
1797static int iwl_set_hw_ready(struct iwl_priv *priv)
1798{
1799 int ret = 0;
1800
1801 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1802 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1803
1804 /* See if we got it */
1805 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1806 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1807 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1808 HW_READY_TIMEOUT);
1809 if (ret != -ETIMEDOUT)
1810 priv->hw_ready = true;
1811 else
1812 priv->hw_ready = false;
1813
1814 IWL_DEBUG_INFO(priv, "hardware %s\n",
1815 (priv->hw_ready == 1) ? "ready" : "not ready");
1816 return ret;
1817}
1818
1819static int iwl_prepare_card_hw(struct iwl_priv *priv)
1820{
1821 int ret = 0;
1822
1823 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
1824
1825 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1826 CSR_HW_IF_CONFIG_REG_PREPARE);
1827
1828 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1829 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
1830 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
1831
1832 if (ret != -ETIMEDOUT)
1833 iwl_set_hw_ready(priv);
1834
1835 return ret;
1836}
1837
b481de9c
ZY
1838#define MAX_HW_RESTARTS 5
1839
5b9f8cd3 1840static int __iwl_up(struct iwl_priv *priv)
b481de9c 1841{
57aab75a
TW
1842 int i;
1843 int ret;
b481de9c
ZY
1844
1845 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 1846 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
1847 return -EIO;
1848 }
1849
e903fbd4 1850 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 1851 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
1852 return -EIO;
1853 }
1854
086ed117
MA
1855 iwl_prepare_card_hw(priv);
1856
1857 if (!priv->hw_ready) {
1858 IWL_WARN(priv, "Exit HW not ready\n");
1859 return -EIO;
1860 }
1861
e655b9f0 1862 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 1863 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 1864 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1865 else
e655b9f0 1866 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1867
c1842d61 1868 if (iwl_is_rfkill(priv)) {
5b9f8cd3 1869 iwl_enable_interrupts(priv);
39aadf8c 1870 IWL_WARN(priv, "Radio disabled by %s RF Kill switch\n",
3bff19c2 1871 test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW");
c1842d61 1872 return 0;
b481de9c
ZY
1873 }
1874
3395f6e9 1875 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 1876
1053d35f 1877 ret = iwl_hw_nic_init(priv);
57aab75a 1878 if (ret) {
15b1687c 1879 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 1880 return ret;
b481de9c
ZY
1881 }
1882
1883 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
1884 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1885 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
1886 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1887
1888 /* clear (again), then enable host interrupts */
3395f6e9 1889 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ef850d7c
MA
1890 /* enable dram interrupt */
1891 iwl_reset_ict(priv);
5b9f8cd3 1892 iwl_enable_interrupts(priv);
b481de9c
ZY
1893
1894 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
1895 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1896 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
1897
1898 /* Copy original ucode data image from disk into backup cache.
1899 * This will be used to initialize the on-board processor's
1900 * data SRAM for a clean start when the runtime program first loads. */
1901 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 1902 priv->ucode_data.len);
b481de9c 1903
b481de9c
ZY
1904 for (i = 0; i < MAX_HW_RESTARTS; i++) {
1905
e11bc028 1906 priv->cfg->ops->smgmt->clear_station_table(priv);
b481de9c
ZY
1907
1908 /* load bootstrap state machine,
1909 * load bootstrap program into processor's memory,
1910 * prepare to load the "initialize" uCode */
57aab75a 1911 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 1912
57aab75a 1913 if (ret) {
15b1687c
WT
1914 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
1915 ret);
b481de9c
ZY
1916 continue;
1917 }
1918
1919 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 1920 iwl_nic_start(priv);
b481de9c 1921
e1623446 1922 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
1923
1924 return 0;
1925 }
1926
1927 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 1928 __iwl_down(priv);
64e72c3e 1929 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
1930
1931 /* tried to restart and config the device for as long as our
1932 * patience could withstand */
15b1687c 1933 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
1934 return -EIO;
1935}
1936
1937
1938/*****************************************************************************
1939 *
1940 * Workqueue callbacks
1941 *
1942 *****************************************************************************/
1943
4a4a9e81 1944static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 1945{
c79dd5b5
TW
1946 struct iwl_priv *priv =
1947 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
1948
1949 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1950 return;
1951
1952 mutex_lock(&priv->mutex);
f3ccc08c 1953 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
1954 mutex_unlock(&priv->mutex);
1955}
1956
4a4a9e81 1957static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 1958{
c79dd5b5
TW
1959 struct iwl_priv *priv =
1960 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
1961
1962 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1963 return;
1964
1965 mutex_lock(&priv->mutex);
4a4a9e81 1966 iwl_alive_start(priv);
b481de9c
ZY
1967 mutex_unlock(&priv->mutex);
1968}
1969
16e727e8
EG
1970static void iwl_bg_run_time_calib_work(struct work_struct *work)
1971{
1972 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1973 run_time_calib_work);
1974
1975 mutex_lock(&priv->mutex);
1976
1977 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1978 test_bit(STATUS_SCANNING, &priv->status)) {
1979 mutex_unlock(&priv->mutex);
1980 return;
1981 }
1982
1983 if (priv->start_calib) {
1984 iwl_chain_noise_calibration(priv, &priv->statistics);
1985
1986 iwl_sensitivity_calibration(priv, &priv->statistics);
1987 }
1988
1989 mutex_unlock(&priv->mutex);
1990 return;
1991}
1992
5b9f8cd3 1993static void iwl_bg_up(struct work_struct *data)
b481de9c 1994{
c79dd5b5 1995 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
1996
1997 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1998 return;
1999
2000 mutex_lock(&priv->mutex);
5b9f8cd3 2001 __iwl_up(priv);
b481de9c 2002 mutex_unlock(&priv->mutex);
80fcc9e2 2003 iwl_rfkill_set_hw_state(priv);
b481de9c
ZY
2004}
2005
5b9f8cd3 2006static void iwl_bg_restart(struct work_struct *data)
b481de9c 2007{
c79dd5b5 2008 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2009
2010 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2011 return;
2012
19cc1087
JB
2013 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2014 mutex_lock(&priv->mutex);
2015 priv->vif = NULL;
2016 priv->is_open = 0;
2017 mutex_unlock(&priv->mutex);
2018 iwl_down(priv);
2019 ieee80211_restart_hw(priv->hw);
2020 } else {
2021 iwl_down(priv);
2022 queue_work(priv->workqueue, &priv->up);
2023 }
b481de9c
ZY
2024}
2025
5b9f8cd3 2026static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2027{
c79dd5b5
TW
2028 struct iwl_priv *priv =
2029 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2030
2031 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2032 return;
2033
2034 mutex_lock(&priv->mutex);
a55360e4 2035 iwl_rx_replenish(priv);
b481de9c
ZY
2036 mutex_unlock(&priv->mutex);
2037}
2038
7878a5a4
MA
2039#define IWL_DELAY_NEXT_SCAN (HZ*2)
2040
5bbe233b 2041void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2042{
b481de9c 2043 struct ieee80211_conf *conf = NULL;
857485c0 2044 int ret = 0;
1ff50bda 2045 unsigned long flags;
b481de9c 2046
05c914fe 2047 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2048 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2049 return;
2050 }
2051
e1623446 2052 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2053 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2054
2055
2056 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2057 return;
2058
b481de9c 2059
508e32e1 2060 if (!priv->vif || !priv->is_open)
948c171c 2061 return;
508e32e1 2062
2a421b91 2063 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2064
b481de9c
ZY
2065 conf = ieee80211_get_hw_conf(priv->hw);
2066
2067 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2068 iwlcore_commit_rxon(priv);
b481de9c 2069
3195c1f3 2070 iwl_setup_rxon_timing(priv);
857485c0 2071 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2072 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2073 if (ret)
39aadf8c 2074 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2075 "Attempting to continue.\n");
2076
2077 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2078
42eb7c64 2079 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2080
45823531
AK
2081 if (priv->cfg->ops->hcmd->set_rxon_chain)
2082 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2083
b481de9c
ZY
2084 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2085
e1623446 2086 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2087 priv->assoc_id, priv->beacon_int);
2088
2089 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2090 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2091 else
2092 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2093
2094 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2095 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2096 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2097 else
2098 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2099
05c914fe 2100 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2101 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2102
2103 }
2104
e0158e61 2105 iwlcore_commit_rxon(priv);
b481de9c
ZY
2106
2107 switch (priv->iw_mode) {
05c914fe 2108 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2109 break;
2110
05c914fe 2111 case NL80211_IFTYPE_ADHOC:
b481de9c 2112
c46fbefa
AK
2113 /* assume default assoc id */
2114 priv->assoc_id = 1;
b481de9c 2115
4f40e4d9 2116 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2117 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2118
2119 break;
2120
2121 default:
15b1687c 2122 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2123 __func__, priv->iw_mode);
b481de9c
ZY
2124 break;
2125 }
2126
05c914fe 2127 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2128 priv->assoc_station_added = 1;
2129
1ff50bda
EG
2130 spin_lock_irqsave(&priv->lock, flags);
2131 iwl_activate_qos(priv, 0);
2132 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2133
04816448
GE
2134 /* the chain noise calibration will enabled PM upon completion
2135 * If chain noise has already been run, then we need to enable
2136 * power management here */
2137 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
7af2c460 2138 iwl_power_update_mode(priv, 0);
c90a74ba
EG
2139
2140 /* Enable Rx differential gain and sensitivity calibrations */
2141 iwl_chain_noise_reset(priv);
2142 priv->start_calib = 1;
2143
508e32e1
RC
2144}
2145
b481de9c
ZY
2146/*****************************************************************************
2147 *
2148 * mac80211 entry point functions
2149 *
2150 *****************************************************************************/
2151
154b25ce 2152#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2153
5b9f8cd3 2154static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2155{
c79dd5b5 2156 struct iwl_priv *priv = hw->priv;
5a66926a 2157 int ret;
b481de9c 2158
e1623446 2159 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2160
2161 /* we should be verifying the device is ready to be opened */
2162 mutex_lock(&priv->mutex);
2163
c1adf9fb 2164 memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd));
5a66926a
ZY
2165 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2166 * ucode filename and max sizes are card-specific. */
b481de9c 2167
5a66926a 2168 if (!priv->ucode_code.len) {
5b9f8cd3 2169 ret = iwl_read_ucode(priv);
5a66926a 2170 if (ret) {
15b1687c 2171 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2172 mutex_unlock(&priv->mutex);
6cd0b1cb 2173 return ret;
5a66926a
ZY
2174 }
2175 }
b481de9c 2176
5b9f8cd3 2177 ret = __iwl_up(priv);
5a66926a 2178
b481de9c 2179 mutex_unlock(&priv->mutex);
5a66926a 2180
80fcc9e2
AG
2181 iwl_rfkill_set_hw_state(priv);
2182
e655b9f0 2183 if (ret)
6cd0b1cb 2184 return ret;
e655b9f0 2185
c1842d61
TW
2186 if (iwl_is_rfkill(priv))
2187 goto out;
2188
e1623446 2189 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2190
fe9b6b72 2191 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2192 * mac80211 will not be run successfully. */
154b25ce
EG
2193 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2194 test_bit(STATUS_READY, &priv->status),
2195 UCODE_READY_TIMEOUT);
2196 if (!ret) {
2197 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2198 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2199 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2200 return -ETIMEDOUT;
5a66926a 2201 }
fe9b6b72 2202 }
0a078ffa 2203
c1842d61 2204out:
0a078ffa 2205 priv->is_open = 1;
e1623446 2206 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2207 return 0;
2208}
2209
5b9f8cd3 2210static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2211{
c79dd5b5 2212 struct iwl_priv *priv = hw->priv;
b481de9c 2213
e1623446 2214 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2215
19cc1087 2216 if (!priv->is_open)
e655b9f0 2217 return;
e655b9f0 2218
b481de9c 2219 priv->is_open = 0;
5a66926a 2220
fee1247a 2221 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
2222 /* stop mac, cancel any scan request and clear
2223 * RXON_FILTER_ASSOC_MSK BIT
2224 */
5a66926a 2225 mutex_lock(&priv->mutex);
2a421b91 2226 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2227 mutex_unlock(&priv->mutex);
fde3571f
MA
2228 }
2229
5b9f8cd3 2230 iwl_down(priv);
5a66926a
ZY
2231
2232 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2233
2234 /* enable interrupts again in order to receive rfkill changes */
2235 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2236 iwl_enable_interrupts(priv);
948c171c 2237
e1623446 2238 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2239}
2240
5b9f8cd3 2241static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2242{
c79dd5b5 2243 struct iwl_priv *priv = hw->priv;
b481de9c 2244
e1623446 2245 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2246
e1623446 2247 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2248 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2249
e039fa4a 2250 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2251 dev_kfree_skb_any(skb);
2252
e1623446 2253 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2254 return NETDEV_TX_OK;
b481de9c
ZY
2255}
2256
60690a6a 2257void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2258{
857485c0 2259 int ret = 0;
1ff50bda 2260 unsigned long flags;
b481de9c 2261
d986bcd1 2262 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2263 return;
2264
2265 /* The following should be done only at AP bring up */
3195c1f3 2266 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2267
2268 /* RXON - unassoc (to set timing command) */
2269 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2270 iwlcore_commit_rxon(priv);
b481de9c
ZY
2271
2272 /* RXON Timing */
3195c1f3 2273 iwl_setup_rxon_timing(priv);
857485c0 2274 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2275 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2276 if (ret)
39aadf8c 2277 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2278 "Attempting to continue.\n");
2279
45823531
AK
2280 if (priv->cfg->ops->hcmd->set_rxon_chain)
2281 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2282
2283 /* FIXME: what should be the assoc_id for AP? */
2284 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2285 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2286 priv->staging_rxon.flags |=
2287 RXON_FLG_SHORT_PREAMBLE_MSK;
2288 else
2289 priv->staging_rxon.flags &=
2290 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2291
2292 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2293 if (priv->assoc_capability &
2294 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2295 priv->staging_rxon.flags |=
2296 RXON_FLG_SHORT_SLOT_MSK;
2297 else
2298 priv->staging_rxon.flags &=
2299 ~RXON_FLG_SHORT_SLOT_MSK;
2300
05c914fe 2301 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2302 priv->staging_rxon.flags &=
2303 ~RXON_FLG_SHORT_SLOT_MSK;
2304 }
2305 /* restore RXON assoc */
2306 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2307 iwlcore_commit_rxon(priv);
1ff50bda
EG
2308 spin_lock_irqsave(&priv->lock, flags);
2309 iwl_activate_qos(priv, 1);
2310 spin_unlock_irqrestore(&priv->lock, flags);
4f40e4d9 2311 iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
e1493deb 2312 }
5b9f8cd3 2313 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2314
2315 /* FIXME - we need to add code here to detect a totally new
2316 * configuration, reset the AP, unassoc, rxon timing, assoc,
2317 * clear sta table, add BCAST sta... */
2318}
2319
5b9f8cd3 2320static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2321 struct ieee80211_key_conf *keyconf, const u8 *addr,
2322 u32 iv32, u16 *phase1key)
2323{
ab885f8c 2324
9f58671e 2325 struct iwl_priv *priv = hw->priv;
e1623446 2326 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2327
9f58671e 2328 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2329
e1623446 2330 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2331}
2332
5b9f8cd3 2333static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2334 struct ieee80211_vif *vif,
2335 struct ieee80211_sta *sta,
b481de9c
ZY
2336 struct ieee80211_key_conf *key)
2337{
c79dd5b5 2338 struct iwl_priv *priv = hw->priv;
42986796
WT
2339 const u8 *addr;
2340 int ret;
2341 u8 sta_id;
2342 bool is_default_wep_key = false;
b481de9c 2343
e1623446 2344 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2345
099b40b7 2346 if (priv->hw_params.sw_crypto) {
e1623446 2347 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2348 return -EOPNOTSUPP;
2349 }
42986796 2350 addr = sta ? sta->addr : iwl_bcast_addr;
e11bc028 2351 sta_id = priv->cfg->ops->smgmt->find_station(priv, addr);
6974e363 2352 if (sta_id == IWL_INVALID_STATION) {
e1623446 2353 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2354 addr);
6974e363 2355 return -EINVAL;
b481de9c 2356
deb09c43 2357 }
b481de9c 2358
6974e363 2359 mutex_lock(&priv->mutex);
2a421b91 2360 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2361 mutex_unlock(&priv->mutex);
2362
2363 /* If we are getting WEP group key and we didn't receive any key mapping
2364 * so far, we are in legacy wep mode (group key only), otherwise we are
2365 * in 1X mode.
2366 * In legacy wep mode, we use another host command to the uCode */
5425e490 2367 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2368 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2369 if (cmd == SET_KEY)
2370 is_default_wep_key = !priv->key_mapping_key;
2371 else
ccc038ab
EG
2372 is_default_wep_key =
2373 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2374 }
052c4b9f 2375
b481de9c 2376 switch (cmd) {
deb09c43 2377 case SET_KEY:
6974e363
EG
2378 if (is_default_wep_key)
2379 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2380 else
7480513f 2381 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2382
e1623446 2383 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2384 break;
2385 case DISABLE_KEY:
6974e363
EG
2386 if (is_default_wep_key)
2387 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2388 else
3ec47732 2389 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2390
e1623446 2391 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2392 break;
2393 default:
deb09c43 2394 ret = -EINVAL;
b481de9c
ZY
2395 }
2396
e1623446 2397 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2398
deb09c43 2399 return ret;
b481de9c
ZY
2400}
2401
5b9f8cd3 2402static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
d783b061 2403 enum ieee80211_ampdu_mlme_action action,
17741cdc 2404 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2405{
2406 struct iwl_priv *priv = hw->priv;
5c2207c6 2407 int ret;
d783b061 2408
e1623446 2409 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2410 sta->addr, tid);
d783b061
TW
2411
2412 if (!(priv->cfg->sku & IWL_SKU_N))
2413 return -EACCES;
2414
2415 switch (action) {
2416 case IEEE80211_AMPDU_RX_START:
e1623446 2417 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2418 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2419 case IEEE80211_AMPDU_RX_STOP:
e1623446 2420 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2421 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2422 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2423 return 0;
2424 else
2425 return ret;
d783b061 2426 case IEEE80211_AMPDU_TX_START:
e1623446 2427 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2428 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2429 case IEEE80211_AMPDU_TX_STOP:
e1623446 2430 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2431 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2432 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2433 return 0;
2434 else
2435 return ret;
d783b061 2436 default:
e1623446 2437 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2438 return -EINVAL;
2439 break;
2440 }
2441 return 0;
2442}
9f58671e 2443
5b9f8cd3 2444static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2445 struct ieee80211_low_level_stats *stats)
2446{
bf403db8
EK
2447 struct iwl_priv *priv = hw->priv;
2448
2449 priv = hw->priv;
e1623446
TW
2450 IWL_DEBUG_MAC80211(priv, "enter\n");
2451 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2452
2453 return 0;
2454}
2455
b481de9c
ZY
2456/*****************************************************************************
2457 *
2458 * sysfs attributes
2459 *
2460 *****************************************************************************/
2461
0a6857e7 2462#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2463
2464/*
2465 * The following adds a new attribute to the sysfs representation
c3a739fa 2466 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2467 * used for controlling the debug level.
2468 *
2469 * See the level definitions in iwl for details.
2470 */
2471
8cf769c6
EK
2472static ssize_t show_debug_level(struct device *d,
2473 struct device_attribute *attr, char *buf)
b481de9c 2474{
928841b1 2475 struct iwl_priv *priv = dev_get_drvdata(d);
8cf769c6
EK
2476
2477 return sprintf(buf, "0x%08X\n", priv->debug_level);
b481de9c 2478}
8cf769c6
EK
2479static ssize_t store_debug_level(struct device *d,
2480 struct device_attribute *attr,
b481de9c
ZY
2481 const char *buf, size_t count)
2482{
928841b1 2483 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2484 unsigned long val;
2485 int ret;
b481de9c 2486
9257746f
TW
2487 ret = strict_strtoul(buf, 0, &val);
2488 if (ret)
978785a3 2489 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
b481de9c 2490 else
8cf769c6 2491 priv->debug_level = val;
b481de9c
ZY
2492
2493 return strnlen(buf, count);
2494}
2495
8cf769c6
EK
2496static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2497 show_debug_level, store_debug_level);
2498
b481de9c 2499
0a6857e7 2500#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2501
b481de9c 2502
bc6f59bc
TW
2503static ssize_t show_version(struct device *d,
2504 struct device_attribute *attr, char *buf)
2505{
928841b1 2506 struct iwl_priv *priv = dev_get_drvdata(d);
885ba202 2507 struct iwl_alive_resp *palive = &priv->card_alive;
f236a265
TW
2508 ssize_t pos = 0;
2509 u16 eeprom_ver;
bc6f59bc
TW
2510
2511 if (palive->is_valid)
f236a265
TW
2512 pos += sprintf(buf + pos,
2513 "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
2514 "fw type: 0x%01X 0x%01X\n",
bc6f59bc
TW
2515 palive->ucode_major, palive->ucode_minor,
2516 palive->sw_rev[0], palive->sw_rev[1],
2517 palive->ver_type, palive->ver_subtype);
bc6f59bc 2518 else
f236a265
TW
2519 pos += sprintf(buf + pos, "fw not loaded\n");
2520
2521 if (priv->eeprom) {
2522 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
0848e297
WYG
2523 pos += sprintf(buf + pos, "NVM Type: %s, version: 0x%x\n",
2524 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
2525 ? "OTP" : "EEPROM", eeprom_ver);
2526
f236a265
TW
2527 } else {
2528 pos += sprintf(buf + pos, "EEPROM not initialzed\n");
2529 }
2530
2531 return pos;
bc6f59bc
TW
2532}
2533
2534static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
2535
b481de9c
ZY
2536static ssize_t show_temperature(struct device *d,
2537 struct device_attribute *attr, char *buf)
2538{
928841b1 2539 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 2540
fee1247a 2541 if (!iwl_is_alive(priv))
b481de9c
ZY
2542 return -EAGAIN;
2543
91dbc5bd 2544 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2545}
2546
2547static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2548
b481de9c
ZY
2549static ssize_t show_tx_power(struct device *d,
2550 struct device_attribute *attr, char *buf)
2551{
928841b1 2552 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
2553
2554 if (!iwl_is_ready_rf(priv))
2555 return sprintf(buf, "off\n");
2556 else
2557 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2558}
2559
2560static ssize_t store_tx_power(struct device *d,
2561 struct device_attribute *attr,
2562 const char *buf, size_t count)
2563{
928841b1 2564 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2565 unsigned long val;
2566 int ret;
b481de9c 2567
9257746f
TW
2568 ret = strict_strtoul(buf, 10, &val);
2569 if (ret)
978785a3 2570 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
b481de9c 2571 else
630fe9b6 2572 iwl_set_tx_power(priv, val, false);
b481de9c
ZY
2573
2574 return count;
2575}
2576
2577static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2578
2579static ssize_t show_flags(struct device *d,
2580 struct device_attribute *attr, char *buf)
2581{
928841b1 2582 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2583
2584 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2585}
2586
2587static ssize_t store_flags(struct device *d,
2588 struct device_attribute *attr,
2589 const char *buf, size_t count)
2590{
928841b1 2591 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2592 unsigned long val;
2593 u32 flags;
2594 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2595 if (ret)
9257746f
TW
2596 return ret;
2597 flags = (u32)val;
b481de9c
ZY
2598
2599 mutex_lock(&priv->mutex);
2600 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2601 /* Cancel any currently running scans... */
2a421b91 2602 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2603 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2604 else {
e1623446 2605 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2606 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2607 iwlcore_commit_rxon(priv);
b481de9c
ZY
2608 }
2609 }
2610 mutex_unlock(&priv->mutex);
2611
2612 return count;
2613}
2614
2615static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2616
2617static ssize_t show_filter_flags(struct device *d,
2618 struct device_attribute *attr, char *buf)
2619{
928841b1 2620 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2621
2622 return sprintf(buf, "0x%04X\n",
2623 le32_to_cpu(priv->active_rxon.filter_flags));
2624}
2625
2626static ssize_t store_filter_flags(struct device *d,
2627 struct device_attribute *attr,
2628 const char *buf, size_t count)
2629{
928841b1 2630 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2631 unsigned long val;
2632 u32 filter_flags;
2633 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2634 if (ret)
9257746f
TW
2635 return ret;
2636 filter_flags = (u32)val;
b481de9c
ZY
2637
2638 mutex_lock(&priv->mutex);
2639 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2640 /* Cancel any currently running scans... */
2a421b91 2641 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2642 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2643 else {
e1623446 2644 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
2645 "0x%04X\n", filter_flags);
2646 priv->staging_rxon.filter_flags =
2647 cpu_to_le32(filter_flags);
e0158e61 2648 iwlcore_commit_rxon(priv);
b481de9c
ZY
2649 }
2650 }
2651 mutex_unlock(&priv->mutex);
2652
2653 return count;
2654}
2655
2656static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2657 store_filter_flags);
2658
b481de9c
ZY
2659static ssize_t store_power_level(struct device *d,
2660 struct device_attribute *attr,
2661 const char *buf, size_t count)
2662{
c79dd5b5 2663 struct iwl_priv *priv = dev_get_drvdata(d);
298df1f6 2664 int ret;
9257746f
TW
2665 unsigned long mode;
2666
b481de9c 2667
b481de9c
ZY
2668 mutex_lock(&priv->mutex);
2669
9257746f 2670 ret = strict_strtoul(buf, 10, &mode);
926f0b2e 2671 if (ret)
9257746f
TW
2672 goto out;
2673
298df1f6
EK
2674 ret = iwl_power_set_user_mode(priv, mode);
2675 if (ret) {
e1623446 2676 IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
5da4b55f 2677 goto out;
b481de9c 2678 }
298df1f6 2679 ret = count;
b481de9c
ZY
2680
2681 out:
2682 mutex_unlock(&priv->mutex);
298df1f6 2683 return ret;
b481de9c
ZY
2684}
2685
b481de9c
ZY
2686static ssize_t show_power_level(struct device *d,
2687 struct device_attribute *attr, char *buf)
2688{
c79dd5b5 2689 struct iwl_priv *priv = dev_get_drvdata(d);
298df1f6 2690 int mode = priv->power_data.user_power_setting;
5da4b55f 2691 int level = priv->power_data.power_mode;
b481de9c
ZY
2692 char *p = buf;
2693
7af2c460
JB
2694 p += sprintf(p, "INDEX:%d\t", level);
2695 p += sprintf(p, "USER:%d\n", mode);
3ac7f146 2696 return p - buf + 1;
b481de9c
ZY
2697}
2698
2699static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
2700 store_power_level);
2701
0b4d0ab4
WYG
2702static ssize_t show_qos(struct device *d,
2703 struct device_attribute *attr, char *buf)
2704{
4eaf16bc 2705 struct iwl_priv *priv = dev_get_drvdata(d);
0b4d0ab4
WYG
2706 char *p = buf;
2707 int q;
2708
2709 for (q = 0; q < AC_NUM; q++) {
2710 p += sprintf(p, "\tcw_min\tcw_max\taifsn\ttxop\n");
2711 p += sprintf(p, "AC[%d]\t%u\t%u\t%u\t%u\n", q,
2712 priv->qos_data.def_qos_parm.ac[q].cw_min,
2713 priv->qos_data.def_qos_parm.ac[q].cw_max,
2714 priv->qos_data.def_qos_parm.ac[q].aifsn,
2715 priv->qos_data.def_qos_parm.ac[q].edca_txop);
2716 }
2717
2718 return p - buf + 1;
2719}
2720
2721static DEVICE_ATTR(qos, S_IRUGO, show_qos, NULL);
b481de9c
ZY
2722
2723static ssize_t show_statistics(struct device *d,
2724 struct device_attribute *attr, char *buf)
2725{
c79dd5b5 2726 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 2727 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 2728 u32 len = 0, ofs = 0;
3ac7f146 2729 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
2730 int rc = 0;
2731
fee1247a 2732 if (!iwl_is_alive(priv))
b481de9c
ZY
2733 return -EAGAIN;
2734
2735 mutex_lock(&priv->mutex);
49ea8596 2736 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
2737 mutex_unlock(&priv->mutex);
2738
2739 if (rc) {
2740 len = sprintf(buf,
2741 "Error sending statistics request: 0x%08X\n", rc);
2742 return len;
2743 }
2744
2745 while (size && (PAGE_SIZE - len)) {
2746 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2747 PAGE_SIZE - len, 1);
2748 len = strlen(buf);
2749 if (PAGE_SIZE - len)
2750 buf[len++] = '\n';
2751
2752 ofs += 16;
2753 size -= min(size, 16U);
2754 }
2755
2756 return len;
2757}
2758
2759static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2760
b481de9c 2761
b481de9c
ZY
2762/*****************************************************************************
2763 *
2764 * driver setup and teardown
2765 *
2766 *****************************************************************************/
2767
4e39317d 2768static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2769{
d21050c7 2770 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
2771
2772 init_waitqueue_head(&priv->wait_command_queue);
2773
5b9f8cd3
EG
2774 INIT_WORK(&priv->up, iwl_bg_up);
2775 INIT_WORK(&priv->restart, iwl_bg_restart);
2776 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
2777 INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill);
2778 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 2779 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
2780 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2781 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 2782
2a421b91 2783 iwl_setup_scan_deferred_work(priv);
bb8c093b 2784
4e39317d
EG
2785 if (priv->cfg->ops->lib->setup_deferred_work)
2786 priv->cfg->ops->lib->setup_deferred_work(priv);
2787
2788 init_timer(&priv->statistics_periodic);
2789 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 2790 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 2791
ef850d7c
MA
2792 if (!priv->cfg->use_isr_legacy)
2793 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2794 iwl_irq_tasklet, (unsigned long)priv);
2795 else
2796 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2797 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
2798}
2799
4e39317d 2800static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2801{
4e39317d
EG
2802 if (priv->cfg->ops->lib->cancel_deferred_work)
2803 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 2804
3ae6a054 2805 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
2806 cancel_delayed_work(&priv->scan_check);
2807 cancel_delayed_work(&priv->alive_start);
b481de9c 2808 cancel_work_sync(&priv->beacon_update);
4e39317d 2809 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
2810}
2811
5b9f8cd3 2812static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
2813 &dev_attr_flags.attr,
2814 &dev_attr_filter_flags.attr,
b481de9c 2815 &dev_attr_power_level.attr,
b481de9c 2816 &dev_attr_statistics.attr,
b481de9c 2817 &dev_attr_temperature.attr,
b481de9c 2818 &dev_attr_tx_power.attr,
8cf769c6
EK
2819#ifdef CONFIG_IWLWIFI_DEBUG
2820 &dev_attr_debug_level.attr,
2821#endif
bc6f59bc 2822 &dev_attr_version.attr,
0b4d0ab4 2823 &dev_attr_qos.attr,
b481de9c
ZY
2824 NULL
2825};
2826
5b9f8cd3 2827static struct attribute_group iwl_attribute_group = {
b481de9c 2828 .name = NULL, /* put in device directory */
5b9f8cd3 2829 .attrs = iwl_sysfs_entries,
b481de9c
ZY
2830};
2831
5b9f8cd3
EG
2832static struct ieee80211_ops iwl_hw_ops = {
2833 .tx = iwl_mac_tx,
2834 .start = iwl_mac_start,
2835 .stop = iwl_mac_stop,
2836 .add_interface = iwl_mac_add_interface,
2837 .remove_interface = iwl_mac_remove_interface,
2838 .config = iwl_mac_config,
5b9f8cd3
EG
2839 .configure_filter = iwl_configure_filter,
2840 .set_key = iwl_mac_set_key,
2841 .update_tkip_key = iwl_mac_update_tkip_key,
2842 .get_stats = iwl_mac_get_stats,
2843 .get_tx_stats = iwl_mac_get_tx_stats,
2844 .conf_tx = iwl_mac_conf_tx,
2845 .reset_tsf = iwl_mac_reset_tsf,
2846 .bss_info_changed = iwl_bss_info_changed,
2847 .ampdu_action = iwl_mac_ampdu_action,
cb43dc25 2848 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
2849};
2850
5b9f8cd3 2851static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
2852{
2853 int err = 0;
c79dd5b5 2854 struct iwl_priv *priv;
b481de9c 2855 struct ieee80211_hw *hw;
82b9a121 2856 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 2857 unsigned long flags;
6cd0b1cb 2858 u16 pci_cmd;
b481de9c 2859
316c30d9
AK
2860 /************************
2861 * 1. Allocating HW data
2862 ************************/
2863
6440adb5
BC
2864 /* Disabling hardware scan means that mac80211 will perform scans
2865 * "the hard way", rather than using device's scan. */
1ea87396 2866 if (cfg->mod_params->disable_hw_scan) {
bf403db8
EK
2867 if (cfg->mod_params->debug & IWL_DL_INFO)
2868 dev_printk(KERN_DEBUG, &(pdev->dev),
2869 "Disabling hw_scan\n");
5b9f8cd3 2870 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
2871 }
2872
5b9f8cd3 2873 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 2874 if (!hw) {
b481de9c
ZY
2875 err = -ENOMEM;
2876 goto out;
2877 }
1d0a082d
AK
2878 priv = hw->priv;
2879 /* At this point both hw and priv are allocated. */
2880
b481de9c
ZY
2881 SET_IEEE80211_DEV(hw, &pdev->dev);
2882
e1623446 2883 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 2884 priv->cfg = cfg;
b481de9c 2885 priv->pci_dev = pdev;
40cefda9 2886 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 2887
0a6857e7 2888#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 2889 priv->debug_level = priv->cfg->mod_params->debug;
b481de9c
ZY
2890 atomic_set(&priv->restrict_refcnt, 0);
2891#endif
b481de9c 2892
316c30d9
AK
2893 /**************************
2894 * 2. Initializing PCI bus
2895 **************************/
2896 if (pci_enable_device(pdev)) {
2897 err = -ENODEV;
2898 goto out_ieee80211_free_hw;
2899 }
2900
2901 pci_set_master(pdev);
2902
093d874c 2903 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 2904 if (!err)
093d874c 2905 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 2906 if (err) {
093d874c 2907 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 2908 if (!err)
093d874c 2909 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 2910 /* both attempts failed: */
316c30d9 2911 if (err) {
978785a3 2912 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 2913 goto out_pci_disable_device;
cc2a8ea8 2914 }
316c30d9
AK
2915 }
2916
2917 err = pci_request_regions(pdev, DRV_NAME);
2918 if (err)
2919 goto out_pci_disable_device;
2920
2921 pci_set_drvdata(pdev, priv);
2922
316c30d9
AK
2923
2924 /***********************
2925 * 3. Read REV register
2926 ***********************/
2927 priv->hw_base = pci_iomap(pdev, 0, 0);
2928 if (!priv->hw_base) {
2929 err = -ENODEV;
2930 goto out_pci_release_regions;
2931 }
2932
e1623446 2933 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 2934 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 2935 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 2936
a8b50a0a
MA
2937 /* this spin lock will be used in apm_ops.init and EEPROM access
2938 * we should init now
2939 */
2940 spin_lock_init(&priv->reg_lock);
b661c819 2941 iwl_hw_detect(priv);
978785a3 2942 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 2943 priv->cfg->name, priv->hw_rev);
316c30d9 2944
e7b63581
TW
2945 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2946 * PCI Tx retries from interfering with C3 CPU state */
2947 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2948
086ed117
MA
2949 iwl_prepare_card_hw(priv);
2950 if (!priv->hw_ready) {
2951 IWL_WARN(priv, "Failed, HW not ready\n");
2952 goto out_iounmap;
2953 }
2954
91238714
TW
2955 /* amp init */
2956 err = priv->cfg->ops->lib->apm_ops.init(priv);
316c30d9 2957 if (err < 0) {
808ff697 2958 IWL_ERR(priv, "Failed to init APMG\n");
316c30d9
AK
2959 goto out_iounmap;
2960 }
91238714
TW
2961 /*****************
2962 * 4. Read EEPROM
2963 *****************/
316c30d9
AK
2964 /* Read the EEPROM */
2965 err = iwl_eeprom_init(priv);
2966 if (err) {
15b1687c 2967 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
2968 goto out_iounmap;
2969 }
8614f360
TW
2970 err = iwl_eeprom_check_version(priv);
2971 if (err)
c8f16138 2972 goto out_free_eeprom;
8614f360 2973
02883017 2974 /* extract MAC Address */
316c30d9 2975 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 2976 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
2977 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
2978
2979 /************************
2980 * 5. Setup HW constants
2981 ************************/
da154e30 2982 if (iwl_set_hw_params(priv)) {
15b1687c 2983 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 2984 goto out_free_eeprom;
316c30d9
AK
2985 }
2986
2987 /*******************
6ba87956 2988 * 6. Setup priv
316c30d9 2989 *******************/
b481de9c 2990
6ba87956 2991 err = iwl_init_drv(priv);
bf85ea4f 2992 if (err)
399f4900 2993 goto out_free_eeprom;
bf85ea4f 2994 /* At this point both hw and priv are initialized. */
316c30d9 2995
316c30d9 2996 /********************
09f9bf79 2997 * 7. Setup services
316c30d9 2998 ********************/
0359facc 2999 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3000 iwl_disable_interrupts(priv);
0359facc 3001 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3002
6cd0b1cb
HS
3003 pci_enable_msi(priv->pci_dev);
3004
ef850d7c
MA
3005 iwl_alloc_isr_ict(priv);
3006 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3007 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3008 if (err) {
3009 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3010 goto out_disable_msi;
3011 }
5b9f8cd3 3012 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3013 if (err) {
15b1687c 3014 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3015 goto out_free_irq;
316c30d9
AK
3016 }
3017
4e39317d 3018 iwl_setup_deferred_work(priv);
653fa4a0 3019 iwl_setup_rx_handlers(priv);
316c30d9 3020
6ba87956 3021 /**********************************
09f9bf79 3022 * 8. Setup and register mac80211
6ba87956
TW
3023 **********************************/
3024
6cd0b1cb
HS
3025 /* enable interrupts if needed: hw bug w/a */
3026 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3027 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3028 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3029 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3030 }
3031
3032 iwl_enable_interrupts(priv);
3033
6ba87956
TW
3034 err = iwl_setup_mac(priv);
3035 if (err)
3036 goto out_remove_sysfs;
3037
3038 err = iwl_dbgfs_register(priv, DRV_NAME);
3039 if (err)
a75fbe8d 3040 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
6ba87956 3041
6cd0b1cb
HS
3042 /* If platform's RF_KILL switch is NOT set to KILL */
3043 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3044 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3045 else
3046 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3047
58d0f361
EG
3048 err = iwl_rfkill_init(priv);
3049 if (err)
15b1687c 3050 IWL_ERR(priv, "Unable to initialize RFKILL system. "
58d0f361 3051 "Ignoring error: %d\n", err);
6cd0b1cb
HS
3052 else
3053 iwl_rfkill_set_hw_state(priv);
3054
58d0f361 3055 iwl_power_initialize(priv);
b481de9c
ZY
3056 return 0;
3057
316c30d9 3058 out_remove_sysfs:
c8f16138
RC
3059 destroy_workqueue(priv->workqueue);
3060 priv->workqueue = NULL;
5b9f8cd3 3061 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3062 out_free_irq:
3063 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3064 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3065 out_disable_msi:
3066 pci_disable_msi(priv->pci_dev);
6ba87956 3067 iwl_uninit_drv(priv);
073d3f5f
TW
3068 out_free_eeprom:
3069 iwl_eeprom_free(priv);
b481de9c
ZY
3070 out_iounmap:
3071 pci_iounmap(pdev, priv->hw_base);
3072 out_pci_release_regions:
316c30d9 3073 pci_set_drvdata(pdev, NULL);
623d563e 3074 pci_release_regions(pdev);
b481de9c
ZY
3075 out_pci_disable_device:
3076 pci_disable_device(pdev);
b481de9c
ZY
3077 out_ieee80211_free_hw:
3078 ieee80211_free_hw(priv->hw);
3079 out:
3080 return err;
3081}
3082
5b9f8cd3 3083static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3084{
c79dd5b5 3085 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3086 unsigned long flags;
b481de9c
ZY
3087
3088 if (!priv)
3089 return;
3090
e1623446 3091 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3092
67249625 3093 iwl_dbgfs_unregister(priv);
5b9f8cd3 3094 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3095
5b9f8cd3
EG
3096 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3097 * to be called and iwl_down since we are removing the device
0b124c31
GG
3098 * we need to set STATUS_EXIT_PENDING bit.
3099 */
3100 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3101 if (priv->mac80211_registered) {
3102 ieee80211_unregister_hw(priv->hw);
3103 priv->mac80211_registered = 0;
0b124c31 3104 } else {
5b9f8cd3 3105 iwl_down(priv);
c4f55232
RR
3106 }
3107
0359facc
MA
3108 /* make sure we flush any pending irq or
3109 * tasklet for the driver
3110 */
3111 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3112 iwl_disable_interrupts(priv);
0359facc
MA
3113 spin_unlock_irqrestore(&priv->lock, flags);
3114
3115 iwl_synchronize_irq(priv);
3116
58d0f361 3117 iwl_rfkill_unregister(priv);
5b9f8cd3 3118 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3119
3120 if (priv->rxq.bd)
a55360e4 3121 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3122 iwl_hw_txq_ctx_free(priv);
b481de9c 3123
e11bc028 3124 priv->cfg->ops->smgmt->clear_station_table(priv);
073d3f5f 3125 iwl_eeprom_free(priv);
b481de9c 3126
b481de9c 3127
948c171c
MA
3128 /*netif_stop_queue(dev); */
3129 flush_workqueue(priv->workqueue);
3130
5b9f8cd3 3131 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3132 * priv->workqueue... so we can't take down the workqueue
3133 * until now... */
3134 destroy_workqueue(priv->workqueue);
3135 priv->workqueue = NULL;
3136
6cd0b1cb
HS
3137 free_irq(priv->pci_dev->irq, priv);
3138 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3139 pci_iounmap(pdev, priv->hw_base);
3140 pci_release_regions(pdev);
3141 pci_disable_device(pdev);
3142 pci_set_drvdata(pdev, NULL);
3143
6ba87956 3144 iwl_uninit_drv(priv);
b481de9c 3145
ef850d7c
MA
3146 iwl_free_isr_ict(priv);
3147
b481de9c
ZY
3148 if (priv->ibss_beacon)
3149 dev_kfree_skb(priv->ibss_beacon);
3150
3151 ieee80211_free_hw(priv->hw);
3152}
3153
b481de9c
ZY
3154
3155/*****************************************************************************
3156 *
3157 * driver and module entry point
3158 *
3159 *****************************************************************************/
3160
fed9017e
RR
3161/* Hardware specific file defines the PCI IDs table for that hardware module */
3162static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3163#ifdef CONFIG_IWL4965
fed9017e
RR
3164 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3165 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3166#endif /* CONFIG_IWL4965 */
5a6a256e 3167#ifdef CONFIG_IWL5000
47408639
EK
3168 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3169 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3170 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3171 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3172 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3173 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3174 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK
3175 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3176 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3177 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW
3178/* 5350 WiFi/WiMax */
3179 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3180 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3181 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW
3182/* 5150 Wifi/WiMax */
3183 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3184 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
e1228374
JS
3185/* 6000/6050 Series */
3186 {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
3187 {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
3188 {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
3189 {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
542cc793 3190 {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000_2agn_cfg)},
e1228374 3191 {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
542cc793 3192 {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000_2agn_cfg)},
e1228374
JS
3193 {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
3194 {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
3195 {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
3196 {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
3197 {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
3198 {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
77dcb6a9
JS
3199/* 1000 Series WiFi */
3200 {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
3201 {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
5a6a256e 3202#endif /* CONFIG_IWL5000 */
7100e924 3203
fed9017e
RR
3204 {0}
3205};
3206MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3207
3208static struct pci_driver iwl_driver = {
b481de9c 3209 .name = DRV_NAME,
fed9017e 3210 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3211 .probe = iwl_pci_probe,
3212 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3213#ifdef CONFIG_PM
5b9f8cd3
EG
3214 .suspend = iwl_pci_suspend,
3215 .resume = iwl_pci_resume,
b481de9c
ZY
3216#endif
3217};
3218
5b9f8cd3 3219static int __init iwl_init(void)
b481de9c
ZY
3220{
3221
3222 int ret;
3223 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3224 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3225
e227ceac 3226 ret = iwlagn_rate_control_register();
897e1cf2 3227 if (ret) {
a3139c59
SO
3228 printk(KERN_ERR DRV_NAME
3229 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3230 return ret;
3231 }
3232
fed9017e 3233 ret = pci_register_driver(&iwl_driver);
b481de9c 3234 if (ret) {
a3139c59 3235 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3236 goto error_register;
b481de9c 3237 }
b481de9c
ZY
3238
3239 return ret;
897e1cf2 3240
897e1cf2 3241error_register:
e227ceac 3242 iwlagn_rate_control_unregister();
897e1cf2 3243 return ret;
b481de9c
ZY
3244}
3245
5b9f8cd3 3246static void __exit iwl_exit(void)
b481de9c 3247{
fed9017e 3248 pci_unregister_driver(&iwl_driver);
e227ceac 3249 iwlagn_rate_control_unregister();
b481de9c
ZY
3250}
3251
5b9f8cd3
EG
3252module_exit(iwl_exit);
3253module_init(iwl_init);