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iwlagn: add temperature offset calib for 6000g2
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn-ucode.c
CommitLineData
792bc3cb
WYG		 1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
81b8176e 33#include <linux/sched.h>
792bc3cb
WYG		 34
35#include "iwl-dev.h"
36#include "iwl-core.h"
81b8176e 37#include "iwl-io.h"
741a6266 38#include "iwl-helpers.h"
19e6cda0 39#include "iwl-agn-hw.h"
741a6266 40#include "iwl-agn.h"
0de76736 41#include "iwl-agn-calib.h"
741a6266
WYG		 42
43static const s8 iwlagn_default_queue_to_tx_fifo[] = {
44 IWL_TX_FIFO_VO,
45 IWL_TX_FIFO_VI,
46 IWL_TX_FIFO_BE,
47 IWL_TX_FIFO_BK,
48 IWLAGN_CMD_FIFO_NUM,
49 IWL_TX_FIFO_UNUSED,
50 IWL_TX_FIFO_UNUSED,
51 IWL_TX_FIFO_UNUSED,
52 IWL_TX_FIFO_UNUSED,
53 IWL_TX_FIFO_UNUSED,
54};
81b8176e 55
13bb9483
JB		 56static const s8 iwlagn_ipan_queue_to_tx_fifo[] = {
57 IWL_TX_FIFO_VO,
58 IWL_TX_FIFO_VI,
59 IWL_TX_FIFO_BE,
60 IWL_TX_FIFO_BK,
751ca305
JB		 61 IWL_TX_FIFO_BK_IPAN,
62 IWL_TX_FIFO_BE_IPAN,
63 IWL_TX_FIFO_VI_IPAN,
64 IWL_TX_FIFO_VO_IPAN,
65 IWL_TX_FIFO_BE_IPAN,
13bb9483
JB		 66 IWLAGN_CMD_FIFO_NUM,
67};
68
f4012413
WYG		 69static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
70 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
71 0, COEX_UNASSOC_IDLE_FLAGS},
72 {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
73 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
74 {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
75 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
76 {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
77 0, COEX_CALIBRATION_FLAGS},
78 {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
79 0, COEX_PERIODIC_CALIBRATION_FLAGS},
80 {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
81 0, COEX_CONNECTION_ESTAB_FLAGS},
82 {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
83 0, COEX_ASSOCIATED_IDLE_FLAGS},
84 {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
85 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
86 {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
87 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
88 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
89 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
90 {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
91 {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
92 {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
93 0, COEX_STAND_ALONE_DEBUG_FLAGS},
94 {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
95 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
96 {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
97 {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
98};
99
81b8176e
WYG		 100/*
101 * ucode
102 */
103static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
104 struct fw_desc *image, u32 dst_addr)
105{
106 dma_addr_t phy_addr = image->p_addr;
107 u32 byte_cnt = image->len;
108 int ret;
109
110 priv->ucode_write_complete = 0;
111
112 iwl_write_direct32(priv,
113 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
114 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
115
116 iwl_write_direct32(priv,
117 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
118
119 iwl_write_direct32(priv,
120 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
121 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
122
123 iwl_write_direct32(priv,
124 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
125 (iwl_get_dma_hi_addr(phy_addr)
126 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
127
128 iwl_write_direct32(priv,
129 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
130 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
131 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
132 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
133
134 iwl_write_direct32(priv,
135 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
136 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
137 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
138 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
139
140 IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
141 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
142 priv->ucode_write_complete, 5 * HZ);
143 if (ret == -ERESTARTSYS) {
144 IWL_ERR(priv, "Could not load the %s uCode section due "
145 "to interrupt\n", name);
146 return ret;
147 }
148 if (!ret) {
149 IWL_ERR(priv, "Could not load the %s uCode section\n",
150 name);
151 return -ETIMEDOUT;
152 }
153
154 return 0;
155}
156
157static int iwlagn_load_given_ucode(struct iwl_priv *priv,
158 struct fw_desc *inst_image,
159 struct fw_desc *data_image)
160{
161 int ret = 0;
162
163 ret = iwlagn_load_section(priv, "INST", inst_image,
19e6cda0 164 IWLAGN_RTC_INST_LOWER_BOUND);
81b8176e
WYG		 165 if (ret)
166 return ret;
167
168 return iwlagn_load_section(priv, "DATA", data_image,
19e6cda0 169 IWLAGN_RTC_DATA_LOWER_BOUND);
81b8176e
WYG		 170}
171
172int iwlagn_load_ucode(struct iwl_priv *priv)
173{
174 int ret = 0;
175
176 /* check whether init ucode should be loaded, or rather runtime ucode */
177 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
178 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
179 ret = iwlagn_load_given_ucode(priv,
180 &priv->ucode_init, &priv->ucode_init_data);
181 if (!ret) {
182 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
183 priv->ucode_type = UCODE_INIT;
184 }
185 } else {
186 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
187 "Loading runtime ucode...\n");
188 ret = iwlagn_load_given_ucode(priv,
189 &priv->ucode_code, &priv->ucode_data);
190 if (!ret) {
191 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
192 priv->ucode_type = UCODE_RT;
193 }
194 }
195
196 return ret;
197}
792bc3cb 198
741a6266
WYG		 199/*
200 * Calibration
201 */
202static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
203{
204 struct iwl_calib_xtal_freq_cmd cmd;
205 __le16 *xtal_calib =
7944f8e4 206 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
741a6266
WYG		 207
208 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
209 cmd.hdr.first_group = 0;
210 cmd.hdr.groups_num = 1;
211 cmd.hdr.data_valid = 1;
212 cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
213 cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
214 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
215 (u8 *)&cmd, sizeof(cmd));
216}
217
bf53f939
SZ		 218static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
219{
220 struct iwl_calib_temperature_offset_cmd cmd;
221 __le16 *offset_calib =
222 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_TEMPERATURE);
223 cmd.hdr.op_code = IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD;
224 cmd.hdr.first_group = 0;
225 cmd.hdr.groups_num = 1;
226 cmd.hdr.data_valid = 1;
227 cmd.radio_sensor_offset = le16_to_cpu(offset_calib[1]);
228 if (!(cmd.radio_sensor_offset))
229 cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
230 cmd.reserved = 0;
231 IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
232 cmd.radio_sensor_offset);
233 return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
234 (u8 *)&cmd, sizeof(cmd));
235}
236
741a6266
WYG		 237static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
238{
239 struct iwl_calib_cfg_cmd calib_cfg_cmd;
240 struct iwl_host_cmd cmd = {
241 .id = CALIBRATION_CFG_CMD,
242 .len = sizeof(struct iwl_calib_cfg_cmd),
243 .data = &calib_cfg_cmd,
244 };
245
246 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
247 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
248 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
249 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
250 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
251
252 return iwl_send_cmd(priv, &cmd);
253}
254
255void iwlagn_rx_calib_result(struct iwl_priv *priv,
256 struct iwl_rx_mem_buffer *rxb)
257{
258 struct iwl_rx_packet *pkt = rxb_addr(rxb);
259 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
260 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
261 int index;
262
263 /* reduce the size of the length field itself */
264 len -= 4;
265
266 /* Define the order in which the results will be sent to the runtime
267 * uCode. iwl_send_calib_results sends them in a row according to
268 * their index. We sort them here
269 */
270 switch (hdr->op_code) {
271 case IWL_PHY_CALIBRATE_DC_CMD:
272 index = IWL_CALIB_DC;
273 break;
274 case IWL_PHY_CALIBRATE_LO_CMD:
275 index = IWL_CALIB_LO;
276 break;
277 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
278 index = IWL_CALIB_TX_IQ;
279 break;
280 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
281 index = IWL_CALIB_TX_IQ_PERD;
282 break;
283 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
284 index = IWL_CALIB_BASE_BAND;
285 break;
286 default:
287 IWL_ERR(priv, "Unknown calibration notification %d\n",
288 hdr->op_code);
289 return;
290 }
291 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
292}
293
294void iwlagn_rx_calib_complete(struct iwl_priv *priv,
295 struct iwl_rx_mem_buffer *rxb)
296{
297 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
298 queue_work(priv->workqueue, &priv->restart);
299}
300
301void iwlagn_init_alive_start(struct iwl_priv *priv)
302{
303 int ret = 0;
304
305 /* Check alive response for "valid" sign from uCode */
306 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
307 /* We had an error bringing up the hardware, so take it
308 * all the way back down so we can try again */
309 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
310 goto restart;
311 }
312
313 /* initialize uCode was loaded... verify inst image.
314 * This is a paranoid check, because we would not have gotten the
315 * "initialize" alive if code weren't properly loaded. */
316 if (iwl_verify_ucode(priv)) {
317 /* Runtime instruction load was bad;
318 * take it all the way back down so we can try again */
319 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
320 goto restart;
321 }
322
323 ret = priv->cfg->ops->lib->alive_notify(priv);
324 if (ret) {
325 IWL_WARN(priv,
326 "Could not complete ALIVE transition: %d\n", ret);
327 goto restart;
328 }
329
7cb1b088
WYG		 330 if (priv->cfg->bt_params &&
331 priv->cfg->bt_params->advanced_bt_coexist) {
f7322f8f
WYG		 332 /*
333 * Tell uCode we are ready to perform calibration
334 * need to perform this before any calibration
335 * no need to close the envlope since we are going
336 * to load the runtime uCode later.
337 */
338 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
339 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
340
341 }
741a6266 342 iwlagn_send_calib_cfg(priv);
bf53f939
SZ		 343
344 /**
345 * temperature offset calibration is only needed for runtime ucode,
346 * so prepare the value now.
347 */
348 if (priv->cfg->need_temp_offset_calib)
349 iwlagn_set_temperature_offset_calib(priv);
350
741a6266
WYG		 351 return;
352
353restart:
354 /* real restart (first load init_ucode) */
355 queue_work(priv->workqueue, &priv->restart);
356}
357
f4012413
WYG		 358static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
359{
360 struct iwl_wimax_coex_cmd coex_cmd;
361
7cb1b088 362 if (priv->cfg->base_params->support_wimax_coexist) {
f4012413
WYG		 363 /* UnMask wake up src at associated sleep */
364 coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
365
366 /* UnMask wake up src at unassociated sleep */
367 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
368 memcpy(coex_cmd.sta_prio, cu_priorities,
369 sizeof(struct iwl_wimax_coex_event_entry) *
370 COEX_NUM_OF_EVENTS);
371
372 /* enabling the coexistence feature */
373 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
374
375 /* enabling the priorities tables */
376 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
377 } else {
378 /* coexistence is disabled */
379 memset(&coex_cmd, 0, sizeof(coex_cmd));
380 }
381 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
382 sizeof(coex_cmd), &coex_cmd);
383}
384
aeb4a2ee
WYG		 385static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
386 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
387 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
388 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
389 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
390 ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
391 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
392 ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
393 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
394 ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
395 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
396 ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
397 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
398 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
399 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
400 ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
401 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
402 ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
403 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
404 0, 0, 0, 0, 0, 0, 0
405};
406
f7322f8f 407void iwlagn_send_prio_tbl(struct iwl_priv *priv)
aeb4a2ee
WYG		 408{
409 struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
410
411 memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
412 sizeof(iwlagn_bt_prio_tbl));
413 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PRIO_TABLE,
414 sizeof(prio_tbl_cmd), &prio_tbl_cmd))
415 IWL_ERR(priv, "failed to send BT prio tbl command\n");
416}
417
f7322f8f 418void iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
aeb4a2ee
WYG		 419{
420 struct iwl_bt_coex_prot_env_cmd env_cmd;
421
422 env_cmd.action = action;
423 env_cmd.type = type;
424 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PROT_ENV,
425 sizeof(env_cmd), &env_cmd))
426 IWL_ERR(priv, "failed to send BT env command\n");
427}
428
429
741a6266
WYG		 430int iwlagn_alive_notify(struct iwl_priv *priv)
431{
13bb9483 432 const s8 *queues;
741a6266
WYG		 433 u32 a;
434 unsigned long flags;
435 int i, chan;
436 u32 reg_val;
437
438 spin_lock_irqsave(&priv->lock, flags);
439
f4388adc
WYG		 440 priv->scd_base_addr = iwl_read_prph(priv, IWLAGN_SCD_SRAM_BASE_ADDR);
441 a = priv->scd_base_addr + IWLAGN_SCD_CONTEXT_DATA_OFFSET;
442 for (; a < priv->scd_base_addr + IWLAGN_SCD_TX_STTS_BITMAP_OFFSET;
741a6266
WYG		 443 a += 4)
444 iwl_write_targ_mem(priv, a, 0);
f4388adc 445 for (; a < priv->scd_base_addr + IWLAGN_SCD_TRANSLATE_TBL_OFFSET;
741a6266
WYG		 446 a += 4)
447 iwl_write_targ_mem(priv, a, 0);
448 for (; a < priv->scd_base_addr +
f4388adc 449 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
741a6266
WYG		 450 iwl_write_targ_mem(priv, a, 0);
451
f4388adc 452 iwl_write_prph(priv, IWLAGN_SCD_DRAM_BASE_ADDR,
741a6266
WYG		 453 priv->scd_bc_tbls.dma >> 10);
454
455 /* Enable DMA channel */
456 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
457 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
458 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
459 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
460
461 /* Update FH chicken bits */
462 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
463 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
464 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
465
f4388adc 466 iwl_write_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL,
13bb9483 467 IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv));
f4388adc 468 iwl_write_prph(priv, IWLAGN_SCD_AGGR_SEL, 0);
741a6266
WYG		 469
470 /* initiate the queues */
471 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
f4388adc 472 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(i), 0);
741a6266
WYG		 473 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
474 iwl_write_targ_mem(priv, priv->scd_base_addr +
f4388adc 475 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
741a6266 476 iwl_write_targ_mem(priv, priv->scd_base_addr +
f4388adc 477 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i) +
741a6266
WYG		 478 sizeof(u32),
479 ((SCD_WIN_SIZE <<
f4388adc
WYG		 480 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
481 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
741a6266 482 ((SCD_FRAME_LIMIT <<
f4388adc
WYG		 483 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
484 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
741a6266
WYG		 485 }
486
f4388adc 487 iwl_write_prph(priv, IWLAGN_SCD_INTERRUPT_MASK,
741a6266
WYG		 488 IWL_MASK(0, priv->hw_params.max_txq_num));
489
490 /* Activate all Tx DMA/FIFO channels */
491 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
492
13bb9483
JB		 493 /* map queues to FIFOs */
494 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
495 queues = iwlagn_ipan_queue_to_tx_fifo;
496 else
497 queues = iwlagn_default_queue_to_tx_fifo;
498
499 iwlagn_set_wr_ptrs(priv, priv->cmd_queue, 0);
741a6266
WYG		 500
501 /* make sure all queue are not stopped */
502 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
503 for (i = 0; i < 4; i++)
504 atomic_set(&priv->queue_stop_count[i], 0);
505
506 /* reset to 0 to enable all the queue first */
507 priv->txq_ctx_active_msk = 0;
13bb9483 508
741a6266 509 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
13bb9483 510 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != 10);
741a6266 511
13bb9483
JB		 512 for (i = 0; i < 10; i++) {
513 int ac = queues[i];
741a6266
WYG		 514
515 iwl_txq_ctx_activate(priv, i);
516
517 if (ac == IWL_TX_FIFO_UNUSED)
518 continue;
519
520 iwlagn_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
521 }
522
523 spin_unlock_irqrestore(&priv->lock, flags);
524
f4012413 525 iwlagn_send_wimax_coex(priv);
741a6266
WYG		 526
527 iwlagn_set_Xtal_calib(priv);
528 iwl_send_calib_results(priv);
529
530 return 0;
531}
db41dd27
WYG		 532
533
534/**
535 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
536 * using sample data 100 bytes apart. If these sample points are good,
537 * it's a pretty good bet that everything between them is good, too.
538 */
539static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
540{
541 u32 val;
542 int ret = 0;
543 u32 errcnt = 0;
544 u32 i;
545
546 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
547
548 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
549 /* read data comes through single port, auto-incr addr */
550 /* NOTE: Use the debugless read so we don't flood kernel log
551 * if IWL_DL_IO is set */
552 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
553 i + IWLAGN_RTC_INST_LOWER_BOUND);
554 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
555 if (val != le32_to_cpu(*image)) {
556 ret = -EIO;
557 errcnt++;
558 if (errcnt >= 3)
559 break;
560 }
561 }
562
563 return ret;
564}
565
566/**
567 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
568 * looking at all data.
569 */
570static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
571 u32 len)
572{
573 u32 val;
574 u32 save_len = len;
575 int ret = 0;
576 u32 errcnt;
577
578 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
579
580 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
581 IWLAGN_RTC_INST_LOWER_BOUND);
582
583 errcnt = 0;
584 for (; len > 0; len -= sizeof(u32), image++) {
585 /* read data comes through single port, auto-incr addr */
586 /* NOTE: Use the debugless read so we don't flood kernel log
587 * if IWL_DL_IO is set */
588 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
589 if (val != le32_to_cpu(*image)) {
590 IWL_ERR(priv, "uCode INST section is invalid at "
591 "offset 0x%x, is 0x%x, s/b 0x%x\n",
592 save_len - len, val, le32_to_cpu(*image));
593 ret = -EIO;
594 errcnt++;
595 if (errcnt >= 20)
596 break;
597 }
598 }
599
600 if (!errcnt)
601 IWL_DEBUG_INFO(priv,
602 "ucode image in INSTRUCTION memory is good\n");
603
604 return ret;
605}
606
607/**
608 * iwl_verify_ucode - determine which instruction image is in SRAM,
609 * and verify its contents
610 */
611int iwl_verify_ucode(struct iwl_priv *priv)
612{
613 __le32 *image;
614 u32 len;
615 int ret;
616
617 /* Try bootstrap */
618 image = (__le32 *)priv->ucode_boot.v_addr;
619 len = priv->ucode_boot.len;
620 ret = iwlcore_verify_inst_sparse(priv, image, len);
621 if (!ret) {
622 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
623 return 0;
624 }
625
626 /* Try initialize */
627 image = (__le32 *)priv->ucode_init.v_addr;
628 len = priv->ucode_init.len;
629 ret = iwlcore_verify_inst_sparse(priv, image, len);
630 if (!ret) {
631 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
632 return 0;
633 }
634
635 /* Try runtime/protocol */
636 image = (__le32 *)priv->ucode_code.v_addr;
637 len = priv->ucode_code.len;
638 ret = iwlcore_verify_inst_sparse(priv, image, len);
639 if (!ret) {
640 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
641 return 0;
642 }
643
644 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
645
646 /* Since nothing seems to match, show first several data entries in
647 * instruction SRAM, so maybe visual inspection will give a clue.
648 * Selection of bootstrap image (vs. other images) is arbitrary. */
649 image = (__le32 *)priv->ucode_boot.v_addr;
650 len = priv->ucode_boot.len;
651 ret = iwl_verify_inst_full(priv, image, len);
652
653 return ret;
654}
Clone of davem's net-next-2.6 tree