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iwlwifi: clean up printing
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
bddadf86 41#include "iwl-3945-fh.h"
600c0e11 42#include "iwl-commands.h"
b481de9c 43#include "iwl-3945.h"
5d08cd1d 44#include "iwl-helpers.h"
5747d47f 45#include "iwl-core.h"
d9829a67 46#include "iwl-agn-rs.h"
b481de9c
ZY		 47
48#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_##r##M_IEEE, \
51 IWL_RATE_##ip##M_INDEX, \
52 IWL_RATE_##in##M_INDEX, \
53 IWL_RATE_##rp##M_INDEX, \
54 IWL_RATE_##rn##M_INDEX, \
55 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 56 IWL_RATE_##np##M_INDEX, \
57 IWL_RATE_##r##M_INDEX_TABLE, \
58 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 59
60/*
61 * Parameter order:
62 * rate, prev rate, next rate, prev tgg rate, next tgg rate
63 *
64 * If there isn't a valid next or previous rate then INV is used which
65 * maps to IWL_RATE_INVALID
66 *
67 */
d9829a67 68const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 69 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
70 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
71 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
72 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 73 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
74 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
75 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
76 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
77 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
78 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
79 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
80 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 81};
82
bb8c093b 83/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 84#define IWL_EVT_DISABLE (0)
85#define IWL_EVT_DISABLE_SIZE (1532/32)
86
87/**
bb8c093b 88 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 89 *
90 * Disable an event by writing "1"s into "disable"
91 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
92 * Default values of 0 enable uCode events to be logged.
93 * Use for only special debugging. This function is just a placeholder as-is,
94 * you'll need to provide the special bits! ...
95 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 96void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 97{
af7cca2a 98 int ret;
b481de9c
ZY		 99 int i;
100 u32 base; /* SRAM address of event log header */
101 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
102 u32 array_size; /* # of u32 entries in array */
103 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
104 0x00000000, /* 31 - 0 Event id numbers */
105 0x00000000, /* 63 - 32 */
106 0x00000000, /* 95 - 64 */
107 0x00000000, /* 127 - 96 */
108 0x00000000, /* 159 - 128 */
109 0x00000000, /* 191 - 160 */
110 0x00000000, /* 223 - 192 */
111 0x00000000, /* 255 - 224 */
112 0x00000000, /* 287 - 256 */
113 0x00000000, /* 319 - 288 */
114 0x00000000, /* 351 - 320 */
115 0x00000000, /* 383 - 352 */
116 0x00000000, /* 415 - 384 */
117 0x00000000, /* 447 - 416 */
118 0x00000000, /* 479 - 448 */
119 0x00000000, /* 511 - 480 */
120 0x00000000, /* 543 - 512 */
121 0x00000000, /* 575 - 544 */
122 0x00000000, /* 607 - 576 */
123 0x00000000, /* 639 - 608 */
124 0x00000000, /* 671 - 640 */
125 0x00000000, /* 703 - 672 */
126 0x00000000, /* 735 - 704 */
127 0x00000000, /* 767 - 736 */
128 0x00000000, /* 799 - 768 */
129 0x00000000, /* 831 - 800 */
130 0x00000000, /* 863 - 832 */
131 0x00000000, /* 895 - 864 */
132 0x00000000, /* 927 - 896 */
133 0x00000000, /* 959 - 928 */
134 0x00000000, /* 991 - 960 */
135 0x00000000, /* 1023 - 992 */
136 0x00000000, /* 1055 - 1024 */
137 0x00000000, /* 1087 - 1056 */
138 0x00000000, /* 1119 - 1088 */
139 0x00000000, /* 1151 - 1120 */
140 0x00000000, /* 1183 - 1152 */
141 0x00000000, /* 1215 - 1184 */
142 0x00000000, /* 1247 - 1216 */
143 0x00000000, /* 1279 - 1248 */
144 0x00000000, /* 1311 - 1280 */
145 0x00000000, /* 1343 - 1312 */
146 0x00000000, /* 1375 - 1344 */
147 0x00000000, /* 1407 - 1376 */
148 0x00000000, /* 1439 - 1408 */
149 0x00000000, /* 1471 - 1440 */
150 0x00000000, /* 1503 - 1472 */
151 };
152
153 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 154 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 155 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
156 return;
157 }
158
5d49f498 159 ret = iwl_grab_nic_access(priv);
af7cca2a 160 if (ret) {
b481de9c
ZY		 161 IWL_WARNING("Can not read from adapter at this time.\n");
162 return;
163 }
164
5d49f498
AK		 165 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
166 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
167 iwl_release_nic_access(priv);
b481de9c
ZY		 168
169 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
170 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
171 disable_ptr);
5d49f498 172 ret = iwl_grab_nic_access(priv);
b481de9c 173 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 174 iwl_write_targ_mem(priv,
af7cca2a
TW		 175 disable_ptr + (i * sizeof(u32)),
176 evt_disable[i]);
b481de9c 177
5d49f498 178 iwl_release_nic_access(priv);
b481de9c
ZY		 179 } else {
180 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
181 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
182 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
183 disable_ptr, array_size);
184 }
185
186}
187
17744ff6
TW		 188static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
189{
190 int idx;
191
192 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
193 if (iwl3945_rates[idx].plcp == plcp)
194 return idx;
195 return -1;
196}
197
b481de9c
ZY		 198/**
199 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
200 * @priv: eeprom and antenna fields are used to determine antenna flags
201 *
f2c7e521 202 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
b481de9c
ZY		 203 * priv->antenna specifies the antenna diversity mode:
204 *
a96a27f9 205 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
b481de9c
ZY		 206 * IWL_ANTENNA_MAIN - Force MAIN antenna
207 * IWL_ANTENNA_AUX - Force AUX antenna
208 */
4a8a4322 209__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
b481de9c
ZY		 210{
211 switch (priv->antenna) {
212 case IWL_ANTENNA_DIVERSITY:
213 return 0;
214
215 case IWL_ANTENNA_MAIN:
f2c7e521 216 if (priv->eeprom39.antenna_switch_type)
b481de9c
ZY		 217 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
218 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
219
220 case IWL_ANTENNA_AUX:
f2c7e521 221 if (priv->eeprom39.antenna_switch_type)
b481de9c
ZY		 222 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
223 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
224 }
225
226 /* bad antenna selector value */
227 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
228 return 0; /* "diversity" is default if error */
229}
230
91c066f2
TW		 231#ifdef CONFIG_IWL3945_DEBUG
232#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
233
234static const char *iwl3945_get_tx_fail_reason(u32 status)
235{
236 switch (status & TX_STATUS_MSK) {
237 case TX_STATUS_SUCCESS:
238 return "SUCCESS";
239 TX_STATUS_ENTRY(SHORT_LIMIT);
240 TX_STATUS_ENTRY(LONG_LIMIT);
241 TX_STATUS_ENTRY(FIFO_UNDERRUN);
242 TX_STATUS_ENTRY(MGMNT_ABORT);
243 TX_STATUS_ENTRY(NEXT_FRAG);
244 TX_STATUS_ENTRY(LIFE_EXPIRE);
245 TX_STATUS_ENTRY(DEST_PS);
246 TX_STATUS_ENTRY(ABORTED);
247 TX_STATUS_ENTRY(BT_RETRY);
248 TX_STATUS_ENTRY(STA_INVALID);
249 TX_STATUS_ENTRY(FRAG_DROPPED);
250 TX_STATUS_ENTRY(TID_DISABLE);
251 TX_STATUS_ENTRY(FRAME_FLUSHED);
252 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
253 TX_STATUS_ENTRY(TX_LOCKED);
254 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
255 }
256
257 return "UNKNOWN";
258}
259#else
260static inline const char *iwl3945_get_tx_fail_reason(u32 status)
261{
262 return "";
263}
264#endif
265
e6a9854b
JB		 266/*
267 * get ieee prev rate from rate scale table.
268 * for A and B mode we need to overright prev
269 * value
270 */
4a8a4322 271int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 272{
273 int next_rate = iwl3945_get_prev_ieee_rate(rate);
274
275 switch (priv->band) {
276 case IEEE80211_BAND_5GHZ:
277 if (rate == IWL_RATE_12M_INDEX)
278 next_rate = IWL_RATE_9M_INDEX;
279 else if (rate == IWL_RATE_6M_INDEX)
280 next_rate = IWL_RATE_6M_INDEX;
281 break;
7262796a
AM		 282 case IEEE80211_BAND_2GHZ:
283 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
284 iwl3945_is_associated(priv)) {
285 if (rate == IWL_RATE_11M_INDEX)
286 next_rate = IWL_RATE_5M_INDEX;
287 }
e6a9854b 288 break;
7262796a 289
e6a9854b
JB		 290 default:
291 break;
292 }
293
294 return next_rate;
295}
296
91c066f2
TW		 297
298/**
299 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
300 *
301 * When FW advances 'R' index, all entries between old and new 'R' index
302 * need to be reclaimed. As result, some free space forms. If there is
303 * enough free space (> low mark), wake the stack that feeds us.
304 */
4a8a4322 305static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 306 int txq_id, int index)
307{
f2c7e521 308 struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
d20b3c65 309 struct iwl_queue *q = &txq->q;
91c066f2
TW		 310 struct iwl3945_tx_info *tx_info;
311
312 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
313
314 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
315 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
316
317 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 318 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2
TW		 319 tx_info->skb[0] = NULL;
320 iwl3945_hw_txq_free_tfd(priv, txq);
321 }
322
d20b3c65 323 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 324 (txq_id != IWL_CMD_QUEUE_NUM) &&
325 priv->mac80211_registered)
326 ieee80211_wake_queue(priv->hw, txq_id);
327}
328
329/**
330 * iwl3945_rx_reply_tx - Handle Tx response
331 */
4a8a4322 332static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 333 struct iwl_rx_mem_buffer *rxb)
91c066f2 334{
3d24a9f7 335 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 336 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
337 int txq_id = SEQ_TO_QUEUE(sequence);
338 int index = SEQ_TO_INDEX(sequence);
f2c7e521 339 struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
e039fa4a 340 struct ieee80211_tx_info *info;
91c066f2
TW		 341 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
342 u32 status = le32_to_cpu(tx_resp->status);
343 int rate_idx;
74221d07 344 int fail;
91c066f2
TW		 345
346 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
347 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
348 "is out of range [0-%d] %d %d\n", txq_id,
349 index, txq->q.n_bd, txq->q.write_ptr,
350 txq->q.read_ptr);
351 return;
352 }
353
e039fa4a 354 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 355 ieee80211_tx_info_clear_status(info);
356
357 /* Fill the MRR chain with some info about on-chip retransmissions */
358 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
359 if (info->band == IEEE80211_BAND_5GHZ)
360 rate_idx -= IWL_FIRST_OFDM_RATE;
361
362 fail = tx_resp->failure_frame;
74221d07
AM		 363
364 info->status.rates[0].idx = rate_idx;
365 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 366
91c066f2 367 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 368 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
369 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 370
371 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
372 txq_id, iwl3945_get_tx_fail_reason(status), status,
373 tx_resp->rate, tx_resp->failure_frame);
374
91c066f2
TW		 375 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
376 iwl3945_tx_queue_reclaim(priv, txq_id, index);
377
378 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
379 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
380}
381
382
383
b481de9c
ZY		 384/*****************************************************************************
385 *
386 * Intel PRO/Wireless 3945ABG/BG Network Connection
387 *
388 * RX handler implementations
389 *
b481de9c
ZY		 390 *****************************************************************************/
391
4a8a4322 392void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 393{
3d24a9f7 394 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 395 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 396 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 397 le32_to_cpu(pkt->len));
398
f2c7e521 399 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 400
ab53d8af
MA		 401 iwl3945_led_background(priv);
402
b481de9c
ZY		 403 priv->last_statistics_time = jiffies;
404}
405
17744ff6
TW		 406/******************************************************************************
407 *
408 * Misc. internal state and helper functions
409 *
410 ******************************************************************************/
411#ifdef CONFIG_IWL3945_DEBUG
412
413/**
414 * iwl3945_report_frame - dump frame to syslog during debug sessions
415 *
416 * You may hack this function to show different aspects of received frames,
417 * including selective frame dumps.
418 * group100 parameter selects whether to show 1 out of 100 good frames.
419 */
4a8a4322 420static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 421 struct iwl_rx_packet *pkt,
17744ff6
TW		 422 struct ieee80211_hdr *header, int group100)
423{
424 u32 to_us;
425 u32 print_summary = 0;
426 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
427 u32 hundred = 0;
428 u32 dataframe = 0;
fd7c8a40 429 __le16 fc;
17744ff6
TW		 430 u16 seq_ctl;
431 u16 channel;
432 u16 phy_flags;
433 u16 length;
434 u16 status;
435 u16 bcn_tmr;
436 u32 tsf_low;
437 u64 tsf;
438 u8 rssi;
439 u8 agc;
440 u16 sig_avg;
441 u16 noise_diff;
442 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
443 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
444 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
445 u8 *data = IWL_RX_DATA(pkt);
446
447 /* MAC header */
fd7c8a40 448 fc = header->frame_control;
17744ff6
TW		 449 seq_ctl = le16_to_cpu(header->seq_ctrl);
450
451 /* metadata */
452 channel = le16_to_cpu(rx_hdr->channel);
453 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
454 length = le16_to_cpu(rx_hdr->len);
455
456 /* end-of-frame status and timestamp */
457 status = le32_to_cpu(rx_end->status);
458 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
459 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
460 tsf = le64_to_cpu(rx_end->timestamp);
461
462 /* signal statistics */
463 rssi = rx_stats->rssi;
464 agc = rx_stats->agc;
465 sig_avg = le16_to_cpu(rx_stats->sig_avg);
466 noise_diff = le16_to_cpu(rx_stats->noise_diff);
467
468 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
469
470 /* if data frame is to us and all is good,
471 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 472 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
473 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 474 dataframe = 1;
475 if (!group100)
476 print_summary = 1; /* print each frame */
477 else if (priv->framecnt_to_us < 100) {
478 priv->framecnt_to_us++;
479 print_summary = 0;
480 } else {
481 priv->framecnt_to_us = 0;
482 print_summary = 1;
483 hundred = 1;
484 }
485 } else {
486 /* print summary for all other frames */
487 print_summary = 1;
488 }
489
490 if (print_summary) {
491 char *title;
0ff1cca0 492 int rate;
17744ff6
TW		 493
494 if (hundred)
495 title = "100Frames";
fd7c8a40 496 else if (ieee80211_has_retry(fc))
17744ff6 497 title = "Retry";
fd7c8a40 498 else if (ieee80211_is_assoc_resp(fc))
17744ff6 499 title = "AscRsp";
fd7c8a40 500 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 501 title = "RasRsp";
fd7c8a40 502 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 503 title = "PrbRsp";
504 print_dump = 1; /* dump frame contents */
505 } else if (ieee80211_is_beacon(fc)) {
506 title = "Beacon";
507 print_dump = 1; /* dump frame contents */
508 } else if (ieee80211_is_atim(fc))
509 title = "ATIM";
510 else if (ieee80211_is_auth(fc))
511 title = "Auth";
512 else if (ieee80211_is_deauth(fc))
513 title = "DeAuth";
514 else if (ieee80211_is_disassoc(fc))
515 title = "DisAssoc";
516 else
517 title = "Frame";
518
519 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
520 if (rate == -1)
521 rate = 0;
522 else
523 rate = iwl3945_rates[rate].ieee / 2;
524
525 /* print frame summary.
526 * MAC addresses show just the last byte (for brevity),
527 * but you can hack it to show more, if you'd like to. */
528 if (dataframe)
529 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 530 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 531 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 532 length, rssi, channel, rate);
533 else {
534 /* src/dst addresses assume managed mode */
535 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
536 "src=0x%02x, rssi=%u, tim=%lu usec, "
537 "phy=0x%02x, chnl=%d\n",
fd7c8a40 538 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 539 header->addr3[5], rssi,
540 tsf_low - priv->scan_start_tsf,
541 phy_flags, channel);
542 }
543 }
544 if (print_dump)
40b8ec0b 545 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6
TW		 546}
547#else
4a8a4322 548static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 549 struct iwl_rx_packet *pkt,
17744ff6
TW		 550 struct ieee80211_hdr *header, int group100)
551{
552}
553#endif
554
4bd9b4f3 555/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 556static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 557 struct ieee80211_hdr *header)
558{
559 /* Filter incoming packets to determine if they are targeted toward
560 * this network, discarding packets coming from ourselves */
561 switch (priv->iw_mode) {
05c914fe 562 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 563 /* packets to our IBSS update information */
564 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 565 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 566 /* packets to our IBSS update information */
567 return !compare_ether_addr(header->addr2, priv->bssid);
568 default:
569 return 1;
570 }
571}
17744ff6 572
4a8a4322 573static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 574 struct iwl_rx_mem_buffer *rxb,
12342c47 575 struct ieee80211_rx_status *stats)
b481de9c 576{
3d24a9f7 577 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
699669f3 578#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 579 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 580#endif
bb8c093b
CH		 581 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
582 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 583 short len = le16_to_cpu(rx_hdr->len);
584
585 /* We received data from the HW, so stop the watchdog */
3d24a9f7 586 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
b481de9c
ZY		 587 IWL_DEBUG_DROP("Corruption detected!\n");
588 return;
589 }
590
591 /* We only process data packets if the interface is open */
592 if (unlikely(!priv->is_open)) {
593 IWL_DEBUG_DROP_LIMIT
594 ("Dropping packet while interface is not open.\n");
595 return;
596 }
b481de9c
ZY		 597
598 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
599 /* Set the size of the skb to the size of the frame */
600 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
601
bb8c093b
CH		 602 if (iwl3945_param_hwcrypto)
603 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 604 le32_to_cpu(rx_end->status), stats);
605
ab53d8af 606#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 607 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 608 priv->rxtxpackets += len;
609#endif
b481de9c
ZY		 610 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
611 rxb->skb = NULL;
612}
613
7878a5a4
MA		 614#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
615
4a8a4322 616static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 617 struct iwl_rx_mem_buffer *rxb)
b481de9c 618{
17744ff6
TW		 619 struct ieee80211_hdr *header;
620 struct ieee80211_rx_status rx_status;
3d24a9f7 621 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 622 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
623 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
624 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 625 int snr;
b481de9c
ZY		 626 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
627 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 628 u8 network_packet;
17744ff6 629
17744ff6
TW		 630 rx_status.flag = 0;
631 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 632 rx_status.freq =
c0186078 633 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 634 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
635 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
636
637 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 638 if (rx_status.band == IEEE80211_BAND_5GHZ)
639 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 640
6f0a2c4d
BR		 641 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
642 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
643
644 /* set the preamble flag if appropriate */
645 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
646 rx_status.flag |= RX_FLAG_SHORTPRE;
647
b481de9c
ZY		 648 if ((unlikely(rx_stats->phy_count > 20))) {
649 IWL_DEBUG_DROP
650 ("dsp size out of range [0,20]: "
651 "%d/n", rx_stats->phy_count);
652 return;
653 }
654
655 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
656 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
657 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
658 return;
659 }
660
56decd3c 661
b481de9c
ZY		 662
663 /* Convert 3945's rssi indicator to dBm */
250bdd21 664 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 665
666 /* Set default noise value to -127 */
667 if (priv->last_rx_noise == 0)
668 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
669
670 /* 3945 provides noise info for OFDM frames only.
671 * sig_avg and noise_diff are measured by the 3945's digital signal
672 * processor (DSP), and indicate linear levels of signal level and
673 * distortion/noise within the packet preamble after
674 * automatic gain control (AGC). sig_avg should stay fairly
675 * constant if the radio's AGC is working well.
676 * Since these values are linear (not dB or dBm), linear
677 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
678 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
679 * to obtain noise level in dBm.
17744ff6 680 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 681 if (rx_stats_noise_diff) {
682 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 683 rx_status.noise = rx_status.signal -
17744ff6 684 iwl3945_calc_db_from_ratio(snr);
566bfe5a 685 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 686 rx_status.noise);
b481de9c
ZY		 687
688 /* If noise info not available, calculate signal quality indicator (%)
689 * using just the dBm signal level. */
690 } else {
17744ff6 691 rx_status.noise = priv->last_rx_noise;
566bfe5a 692 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 693 }
694
695
696 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 697 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 698 rx_stats_sig_avg, rx_stats_noise_diff);
699
b481de9c
ZY		 700 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
701
bb8c093b 702 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 703
17744ff6
TW		 704 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
705 network_packet ? '*' : ' ',
706 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 707 rx_status.signal, rx_status.signal,
708 rx_status.noise, rx_status.rate_idx);
b481de9c 709
17744ff6 710#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 711 if (priv->debug_level & (IWL_DL_RX))
b481de9c 712 /* Set "1" to report good data frames in groups of 100 */
17744ff6 713 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 714#endif
715
716 if (network_packet) {
717 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
718 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 719 priv->last_rx_rssi = rx_status.signal;
17744ff6 720 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 721 }
722
12e5e22d 723 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 724}
725
4a8a4322 726int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 727 dma_addr_t addr, u16 len)
728{
729 int count;
730 u32 pad;
bb8c093b 731 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
b481de9c
ZY		 732
733 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
734 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
735
736 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
737 IWL_ERROR("Error can not send more than %d chunks\n",
738 NUM_TFD_CHUNKS);
739 return -EINVAL;
740 }
741
742 tfd->pa[count].addr = cpu_to_le32(addr);
743 tfd->pa[count].len = cpu_to_le32(len);
744
745 count++;
746
747 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
748 TFD_CTL_PAD_SET(pad));
749
750 return 0;
751}
752
753/**
bb8c093b 754 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 755 *
756 * Does NOT advance any indexes
757 */
4a8a4322 758int iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 759{
bb8c093b
CH		 760 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
761 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 762 struct pci_dev *dev = priv->pci_dev;
763 int i;
764 int counter;
765
766 /* classify bd */
767 if (txq->q.id == IWL_CMD_QUEUE_NUM)
768 /* nothing to cleanup after for host commands */
769 return 0;
770
771 /* sanity check */
772 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
773 if (counter > NUM_TFD_CHUNKS) {
774 IWL_ERROR("Too many chunks: %i\n", counter);
775 /* @todo issue fatal error, it is quite serious situation */
776 return 0;
777 }
778
779 /* unmap chunks if any */
780
781 for (i = 1; i < counter; i++) {
782 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
783 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 784 if (txq->txb[txq->q.read_ptr].skb[0]) {
785 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
786 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 787 /* Can be called from interrupt context */
788 dev_kfree_skb_any(skb);
fc4b6853 789 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 790 }
791 }
792 }
793 return 0;
794}
795
4a8a4322 796u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c 797{
c93007ef 798 int i, start = IWL_AP_ID;
b481de9c
ZY		 799 int ret = IWL_INVALID_STATION;
800 unsigned long flags;
801
c93007ef
SO		 802 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
803 (priv->iw_mode == NL80211_IFTYPE_AP))
804 start = IWL_STA_ID;
805
806 if (is_broadcast_ether_addr(addr))
3832ec9d 807 return priv->hw_params.bcast_sta_id;
c93007ef 808
b481de9c 809 spin_lock_irqsave(&priv->sta_lock, flags);
3832ec9d 810 for (i = start; i < priv->hw_params.max_stations; i++)
f2c7e521 811 if ((priv->stations_39[i].used) &&
b481de9c 812 (!compare_ether_addr
f2c7e521 813 (priv->stations_39[i].sta.sta.addr, addr))) {
b481de9c
ZY		 814 ret = i;
815 goto out;
816 }
817
e174961c
JB		 818 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
819 addr, priv->num_stations);
b481de9c
ZY		 820 out:
821 spin_unlock_irqrestore(&priv->sta_lock, flags);
822 return ret;
823}
824
825/**
bb8c093b 826 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 827 *
828*/
4a8a4322 829void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
bb8c093b 830 struct iwl3945_cmd *cmd,
e039fa4a 831 struct ieee80211_tx_info *info,
b481de9c
ZY		 832 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
833{
e039fa4a 834 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 835 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 836 u16 rate_mask;
837 int rate;
838 u8 rts_retry_limit;
839 u8 data_retry_limit;
840 __le32 tx_flags;
fd7c8a40 841 __le16 fc = hdr->frame_control;
b481de9c 842
bb8c093b 843 rate = iwl3945_rates[rate_index].plcp;
b481de9c
ZY		 844 tx_flags = cmd->cmd.tx.tx_flags;
845
846 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 847 * in this running context */
b481de9c
ZY		 848 rate_mask = IWL_RATES_MASK;
849
b481de9c
ZY		 850 if (tx_id >= IWL_CMD_QUEUE_NUM)
851 rts_retry_limit = 3;
852 else
853 rts_retry_limit = 7;
854
fd7c8a40 855 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 856 data_retry_limit = 3;
857 if (data_retry_limit < rts_retry_limit)
858 rts_retry_limit = data_retry_limit;
859 } else
860 data_retry_limit = IWL_DEFAULT_TX_RETRY;
861
862 if (priv->data_retry_limit != -1)
863 data_retry_limit = priv->data_retry_limit;
864
fd7c8a40
HH		 865 if (ieee80211_is_mgmt(fc)) {
866 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
867 case cpu_to_le16(IEEE80211_STYPE_AUTH):
868 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
869 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
870 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 871 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
872 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
873 tx_flags |= TX_CMD_FLG_CTS_MSK;
874 }
875 break;
876 default:
877 break;
878 }
879 }
880
881 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
882 cmd->cmd.tx.data_retry_limit = data_retry_limit;
883 cmd->cmd.tx.rate = rate;
884 cmd->cmd.tx.tx_flags = tx_flags;
885
886 /* OFDM */
14577f23
MA		 887 cmd->cmd.tx.supp_rates[0] =
888 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 889
890 /* CCK */
14577f23 891 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 892
893 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
894 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
895 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
896 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
897}
898
4a8a4322 899u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 900{
901 unsigned long flags_spin;
bb8c093b 902 struct iwl3945_station_entry *station;
b481de9c
ZY		 903
904 if (sta_id == IWL_INVALID_STATION)
905 return IWL_INVALID_STATION;
906
907 spin_lock_irqsave(&priv->sta_lock, flags_spin);
f2c7e521 908 station = &priv->stations_39[sta_id];
b481de9c
ZY		 909
910 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
911 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 912 station->sta.mode = STA_CONTROL_MODIFY_MSK;
913
914 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
915
bb8c093b 916 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 917 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
918 sta_id, tx_rate);
919 return sta_id;
920}
921
4a8a4322 922static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
b481de9c
ZY		 923{
924 int rc;
925 unsigned long flags;
926
927 spin_lock_irqsave(&priv->lock, flags);
5d49f498 928 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 929 if (rc) {
930 spin_unlock_irqrestore(&priv->lock, flags);
931 return rc;
932 }
933
934 if (!pwr_max) {
935 u32 val;
936
937 rc = pci_read_config_dword(priv->pci_dev,
938 PCI_POWER_SOURCE, &val);
939 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
5d49f498 940 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 941 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
942 ~APMG_PS_CTRL_MSK_PWR_SRC);
5d49f498 943 iwl_release_nic_access(priv);
b481de9c 944
5d49f498 945 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 946 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
947 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
948 } else
5d49f498 949 iwl_release_nic_access(priv);
b481de9c 950 } else {
5d49f498 951 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 952 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
953 ~APMG_PS_CTRL_MSK_PWR_SRC);
954
5d49f498
AK		 955 iwl_release_nic_access(priv);
956 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 957 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
958 }
959 spin_unlock_irqrestore(&priv->lock, flags);
960
961 return rc;
962}
963
4a8a4322 964static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c
ZY		 965{
966 int rc;
967 unsigned long flags;
968
969 spin_lock_irqsave(&priv->lock, flags);
5d49f498 970 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 971 if (rc) {
972 spin_unlock_irqrestore(&priv->lock, flags);
973 return rc;
974 }
975
5d49f498
AK		 976 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
977 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0),
3832ec9d 978 priv->shared_phys +
bb8c093b 979 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
5d49f498
AK		 980 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
981 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 982 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
983 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
984 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
985 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
986 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
987 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
988 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
989 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 990
991 /* fake read to flush all prev I/O */
5d49f498 992 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 993
5d49f498 994 iwl_release_nic_access(priv);
b481de9c
ZY		 995 spin_unlock_irqrestore(&priv->lock, flags);
996
997 return 0;
998}
999
4a8a4322 1000static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1001{
1002 int rc;
1003 unsigned long flags;
1004
1005 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1006 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1007 if (rc) {
1008 spin_unlock_irqrestore(&priv->lock, flags);
1009 return rc;
1010 }
1011
1012 /* bypass mode */
5d49f498 1013 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 1014
1015 /* RA 0 is active */
5d49f498 1016 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1017
1018 /* all 6 fifo are active */
5d49f498 1019 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1020
5d49f498
AK		 1021 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1022 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1023 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1024 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1025
5d49f498 1026 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 1027 priv->shared_phys);
b481de9c 1028
5d49f498 1029 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 1030 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1031 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1032 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1033 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1034 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1035 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1036 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 1037
5d49f498 1038 iwl_release_nic_access(priv);
b481de9c
ZY		 1039 spin_unlock_irqrestore(&priv->lock, flags);
1040
1041 return 0;
1042}
1043
1044/**
1045 * iwl3945_txq_ctx_reset - Reset TX queue context
1046 *
1047 * Destroys all DMA structures and initialize them again
1048 */
4a8a4322 1049static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1050{
1051 int rc;
1052 int txq_id, slots_num;
1053
bb8c093b 1054 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1055
1056 /* Tx CMD queue */
1057 rc = iwl3945_tx_reset(priv);
1058 if (rc)
1059 goto error;
1060
1061 /* Tx queue(s) */
1062 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1063 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1064 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
f2c7e521 1065 rc = iwl3945_tx_queue_init(priv, &priv->txq39[txq_id], slots_num,
b481de9c
ZY		 1066 txq_id);
1067 if (rc) {
1068 IWL_ERROR("Tx %d queue init failed\n", txq_id);
1069 goto error;
1070 }
1071 }
1072
1073 return rc;
1074
1075 error:
bb8c093b 1076 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1077 return rc;
1078}
1079
4a8a4322 1080int iwl3945_hw_nic_init(struct iwl_priv *priv)
b481de9c
ZY		 1081{
1082 u8 rev_id;
1083 int rc;
1084 unsigned long flags;
cc2f362c 1085 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1086
bb8c093b 1087 iwl3945_power_init_handle(priv);
b481de9c
ZY		 1088
1089 spin_lock_irqsave(&priv->lock, flags);
5d49f498
AK		 1090 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
1091 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 1092 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1093
5d49f498
AK		 1094 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1095 rc = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1096 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c
ZY		 1097 if (rc < 0) {
1098 spin_unlock_irqrestore(&priv->lock, flags);
1099 IWL_DEBUG_INFO("Failed to init the card\n");
1100 return rc;
1101 }
1102
5d49f498 1103 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1104 if (rc) {
1105 spin_unlock_irqrestore(&priv->lock, flags);
1106 return rc;
1107 }
5d49f498 1108 iwl_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1109 APMG_CLK_VAL_DMA_CLK_RQT |
1110 APMG_CLK_VAL_BSM_CLK_RQT);
1111 udelay(20);
5d49f498 1112 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c 1113 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
5d49f498 1114 iwl_release_nic_access(priv);
b481de9c
ZY		 1115 spin_unlock_irqrestore(&priv->lock, flags);
1116
1117 /* Determine HW type */
1118 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1119 if (rc)
1120 return rc;
1121 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1122
1123 iwl3945_nic_set_pwr_src(priv, 1);
1124 spin_lock_irqsave(&priv->lock, flags);
1125
1126 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1127 IWL_DEBUG_INFO("RTP type \n");
1128 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1129 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
5d49f498 1130 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1131 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1132 } else {
6f83eaa1 1133 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
5d49f498 1134 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1135 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1136 }
1137
f2c7e521 1138 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) {
b481de9c 1139 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
5d49f498 1140 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1141 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1142 } else
1143 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1144
f2c7e521 1145 if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) {
b481de9c 1146 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
f2c7e521 1147 priv->eeprom39.board_revision);
5d49f498 1148 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1149 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1150 } else {
1151 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
f2c7e521 1152 priv->eeprom39.board_revision);
5d49f498 1153 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1154 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1155 }
1156
f2c7e521 1157 if (priv->eeprom39.almgor_m_version <= 1) {
5d49f498 1158 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1159 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c 1160 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
f2c7e521 1161 priv->eeprom39.almgor_m_version);
b481de9c
ZY		 1162 } else {
1163 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
f2c7e521 1164 priv->eeprom39.almgor_m_version);
5d49f498 1165 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1166 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1167 }
1168 spin_unlock_irqrestore(&priv->lock, flags);
1169
f2c7e521 1170 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
b481de9c
ZY		 1171 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1172
f2c7e521 1173 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
b481de9c
ZY		 1174 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1175
1176 /* Allocate the RX queue, or reset if it is already allocated */
1177 if (!rxq->bd) {
bb8c093b 1178 rc = iwl3945_rx_queue_alloc(priv);
b481de9c
ZY		 1179 if (rc) {
1180 IWL_ERROR("Unable to initialize Rx queue\n");
1181 return -ENOMEM;
1182 }
1183 } else
bb8c093b 1184 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1185
bb8c093b 1186 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1187
1188 iwl3945_rx_init(priv, rxq);
1189
1190 spin_lock_irqsave(&priv->lock, flags);
1191
1192 /* Look at using this instead:
1193 rxq->need_update = 1;
bb8c093b 1194 iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1195 */
1196
5d49f498 1197 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1198 if (rc) {
1199 spin_unlock_irqrestore(&priv->lock, flags);
1200 return rc;
1201 }
5d49f498
AK		 1202 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1203 iwl_release_nic_access(priv);
b481de9c
ZY		 1204
1205 spin_unlock_irqrestore(&priv->lock, flags);
1206
1207 rc = iwl3945_txq_ctx_reset(priv);
1208 if (rc)
1209 return rc;
1210
1211 set_bit(STATUS_INIT, &priv->status);
1212
1213 return 0;
1214}
1215
1216/**
bb8c093b 1217 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1218 *
1219 * Destroy all TX DMA queues and structures
1220 */
4a8a4322 1221void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1222{
1223 int txq_id;
1224
1225 /* Tx queues */
1226 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
f2c7e521 1227 iwl3945_tx_queue_free(priv, &priv->txq39[txq_id]);
b481de9c
ZY		 1228}
1229
4a8a4322 1230void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1231{
bddadf86 1232 int txq_id;
b481de9c
ZY		 1233 unsigned long flags;
1234
1235 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1236 if (iwl_grab_nic_access(priv)) {
b481de9c 1237 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1238 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1239 return;
1240 }
1241
1242 /* stop SCD */
5d49f498 1243 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1244
1245 /* reset TFD queues */
bddadf86 1246 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
5d49f498
AK		 1247 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1248 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1249 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1250 1000);
1251 }
1252
5d49f498 1253 iwl_release_nic_access(priv);
b481de9c
ZY		 1254 spin_unlock_irqrestore(&priv->lock, flags);
1255
bb8c093b 1256 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1257}
1258
4a8a4322 1259int iwl3945_hw_nic_stop_master(struct iwl_priv *priv)
b481de9c
ZY		 1260{
1261 int rc = 0;
1262 u32 reg_val;
1263 unsigned long flags;
1264
1265 spin_lock_irqsave(&priv->lock, flags);
1266
1267 /* set stop master bit */
5d49f498 1268 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1269
5d49f498 1270 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 1271
1272 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1273 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1274 IWL_DEBUG_INFO("Card in power save, master is already "
1275 "stopped\n");
1276 else {
5d49f498 1277 rc = iwl_poll_direct_bit(priv, CSR_RESET,
b481de9c
ZY		 1278 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1279 if (rc < 0) {
1280 spin_unlock_irqrestore(&priv->lock, flags);
1281 return rc;
1282 }
1283 }
1284
1285 spin_unlock_irqrestore(&priv->lock, flags);
1286 IWL_DEBUG_INFO("stop master\n");
1287
1288 return rc;
1289}
1290
4a8a4322 1291int iwl3945_hw_nic_reset(struct iwl_priv *priv)
b481de9c
ZY		 1292{
1293 int rc;
1294 unsigned long flags;
1295
bb8c093b 1296 iwl3945_hw_nic_stop_master(priv);
b481de9c
ZY		 1297
1298 spin_lock_irqsave(&priv->lock, flags);
1299
5d49f498 1300 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c 1301
5d49f498 1302 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1303 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1304
5d49f498 1305 rc = iwl_grab_nic_access(priv);
b481de9c 1306 if (!rc) {
5d49f498 1307 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1308 APMG_CLK_VAL_BSM_CLK_RQT);
1309
1310 udelay(10);
1311
5d49f498 1312 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1313 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1314
5d49f498
AK		 1315 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1316 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1317 0xFFFFFFFF);
1318
1319 /* enable DMA */
5d49f498 1320 iwl_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1321 APMG_CLK_VAL_DMA_CLK_RQT |
1322 APMG_CLK_VAL_BSM_CLK_RQT);
1323 udelay(10);
1324
5d49f498 1325 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1326 APMG_PS_CTRL_VAL_RESET_REQ);
1327 udelay(5);
5d49f498 1328 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1329 APMG_PS_CTRL_VAL_RESET_REQ);
5d49f498 1330 iwl_release_nic_access(priv);
b481de9c
ZY		 1331 }
1332
1333 /* Clear the 'host command active' bit... */
1334 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1335
1336 wake_up_interruptible(&priv->wait_command_queue);
1337 spin_unlock_irqrestore(&priv->lock, flags);
1338
1339 return rc;
1340}
1341
1342/**
bb8c093b 1343 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1344 * return index delta into power gain settings table
1345*/
bb8c093b 1346static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1347{
1348 return (new_reading - old_reading) * (-11) / 100;
1349}
1350
1351/**
bb8c093b 1352 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1353 */
bb8c093b 1354static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1355{
3ac7f146 1356 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1357}
1358
4a8a4322 1359int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1360{
5d49f498 1361 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1362}
1363
1364/**
bb8c093b 1365 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1366 * get the current temperature by reading from NIC
1367*/
4a8a4322 1368static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 1369{
1370 int temperature;
1371
bb8c093b 1372 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1373
1374 /* driver's okay range is -260 to +25.
1375 * human readable okay range is 0 to +285 */
1376 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1377
1378 /* handle insane temp reading */
bb8c093b 1379 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
b481de9c
ZY		 1380 IWL_ERROR("Error bad temperature value %d\n", temperature);
1381
1382 /* if really really hot(?),
1383 * substitute the 3rd band/group's temp measured at factory */
1384 if (priv->last_temperature > 100)
f2c7e521 1385 temperature = priv->eeprom39.groups[2].temperature;
b481de9c
ZY		 1386 else /* else use most recent "sane" value from driver */
1387 temperature = priv->last_temperature;
1388 }
1389
1390 return temperature; /* raw, not "human readable" */
1391}
1392
1393/* Adjust Txpower only if temperature variance is greater than threshold.
1394 *
1395 * Both are lower than older versions' 9 degrees */
1396#define IWL_TEMPERATURE_LIMIT_TIMER 6
1397
1398/**
1399 * is_temp_calib_needed - determines if new calibration is needed
1400 *
1401 * records new temperature in tx_mgr->temperature.
1402 * replaces tx_mgr->last_temperature *only* if calib needed
1403 * (assumes caller will actually do the calibration!). */
4a8a4322 1404static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1405{
1406 int temp_diff;
1407
bb8c093b 1408 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1409 temp_diff = priv->temperature - priv->last_temperature;
1410
1411 /* get absolute value */
1412 if (temp_diff < 0) {
1413 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1414 temp_diff = -temp_diff;
1415 } else if (temp_diff == 0)
1416 IWL_DEBUG_POWER("Same temp,\n");
1417 else
1418 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1419
1420 /* if we don't need calibration, *don't* update last_temperature */
1421 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1422 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1423 return 0;
1424 }
1425
1426 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1427
1428 /* assume that caller will actually do calib ...
1429 * update the "last temperature" value */
1430 priv->last_temperature = priv->temperature;
1431 return 1;
1432}
1433
1434#define IWL_MAX_GAIN_ENTRIES 78
1435#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1436#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1437
1438/* radio and DSP power table, each step is 1/2 dB.
1439 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1440static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1441 {
1442 {251, 127}, /* 2.4 GHz, highest power */
1443 {251, 127},
1444 {251, 127},
1445 {251, 127},
1446 {251, 125},
1447 {251, 110},
1448 {251, 105},
1449 {251, 98},
1450 {187, 125},
1451 {187, 115},
1452 {187, 108},
1453 {187, 99},
1454 {243, 119},
1455 {243, 111},
1456 {243, 105},
1457 {243, 97},
1458 {243, 92},
1459 {211, 106},
1460 {211, 100},
1461 {179, 120},
1462 {179, 113},
1463 {179, 107},
1464 {147, 125},
1465 {147, 119},
1466 {147, 112},
1467 {147, 106},
1468 {147, 101},
1469 {147, 97},
1470 {147, 91},
1471 {115, 107},
1472 {235, 121},
1473 {235, 115},
1474 {235, 109},
1475 {203, 127},
1476 {203, 121},
1477 {203, 115},
1478 {203, 108},
1479 {203, 102},
1480 {203, 96},
1481 {203, 92},
1482 {171, 110},
1483 {171, 104},
1484 {171, 98},
1485 {139, 116},
1486 {227, 125},
1487 {227, 119},
1488 {227, 113},
1489 {227, 107},
1490 {227, 101},
1491 {227, 96},
1492 {195, 113},
1493 {195, 106},
1494 {195, 102},
1495 {195, 95},
1496 {163, 113},
1497 {163, 106},
1498 {163, 102},
1499 {163, 95},
1500 {131, 113},
1501 {131, 106},
1502 {131, 102},
1503 {131, 95},
1504 {99, 113},
1505 {99, 106},
1506 {99, 102},
1507 {99, 95},
1508 {67, 113},
1509 {67, 106},
1510 {67, 102},
1511 {67, 95},
1512 {35, 113},
1513 {35, 106},
1514 {35, 102},
1515 {35, 95},
1516 {3, 113},
1517 {3, 106},
1518 {3, 102},
1519 {3, 95} }, /* 2.4 GHz, lowest power */
1520 {
1521 {251, 127}, /* 5.x GHz, highest power */
1522 {251, 120},
1523 {251, 114},
1524 {219, 119},
1525 {219, 101},
1526 {187, 113},
1527 {187, 102},
1528 {155, 114},
1529 {155, 103},
1530 {123, 117},
1531 {123, 107},
1532 {123, 99},
1533 {123, 92},
1534 {91, 108},
1535 {59, 125},
1536 {59, 118},
1537 {59, 109},
1538 {59, 102},
1539 {59, 96},
1540 {59, 90},
1541 {27, 104},
1542 {27, 98},
1543 {27, 92},
1544 {115, 118},
1545 {115, 111},
1546 {115, 104},
1547 {83, 126},
1548 {83, 121},
1549 {83, 113},
1550 {83, 105},
1551 {83, 99},
1552 {51, 118},
1553 {51, 111},
1554 {51, 104},
1555 {51, 98},
1556 {19, 116},
1557 {19, 109},
1558 {19, 102},
1559 {19, 98},
1560 {19, 93},
1561 {171, 113},
1562 {171, 107},
1563 {171, 99},
1564 {139, 120},
1565 {139, 113},
1566 {139, 107},
1567 {139, 99},
1568 {107, 120},
1569 {107, 113},
1570 {107, 107},
1571 {107, 99},
1572 {75, 120},
1573 {75, 113},
1574 {75, 107},
1575 {75, 99},
1576 {43, 120},
1577 {43, 113},
1578 {43, 107},
1579 {43, 99},
1580 {11, 120},
1581 {11, 113},
1582 {11, 107},
1583 {11, 99},
1584 {131, 107},
1585 {131, 99},
1586 {99, 120},
1587 {99, 113},
1588 {99, 107},
1589 {99, 99},
1590 {67, 120},
1591 {67, 113},
1592 {67, 107},
1593 {67, 99},
1594 {35, 120},
1595 {35, 113},
1596 {35, 107},
1597 {35, 99},
1598 {3, 120} } /* 5.x GHz, lowest power */
1599};
1600
bb8c093b 1601static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1602{
1603 if (index < 0)
1604 return 0;
1605 if (index >= IWL_MAX_GAIN_ENTRIES)
1606 return IWL_MAX_GAIN_ENTRIES - 1;
1607 return (u8) index;
1608}
1609
1610/* Kick off thermal recalibration check every 60 seconds */
1611#define REG_RECALIB_PERIOD (60)
1612
1613/**
bb8c093b 1614 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1615 *
1616 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1617 * or 6 Mbit (OFDM) rates.
1618 */
4a8a4322 1619static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1620 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1621 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1622 int band_index)
1623{
bb8c093b 1624 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1625 s8 power;
1626 u8 power_index;
1627
1628 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1629
1630 /* use this channel group's 6Mbit clipping/saturation pwr,
1631 * but cap at regulatory scan power restriction (set during init
1632 * based on eeprom channel data) for this channel. */
14577f23 1633 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1634
1635 /* further limit to user's max power preference.
1636 * FIXME: Other spectrum management power limitations do not
1637 * seem to apply?? */
1638 power = min(power, priv->user_txpower_limit);
1639 scan_power_info->requested_power = power;
1640
1641 /* find difference between new scan *power* and current "normal"
1642 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1643 * current "normal" temperature-compensated Tx power *index* for
1644 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1645 * *index*. */
1646 power_index = ch_info->power_info[rate_index].power_table_index
1647 - (power - ch_info->power_info
14577f23 1648 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1649
1650 /* store reference index that we use when adjusting *all* scan
1651 * powers. So we can accommodate user (all channel) or spectrum
1652 * management (single channel) power changes "between" temperature
1653 * feedback compensation procedures.
1654 * don't force fit this reference index into gain table; it may be a
1655 * negative number. This will help avoid errors when we're at
1656 * the lower bounds (highest gains, for warmest temperatures)
1657 * of the table. */
1658
1659 /* don't exceed table bounds for "real" setting */
bb8c093b 1660 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1661
1662 scan_power_info->power_table_index = power_index;
1663 scan_power_info->tpc.tx_gain =
1664 power_gain_table[band_index][power_index].tx_gain;
1665 scan_power_info->tpc.dsp_atten =
1666 power_gain_table[band_index][power_index].dsp_atten;
1667}
1668
1669/**
bb8c093b 1670 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
b481de9c
ZY		 1671 *
1672 * Configures power settings for all rates for the current channel,
1673 * using values from channel info struct, and send to NIC
1674 */
4a8a4322 1675int iwl3945_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 1676{
14577f23 1677 int rate_idx, i;
d20b3c65 1678 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1679 struct iwl3945_txpowertable_cmd txpower = {
f2c7e521 1680 .channel = priv->active39_rxon.channel,
b481de9c
ZY		 1681 };
1682
8318d78a 1683 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
bb8c093b 1684 ch_info = iwl3945_get_channel_info(priv,
8318d78a 1685 priv->band,
f2c7e521 1686 le16_to_cpu(priv->active39_rxon.channel));
b481de9c
ZY		 1687 if (!ch_info) {
1688 IWL_ERROR
1689 ("Failed to get channel info for channel %d [%d]\n",
f2c7e521 1690 le16_to_cpu(priv->active39_rxon.channel), priv->band);
b481de9c
ZY		 1691 return -EINVAL;
1692 }
1693
1694 if (!is_channel_valid(ch_info)) {
1695 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1696 "non-Tx channel.\n");
1697 return 0;
1698 }
1699
1700 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1701 /* Fill OFDM rate */
1702 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1703 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1704
1705 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1706 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1707
1708 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1709 le16_to_cpu(txpower.channel),
1710 txpower.band,
14577f23
MA		 1711 txpower.power[i].tpc.tx_gain,
1712 txpower.power[i].tpc.dsp_atten,
1713 txpower.power[i].rate);
1714 }
1715 /* Fill CCK rates */
1716 for (rate_idx = IWL_FIRST_CCK_RATE;
1717 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1718 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1719 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1720
1721 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1722 le16_to_cpu(txpower.channel),
1723 txpower.band,
1724 txpower.power[i].tpc.tx_gain,
1725 txpower.power[i].tpc.dsp_atten,
1726 txpower.power[i].rate);
b481de9c
ZY		 1727 }
1728
bb8c093b
CH		 1729 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1730 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
b481de9c
ZY		 1731
1732}
1733
1734/**
bb8c093b 1735 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1736 * @ch_info: Channel to update. Uses power_info.requested_power.
1737 *
1738 * Replace requested_power and base_power_index ch_info fields for
1739 * one channel.
1740 *
1741 * Called if user or spectrum management changes power preferences.
1742 * Takes into account h/w and modulation limitations (clip power).
1743 *
1744 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1745 *
1746 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1747 * properly fill out the scan powers, and actual h/w gain settings,
1748 * and send changes to NIC
1749 */
4a8a4322 1750static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1751 struct iwl_channel_info *ch_info)
b481de9c 1752{
bb8c093b 1753 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1754 int power_changed = 0;
1755 int i;
1756 const s8 *clip_pwrs;
1757 int power;
1758
1759 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1760 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1761
1762 /* Get this channel's rate-to-current-power settings table */
1763 power_info = ch_info->power_info;
1764
1765 /* update OFDM Txpower settings */
14577f23 1766 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1767 i++, ++power_info) {
1768 int delta_idx;
1769
1770 /* limit new power to be no more than h/w capability */
1771 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1772 if (power == power_info->requested_power)
1773 continue;
1774
1775 /* find difference between old and new requested powers,
1776 * update base (non-temp-compensated) power index */
1777 delta_idx = (power - power_info->requested_power) * 2;
1778 power_info->base_power_index -= delta_idx;
1779
1780 /* save new requested power value */
1781 power_info->requested_power = power;
1782
1783 power_changed = 1;
1784 }
1785
1786 /* update CCK Txpower settings, based on OFDM 12M setting ...
1787 * ... all CCK power settings for a given channel are the *same*. */
1788 if (power_changed) {
1789 power =
14577f23 1790 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1791 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1792
bb8c093b 1793 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1794 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1795 power_info->requested_power = power;
1796 power_info->base_power_index =
14577f23 1797 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1798 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1799 ++power_info;
1800 }
1801 }
1802
1803 return 0;
1804}
1805
1806/**
bb8c093b 1807 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1808 *
1809 * NOTE: Returned power limit may be less (but not more) than requested,
1810 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1811 * (no consideration for h/w clipping limitations).
1812 */
d20b3c65 1813static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1814{
1815 s8 max_power;
1816
1817#if 0
1818 /* if we're using TGd limits, use lower of TGd or EEPROM */
1819 if (ch_info->tgd_data.max_power != 0)
1820 max_power = min(ch_info->tgd_data.max_power,
1821 ch_info->eeprom.max_power_avg);
1822
1823 /* else just use EEPROM limits */
1824 else
1825#endif
1826 max_power = ch_info->eeprom.max_power_avg;
1827
1828 return min(max_power, ch_info->max_power_avg);
1829}
1830
1831/**
bb8c093b 1832 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1833 *
1834 * Compensate txpower settings of *all* channels for temperature.
1835 * This only accounts for the difference between current temperature
1836 * and the factory calibration temperatures, and bases the new settings
1837 * on the channel's base_power_index.
1838 *
1839 * If RxOn is "associated", this sends the new Txpower to NIC!
1840 */
4a8a4322 1841static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1842{
d20b3c65 1843 struct iwl_channel_info *ch_info = NULL;
b481de9c
ZY		 1844 int delta_index;
1845 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1846 u8 a_band;
1847 u8 rate_index;
1848 u8 scan_tbl_index;
1849 u8 i;
1850 int ref_temp;
1851 int temperature = priv->temperature;
1852
1853 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1854 for (i = 0; i < priv->channel_count; i++) {
1855 ch_info = &priv->channel_info[i];
1856 a_band = is_channel_a_band(ch_info);
1857
1858 /* Get this chnlgrp's factory calibration temperature */
f2c7e521 1859 ref_temp = (s16)priv->eeprom39.groups[ch_info->group_index].
b481de9c
ZY		 1860 temperature;
1861
a96a27f9 1862 /* get power index adjustment based on current and factory
b481de9c 1863 * temps */
bb8c093b 1864 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1865 ref_temp);
1866
1867 /* set tx power value for all rates, OFDM and CCK */
1868 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1869 rate_index++) {
1870 int power_idx =
1871 ch_info->power_info[rate_index].base_power_index;
1872
1873 /* temperature compensate */
1874 power_idx += delta_index;
1875
1876 /* stay within table range */
bb8c093b 1877 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1878 ch_info->power_info[rate_index].
1879 power_table_index = (u8) power_idx;
1880 ch_info->power_info[rate_index].tpc =
1881 power_gain_table[a_band][power_idx];
1882 }
1883
1884 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1885 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1886
1887 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1888 for (scan_tbl_index = 0;
1889 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1890 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1891 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1892 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1893 actual_index, clip_pwrs,
1894 ch_info, a_band);
1895 }
1896 }
1897
1898 /* send Txpower command for current channel to ucode */
bb8c093b 1899 return iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1900}
1901
4a8a4322 1902int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1903{
d20b3c65 1904 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1905 s8 max_power;
1906 u8 a_band;
1907 u8 i;
1908
1909 if (priv->user_txpower_limit == power) {
1910 IWL_DEBUG_POWER("Requested Tx power same as current "
1911 "limit: %ddBm.\n", power);
1912 return 0;
1913 }
1914
1915 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1916 priv->user_txpower_limit = power;
1917
1918 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1919
1920 for (i = 0; i < priv->channel_count; i++) {
1921 ch_info = &priv->channel_info[i];
1922 a_band = is_channel_a_band(ch_info);
1923
1924 /* find minimum power of all user and regulatory constraints
1925 * (does not consider h/w clipping limitations) */
bb8c093b 1926 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1927 max_power = min(power, max_power);
1928 if (max_power != ch_info->curr_txpow) {
1929 ch_info->curr_txpow = max_power;
1930
1931 /* this considers the h/w clipping limitations */
bb8c093b 1932 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1933 }
1934 }
1935
1936 /* update txpower settings for all channels,
1937 * send to NIC if associated. */
1938 is_temp_calib_needed(priv);
bb8c093b 1939 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1940
1941 return 0;
1942}
1943
1944/* will add 3945 channel switch cmd handling later */
4a8a4322 1945int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1946{
1947 return 0;
1948}
1949
1950/**
1951 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1952 *
1953 * -- reset periodic timer
1954 * -- see if temp has changed enough to warrant re-calibration ... if so:
1955 * -- correct coeffs for temp (can reset temp timer)
1956 * -- save this temp as "last",
1957 * -- send new set of gain settings to NIC
1958 * NOTE: This should continue working, even when we're not associated,
1959 * so we can keep our internal table of scan powers current. */
4a8a4322 1960void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1961{
1962 /* This will kick in the "brute force"
bb8c093b 1963 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1964 if (!is_temp_calib_needed(priv))
1965 goto reschedule;
1966
1967 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1968 * This is based *only* on current temperature,
1969 * ignoring any previous power measurements */
bb8c093b 1970 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1971
1972 reschedule:
1973 queue_delayed_work(priv->workqueue,
1974 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1975}
1976
416e1438 1977static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 1978{
4a8a4322 1979 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1980 thermal_periodic.work);
1981
1982 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1983 return;
1984
1985 mutex_lock(&priv->mutex);
1986 iwl3945_reg_txpower_periodic(priv);
1987 mutex_unlock(&priv->mutex);
1988}
1989
1990/**
bb8c093b 1991 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 1992 * for the channel.
1993 *
1994 * This function is used when initializing channel-info structs.
1995 *
1996 * NOTE: These channel groups do *NOT* match the bands above!
1997 * These channel groups are based on factory-tested channels;
1998 * on A-band, EEPROM's "group frequency" entries represent the top
1999 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2000 */
4a8a4322 2001static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2002 const struct iwl_channel_info *ch_info)
b481de9c 2003{
f2c7e521 2004 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom39.groups[0];
b481de9c
ZY		 2005 u8 group;
2006 u16 group_index = 0; /* based on factory calib frequencies */
2007 u8 grp_channel;
2008
2009 /* Find the group index for the channel ... don't use index 1(?) */
2010 if (is_channel_a_band(ch_info)) {
2011 for (group = 1; group < 5; group++) {
2012 grp_channel = ch_grp[group].group_channel;
2013 if (ch_info->channel <= grp_channel) {
2014 group_index = group;
2015 break;
2016 }
2017 }
2018 /* group 4 has a few channels *above* its factory cal freq */
2019 if (group == 5)
2020 group_index = 4;
2021 } else
2022 group_index = 0; /* 2.4 GHz, group 0 */
2023
2024 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2025 group_index);
2026 return group_index;
2027}
2028
2029/**
bb8c093b 2030 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2031 *
2032 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2033 * into radio/DSP gain settings table for requested power.
2034 */
4a8a4322 2035static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2036 s8 requested_power,
2037 s32 setting_index, s32 *new_index)
2038{
bb8c093b 2039 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
b481de9c
ZY		 2040 s32 index0, index1;
2041 s32 power = 2 * requested_power;
2042 s32 i;
bb8c093b 2043 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2044 s32 gains0, gains1;
2045 s32 res;
2046 s32 denominator;
2047
f2c7e521 2048 chnl_grp = &priv->eeprom39.groups[setting_index];
b481de9c
ZY		 2049 samples = chnl_grp->samples;
2050 for (i = 0; i < 5; i++) {
2051 if (power == samples[i].power) {
2052 *new_index = samples[i].gain_index;
2053 return 0;
2054 }
2055 }
2056
2057 if (power > samples[1].power) {
2058 index0 = 0;
2059 index1 = 1;
2060 } else if (power > samples[2].power) {
2061 index0 = 1;
2062 index1 = 2;
2063 } else if (power > samples[3].power) {
2064 index0 = 2;
2065 index1 = 3;
2066 } else {
2067 index0 = 3;
2068 index1 = 4;
2069 }
2070
2071 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2072 if (denominator == 0)
2073 return -EINVAL;
2074 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2075 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2076 res = gains0 + (gains1 - gains0) *
2077 ((s32) power - (s32) samples[index0].power) / denominator +
2078 (1 << 18);
2079 *new_index = res >> 19;
2080 return 0;
2081}
2082
4a8a4322 2083static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2084{
2085 u32 i;
2086 s32 rate_index;
bb8c093b 2087 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2088
2089 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2090
2091 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2092 s8 *clip_pwrs; /* table of power levels for each rate */
2093 s8 satur_pwr; /* saturation power for each chnl group */
f2c7e521 2094 group = &priv->eeprom39.groups[i];
b481de9c
ZY		 2095
2096 /* sanity check on factory saturation power value */
2097 if (group->saturation_power < 40) {
2098 IWL_WARNING("Error: saturation power is %d, "
2099 "less than minimum expected 40\n",
2100 group->saturation_power);
2101 return;
2102 }
2103
2104 /*
2105 * Derive requested power levels for each rate, based on
2106 * hardware capabilities (saturation power for band).
2107 * Basic value is 3dB down from saturation, with further
2108 * power reductions for highest 3 data rates. These
2109 * backoffs provide headroom for high rate modulation
2110 * power peaks, without too much distortion (clipping).
2111 */
2112 /* we'll fill in this array with h/w max power levels */
f2c7e521 2113 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2114
2115 /* divide factory saturation power by 2 to find -3dB level */
2116 satur_pwr = (s8) (group->saturation_power >> 1);
2117
2118 /* fill in channel group's nominal powers for each rate */
2119 for (rate_index = 0;
2120 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2121 switch (rate_index) {
14577f23 2122 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2123 if (i == 0) /* B/G */
2124 *clip_pwrs = satur_pwr;
2125 else /* A */
2126 *clip_pwrs = satur_pwr - 5;
2127 break;
14577f23 2128 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2129 if (i == 0)
2130 *clip_pwrs = satur_pwr - 7;
2131 else
2132 *clip_pwrs = satur_pwr - 10;
2133 break;
14577f23 2134 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2135 if (i == 0)
2136 *clip_pwrs = satur_pwr - 9;
2137 else
2138 *clip_pwrs = satur_pwr - 12;
2139 break;
2140 default:
2141 *clip_pwrs = satur_pwr;
2142 break;
2143 }
2144 }
2145 }
2146}
2147
2148/**
2149 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2150 *
2151 * Second pass (during init) to set up priv->channel_info
2152 *
2153 * Set up Tx-power settings in our channel info database for each VALID
2154 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2155 * and current temperature.
2156 *
2157 * Since this is based on current temperature (at init time), these values may
2158 * not be valid for very long, but it gives us a starting/default point,
2159 * and allows us to active (i.e. using Tx) scan.
2160 *
2161 * This does *not* write values to NIC, just sets up our internal table.
2162 */
4a8a4322 2163int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2164{
d20b3c65 2165 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2166 struct iwl3945_channel_power_info *pwr_info;
b481de9c
ZY		 2167 int delta_index;
2168 u8 rate_index;
2169 u8 scan_tbl_index;
2170 const s8 *clip_pwrs; /* array of power levels for each rate */
2171 u8 gain, dsp_atten;
2172 s8 power;
2173 u8 pwr_index, base_pwr_index, a_band;
2174 u8 i;
2175 int temperature;
2176
2177 /* save temperature reference,
2178 * so we can determine next time to calibrate */
bb8c093b 2179 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2180 priv->last_temperature = temperature;
2181
bb8c093b 2182 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2183
2184 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2185 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2186 i++, ch_info++) {
2187 a_band = is_channel_a_band(ch_info);
2188 if (!is_channel_valid(ch_info))
2189 continue;
2190
2191 /* find this channel's channel group (*not* "band") index */
2192 ch_info->group_index =
bb8c093b 2193 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2194
2195 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2196 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2197
2198 /* calculate power index *adjustment* value according to
2199 * diff between current temperature and factory temperature */
bb8c093b 2200 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
f2c7e521 2201 priv->eeprom39.groups[ch_info->group_index].
b481de9c
ZY		 2202 temperature);
2203
2204 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2205 ch_info->channel, delta_index, temperature +
2206 IWL_TEMP_CONVERT);
2207
2208 /* set tx power value for all OFDM rates */
2209 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2210 rate_index++) {
25a4ccea 2211 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2212 int rc;
2213
2214 /* use channel group's clip-power table,
2215 * but don't exceed channel's max power */
2216 s8 pwr = min(ch_info->max_power_avg,
2217 clip_pwrs[rate_index]);
2218
2219 pwr_info = &ch_info->power_info[rate_index];
2220
2221 /* get base (i.e. at factory-measured temperature)
2222 * power table index for this rate's power */
bb8c093b 2223 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2224 ch_info->group_index,
2225 &power_idx);
2226 if (rc) {
2227 IWL_ERROR("Invalid power index\n");
2228 return rc;
2229 }
2230 pwr_info->base_power_index = (u8) power_idx;
2231
2232 /* temperature compensate */
2233 power_idx += delta_index;
2234
2235 /* stay within range of gain table */
bb8c093b 2236 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2237
bb8c093b 2238 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2239 pwr_info->requested_power = pwr;
2240 pwr_info->power_table_index = (u8) power_idx;
2241 pwr_info->tpc.tx_gain =
2242 power_gain_table[a_band][power_idx].tx_gain;
2243 pwr_info->tpc.dsp_atten =
2244 power_gain_table[a_band][power_idx].dsp_atten;
2245 }
2246
2247 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2248 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2249 power = pwr_info->requested_power +
2250 IWL_CCK_FROM_OFDM_POWER_DIFF;
2251 pwr_index = pwr_info->power_table_index +
2252 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2253 base_pwr_index = pwr_info->base_power_index +
2254 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2255
2256 /* stay within table range */
bb8c093b 2257 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2258 gain = power_gain_table[a_band][pwr_index].tx_gain;
2259 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2260
bb8c093b 2261 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2262 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2263 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2264 for (rate_index = 0;
2265 rate_index < IWL_CCK_RATES; rate_index++) {
2266 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2267 pwr_info->requested_power = power;
2268 pwr_info->power_table_index = pwr_index;
2269 pwr_info->base_power_index = base_pwr_index;
2270 pwr_info->tpc.tx_gain = gain;
2271 pwr_info->tpc.dsp_atten = dsp_atten;
2272 }
2273
2274 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2275 for (scan_tbl_index = 0;
2276 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2277 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2278 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2279 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2280 actual_index, clip_pwrs, ch_info, a_band);
2281 }
2282 }
2283
2284 return 0;
2285}
2286
4a8a4322 2287int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2288{
2289 int rc;
2290 unsigned long flags;
2291
2292 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2293 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2294 if (rc) {
2295 spin_unlock_irqrestore(&priv->lock, flags);
2296 return rc;
2297 }
2298
5d49f498
AK		 2299 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2300 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2301 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c
ZY		 2302 if (rc < 0)
2303 IWL_ERROR("Can't stop Rx DMA.\n");
2304
5d49f498 2305 iwl_release_nic_access(priv);
b481de9c
ZY		 2306 spin_unlock_irqrestore(&priv->lock, flags);
2307
2308 return 0;
2309}
2310
4a8a4322 2311int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c
ZY		 2312{
2313 int rc;
2314 unsigned long flags;
2315 int txq_id = txq->q.id;
2316
3832ec9d 2317 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2318
2319 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2320
2321 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2322 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2323 if (rc) {
2324 spin_unlock_irqrestore(&priv->lock, flags);
2325 return rc;
2326 }
5d49f498
AK		 2327 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2328 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2329
5d49f498 2330 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2331 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2332 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2333 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2334 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2335 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
5d49f498 2336 iwl_release_nic_access(priv);
b481de9c
ZY		 2337
2338 /* fake read to flush all prev. writes */
5d49f498 2339 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2340 spin_unlock_irqrestore(&priv->lock, flags);
2341
2342 return 0;
2343}
2344
4a8a4322 2345int iwl3945_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 2346{
3832ec9d 2347 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2348
2349 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2350}
2351
2352/**
2353 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2354 */
4a8a4322 2355int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2356{
14577f23 2357 int rc, i, index, prev_index;
bb8c093b 2358 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2359 .reserved = {0, 0, 0},
2360 };
bb8c093b 2361 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2362
bb8c093b
CH		 2363 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2364 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2365
2366 table[index].rate_n_flags =
bb8c093b 2367 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2368 table[index].try_cnt = priv->retry_rate;
bb8c093b 2369 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2370 table[index].next_rate_index =
2371 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2372 }
2373
8318d78a
JB		 2374 switch (priv->band) {
2375 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2376 IWL_DEBUG_RATE("Select A mode rate scale\n");
2377 /* If one of the following CCK rates is used,
2378 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2379 for (i = IWL_RATE_1M_INDEX_TABLE;
2380 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2381 table[i].next_rate_index =
2382 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2383
2384 /* Don't fall back to CCK rates */
7262796a
AM		 2385 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2386 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2387
2388 /* Don't drop out of OFDM rates */
14577f23 2389 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2390 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2391 break;
2392
8318d78a
JB		 2393 case IEEE80211_BAND_2GHZ:
2394 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2395 /* If an OFDM rate is used, have it fall back to the
2396 * 1M CCK rates */
b481de9c 2397
7262796a
AM		 2398 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2399 iwl3945_is_associated(priv)) {
2400
2401 index = IWL_FIRST_CCK_RATE;
2402 for (i = IWL_RATE_6M_INDEX_TABLE;
2403 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2404 table[i].next_rate_index =
2405 iwl3945_rates[index].table_rs_index;
2406
2407 index = IWL_RATE_11M_INDEX_TABLE;
2408 /* CCK shouldn't fall back to OFDM... */
2409 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2410 }
b481de9c
ZY		 2411 break;
2412
2413 default:
8318d78a 2414 WARN_ON(1);
b481de9c
ZY		 2415 break;
2416 }
2417
2418 /* Update the rate scaling for control frame Tx */
2419 rate_cmd.table_id = 0;
bb8c093b 2420 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2421 &rate_cmd);
2422 if (rc)
2423 return rc;
2424
2425 /* Update the rate scaling for data frame Tx */
2426 rate_cmd.table_id = 1;
bb8c093b 2427 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2428 &rate_cmd);
2429}
2430
796083cb 2431/* Called when initializing driver */
4a8a4322 2432int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2433{
3832ec9d
AK		 2434 memset((void *)&priv->hw_params, 0,
2435 sizeof(struct iwl_hw_params));
b481de9c 2436
3832ec9d 2437 priv->shared_virt =
b481de9c 2438 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2439 sizeof(struct iwl3945_shared),
3832ec9d 2440 &priv->shared_phys);
b481de9c 2441
3832ec9d 2442 if (!priv->shared_virt) {
b481de9c
ZY		 2443 IWL_ERROR("failed to allocate pci memory\n");
2444 mutex_unlock(&priv->mutex);
2445 return -ENOMEM;
2446 }
2447
3832ec9d
AK		 2448 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE;
2449 priv->hw_params.max_pkt_size = 2342;
2450 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2451 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2452 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2453 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2454
3832ec9d 2455 priv->hw_params.tx_ant_num = 2;
b481de9c
ZY		 2456 return 0;
2457}
2458
4a8a4322 2459unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2460 struct iwl3945_frame *frame, u8 rate)
b481de9c 2461{
bb8c093b 2462 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2463 unsigned int frame_size;
2464
bb8c093b 2465 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2466 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2467
3832ec9d 2468 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2469 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2470
bb8c093b 2471 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2472 tx_beacon_cmd->frame,
b481de9c
ZY		 2473 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2474
2475 BUG_ON(frame_size > MAX_MPDU_SIZE);
2476 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2477
2478 tx_beacon_cmd->tx.rate = rate;
2479 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2480 TX_CMD_FLG_TSF_MSK);
2481
14577f23
MA		 2482 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2483 tx_beacon_cmd->tx.supp_rates[0] =
2484 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2485
b481de9c 2486 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2487 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2488
3ac7f146 2489 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2490}
2491
4a8a4322 2492void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2493{
91c066f2 2494 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2495 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2496}
2497
4a8a4322 2498void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2499{
2500 INIT_DELAYED_WORK(&priv->thermal_periodic,
2501 iwl3945_bg_reg_txpower_periodic);
2502}
2503
4a8a4322 2504void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2505{
2506 cancel_delayed_work(&priv->thermal_periodic);
2507}
2508
c0f20d91 2509static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2510 .name = "3945BG",
a0987a8d
RC		 2511 .fw_name_pre = IWL3945_FW_PRE,
2512 .ucode_api_max = IWL3945_UCODE_API_MAX,
2513 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121
TW		 2514 .sku = IWL_SKU_G,
2515};
2516
c0f20d91 2517static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2518 .name = "3945ABG",
a0987a8d
RC		 2519 .fw_name_pre = IWL3945_FW_PRE,
2520 .ucode_api_max = IWL3945_UCODE_API_MAX,
2521 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121
TW		 2522 .sku = IWL_SKU_A|IWL_SKU_G,
2523};
2524
bb8c093b 2525struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2526 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2527 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2528 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2529 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2530 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2531 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2532 {0}
2533};
2534
bb8c093b 2535MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Clone of davem's net-next-2.6 tree