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b43legacy: Fixes for beaconing
[net-next-2.6.git] / drivers / net / wireless / b43legacy / main.c
CommitLineData
75388acd
LF		 1/*
2 *
3 * Broadcom B43legacy wireless driver
4 *
5 * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6fff1c64 6 * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
75388acd
LF		 7 * Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11 *
12 * Some parts of the code in this file are derived from the ipw2200
13 * driver Copyright(c) 2003 - 2004 Intel Corporation.
14
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING. If not, write to
27 * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28 * Boston, MA 02110-1301, USA.
29 *
30 */
31
32#include <linux/delay.h>
33#include <linux/init.h>
34#include <linux/moduleparam.h>
35#include <linux/if_arp.h>
36#include <linux/etherdevice.h>
75388acd
LF		 37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
40#include <linux/skbuff.h>
41#include <linux/dma-mapping.h>
42#include <net/dst.h>
43#include <asm/unaligned.h>
44
45#include "b43legacy.h"
46#include "main.h"
47#include "debugfs.h"
48#include "phy.h"
49#include "dma.h"
50#include "pio.h"
51#include "sysfs.h"
52#include "xmit.h"
53#include "radio.h"
54
55
56MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
57MODULE_AUTHOR("Martin Langer");
58MODULE_AUTHOR("Stefano Brivio");
59MODULE_AUTHOR("Michael Buesch");
60MODULE_LICENSE("GPL");
61
1a1c360d
SB		 62MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
63
75388acd
LF		 64#if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
65static int modparam_pio;
66module_param_named(pio, modparam_pio, int, 0444);
67MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
68#elif defined(CONFIG_B43LEGACY_DMA)
69# define modparam_pio 0
70#elif defined(CONFIG_B43LEGACY_PIO)
71# define modparam_pio 1
72#endif
73
74static int modparam_bad_frames_preempt;
75module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
76MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
77 " Preemption");
78
75388acd
LF		 79static char modparam_fwpostfix[16];
80module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
81MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
82
75388acd
LF		 83/* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
84static const struct ssb_device_id b43legacy_ssb_tbl[] = {
85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
86 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
87 SSB_DEVTABLE_END
88};
89MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
90
91
92/* Channel and ratetables are shared for all devices.
93 * They can't be const, because ieee80211 puts some precalculated
94 * data in there. This data is the same for all devices, so we don't
95 * get concurrency issues */
96#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 97 { \
98 .bitrate = B43legacy_RATE_TO_100KBPS(_rateid), \
99 .hw_value = (_rateid), \
100 .flags = (_flags), \
75388acd 101 }
8318d78a
JB		 102/*
103 * NOTE: When changing this, sync with xmit.c's
104 * b43legacy_plcp_get_bitrate_idx_* functions!
105 */
75388acd 106static struct ieee80211_rate __b43legacy_ratetable[] = {
8318d78a
JB		 107 RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
108 RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
109 RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
110 RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
111 RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
112 RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
113 RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
114 RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
115 RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
116 RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
117 RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
118 RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
75388acd 119};
75388acd
LF		 120#define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
121#define b43legacy_b_ratetable_size 4
122#define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
123#define b43legacy_g_ratetable_size 12
124
125#define CHANTAB_ENT(_chanid, _freq) \
126 { \
8318d78a
JB		 127 .center_freq = (_freq), \
128 .hw_value = (_chanid), \
75388acd
LF		 129 }
130static struct ieee80211_channel b43legacy_bg_chantable[] = {
131 CHANTAB_ENT(1, 2412),
132 CHANTAB_ENT(2, 2417),
133 CHANTAB_ENT(3, 2422),
134 CHANTAB_ENT(4, 2427),
135 CHANTAB_ENT(5, 2432),
136 CHANTAB_ENT(6, 2437),
137 CHANTAB_ENT(7, 2442),
138 CHANTAB_ENT(8, 2447),
139 CHANTAB_ENT(9, 2452),
140 CHANTAB_ENT(10, 2457),
141 CHANTAB_ENT(11, 2462),
142 CHANTAB_ENT(12, 2467),
143 CHANTAB_ENT(13, 2472),
144 CHANTAB_ENT(14, 2484),
145};
8318d78a
JB		 146
147static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
148 .channels = b43legacy_bg_chantable,
149 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
150 .bitrates = b43legacy_b_ratetable,
151 .n_bitrates = b43legacy_b_ratetable_size,
152};
153
154static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
155 .channels = b43legacy_bg_chantable,
156 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
157 .bitrates = b43legacy_g_ratetable,
158 .n_bitrates = b43legacy_g_ratetable_size,
159};
75388acd
LF		 160
161static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
162static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
163static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
164static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
165
166
167static int b43legacy_ratelimit(struct b43legacy_wl *wl)
168{
169 if (!wl || !wl->current_dev)
170 return 1;
171 if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
172 return 1;
173 /* We are up and running.
174 * Ratelimit the messages to avoid DoS over the net. */
175 return net_ratelimit();
176}
177
178void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
179{
180 va_list args;
181
182 if (!b43legacy_ratelimit(wl))
183 return;
184 va_start(args, fmt);
185 printk(KERN_INFO "b43legacy-%s: ",
186 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
187 vprintk(fmt, args);
188 va_end(args);
189}
190
191void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
192{
193 va_list args;
194
195 if (!b43legacy_ratelimit(wl))
196 return;
197 va_start(args, fmt);
198 printk(KERN_ERR "b43legacy-%s ERROR: ",
199 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
200 vprintk(fmt, args);
201 va_end(args);
202}
203
204void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
205{
206 va_list args;
207
208 if (!b43legacy_ratelimit(wl))
209 return;
210 va_start(args, fmt);
211 printk(KERN_WARNING "b43legacy-%s warning: ",
212 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
213 vprintk(fmt, args);
214 va_end(args);
215}
216
217#if B43legacy_DEBUG
218void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
219{
220 va_list args;
221
222 va_start(args, fmt);
223 printk(KERN_DEBUG "b43legacy-%s debug: ",
224 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
225 vprintk(fmt, args);
226 va_end(args);
227}
228#endif /* DEBUG */
229
230static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
231 u32 val)
232{
233 u32 status;
234
235 B43legacy_WARN_ON(offset % 4 != 0);
236
e78c9d28
SB		 237 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
238 if (status & B43legacy_MACCTL_BE)
75388acd
LF		 239 val = swab32(val);
240
241 b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
242 mmiowb();
243 b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
244}
245
246static inline
247void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
248 u16 routing, u16 offset)
249{
250 u32 control;
251
252 /* "offset" is the WORD offset. */
253
254 control = routing;
255 control <<= 16;
256 control |= offset;
257 b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
258}
259
260u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
261 u16 routing, u16 offset)
262{
263 u32 ret;
264
265 if (routing == B43legacy_SHM_SHARED) {
266 B43legacy_WARN_ON((offset & 0x0001) != 0);
267 if (offset & 0x0003) {
268 /* Unaligned access */
269 b43legacy_shm_control_word(dev, routing, offset >> 2);
270 ret = b43legacy_read16(dev,
271 B43legacy_MMIO_SHM_DATA_UNALIGNED);
272 ret <<= 16;
273 b43legacy_shm_control_word(dev, routing,
274 (offset >> 2) + 1);
275 ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
276
277 return ret;
278 }
279 offset >>= 2;
280 }
281 b43legacy_shm_control_word(dev, routing, offset);
282 ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
283
284 return ret;
285}
286
287u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
288 u16 routing, u16 offset)
289{
290 u16 ret;
291
292 if (routing == B43legacy_SHM_SHARED) {
293 B43legacy_WARN_ON((offset & 0x0001) != 0);
294 if (offset & 0x0003) {
295 /* Unaligned access */
296 b43legacy_shm_control_word(dev, routing, offset >> 2);
297 ret = b43legacy_read16(dev,
298 B43legacy_MMIO_SHM_DATA_UNALIGNED);
299
300 return ret;
301 }
302 offset >>= 2;
303 }
304 b43legacy_shm_control_word(dev, routing, offset);
305 ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
306
307 return ret;
308}
309
310void b43legacy_shm_write32(struct b43legacy_wldev *dev,
311 u16 routing, u16 offset,
312 u32 value)
313{
314 if (routing == B43legacy_SHM_SHARED) {
315 B43legacy_WARN_ON((offset & 0x0001) != 0);
316 if (offset & 0x0003) {
317 /* Unaligned access */
318 b43legacy_shm_control_word(dev, routing, offset >> 2);
319 mmiowb();
320 b43legacy_write16(dev,
321 B43legacy_MMIO_SHM_DATA_UNALIGNED,
322 (value >> 16) & 0xffff);
323 mmiowb();
324 b43legacy_shm_control_word(dev, routing,
325 (offset >> 2) + 1);
326 mmiowb();
327 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
328 value & 0xffff);
329 return;
330 }
331 offset >>= 2;
332 }
333 b43legacy_shm_control_word(dev, routing, offset);
334 mmiowb();
335 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
336}
337
338void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
339 u16 value)
340{
341 if (routing == B43legacy_SHM_SHARED) {
342 B43legacy_WARN_ON((offset & 0x0001) != 0);
343 if (offset & 0x0003) {
344 /* Unaligned access */
345 b43legacy_shm_control_word(dev, routing, offset >> 2);
346 mmiowb();
347 b43legacy_write16(dev,
348 B43legacy_MMIO_SHM_DATA_UNALIGNED,
349 value);
350 return;
351 }
352 offset >>= 2;
353 }
354 b43legacy_shm_control_word(dev, routing, offset);
355 mmiowb();
356 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
357}
358
359/* Read HostFlags */
360u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
361{
362 u32 ret;
363
364 ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
365 B43legacy_SHM_SH_HOSTFHI);
366 ret <<= 16;
367 ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
368 B43legacy_SHM_SH_HOSTFLO);
369
370 return ret;
371}
372
373/* Write HostFlags */
374void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
375{
376 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
377 B43legacy_SHM_SH_HOSTFLO,
378 (value & 0x0000FFFF));
379 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
380 B43legacy_SHM_SH_HOSTFHI,
381 ((value & 0xFFFF0000) >> 16));
382}
383
384void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
385{
386 /* We need to be careful. As we read the TSF from multiple
387 * registers, we should take care of register overflows.
388 * In theory, the whole tsf read process should be atomic.
389 * We try to be atomic here, by restaring the read process,
390 * if any of the high registers changed (overflew).
391 */
392 if (dev->dev->id.revision >= 3) {
393 u32 low;
394 u32 high;
395 u32 high2;
396
397 do {
398 high = b43legacy_read32(dev,
399 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
400 low = b43legacy_read32(dev,
401 B43legacy_MMIO_REV3PLUS_TSF_LOW);
402 high2 = b43legacy_read32(dev,
403 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
404 } while (unlikely(high != high2));
405
406 *tsf = high;
407 *tsf <<= 32;
408 *tsf |= low;
409 } else {
410 u64 tmp;
411 u16 v0;
412 u16 v1;
413 u16 v2;
414 u16 v3;
415 u16 test1;
416 u16 test2;
417 u16 test3;
418
419 do {
420 v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
421 v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
422 v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
423 v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
424
425 test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
426 test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
427 test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
428 } while (v3 != test3 || v2 != test2 || v1 != test1);
429
430 *tsf = v3;
431 *tsf <<= 48;
432 tmp = v2;
433 tmp <<= 32;
434 *tsf |= tmp;
435 tmp = v1;
436 tmp <<= 16;
437 *tsf |= tmp;
438 *tsf |= v0;
439 }
440}
441
442static void b43legacy_time_lock(struct b43legacy_wldev *dev)
443{
444 u32 status;
445
e78c9d28
SB		 446 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
447 status |= B43legacy_MACCTL_TBTTHOLD;
448 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
75388acd
LF		 449 mmiowb();
450}
451
452static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
453{
454 u32 status;
455
e78c9d28
SB		 456 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
457 status &= ~B43legacy_MACCTL_TBTTHOLD;
458 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
75388acd
LF		 459}
460
461static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
462{
463 /* Be careful with the in-progress timer.
464 * First zero out the low register, so we have a full
465 * register-overflow duration to complete the operation.
466 */
467 if (dev->dev->id.revision >= 3) {
468 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
469 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
470
471 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
472 mmiowb();
473 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
474 hi);
475 mmiowb();
476 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
477 lo);
478 } else {
479 u16 v0 = (tsf & 0x000000000000FFFFULL);
480 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
481 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
482 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
483
484 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
485 mmiowb();
486 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
487 mmiowb();
488 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
489 mmiowb();
490 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
491 mmiowb();
492 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
493 }
494}
495
496void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
497{
498 b43legacy_time_lock(dev);
499 b43legacy_tsf_write_locked(dev, tsf);
500 b43legacy_time_unlock(dev);
501}
502
503static
504void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
505 u16 offset, const u8 *mac)
506{
507 static const u8 zero_addr[ETH_ALEN] = { 0 };
508 u16 data;
509
510 if (!mac)
511 mac = zero_addr;
512
513 offset |= 0x0020;
514 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
515
516 data = mac[0];
517 data |= mac[1] << 8;
518 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
519 data = mac[2];
520 data |= mac[3] << 8;
521 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
522 data = mac[4];
523 data |= mac[5] << 8;
524 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
525}
526
527static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
528{
529 static const u8 zero_addr[ETH_ALEN] = { 0 };
530 const u8 *mac = dev->wl->mac_addr;
531 const u8 *bssid = dev->wl->bssid;
532 u8 mac_bssid[ETH_ALEN * 2];
533 int i;
534 u32 tmp;
535
536 if (!bssid)
537 bssid = zero_addr;
538 if (!mac)
539 mac = zero_addr;
540
541 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
542
543 memcpy(mac_bssid, mac, ETH_ALEN);
544 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
545
546 /* Write our MAC address and BSSID to template ram */
547 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
548 tmp = (u32)(mac_bssid[i + 0]);
549 tmp |= (u32)(mac_bssid[i + 1]) << 8;
550 tmp |= (u32)(mac_bssid[i + 2]) << 16;
551 tmp |= (u32)(mac_bssid[i + 3]) << 24;
552 b43legacy_ram_write(dev, 0x20 + i, tmp);
553 b43legacy_ram_write(dev, 0x78 + i, tmp);
554 b43legacy_ram_write(dev, 0x478 + i, tmp);
555 }
556}
557
4150c572 558static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
75388acd 559{
75388acd 560 b43legacy_write_mac_bssid_templates(dev);
4150c572
JB		 561 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
562 dev->wl->mac_addr);
75388acd
LF		 563}
564
565static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
566 u16 slot_time)
567{
568 /* slot_time is in usec. */
569 if (dev->phy.type != B43legacy_PHYTYPE_G)
570 return;
571 b43legacy_write16(dev, 0x684, 510 + slot_time);
572 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
573 slot_time);
574}
575
576static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
577{
578 b43legacy_set_slot_time(dev, 9);
75388acd
LF		 579}
580
581static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
582{
583 b43legacy_set_slot_time(dev, 20);
75388acd
LF		 584}
585
586/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
587 * Returns the _previously_ enabled IRQ mask.
588 */
589static inline u32 b43legacy_interrupt_enable(struct b43legacy_wldev *dev,
590 u32 mask)
591{
592 u32 old_mask;
593
594 old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
595 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask |
596 mask);
597
598 return old_mask;
599}
600
601/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
602 * Returns the _previously_ enabled IRQ mask.
603 */
604static inline u32 b43legacy_interrupt_disable(struct b43legacy_wldev *dev,
605 u32 mask)
606{
607 u32 old_mask;
608
609 old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
610 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
611
612 return old_mask;
613}
614
615/* Synchronize IRQ top- and bottom-half.
616 * IRQs must be masked before calling this.
617 * This must not be called with the irq_lock held.
618 */
619static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
620{
621 synchronize_irq(dev->dev->irq);
622 tasklet_kill(&dev->isr_tasklet);
623}
624
625/* DummyTransmission function, as documented on
626 * http://bcm-specs.sipsolutions.net/DummyTransmission
627 */
628void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
629{
630 struct b43legacy_phy *phy = &dev->phy;
631 unsigned int i;
632 unsigned int max_loop;
633 u16 value;
634 u32 buffer[5] = {
635 0x00000000,
636 0x00D40000,
637 0x00000000,
638 0x01000000,
639 0x00000000,
640 };
641
642 switch (phy->type) {
643 case B43legacy_PHYTYPE_B:
644 case B43legacy_PHYTYPE_G:
645 max_loop = 0xFA;
646 buffer[0] = 0x000B846E;
647 break;
648 default:
649 B43legacy_BUG_ON(1);
650 return;
651 }
652
653 for (i = 0; i < 5; i++)
654 b43legacy_ram_write(dev, i * 4, buffer[i]);
655
656 /* dummy read follows */
e78c9d28 657 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
75388acd
LF		 658
659 b43legacy_write16(dev, 0x0568, 0x0000);
660 b43legacy_write16(dev, 0x07C0, 0x0000);
661 b43legacy_write16(dev, 0x050C, 0x0000);
662 b43legacy_write16(dev, 0x0508, 0x0000);
663 b43legacy_write16(dev, 0x050A, 0x0000);
664 b43legacy_write16(dev, 0x054C, 0x0000);
665 b43legacy_write16(dev, 0x056A, 0x0014);
666 b43legacy_write16(dev, 0x0568, 0x0826);
667 b43legacy_write16(dev, 0x0500, 0x0000);
668 b43legacy_write16(dev, 0x0502, 0x0030);
669
670 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
671 b43legacy_radio_write16(dev, 0x0051, 0x0017);
672 for (i = 0x00; i < max_loop; i++) {
673 value = b43legacy_read16(dev, 0x050E);
674 if (value & 0x0080)
675 break;
676 udelay(10);
677 }
678 for (i = 0x00; i < 0x0A; i++) {
679 value = b43legacy_read16(dev, 0x050E);
680 if (value & 0x0400)
681 break;
682 udelay(10);
683 }
684 for (i = 0x00; i < 0x0A; i++) {
685 value = b43legacy_read16(dev, 0x0690);
686 if (!(value & 0x0100))
687 break;
688 udelay(10);
689 }
690 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
691 b43legacy_radio_write16(dev, 0x0051, 0x0037);
692}
693
694/* Turn the Analog ON/OFF */
695static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
696{
697 b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
698}
699
700void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
701{
702 u32 tmslow;
703 u32 macctl;
704
705 flags |= B43legacy_TMSLOW_PHYCLKEN;
706 flags |= B43legacy_TMSLOW_PHYRESET;
707 ssb_device_enable(dev->dev, flags);
708 msleep(2); /* Wait for the PLL to turn on. */
709
710 /* Now take the PHY out of Reset again */
711 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
712 tmslow |= SSB_TMSLOW_FGC;
713 tmslow &= ~B43legacy_TMSLOW_PHYRESET;
714 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
715 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
716 msleep(1);
717 tmslow &= ~SSB_TMSLOW_FGC;
718 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
719 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
720 msleep(1);
721
722 /* Turn Analog ON */
723 b43legacy_switch_analog(dev, 1);
724
725 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
726 macctl &= ~B43legacy_MACCTL_GMODE;
727 if (flags & B43legacy_TMSLOW_GMODE) {
728 macctl |= B43legacy_MACCTL_GMODE;
729 dev->phy.gmode = 1;
730 } else
731 dev->phy.gmode = 0;
732 macctl |= B43legacy_MACCTL_IHR_ENABLED;
733 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
734}
735
736static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
737{
738 u32 v0;
739 u32 v1;
740 u16 tmp;
741 struct b43legacy_txstatus stat;
742
743 while (1) {
744 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
745 if (!(v0 & 0x00000001))
746 break;
747 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
748
749 stat.cookie = (v0 >> 16);
750 stat.seq = (v1 & 0x0000FFFF);
751 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
752 tmp = (v0 & 0x0000FFFF);
753 stat.frame_count = ((tmp & 0xF000) >> 12);
754 stat.rts_count = ((tmp & 0x0F00) >> 8);
755 stat.supp_reason = ((tmp & 0x001C) >> 2);
756 stat.pm_indicated = !!(tmp & 0x0080);
757 stat.intermediate = !!(tmp & 0x0040);
758 stat.for_ampdu = !!(tmp & 0x0020);
759 stat.acked = !!(tmp & 0x0002);
760
761 b43legacy_handle_txstatus(dev, &stat);
762 }
763}
764
765static void drain_txstatus_queue(struct b43legacy_wldev *dev)
766{
767 u32 dummy;
768
769 if (dev->dev->id.revision < 5)
770 return;
771 /* Read all entries from the microcode TXstatus FIFO
772 * and throw them away.
773 */
774 while (1) {
775 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
776 if (!(dummy & 0x00000001))
777 break;
778 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
779 }
780}
781
782static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
783{
784 u32 val = 0;
785
786 val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
787 val <<= 16;
788 val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
789
790 return val;
791}
792
793static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
794{
795 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
796 (jssi & 0x0000FFFF));
797 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
798 (jssi & 0xFFFF0000) >> 16);
799}
800
801static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
802{
803 b43legacy_jssi_write(dev, 0x7F7F7F7F);
e78c9d28 804 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
eed0fd21
SB		 805 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
806 | B43legacy_MACCMD_BGNOISE);
75388acd
LF		 807 B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
808 dev->phy.channel);
809}
810
811static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
812{
813 /* Top half of Link Quality calculation. */
814
815 if (dev->noisecalc.calculation_running)
816 return;
817 dev->noisecalc.channel_at_start = dev->phy.channel;
818 dev->noisecalc.calculation_running = 1;
819 dev->noisecalc.nr_samples = 0;
820
821 b43legacy_generate_noise_sample(dev);
822}
823
824static void handle_irq_noise(struct b43legacy_wldev *dev)
825{
826 struct b43legacy_phy *phy = &dev->phy;
827 u16 tmp;
828 u8 noise[4];
829 u8 i;
830 u8 j;
831 s32 average;
832
833 /* Bottom half of Link Quality calculation. */
834
835 B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
836 if (dev->noisecalc.channel_at_start != phy->channel)
837 goto drop_calculation;
838 *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
839 if (noise[0] == 0x7F || noise[1] == 0x7F ||
840 noise[2] == 0x7F || noise[3] == 0x7F)
841 goto generate_new;
842
843 /* Get the noise samples. */
844 B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
845 i = dev->noisecalc.nr_samples;
ca21614d
HH		 846 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
847 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
848 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
849 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
75388acd
LF		 850 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
851 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
852 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
853 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
854 dev->noisecalc.nr_samples++;
855 if (dev->noisecalc.nr_samples == 8) {
856 /* Calculate the Link Quality by the noise samples. */
857 average = 0;
858 for (i = 0; i < 8; i++) {
859 for (j = 0; j < 4; j++)
860 average += dev->noisecalc.samples[i][j];
861 }
862 average /= (8 * 4);
863 average *= 125;
864 average += 64;
865 average /= 128;
866 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
867 0x40C);
868 tmp = (tmp / 128) & 0x1F;
869 if (tmp >= 8)
870 average += 2;
871 else
872 average -= 25;
873 if (tmp == 8)
874 average -= 72;
875 else
876 average -= 48;
877
878 dev->stats.link_noise = average;
879drop_calculation:
880 dev->noisecalc.calculation_running = 0;
881 return;
882 }
883generate_new:
884 b43legacy_generate_noise_sample(dev);
885}
886
887static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
888{
05c914fe 889 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
75388acd
LF		 890 /* TODO: PS TBTT */
891 } else {
892 if (1/*FIXME: the last PSpoll frame was sent successfully */)
893 b43legacy_power_saving_ctl_bits(dev, -1, -1);
894 }
05c914fe 895 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
eed0fd21 896 dev->dfq_valid = 1;
75388acd
LF		 897}
898
899static void handle_irq_atim_end(struct b43legacy_wldev *dev)
900{
eed0fd21
SB		 901 if (dev->dfq_valid) {
902 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
903 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
904 | B43legacy_MACCMD_DFQ_VALID);
905 dev->dfq_valid = 0;
906 }
75388acd
LF		 907}
908
909static void handle_irq_pmq(struct b43legacy_wldev *dev)
910{
911 u32 tmp;
912
913 /* TODO: AP mode. */
914
915 while (1) {
916 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
917 if (!(tmp & 0x00000008))
918 break;
919 }
920 /* 16bit write is odd, but correct. */
921 b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
922}
923
924static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
925 const u8 *data, u16 size,
926 u16 ram_offset,
927 u16 shm_size_offset, u8 rate)
928{
929 u32 i;
930 u32 tmp;
931 struct b43legacy_plcp_hdr4 plcp;
932
933 plcp.data = 0;
934 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
935 b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
936 ram_offset += sizeof(u32);
937 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
938 * So leave the first two bytes of the next write blank.
939 */
940 tmp = (u32)(data[0]) << 16;
941 tmp |= (u32)(data[1]) << 24;
942 b43legacy_ram_write(dev, ram_offset, tmp);
943 ram_offset += sizeof(u32);
944 for (i = 2; i < size; i += sizeof(u32)) {
945 tmp = (u32)(data[i + 0]);
946 if (i + 1 < size)
947 tmp |= (u32)(data[i + 1]) << 8;
948 if (i + 2 < size)
949 tmp |= (u32)(data[i + 2]) << 16;
950 if (i + 3 < size)
951 tmp |= (u32)(data[i + 3]) << 24;
952 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
953 }
954 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
955 size + sizeof(struct b43legacy_plcp_hdr6));
956}
957
958static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
959 u16 ram_offset,
960 u16 shm_size_offset, u8 rate)
961{
75388acd 962
a297170d
SB		 963 unsigned int i, len, variable_len;
964 const struct ieee80211_mgmt *bcn;
965 const u8 *ie;
966 bool tim_found = 0;
967
968 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
969 len = min((size_t)dev->wl->current_beacon->len,
75388acd 970 0x200 - sizeof(struct b43legacy_plcp_hdr6));
a297170d
SB		 971
972 b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
75388acd 973 shm_size_offset, rate);
a297170d
SB		 974
975 /* Find the position of the TIM and the DTIM_period value
976 * and write them to SHM. */
977 ie = bcn->u.beacon.variable;
978 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
979 for (i = 0; i < variable_len - 2; ) {
980 uint8_t ie_id, ie_len;
981
982 ie_id = ie[i];
983 ie_len = ie[i + 1];
984 if (ie_id == 5) {
985 u16 tim_position;
986 u16 dtim_period;
987 /* This is the TIM Information Element */
988
989 /* Check whether the ie_len is in the beacon data range. */
990 if (variable_len < ie_len + 2 + i)
991 break;
992 /* A valid TIM is at least 4 bytes long. */
993 if (ie_len < 4)
994 break;
995 tim_found = 1;
996
997 tim_position = sizeof(struct b43legacy_plcp_hdr6);
998 tim_position += offsetof(struct ieee80211_mgmt,
999 u.beacon.variable);
1000 tim_position += i;
1001
1002 dtim_period = ie[i + 3];
1003
1004 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1005 B43legacy_SHM_SH_TIMPOS, tim_position);
1006 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1007 B43legacy_SHM_SH_DTIMP, dtim_period);
1008 break;
1009 }
1010 i += ie_len + 2;
1011 }
1012 if (!tim_found) {
1013 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1014 "beacon template packet. AP or IBSS operation "
1015 "may be broken.\n");
7858e07b
LF		 1016 } else
1017 b43legacydbg(dev->wl, "Updated beacon template\n");
75388acd
LF		 1018}
1019
1020static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1021 u16 shm_offset, u16 size,
8318d78a 1022 struct ieee80211_rate *rate)
75388acd
LF		 1023{
1024 struct b43legacy_plcp_hdr4 plcp;
1025 u32 tmp;
1026 __le16 dur;
1027
1028 plcp.data = 0;
8318d78a 1029 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->bitrate);
75388acd 1030 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1031 dev->wl->vif,
75388acd 1032 size,
8318d78a 1033 rate);
75388acd
LF		 1034 /* Write PLCP in two parts and timing for packet transfer */
1035 tmp = le32_to_cpu(plcp.data);
1036 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1037 tmp & 0xFFFF);
1038 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1039 tmp >> 16);
1040 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1041 le16_to_cpu(dur));
1042}
1043
1044/* Instead of using custom probe response template, this function
1045 * just patches custom beacon template by:
1046 * 1) Changing packet type
1047 * 2) Patching duration field
1048 * 3) Stripping TIM
1049 */
a297170d
SB		 1050static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1051 u16 *dest_size,
1052 struct ieee80211_rate *rate)
75388acd
LF		 1053{
1054 const u8 *src_data;
1055 u8 *dest_data;
a297170d 1056 u16 src_size, elem_size, src_pos, dest_pos;
75388acd
LF		 1057 __le16 dur;
1058 struct ieee80211_hdr *hdr;
a297170d
SB		 1059 size_t ie_start;
1060
1061 src_size = dev->wl->current_beacon->len;
1062 src_data = (const u8 *)dev->wl->current_beacon->data;
75388acd 1063
a297170d
SB		 1064 /* Get the start offset of the variable IEs in the packet. */
1065 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1066 B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1067 u.beacon.variable));
75388acd 1068
4688be30 1069 if (B43legacy_WARN_ON(src_size < ie_start))
75388acd 1070 return NULL;
75388acd
LF		 1071
1072 dest_data = kmalloc(src_size, GFP_ATOMIC);
1073 if (unlikely(!dest_data))
1074 return NULL;
1075
a297170d
SB		 1076 /* Copy the static data and all Information Elements, except the TIM. */
1077 memcpy(dest_data, src_data, ie_start);
1078 src_pos = ie_start;
1079 dest_pos = ie_start;
1080 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
75388acd 1081 elem_size = src_data[src_pos + 1] + 2;
a297170d
SB		 1082 if (src_data[src_pos] == 5) {
1083 /* This is the TIM. */
1084 continue;
75388acd 1085 }
a297170d
SB		 1086 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1087 dest_pos += elem_size;
75388acd
LF		 1088 }
1089 *dest_size = dest_pos;
1090 hdr = (struct ieee80211_hdr *)dest_data;
1091
1092 /* Set the frame control. */
1093 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1094 IEEE80211_STYPE_PROBE_RESP);
1095 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1096 dev->wl->vif,
75388acd 1097 *dest_size,
8318d78a 1098 rate);
75388acd
LF		 1099 hdr->duration_id = dur;
1100
1101 return dest_data;
1102}
1103
1104static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1105 u16 ram_offset,
8318d78a
JB		 1106 u16 shm_size_offset,
1107 struct ieee80211_rate *rate)
75388acd 1108{
a297170d 1109 const u8 *probe_resp_data;
75388acd
LF		 1110 u16 size;
1111
a297170d 1112 size = dev->wl->current_beacon->len;
75388acd
LF		 1113 probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1114 if (unlikely(!probe_resp_data))
1115 return;
1116
1117 /* Looks like PLCP headers plus packet timings are stored for
1118 * all possible basic rates
1119 */
1120 b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
8318d78a 1121 &b43legacy_b_ratetable[0]);
75388acd 1122 b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
8318d78a 1123 &b43legacy_b_ratetable[1]);
75388acd 1124 b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
8318d78a 1125 &b43legacy_b_ratetable[2]);
75388acd 1126 b43legacy_write_probe_resp_plcp(dev, 0x350, size,
8318d78a 1127 &b43legacy_b_ratetable[3]);
75388acd
LF		 1128
1129 size = min((size_t)size,
1130 0x200 - sizeof(struct b43legacy_plcp_hdr6));
1131 b43legacy_write_template_common(dev, probe_resp_data,
1132 size, ram_offset,
8318d78a 1133 shm_size_offset, rate->bitrate);
75388acd
LF		 1134 kfree(probe_resp_data);
1135}
1136
7858e07b
LF		 1137static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1138{
1139 struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1140 beacon_update_trigger);
1141 struct b43legacy_wldev *dev;
1142
1143 mutex_lock(&wl->mutex);
1144 dev = wl->current_dev;
1145 if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
1146 /* Force the microcode to trigger the
1147 * beacon update bottom-half IRQ. */
1148 spin_lock_irq(&wl->irq_lock);
1149 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
1150 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
1151 | B43legacy_MACCMD_BEACON0_VALID
1152 | B43legacy_MACCMD_BEACON1_VALID);
1153 spin_unlock_irq(&wl->irq_lock);
1154 }
1155 mutex_unlock(&wl->mutex);
1156}
1157
a297170d
SB		 1158/* Asynchronously update the packet templates in template RAM.
1159 * Locking: Requires wl->irq_lock to be locked. */
9d139c81 1160static void b43legacy_update_templates(struct b43legacy_wl *wl)
75388acd 1161{
9d139c81 1162 struct sk_buff *beacon;
a297170d
SB		 1163 /* This is the top half of the ansynchronous beacon update. The bottom
1164 * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1165 * sending an invalid beacon. This can happen for example, if the
1166 * firmware transmits a beacon while we are updating it. */
75388acd 1167
9d139c81
JB		 1168 /* We could modify the existing beacon and set the aid bit in the TIM
1169 * field, but that would probably require resizing and moving of data
1170 * within the beacon template. Simply request a new beacon and let
1171 * mac80211 do the hard work. */
1172 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1173 if (unlikely(!beacon))
1174 return;
1175
a297170d
SB		 1176 if (wl->current_beacon)
1177 dev_kfree_skb_any(wl->current_beacon);
1178 wl->current_beacon = beacon;
1179 wl->beacon0_uploaded = 0;
1180 wl->beacon1_uploaded = 0;
7858e07b 1181 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
75388acd
LF		 1182}
1183
75388acd
LF		 1184static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1185 u16 beacon_int)
1186{
1187 b43legacy_time_lock(dev);
7858e07b
LF		 1188 if (dev->dev->id.revision >= 3) {
1189 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1190 (beacon_int << 16));
1191 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1192 (beacon_int << 10));
1193 } else {
75388acd
LF		 1194 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1195 b43legacy_write16(dev, 0x610, beacon_int);
1196 }
1197 b43legacy_time_unlock(dev);
7858e07b 1198 b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
75388acd
LF		 1199}
1200
1201static void handle_irq_beacon(struct b43legacy_wldev *dev)
1202{
a297170d
SB		 1203 struct b43legacy_wl *wl = dev->wl;
1204 u32 cmd;
7858e07b 1205 u32 beacon0_valid, beacon1_valid;
75388acd 1206
05c914fe 1207 if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
75388acd
LF		 1208 return;
1209
a297170d 1210 /* This is the bottom half of the asynchronous beacon update. */
75388acd 1211
a297170d 1212 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
7858e07b
LF		 1213 beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1214 beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1215 cmd &= ~(B43legacy_MACCMD_BEACON0_VALID | B43legacy_MACCMD_BEACON1_VALID);
1216
1217 if (!beacon0_valid) {
a297170d
SB		 1218 if (!wl->beacon0_uploaded) {
1219 b43legacy_write_beacon_template(dev, 0x68,
1220 B43legacy_SHM_SH_BTL0,
1221 B43legacy_CCK_RATE_1MB);
1222 b43legacy_write_probe_resp_template(dev, 0x268,
1223 B43legacy_SHM_SH_PRTLEN,
1224 &__b43legacy_ratetable[3]);
1225 wl->beacon0_uploaded = 1;
1226 }
1227 cmd |= B43legacy_MACCMD_BEACON0_VALID;
7858e07b 1228 } else if (!beacon1_valid) {
a297170d
SB		 1229 if (!wl->beacon1_uploaded) {
1230 b43legacy_write_beacon_template(dev, 0x468,
1231 B43legacy_SHM_SH_BTL1,
1232 B43legacy_CCK_RATE_1MB);
1233 wl->beacon1_uploaded = 1;
1234 }
1235 cmd |= B43legacy_MACCMD_BEACON1_VALID;
75388acd 1236 }
a297170d 1237 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
75388acd
LF		 1238}
1239
1240static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1241{
1242}
1243
1244/* Interrupt handler bottom-half */
1245static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1246{
1247 u32 reason;
1248 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1249 u32 merged_dma_reason = 0;
1250 int i;
75388acd
LF		 1251 unsigned long flags;
1252
1253 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1254
1255 B43legacy_WARN_ON(b43legacy_status(dev) <
1256 B43legacy_STAT_INITIALIZED);
1257
1258 reason = dev->irq_reason;
1259 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1260 dma_reason[i] = dev->dma_reason[i];
1261 merged_dma_reason |= dma_reason[i];
1262 }
1263
1264 if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1265 b43legacyerr(dev->wl, "MAC transmission error\n");
1266
a293ee99 1267 if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
75388acd 1268 b43legacyerr(dev->wl, "PHY transmission error\n");
a293ee99
SB		 1269 rmb();
1270 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1271 b43legacyerr(dev->wl, "Too many PHY TX errors, "
1272 "restarting the controller\n");
1273 b43legacy_controller_restart(dev, "PHY TX errors");
1274 }
1275 }
75388acd
LF		 1276
1277 if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1278 B43legacy_DMAIRQ_NONFATALMASK))) {
1279 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1280 b43legacyerr(dev->wl, "Fatal DMA error: "
1281 "0x%08X, 0x%08X, 0x%08X, "
1282 "0x%08X, 0x%08X, 0x%08X\n",
1283 dma_reason[0], dma_reason[1],
1284 dma_reason[2], dma_reason[3],
1285 dma_reason[4], dma_reason[5]);
1286 b43legacy_controller_restart(dev, "DMA error");
1287 mmiowb();
1288 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1289 return;
1290 }
1291 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1292 b43legacyerr(dev->wl, "DMA error: "
1293 "0x%08X, 0x%08X, 0x%08X, "
1294 "0x%08X, 0x%08X, 0x%08X\n",
1295 dma_reason[0], dma_reason[1],
1296 dma_reason[2], dma_reason[3],
1297 dma_reason[4], dma_reason[5]);
1298 }
1299
1300 if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1301 handle_irq_ucode_debug(dev);
1302 if (reason & B43legacy_IRQ_TBTT_INDI)
1303 handle_irq_tbtt_indication(dev);
1304 if (reason & B43legacy_IRQ_ATIM_END)
1305 handle_irq_atim_end(dev);
1306 if (reason & B43legacy_IRQ_BEACON)
1307 handle_irq_beacon(dev);
1308 if (reason & B43legacy_IRQ_PMQ)
1309 handle_irq_pmq(dev);
1310 if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1311 ;/*TODO*/
1312 if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1313 handle_irq_noise(dev);
1314
1315 /* Check the DMA reason registers for received data. */
1316 if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1317 if (b43legacy_using_pio(dev))
1318 b43legacy_pio_rx(dev->pio.queue0);
1319 else
1320 b43legacy_dma_rx(dev->dma.rx_ring0);
75388acd
LF		 1321 }
1322 B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1323 B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1324 if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1325 if (b43legacy_using_pio(dev))
1326 b43legacy_pio_rx(dev->pio.queue3);
1327 else
1328 b43legacy_dma_rx(dev->dma.rx_ring3);
75388acd
LF		 1329 }
1330 B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1331 B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1332
ba48f7bb 1333 if (reason & B43legacy_IRQ_TX_OK)
75388acd 1334 handle_irq_transmit_status(dev);
75388acd 1335
75388acd
LF		 1336 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
1337 mmiowb();
1338 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1339}
1340
1341static void pio_irq_workaround(struct b43legacy_wldev *dev,
1342 u16 base, int queueidx)
1343{
1344 u16 rxctl;
1345
1346 rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1347 if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1348 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1349 else
1350 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1351}
1352
1353static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1354{
1355 if (b43legacy_using_pio(dev) &&
1356 (dev->dev->id.revision < 3) &&
1357 (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1358 /* Apply a PIO specific workaround to the dma_reasons */
1359 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1360 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1361 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1362 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1363 }
1364
1365 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1366
1367 b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1368 dev->dma_reason[0]);
1369 b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1370 dev->dma_reason[1]);
1371 b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1372 dev->dma_reason[2]);
1373 b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1374 dev->dma_reason[3]);
1375 b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1376 dev->dma_reason[4]);
1377 b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1378 dev->dma_reason[5]);
1379}
1380
1381/* Interrupt handler top-half */
1382static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1383{
1384 irqreturn_t ret = IRQ_NONE;
1385 struct b43legacy_wldev *dev = dev_id;
1386 u32 reason;
1387
1388 if (!dev)
1389 return IRQ_NONE;
1390
1391 spin_lock(&dev->wl->irq_lock);
1392
1393 if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
1394 goto out;
1395 reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1396 if (reason == 0xffffffff) /* shared IRQ */
1397 goto out;
1398 ret = IRQ_HANDLED;
1399 reason &= b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
1400 if (!reason)
1401 goto out;
1402
1403 dev->dma_reason[0] = b43legacy_read32(dev,
1404 B43legacy_MMIO_DMA0_REASON)
1405 & 0x0001DC00;
1406 dev->dma_reason[1] = b43legacy_read32(dev,
1407 B43legacy_MMIO_DMA1_REASON)
1408 & 0x0000DC00;
1409 dev->dma_reason[2] = b43legacy_read32(dev,
1410 B43legacy_MMIO_DMA2_REASON)
1411 & 0x0000DC00;
1412 dev->dma_reason[3] = b43legacy_read32(dev,
1413 B43legacy_MMIO_DMA3_REASON)
1414 & 0x0001DC00;
1415 dev->dma_reason[4] = b43legacy_read32(dev,
1416 B43legacy_MMIO_DMA4_REASON)
1417 & 0x0000DC00;
1418 dev->dma_reason[5] = b43legacy_read32(dev,
1419 B43legacy_MMIO_DMA5_REASON)
1420 & 0x0000DC00;
1421
1422 b43legacy_interrupt_ack(dev, reason);
1423 /* disable all IRQs. They are enabled again in the bottom half. */
1424 dev->irq_savedstate = b43legacy_interrupt_disable(dev,
1425 B43legacy_IRQ_ALL);
1426 /* save the reason code and call our bottom half. */
1427 dev->irq_reason = reason;
1428 tasklet_schedule(&dev->isr_tasklet);
1429out:
1430 mmiowb();
1431 spin_unlock(&dev->wl->irq_lock);
1432
1433 return ret;
1434}
1435
1436static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1437{
1438 release_firmware(dev->fw.ucode);
1439 dev->fw.ucode = NULL;
1440 release_firmware(dev->fw.pcm);
1441 dev->fw.pcm = NULL;
1442 release_firmware(dev->fw.initvals);
1443 dev->fw.initvals = NULL;
1444 release_firmware(dev->fw.initvals_band);
1445 dev->fw.initvals_band = NULL;
1446}
1447
1448static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1449{
1450 b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
354807e0 1451 "Drivers/b43#devicefirmware "
75388acd
LF		 1452 "and download the correct firmware (version 3).\n");
1453}
1454
1455static int do_request_fw(struct b43legacy_wldev *dev,
1456 const char *name,
1457 const struct firmware **fw)
1458{
1459 char path[sizeof(modparam_fwpostfix) + 32];
1460 struct b43legacy_fw_header *hdr;
1461 u32 size;
1462 int err;
1463
1464 if (!name)
1465 return 0;
1466
1467 snprintf(path, ARRAY_SIZE(path),
1468 "b43legacy%s/%s.fw",
1469 modparam_fwpostfix, name);
1470 err = request_firmware(fw, path, dev->dev->dev);
1471 if (err) {
1472 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1473 "or load failed.\n", path);
1474 return err;
1475 }
1476 if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1477 goto err_format;
1478 hdr = (struct b43legacy_fw_header *)((*fw)->data);
1479 switch (hdr->type) {
1480 case B43legacy_FW_TYPE_UCODE:
1481 case B43legacy_FW_TYPE_PCM:
1482 size = be32_to_cpu(hdr->size);
1483 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1484 goto err_format;
1485 /* fallthrough */
1486 case B43legacy_FW_TYPE_IV:
1487 if (hdr->ver != 1)
1488 goto err_format;
1489 break;
1490 default:
1491 goto err_format;
1492 }
1493
1494 return err;
1495
1496err_format:
1497 b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1498 return -EPROTO;
1499}
1500
1501static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1502{
1503 struct b43legacy_firmware *fw = &dev->fw;
1504 const u8 rev = dev->dev->id.revision;
1505 const char *filename;
1506 u32 tmshigh;
1507 int err;
1508
1509 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1510 if (!fw->ucode) {
1511 if (rev == 2)
1512 filename = "ucode2";
1513 else if (rev == 4)
1514 filename = "ucode4";
1515 else
1516 filename = "ucode5";
1517 err = do_request_fw(dev, filename, &fw->ucode);
1518 if (err)
1519 goto err_load;
1520 }
1521 if (!fw->pcm) {
1522 if (rev < 5)
1523 filename = "pcm4";
1524 else
1525 filename = "pcm5";
1526 err = do_request_fw(dev, filename, &fw->pcm);
1527 if (err)
1528 goto err_load;
1529 }
1530 if (!fw->initvals) {
1531 switch (dev->phy.type) {
385f848a 1532 case B43legacy_PHYTYPE_B:
75388acd
LF		 1533 case B43legacy_PHYTYPE_G:
1534 if ((rev >= 5) && (rev <= 10))
1535 filename = "b0g0initvals5";
1536 else if (rev == 2 || rev == 4)
1537 filename = "b0g0initvals2";
1538 else
1539 goto err_no_initvals;
1540 break;
1541 default:
1542 goto err_no_initvals;
1543 }
1544 err = do_request_fw(dev, filename, &fw->initvals);
1545 if (err)
1546 goto err_load;
1547 }
1548 if (!fw->initvals_band) {
1549 switch (dev->phy.type) {
385f848a 1550 case B43legacy_PHYTYPE_B:
75388acd
LF		 1551 case B43legacy_PHYTYPE_G:
1552 if ((rev >= 5) && (rev <= 10))
1553 filename = "b0g0bsinitvals5";
1554 else if (rev >= 11)
1555 filename = NULL;
1556 else if (rev == 2 || rev == 4)
1557 filename = NULL;
1558 else
1559 goto err_no_initvals;
1560 break;
1561 default:
1562 goto err_no_initvals;
1563 }
1564 err = do_request_fw(dev, filename, &fw->initvals_band);
1565 if (err)
1566 goto err_load;
1567 }
1568
1569 return 0;
1570
1571err_load:
1572 b43legacy_print_fw_helptext(dev->wl);
1573 goto error;
1574
1575err_no_initvals:
1576 err = -ENODEV;
1577 b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1578 "core rev %u\n", dev->phy.type, rev);
1579 goto error;
1580
1581error:
1582 b43legacy_release_firmware(dev);
1583 return err;
1584}
1585
1586static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1587{
1588 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1589 const __be32 *data;
1590 unsigned int i;
1591 unsigned int len;
1592 u16 fwrev;
1593 u16 fwpatch;
1594 u16 fwdate;
1595 u16 fwtime;
e78c9d28 1596 u32 tmp, macctl;
75388acd
LF		 1597 int err = 0;
1598
e78c9d28
SB		 1599 /* Jump the microcode PSM to offset 0 */
1600 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1601 B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1602 macctl |= B43legacy_MACCTL_PSM_JMP0;
1603 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1604 /* Zero out all microcode PSM registers and shared memory. */
1605 for (i = 0; i < 64; i++)
1606 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1607 for (i = 0; i < 4096; i += 2)
1608 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1609
75388acd
LF		 1610 /* Upload Microcode. */
1611 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1612 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1613 b43legacy_shm_control_word(dev,
1614 B43legacy_SHM_UCODE |
1615 B43legacy_SHM_AUTOINC_W,
1616 0x0000);
1617 for (i = 0; i < len; i++) {
1618 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1619 be32_to_cpu(data[i]));
1620 udelay(10);
1621 }
1622
1623 if (dev->fw.pcm) {
1624 /* Upload PCM data. */
1625 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1626 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1627 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1628 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1629 /* No need for autoinc bit in SHM_HW */
1630 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1631 for (i = 0; i < len; i++) {
1632 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1633 be32_to_cpu(data[i]));
1634 udelay(10);
1635 }
1636 }
1637
1638 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1639 B43legacy_IRQ_ALL);
e78c9d28
SB		 1640
1641 /* Start the microcode PSM */
1642 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1643 macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1644 macctl |= B43legacy_MACCTL_PSM_RUN;
1645 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
75388acd
LF		 1646
1647 /* Wait for the microcode to load and respond */
1648 i = 0;
1649 while (1) {
1650 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1651 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1652 break;
1653 i++;
1654 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1655 b43legacyerr(dev->wl, "Microcode not responding\n");
1656 b43legacy_print_fw_helptext(dev->wl);
1657 err = -ENODEV;
e78c9d28
SB		 1658 goto error;
1659 }
1660 msleep_interruptible(50);
1661 if (signal_pending(current)) {
1662 err = -EINTR;
1663 goto error;
75388acd 1664 }
75388acd
LF		 1665 }
1666 /* dummy read follows */
1667 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1668
1669 /* Get and check the revisions. */
1670 fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1671 B43legacy_SHM_SH_UCODEREV);
1672 fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1673 B43legacy_SHM_SH_UCODEPATCH);
1674 fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1675 B43legacy_SHM_SH_UCODEDATE);
1676 fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1677 B43legacy_SHM_SH_UCODETIME);
1678
1679 if (fwrev > 0x128) {
1680 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1681 " Only firmware from binary drivers version 3.x"
1682 " is supported. You must change your firmware"
1683 " files.\n");
1684 b43legacy_print_fw_helptext(dev->wl);
75388acd 1685 err = -EOPNOTSUPP;
e78c9d28 1686 goto error;
75388acd 1687 }
cfbc35b6
SB		 1688 b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1689 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1690 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1691 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1692 fwtime & 0x1F);
75388acd
LF		 1693
1694 dev->fw.rev = fwrev;
1695 dev->fw.patch = fwpatch;
1696
e78c9d28
SB		 1697 return 0;
1698
1699error:
1700 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1701 macctl &= ~B43legacy_MACCTL_PSM_RUN;
1702 macctl |= B43legacy_MACCTL_PSM_JMP0;
1703 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1704
75388acd
LF		 1705 return err;
1706}
1707
1708static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1709 const struct b43legacy_iv *ivals,
1710 size_t count,
1711 size_t array_size)
1712{
1713 const struct b43legacy_iv *iv;
1714 u16 offset;
1715 size_t i;
1716 bool bit32;
1717
1718 BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1719 iv = ivals;
1720 for (i = 0; i < count; i++) {
1721 if (array_size < sizeof(iv->offset_size))
1722 goto err_format;
1723 array_size -= sizeof(iv->offset_size);
1724 offset = be16_to_cpu(iv->offset_size);
1725 bit32 = !!(offset & B43legacy_IV_32BIT);
1726 offset &= B43legacy_IV_OFFSET_MASK;
1727 if (offset >= 0x1000)
1728 goto err_format;
1729 if (bit32) {
1730 u32 value;
1731
1732 if (array_size < sizeof(iv->data.d32))
1733 goto err_format;
1734 array_size -= sizeof(iv->data.d32);
1735
533dd1b0 1736 value = get_unaligned_be32(&iv->data.d32);
75388acd
LF		 1737 b43legacy_write32(dev, offset, value);
1738
1739 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1740 sizeof(__be16) +
1741 sizeof(__be32));
1742 } else {
1743 u16 value;
1744
1745 if (array_size < sizeof(iv->data.d16))
1746 goto err_format;
1747 array_size -= sizeof(iv->data.d16);
1748
1749 value = be16_to_cpu(iv->data.d16);
1750 b43legacy_write16(dev, offset, value);
1751
1752 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1753 sizeof(__be16) +
1754 sizeof(__be16));
1755 }
1756 }
1757 if (array_size)
1758 goto err_format;
1759
1760 return 0;
1761
1762err_format:
1763 b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1764 b43legacy_print_fw_helptext(dev->wl);
1765
1766 return -EPROTO;
1767}
1768
1769static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1770{
1771 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1772 const struct b43legacy_fw_header *hdr;
1773 struct b43legacy_firmware *fw = &dev->fw;
1774 const struct b43legacy_iv *ivals;
1775 size_t count;
1776 int err;
1777
1778 hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1779 ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1780 count = be32_to_cpu(hdr->size);
1781 err = b43legacy_write_initvals(dev, ivals, count,
1782 fw->initvals->size - hdr_len);
1783 if (err)
1784 goto out;
1785 if (fw->initvals_band) {
1786 hdr = (const struct b43legacy_fw_header *)
1787 (fw->initvals_band->data);
1788 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1789 + hdr_len);
1790 count = be32_to_cpu(hdr->size);
1791 err = b43legacy_write_initvals(dev, ivals, count,
1792 fw->initvals_band->size - hdr_len);
1793 if (err)
1794 goto out;
1795 }
1796out:
1797
1798 return err;
1799}
1800
1801/* Initialize the GPIOs
1802 * http://bcm-specs.sipsolutions.net/GPIO
1803 */
1804static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1805{
1806 struct ssb_bus *bus = dev->dev->bus;
1807 struct ssb_device *gpiodev, *pcidev = NULL;
1808 u32 mask;
1809 u32 set;
1810
e78c9d28 1811 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1812 b43legacy_read32(dev,
e78c9d28 1813 B43legacy_MMIO_MACCTL)
75388acd
LF		 1814 & 0xFFFF3FFF);
1815
75388acd
LF		 1816 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1817 b43legacy_read16(dev,
1818 B43legacy_MMIO_GPIO_MASK)
1819 | 0x000F);
1820
1821 mask = 0x0000001F;
1822 set = 0x0000000F;
1823 if (dev->dev->bus->chip_id == 0x4301) {
1824 mask |= 0x0060;
1825 set |= 0x0060;
1826 }
7797aa38 1827 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
75388acd
LF		 1828 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1829 b43legacy_read16(dev,
1830 B43legacy_MMIO_GPIO_MASK)
1831 | 0x0200);
1832 mask |= 0x0200;
1833 set |= 0x0200;
1834 }
1835 if (dev->dev->id.revision >= 2)
1836 mask |= 0x0010; /* FIXME: This is redundant. */
1837
1838#ifdef CONFIG_SSB_DRIVER_PCICORE
1839 pcidev = bus->pcicore.dev;
1840#endif
1841 gpiodev = bus->chipco.dev ? : pcidev;
1842 if (!gpiodev)
1843 return 0;
1844 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1845 (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1846 & mask) | set);
1847
1848 return 0;
1849}
1850
1851/* Turn off all GPIO stuff. Call this on module unload, for example. */
1852static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1853{
1854 struct ssb_bus *bus = dev->dev->bus;
1855 struct ssb_device *gpiodev, *pcidev = NULL;
1856
1857#ifdef CONFIG_SSB_DRIVER_PCICORE
1858 pcidev = bus->pcicore.dev;
1859#endif
1860 gpiodev = bus->chipco.dev ? : pcidev;
1861 if (!gpiodev)
1862 return;
1863 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1864}
1865
1866/* http://bcm-specs.sipsolutions.net/EnableMac */
1867void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1868{
1869 dev->mac_suspended--;
1870 B43legacy_WARN_ON(dev->mac_suspended < 0);
f34eb692 1871 B43legacy_WARN_ON(irqs_disabled());
75388acd 1872 if (dev->mac_suspended == 0) {
e78c9d28 1873 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1874 b43legacy_read32(dev,
e78c9d28
SB		 1875 B43legacy_MMIO_MACCTL)
1876 | B43legacy_MACCTL_ENABLED);
75388acd
LF		 1877 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1878 B43legacy_IRQ_MAC_SUSPENDED);
1879 /* the next two are dummy reads */
e78c9d28 1880 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
75388acd
LF		 1881 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1882 b43legacy_power_saving_ctl_bits(dev, -1, -1);
f34eb692
LF		 1883
1884 /* Re-enable IRQs. */
1885 spin_lock_irq(&dev->wl->irq_lock);
1886 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
1887 spin_unlock_irq(&dev->wl->irq_lock);
75388acd
LF		 1888 }
1889}
1890
1891/* http://bcm-specs.sipsolutions.net/SuspendMAC */
1892void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1893{
1894 int i;
1895 u32 tmp;
1896
f34eb692
LF		 1897 might_sleep();
1898 B43legacy_WARN_ON(irqs_disabled());
75388acd 1899 B43legacy_WARN_ON(dev->mac_suspended < 0);
f34eb692 1900
75388acd 1901 if (dev->mac_suspended == 0) {
f34eb692
LF		 1902 /* Mask IRQs before suspending MAC. Otherwise
1903 * the MAC stays busy and won't suspend. */
1904 spin_lock_irq(&dev->wl->irq_lock);
1905 tmp = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
1906 spin_unlock_irq(&dev->wl->irq_lock);
1907 b43legacy_synchronize_irq(dev);
1908 dev->irq_savedstate = tmp;
1909
75388acd 1910 b43legacy_power_saving_ctl_bits(dev, -1, 1);
e78c9d28 1911 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1912 b43legacy_read32(dev,
e78c9d28
SB		 1913 B43legacy_MMIO_MACCTL)
1914 & ~B43legacy_MACCTL_ENABLED);
75388acd 1915 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
f34eb692 1916 for (i = 40; i; i--) {
75388acd
LF		 1917 tmp = b43legacy_read32(dev,
1918 B43legacy_MMIO_GEN_IRQ_REASON);
1919 if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1920 goto out;
f34eb692 1921 msleep(1);
75388acd
LF		 1922 }
1923 b43legacyerr(dev->wl, "MAC suspend failed\n");
1924 }
1925out:
1926 dev->mac_suspended++;
1927}
1928
1929static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1930{
1931 struct b43legacy_wl *wl = dev->wl;
1932 u32 ctl;
1933 u16 cfp_pretbtt;
1934
1935 ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1936 /* Reset status to STA infrastructure mode. */
1937 ctl &= ~B43legacy_MACCTL_AP;
1938 ctl &= ~B43legacy_MACCTL_KEEP_CTL;
1939 ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
1940 ctl &= ~B43legacy_MACCTL_KEEP_BAD;
1941 ctl &= ~B43legacy_MACCTL_PROMISC;
4150c572 1942 ctl &= ~B43legacy_MACCTL_BEACPROMISC;
75388acd
LF		 1943 ctl |= B43legacy_MACCTL_INFRA;
1944
05c914fe 1945 if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
4150c572 1946 ctl |= B43legacy_MACCTL_AP;
05c914fe 1947 else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 1948 ctl &= ~B43legacy_MACCTL_INFRA;
1949
1950 if (wl->filter_flags & FIF_CONTROL)
75388acd 1951 ctl |= B43legacy_MACCTL_KEEP_CTL;
4150c572
JB		 1952 if (wl->filter_flags & FIF_FCSFAIL)
1953 ctl |= B43legacy_MACCTL_KEEP_BAD;
1954 if (wl->filter_flags & FIF_PLCPFAIL)
1955 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
1956 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
75388acd 1957 ctl |= B43legacy_MACCTL_PROMISC;
4150c572
JB		 1958 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
1959 ctl |= B43legacy_MACCTL_BEACPROMISC;
1960
75388acd
LF		 1961 /* Workaround: On old hardware the HW-MAC-address-filter
1962 * doesn't work properly, so always run promisc in filter
1963 * it in software. */
1964 if (dev->dev->id.revision <= 4)
1965 ctl |= B43legacy_MACCTL_PROMISC;
1966
1967 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
1968
1969 cfp_pretbtt = 2;
1970 if ((ctl & B43legacy_MACCTL_INFRA) &&
1971 !(ctl & B43legacy_MACCTL_AP)) {
1972 if (dev->dev->bus->chip_id == 0x4306 &&
1973 dev->dev->bus->chip_rev == 3)
1974 cfp_pretbtt = 100;
1975 else
1976 cfp_pretbtt = 50;
1977 }
1978 b43legacy_write16(dev, 0x612, cfp_pretbtt);
1979}
1980
1981static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
1982 u16 rate,
1983 int is_ofdm)
1984{
1985 u16 offset;
1986
1987 if (is_ofdm) {
1988 offset = 0x480;
1989 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
1990 } else {
1991 offset = 0x4C0;
1992 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
1993 }
1994 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
1995 b43legacy_shm_read16(dev,
1996 B43legacy_SHM_SHARED, offset));
1997}
1998
1999static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2000{
2001 switch (dev->phy.type) {
2002 case B43legacy_PHYTYPE_G:
2003 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2004 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2005 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2006 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2007 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2008 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2009 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2010 /* fallthrough */
2011 case B43legacy_PHYTYPE_B:
2012 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2013 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2014 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2015 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2016 break;
2017 default:
2018 B43legacy_BUG_ON(1);
2019 }
2020}
2021
2022/* Set the TX-Antenna for management frames sent by firmware. */
2023static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2024 int antenna)
2025{
2026 u16 ant = 0;
2027 u16 tmp;
2028
2029 switch (antenna) {
2030 case B43legacy_ANTENNA0:
2031 ant |= B43legacy_TX4_PHY_ANT0;
2032 break;
2033 case B43legacy_ANTENNA1:
2034 ant |= B43legacy_TX4_PHY_ANT1;
2035 break;
2036 case B43legacy_ANTENNA_AUTO:
2037 ant |= B43legacy_TX4_PHY_ANTLAST;
2038 break;
2039 default:
2040 B43legacy_BUG_ON(1);
2041 }
2042
2043 /* FIXME We also need to set the other flags of the PHY control
2044 * field somewhere. */
2045
2046 /* For Beacons */
2047 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2048 B43legacy_SHM_SH_BEACPHYCTL);
2049 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2050 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2051 B43legacy_SHM_SH_BEACPHYCTL, tmp);
2052 /* For ACK/CTS */
2053 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2054 B43legacy_SHM_SH_ACKCTSPHYCTL);
2055 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2056 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2057 B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2058 /* For Probe Resposes */
2059 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2060 B43legacy_SHM_SH_PRPHYCTL);
2061 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2062 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2063 B43legacy_SHM_SH_PRPHYCTL, tmp);
2064}
2065
2066/* This is the opposite of b43legacy_chip_init() */
2067static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2068{
93bb7f3a 2069 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 2070 b43legacy_gpio_cleanup(dev);
2071 /* firmware is released later */
2072}
2073
2074/* Initialize the chip
2075 * http://bcm-specs.sipsolutions.net/ChipInit
2076 */
2077static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2078{
2079 struct b43legacy_phy *phy = &dev->phy;
2080 int err;
2081 int tmp;
e78c9d28 2082 u32 value32, macctl;
75388acd
LF		 2083 u16 value16;
2084
e78c9d28
SB		 2085 /* Initialize the MAC control */
2086 macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2087 if (dev->phy.gmode)
2088 macctl |= B43legacy_MACCTL_GMODE;
2089 macctl |= B43legacy_MACCTL_INFRA;
2090 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
75388acd
LF		 2091
2092 err = b43legacy_request_firmware(dev);
2093 if (err)
2094 goto out;
2095 err = b43legacy_upload_microcode(dev);
2096 if (err)
2097 goto out; /* firmware is released later */
2098
2099 err = b43legacy_gpio_init(dev);
2100 if (err)
2101 goto out; /* firmware is released later */
ba48f7bb 2102
75388acd
LF		 2103 err = b43legacy_upload_initvals(dev);
2104 if (err)
4ad36d78 2105 goto err_gpio_clean;
75388acd 2106 b43legacy_radio_turn_on(dev);
75388acd
LF		 2107
2108 b43legacy_write16(dev, 0x03E6, 0x0000);
2109 err = b43legacy_phy_init(dev);
2110 if (err)
2111 goto err_radio_off;
2112
2113 /* Select initial Interference Mitigation. */
2114 tmp = phy->interfmode;
2115 phy->interfmode = B43legacy_INTERFMODE_NONE;
2116 b43legacy_radio_set_interference_mitigation(dev, tmp);
2117
2118 b43legacy_phy_set_antenna_diversity(dev);
2119 b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2120
2121 if (phy->type == B43legacy_PHYTYPE_B) {
2122 value16 = b43legacy_read16(dev, 0x005E);
2123 value16 |= 0x0004;
2124 b43legacy_write16(dev, 0x005E, value16);
2125 }
2126 b43legacy_write32(dev, 0x0100, 0x01000000);
2127 if (dev->dev->id.revision < 5)
2128 b43legacy_write32(dev, 0x010C, 0x01000000);
2129
e78c9d28
SB		 2130 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2131 value32 &= ~B43legacy_MACCTL_INFRA;
2132 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2133 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2134 value32 |= B43legacy_MACCTL_INFRA;
2135 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
75388acd 2136
75388acd
LF		 2137 if (b43legacy_using_pio(dev)) {
2138 b43legacy_write32(dev, 0x0210, 0x00000100);
2139 b43legacy_write32(dev, 0x0230, 0x00000100);
2140 b43legacy_write32(dev, 0x0250, 0x00000100);
2141 b43legacy_write32(dev, 0x0270, 0x00000100);
2142 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2143 0x0000);
2144 }
2145
2146 /* Probe Response Timeout value */
2147 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2148 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2149
2150 /* Initially set the wireless operation mode. */
2151 b43legacy_adjust_opmode(dev);
2152
2153 if (dev->dev->id.revision < 3) {
2154 b43legacy_write16(dev, 0x060E, 0x0000);
2155 b43legacy_write16(dev, 0x0610, 0x8000);
2156 b43legacy_write16(dev, 0x0604, 0x0000);
2157 b43legacy_write16(dev, 0x0606, 0x0200);
2158 } else {
2159 b43legacy_write32(dev, 0x0188, 0x80000000);
2160 b43legacy_write32(dev, 0x018C, 0x02000000);
2161 }
2162 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2163 b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2164 b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2165 b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2166 b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2167 b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2168 b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2169
2170 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2171 value32 |= 0x00100000;
2172 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2173
2174 b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2175 dev->dev->bus->chipco.fast_pwrup_delay);
2176
a293ee99
SB		 2177 /* PHY TX errors counter. */
2178 atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2179
75388acd
LF		 2180 B43legacy_WARN_ON(err != 0);
2181 b43legacydbg(dev->wl, "Chip initialized\n");
2182out:
2183 return err;
2184
2185err_radio_off:
93bb7f3a 2186 b43legacy_radio_turn_off(dev, 1);
4ad36d78 2187err_gpio_clean:
75388acd
LF		 2188 b43legacy_gpio_cleanup(dev);
2189 goto out;
2190}
2191
2192static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2193{
2194 struct b43legacy_phy *phy = &dev->phy;
2195
2196 if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2197 return;
2198
2199 b43legacy_mac_suspend(dev);
2200 b43legacy_phy_lo_g_measure(dev);
2201 b43legacy_mac_enable(dev);
2202}
2203
2204static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2205{
2206 b43legacy_phy_lo_mark_all_unused(dev);
7797aa38 2207 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
75388acd
LF		 2208 b43legacy_mac_suspend(dev);
2209 b43legacy_calc_nrssi_slope(dev);
2210 b43legacy_mac_enable(dev);
2211 }
2212}
2213
2214static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2215{
2216 /* Update device statistics. */
2217 b43legacy_calculate_link_quality(dev);
2218}
2219
2220static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2221{
2222 b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
a293ee99
SB		 2223
2224 atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2225 wmb();
75388acd
LF		 2226}
2227
75388acd
LF		 2228static void do_periodic_work(struct b43legacy_wldev *dev)
2229{
2230 unsigned int state;
2231
2232 state = dev->periodic_state;
6be50837 2233 if (state % 8 == 0)
75388acd 2234 b43legacy_periodic_every120sec(dev);
6be50837 2235 if (state % 4 == 0)
75388acd 2236 b43legacy_periodic_every60sec(dev);
6be50837 2237 if (state % 2 == 0)
75388acd 2238 b43legacy_periodic_every30sec(dev);
6be50837 2239 b43legacy_periodic_every15sec(dev);
75388acd
LF		 2240}
2241
f34eb692
LF		 2242/* Periodic work locking policy:
2243 * The whole periodic work handler is protected by
2244 * wl->mutex. If another lock is needed somewhere in the
2245 * pwork callchain, it's aquired in-place, where it's needed.
75388acd 2246 */
75388acd
LF		 2247static void b43legacy_periodic_work_handler(struct work_struct *work)
2248{
f34eb692
LF		 2249 struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2250 periodic_work.work);
2251 struct b43legacy_wl *wl = dev->wl;
75388acd 2252 unsigned long delay;
75388acd 2253
f34eb692 2254 mutex_lock(&wl->mutex);
75388acd
LF		 2255
2256 if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2257 goto out;
2258 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2259 goto out_requeue;
2260
f34eb692 2261 do_periodic_work(dev);
75388acd 2262
75388acd
LF		 2263 dev->periodic_state++;
2264out_requeue:
2265 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2266 delay = msecs_to_jiffies(50);
2267 else
6be50837 2268 delay = round_jiffies_relative(HZ * 15);
f34eb692 2269 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
75388acd 2270out:
f34eb692 2271 mutex_unlock(&wl->mutex);
75388acd
LF		 2272}
2273
2274static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2275{
2276 struct delayed_work *work = &dev->periodic_work;
2277
2278 dev->periodic_state = 0;
2279 INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2280 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2281}
2282
2283/* Validate access to the chip (SHM) */
2284static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2285{
2286 u32 value;
2287 u32 shm_backup;
2288
2289 shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2290 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2291 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2292 0xAA5555AA)
2293 goto error;
2294 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2295 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2296 0x55AAAA55)
2297 goto error;
2298 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2299
2300 value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2301 if ((value | B43legacy_MACCTL_GMODE) !=
2302 (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2303 goto error;
2304
2305 value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2306 if (value)
2307 goto error;
2308
2309 return 0;
2310error:
2311 b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2312 return -ENODEV;
2313}
2314
2315static void b43legacy_security_init(struct b43legacy_wldev *dev)
2316{
2317 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2318 B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2319 dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2320 0x0056);
2321 /* KTP is a word address, but we address SHM bytewise.
2322 * So multiply by two.
2323 */
2324 dev->ktp *= 2;
2325 if (dev->dev->id.revision >= 5)
2326 /* Number of RCMTA address slots */
2327 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2328 dev->max_nr_keys - 8);
2329}
2330
910cfee3 2331#ifdef CONFIG_B43LEGACY_HWRNG
75388acd
LF		 2332static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2333{
2334 struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2335 unsigned long flags;
2336
2337 /* Don't take wl->mutex here, as it could deadlock with
2338 * hwrng internal locking. It's not needed to take
2339 * wl->mutex here, anyway. */
2340
2341 spin_lock_irqsave(&wl->irq_lock, flags);
2342 *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2343 spin_unlock_irqrestore(&wl->irq_lock, flags);
2344
2345 return (sizeof(u16));
2346}
910cfee3 2347#endif
75388acd
LF		 2348
2349static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2350{
910cfee3 2351#ifdef CONFIG_B43LEGACY_HWRNG
75388acd
LF		 2352 if (wl->rng_initialized)
2353 hwrng_unregister(&wl->rng);
910cfee3 2354#endif
75388acd
LF		 2355}
2356
2357static int b43legacy_rng_init(struct b43legacy_wl *wl)
2358{
910cfee3 2359 int err = 0;
75388acd 2360
910cfee3 2361#ifdef CONFIG_B43LEGACY_HWRNG
75388acd
LF		 2362 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2363 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2364 wl->rng.name = wl->rng_name;
2365 wl->rng.data_read = b43legacy_rng_read;
2366 wl->rng.priv = (unsigned long)wl;
2367 wl->rng_initialized = 1;
2368 err = hwrng_register(&wl->rng);
2369 if (err) {
2370 wl->rng_initialized = 0;
2371 b43legacyerr(wl, "Failed to register the random "
2372 "number generator (%d)\n", err);
2373 }
2374
910cfee3 2375#endif
75388acd
LF		 2376 return err;
2377}
2378
33a3dc93 2379static int b43legacy_op_tx(struct ieee80211_hw *hw,
e039fa4a 2380 struct sk_buff *skb)
75388acd
LF		 2381{
2382 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2383 struct b43legacy_wldev *dev = wl->current_dev;
2384 int err = -ENODEV;
2385 unsigned long flags;
2386
2387 if (unlikely(!dev))
2388 goto out;
2389 if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2390 goto out;
2391 /* DMA-TX is done without a global lock. */
2392 if (b43legacy_using_pio(dev)) {
2393 spin_lock_irqsave(&wl->irq_lock, flags);
e039fa4a 2394 err = b43legacy_pio_tx(dev, skb);
75388acd
LF		 2395 spin_unlock_irqrestore(&wl->irq_lock, flags);
2396 } else
e039fa4a 2397 err = b43legacy_dma_tx(dev, skb);
75388acd 2398out:
664f2006
MB		 2399 if (unlikely(err)) {
2400 /* Drop the packet. */
2401 dev_kfree_skb_any(skb);
2402 }
75388acd
LF		 2403 return NETDEV_TX_OK;
2404}
2405
e100bb64 2406static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
33a3dc93 2407 const struct ieee80211_tx_queue_params *params)
75388acd
LF		 2408{
2409 return 0;
2410}
2411
33a3dc93
SB		 2412static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
2413 struct ieee80211_tx_queue_stats *stats)
75388acd
LF		 2414{
2415 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2416 struct b43legacy_wldev *dev = wl->current_dev;
2417 unsigned long flags;
2418 int err = -ENODEV;
2419
2420 if (!dev)
2421 goto out;
2422 spin_lock_irqsave(&wl->irq_lock, flags);
2423 if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
2424 if (b43legacy_using_pio(dev))
2425 b43legacy_pio_get_tx_stats(dev, stats);
2426 else
2427 b43legacy_dma_get_tx_stats(dev, stats);
2428 err = 0;
2429 }
2430 spin_unlock_irqrestore(&wl->irq_lock, flags);
2431out:
2432 return err;
2433}
2434
33a3dc93
SB		 2435static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2436 struct ieee80211_low_level_stats *stats)
75388acd
LF		 2437{
2438 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2439 unsigned long flags;
2440
2441 spin_lock_irqsave(&wl->irq_lock, flags);
2442 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2443 spin_unlock_irqrestore(&wl->irq_lock, flags);
2444
2445 return 0;
2446}
2447
2448static const char *phymode_to_string(unsigned int phymode)
2449{
2450 switch (phymode) {
2451 case B43legacy_PHYMODE_B:
2452 return "B";
2453 case B43legacy_PHYMODE_G:
2454 return "G";
2455 default:
2456 B43legacy_BUG_ON(1);
2457 }
2458 return "";
2459}
2460
2461static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2462 unsigned int phymode,
2463 struct b43legacy_wldev **dev,
2464 bool *gmode)
2465{
2466 struct b43legacy_wldev *d;
2467
2468 list_for_each_entry(d, &wl->devlist, list) {
2469 if (d->phy.possible_phymodes & phymode) {
2470 /* Ok, this device supports the PHY-mode.
2471 * Set the gmode bit. */
2472 *gmode = 1;
2473 *dev = d;
2474
2475 return 0;
2476 }
2477 }
2478
2479 return -ESRCH;
2480}
2481
2482static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2483{
2484 struct ssb_device *sdev = dev->dev;
2485 u32 tmslow;
2486
2487 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2488 tmslow &= ~B43legacy_TMSLOW_GMODE;
2489 tmslow |= B43legacy_TMSLOW_PHYRESET;
2490 tmslow |= SSB_TMSLOW_FGC;
2491 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2492 msleep(1);
2493
2494 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2495 tmslow &= ~SSB_TMSLOW_FGC;
2496 tmslow |= B43legacy_TMSLOW_PHYRESET;
2497 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2498 msleep(1);
2499}
2500
2501/* Expects wl->mutex locked */
2502static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2503 unsigned int new_mode)
2504{
08cb7e01 2505 struct b43legacy_wldev *uninitialized_var(up_dev);
75388acd
LF		 2506 struct b43legacy_wldev *down_dev;
2507 int err;
2508 bool gmode = 0;
2509 int prev_status;
2510
2511 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2512 if (err) {
2513 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2514 phymode_to_string(new_mode));
2515 return err;
2516 }
2517 if ((up_dev == wl->current_dev) &&
2518 (!!wl->current_dev->phy.gmode == !!gmode))
2519 /* This device is already running. */
2520 return 0;
2521 b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2522 phymode_to_string(new_mode));
2523 down_dev = wl->current_dev;
2524
2525 prev_status = b43legacy_status(down_dev);
2526 /* Shutdown the currently running core. */
2527 if (prev_status >= B43legacy_STAT_STARTED)
2528 b43legacy_wireless_core_stop(down_dev);
2529 if (prev_status >= B43legacy_STAT_INITIALIZED)
2530 b43legacy_wireless_core_exit(down_dev);
2531
2532 if (down_dev != up_dev)
2533 /* We switch to a different core, so we put PHY into
2534 * RESET on the old core. */
2535 b43legacy_put_phy_into_reset(down_dev);
2536
2537 /* Now start the new core. */
2538 up_dev->phy.gmode = gmode;
2539 if (prev_status >= B43legacy_STAT_INITIALIZED) {
2540 err = b43legacy_wireless_core_init(up_dev);
2541 if (err) {
2542 b43legacyerr(wl, "Fatal: Could not initialize device"
2543 " for newly selected %s-PHY mode\n",
2544 phymode_to_string(new_mode));
2545 goto init_failure;
2546 }
2547 }
2548 if (prev_status >= B43legacy_STAT_STARTED) {
2549 err = b43legacy_wireless_core_start(up_dev);
2550 if (err) {
2551 b43legacyerr(wl, "Fatal: Coult not start device for "
2552 "newly selected %s-PHY mode\n",
2553 phymode_to_string(new_mode));
2554 b43legacy_wireless_core_exit(up_dev);
2555 goto init_failure;
2556 }
2557 }
2558 B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2559
2560 b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2561
2562 wl->current_dev = up_dev;
2563
2564 return 0;
2565init_failure:
2566 /* Whoops, failed to init the new core. No core is operating now. */
2567 wl->current_dev = NULL;
2568 return err;
2569}
2570
9124b077
JB		 2571/* Write the short and long frame retry limit values. */
2572static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2573 unsigned int short_retry,
2574 unsigned int long_retry)
2575{
2576 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2577 * the chip-internal counter. */
2578 short_retry = min(short_retry, (unsigned int)0xF);
2579 long_retry = min(long_retry, (unsigned int)0xF);
2580
2581 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2582 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2583}
2584
33a3dc93 2585static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
e8975581 2586 u32 changed)
75388acd
LF		 2587{
2588 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2589 struct b43legacy_wldev *dev;
2590 struct b43legacy_phy *phy;
e8975581 2591 struct ieee80211_conf *conf = &hw->conf;
75388acd
LF		 2592 unsigned long flags;
2593 unsigned int new_phymode = 0xFFFF;
2594 int antenna_tx;
2595 int antenna_rx;
2596 int err = 0;
2597 u32 savedirqs;
2598
0f4ac38b
JB		 2599 antenna_tx = B43legacy_ANTENNA_DEFAULT;
2600 antenna_rx = B43legacy_ANTENNA_DEFAULT;
75388acd
LF		 2601
2602 mutex_lock(&wl->mutex);
8318d78a
JB		 2603 dev = wl->current_dev;
2604 phy = &dev->phy;
75388acd 2605
9124b077
JB		 2606 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2607 b43legacy_set_retry_limits(dev,
2608 conf->short_frame_max_tx_count,
2609 conf->long_frame_max_tx_count);
2610 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2611 if (!changed)
2612 goto out_unlock_mutex;
2613
75388acd 2614 /* Switch the PHY mode (if necessary). */
8318d78a
JB		 2615 switch (conf->channel->band) {
2616 case IEEE80211_BAND_2GHZ:
2617 if (phy->type == B43legacy_PHYTYPE_B)
2618 new_phymode = B43legacy_PHYMODE_B;
2619 else
2620 new_phymode = B43legacy_PHYMODE_G;
75388acd
LF		 2621 break;
2622 default:
2623 B43legacy_WARN_ON(1);
2624 }
2625 err = b43legacy_switch_phymode(wl, new_phymode);
2626 if (err)
2627 goto out_unlock_mutex;
75388acd
LF		 2628
2629 /* Disable IRQs while reconfiguring the device.
2630 * This makes it possible to drop the spinlock throughout
2631 * the reconfiguration process. */
2632 spin_lock_irqsave(&wl->irq_lock, flags);
2633 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2634 spin_unlock_irqrestore(&wl->irq_lock, flags);
2635 goto out_unlock_mutex;
2636 }
2637 savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
2638 spin_unlock_irqrestore(&wl->irq_lock, flags);
2639 b43legacy_synchronize_irq(dev);
2640
2641 /* Switch to the requested channel.
2642 * The firmware takes care of races with the TX handler. */
8318d78a
JB		 2643 if (conf->channel->hw_value != phy->channel)
2644 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
75388acd 2645
5be3bda8
JB		 2646 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2647
75388acd
LF		 2648 /* Adjust the desired TX power level. */
2649 if (conf->power_level != 0) {
2650 if (conf->power_level != phy->power_level) {
2651 phy->power_level = conf->power_level;
2652 b43legacy_phy_xmitpower(dev);
2653 }
2654 }
2655
2656 /* Antennas for RX and management frame TX. */
2657 b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2658
2659 /* Update templates for AP mode. */
05c914fe 2660 if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
75388acd
LF		 2661 b43legacy_set_beacon_int(dev, conf->beacon_int);
2662
2663
42a9174f
LF		 2664 if (!!conf->radio_enabled != phy->radio_on) {
2665 if (conf->radio_enabled) {
2666 b43legacy_radio_turn_on(dev);
2667 b43legacyinfo(dev->wl, "Radio turned on by software\n");
2668 if (!dev->radio_hw_enable)
2669 b43legacyinfo(dev->wl, "The hardware RF-kill"
2670 " button still turns the radio"
2671 " physically off. Press the"
2672 " button to turn it on.\n");
2673 } else {
93bb7f3a 2674 b43legacy_radio_turn_off(dev, 0);
42a9174f
LF		 2675 b43legacyinfo(dev->wl, "Radio turned off by"
2676 " software\n");
2677 }
2678 }
2679
75388acd
LF		 2680 spin_lock_irqsave(&wl->irq_lock, flags);
2681 b43legacy_interrupt_enable(dev, savedirqs);
2682 mmiowb();
2683 spin_unlock_irqrestore(&wl->irq_lock, flags);
2684out_unlock_mutex:
2685 mutex_unlock(&wl->mutex);
2686
2687 return err;
2688}
2689
881d948c 2690static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
7f3704e9
JB		 2691{
2692 struct ieee80211_supported_band *sband =
2693 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2694 struct ieee80211_rate *rate;
2695 int i;
2696 u16 basic, direct, offset, basic_offset, rateptr;
2697
2698 for (i = 0; i < sband->n_bitrates; i++) {
2699 rate = &sband->bitrates[i];
2700
2701 if (b43legacy_is_cck_rate(rate->hw_value)) {
2702 direct = B43legacy_SHM_SH_CCKDIRECT;
2703 basic = B43legacy_SHM_SH_CCKBASIC;
2704 offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2705 offset &= 0xF;
2706 } else {
2707 direct = B43legacy_SHM_SH_OFDMDIRECT;
2708 basic = B43legacy_SHM_SH_OFDMBASIC;
2709 offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2710 offset &= 0xF;
2711 }
2712
2713 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2714
2715 if (b43legacy_is_cck_rate(rate->hw_value)) {
2716 basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2717 basic_offset &= 0xF;
2718 } else {
2719 basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2720 basic_offset &= 0xF;
2721 }
2722
2723 /*
2724 * Get the pointer that we need to point to
2725 * from the direct map
2726 */
2727 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2728 direct + 2 * basic_offset);
2729 /* and write it to the basic map */
2730 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2731 basic + 2 * offset, rateptr);
2732 }
2733}
2734
2735static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2736 struct ieee80211_vif *vif,
2737 struct ieee80211_bss_conf *conf,
2738 u32 changed)
2739{
2740 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2741 struct b43legacy_wldev *dev;
2742 struct b43legacy_phy *phy;
2743 unsigned long flags;
2744 u32 savedirqs;
2745
2746 mutex_lock(&wl->mutex);
2747
2748 dev = wl->current_dev;
2749 phy = &dev->phy;
2750
2751 /* Disable IRQs while reconfiguring the device.
2752 * This makes it possible to drop the spinlock throughout
2753 * the reconfiguration process. */
2754 spin_lock_irqsave(&wl->irq_lock, flags);
2755 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2756 spin_unlock_irqrestore(&wl->irq_lock, flags);
2757 goto out_unlock_mutex;
2758 }
2759 savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
2760 spin_unlock_irqrestore(&wl->irq_lock, flags);
2761 b43legacy_synchronize_irq(dev);
2762
2763 b43legacy_mac_suspend(dev);
2764
2765 if (changed & BSS_CHANGED_BASIC_RATES)
2766 b43legacy_update_basic_rates(dev, conf->basic_rates);
2767
2768 if (changed & BSS_CHANGED_ERP_SLOT) {
2769 if (conf->use_short_slot)
2770 b43legacy_short_slot_timing_enable(dev);
2771 else
2772 b43legacy_short_slot_timing_disable(dev);
2773 }
2774
2775 b43legacy_mac_enable(dev);
2776
2777 spin_lock_irqsave(&wl->irq_lock, flags);
2778 b43legacy_interrupt_enable(dev, savedirqs);
2779 /* XXX: why? */
2780 mmiowb();
2781 spin_unlock_irqrestore(&wl->irq_lock, flags);
2782 out_unlock_mutex:
2783 mutex_unlock(&wl->mutex);
2784
2785 return;
2786}
2787
33a3dc93
SB		 2788static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2789 unsigned int changed,
2790 unsigned int *fflags,
2791 int mc_count,
2792 struct dev_addr_list *mc_list)
75388acd
LF		 2793{
2794 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2795 struct b43legacy_wldev *dev = wl->current_dev;
2796 unsigned long flags;
2797
4150c572
JB		 2798 if (!dev) {
2799 *fflags = 0;
75388acd 2800 return;
75388acd 2801 }
4150c572
JB		 2802
2803 spin_lock_irqsave(&wl->irq_lock, flags);
2804 *fflags &= FIF_PROMISC_IN_BSS |
2805 FIF_ALLMULTI |
2806 FIF_FCSFAIL |
2807 FIF_PLCPFAIL |
2808 FIF_CONTROL |
2809 FIF_OTHER_BSS |
2810 FIF_BCN_PRBRESP_PROMISC;
2811
2812 changed &= FIF_PROMISC_IN_BSS |
2813 FIF_ALLMULTI |
2814 FIF_FCSFAIL |
2815 FIF_PLCPFAIL |
2816 FIF_CONTROL |
2817 FIF_OTHER_BSS |
2818 FIF_BCN_PRBRESP_PROMISC;
2819
2820 wl->filter_flags = *fflags;
2821
2822 if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2823 b43legacy_adjust_opmode(dev);
75388acd
LF		 2824 spin_unlock_irqrestore(&wl->irq_lock, flags);
2825}
2826
33a3dc93 2827static int b43legacy_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 2828 struct ieee80211_vif *vif,
33a3dc93 2829 struct ieee80211_if_conf *conf)
75388acd
LF		 2830{
2831 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2832 struct b43legacy_wldev *dev = wl->current_dev;
2833 unsigned long flags;
2834
2835 if (!dev)
2836 return -ENODEV;
2837 mutex_lock(&wl->mutex);
2838 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 2839 B43legacy_WARN_ON(wl->vif != vif);
4150c572
JB		 2840 if (conf->bssid)
2841 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2842 else
2843 memset(wl->bssid, 0, ETH_ALEN);
2844 if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
05c914fe
JB		 2845 if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP)) {
2846 B43legacy_WARN_ON(vif->type != NL80211_IFTYPE_AP);
9d139c81
JB		 2847 if (conf->changed & IEEE80211_IFCC_BEACON)
2848 b43legacy_update_templates(wl);
05c914fe 2849 } else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)) {
9d139c81
JB		 2850 if (conf->changed & IEEE80211_IFCC_BEACON)
2851 b43legacy_update_templates(wl);
75388acd 2852 }
4150c572 2853 b43legacy_write_mac_bssid_templates(dev);
75388acd
LF		 2854 }
2855 spin_unlock_irqrestore(&wl->irq_lock, flags);
2856 mutex_unlock(&wl->mutex);
2857
2858 return 0;
2859}
2860
2861/* Locking: wl->mutex */
2862static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2863{
2864 struct b43legacy_wl *wl = dev->wl;
2865 unsigned long flags;
2866
2867 if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2868 return;
440cb58a
SB		 2869
2870 /* Disable and sync interrupts. We must do this before than
2871 * setting the status to INITIALIZED, as the interrupt handler
2872 * won't care about IRQs then. */
2873 spin_lock_irqsave(&wl->irq_lock, flags);
2874 dev->irq_savedstate = b43legacy_interrupt_disable(dev,
2875 B43legacy_IRQ_ALL);
2876 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2877 spin_unlock_irqrestore(&wl->irq_lock, flags);
2878 b43legacy_synchronize_irq(dev);
2879
75388acd
LF		 2880 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2881
2882 mutex_unlock(&wl->mutex);
2883 /* Must unlock as it would otherwise deadlock. No races here.
2884 * Cancel the possibly running self-rearming periodic work. */
2885 cancel_delayed_work_sync(&dev->periodic_work);
2886 mutex_lock(&wl->mutex);
2887
2888 ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2889
75388acd
LF		 2890 b43legacy_mac_suspend(dev);
2891 free_irq(dev->dev->irq, dev);
2892 b43legacydbg(wl, "Wireless interface stopped\n");
2893}
2894
2895/* Locking: wl->mutex */
2896static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2897{
2898 int err;
2899
2900 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2901
2902 drain_txstatus_queue(dev);
2903 err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2904 IRQF_SHARED, KBUILD_MODNAME, dev);
2905 if (err) {
2906 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2907 dev->dev->irq);
2908 goto out;
2909 }
2910 /* We are ready to run. */
2911 b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2912
2913 /* Start data flow (TX/RX) */
2914 b43legacy_mac_enable(dev);
2915 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
75388acd
LF		 2916
2917 /* Start maintenance work */
2918 b43legacy_periodic_tasks_setup(dev);
2919
2920 b43legacydbg(dev->wl, "Wireless interface started\n");
2921out:
2922 return err;
2923}
2924
2925/* Get PHY and RADIO versioning numbers */
2926static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2927{
2928 struct b43legacy_phy *phy = &dev->phy;
2929 u32 tmp;
2930 u8 analog_type;
2931 u8 phy_type;
2932 u8 phy_rev;
2933 u16 radio_manuf;
2934 u16 radio_ver;
2935 u16 radio_rev;
2936 int unsupported = 0;
2937
2938 /* Get PHY versioning */
2939 tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2940 analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2941 >> B43legacy_PHYVER_ANALOG_SHIFT;
2942 phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2943 phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2944 switch (phy_type) {
2945 case B43legacy_PHYTYPE_B:
2946 if (phy_rev != 2 && phy_rev != 4
2947 && phy_rev != 6 && phy_rev != 7)
2948 unsupported = 1;
2949 break;
2950 case B43legacy_PHYTYPE_G:
2951 if (phy_rev > 8)
2952 unsupported = 1;
2953 break;
2954 default:
2955 unsupported = 1;
2956 };
2957 if (unsupported) {
2958 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2959 "(Analog %u, Type %u, Revision %u)\n",
2960 analog_type, phy_type, phy_rev);
2961 return -EOPNOTSUPP;
2962 }
2963 b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2964 analog_type, phy_type, phy_rev);
2965
2966
2967 /* Get RADIO versioning */
2968 if (dev->dev->bus->chip_id == 0x4317) {
2969 if (dev->dev->bus->chip_rev == 0)
2970 tmp = 0x3205017F;
2971 else if (dev->dev->bus->chip_rev == 1)
2972 tmp = 0x4205017F;
2973 else
2974 tmp = 0x5205017F;
2975 } else {
2976 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2977 B43legacy_RADIOCTL_ID);
2978 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
2979 tmp <<= 16;
2980 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2981 B43legacy_RADIOCTL_ID);
2982 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
2983 }
2984 radio_manuf = (tmp & 0x00000FFF);
2985 radio_ver = (tmp & 0x0FFFF000) >> 12;
2986 radio_rev = (tmp & 0xF0000000) >> 28;
2987 switch (phy_type) {
2988 case B43legacy_PHYTYPE_B:
2989 if ((radio_ver & 0xFFF0) != 0x2050)
2990 unsupported = 1;
2991 break;
2992 case B43legacy_PHYTYPE_G:
2993 if (radio_ver != 0x2050)
2994 unsupported = 1;
2995 break;
2996 default:
2997 B43legacy_BUG_ON(1);
2998 }
2999 if (unsupported) {
3000 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
3001 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3002 radio_manuf, radio_ver, radio_rev);
3003 return -EOPNOTSUPP;
3004 }
3005 b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
3006 " Revision %u\n", radio_manuf, radio_ver, radio_rev);
3007
3008
3009 phy->radio_manuf = radio_manuf;
3010 phy->radio_ver = radio_ver;
3011 phy->radio_rev = radio_rev;
3012
3013 phy->analog = analog_type;
3014 phy->type = phy_type;
3015 phy->rev = phy_rev;
3016
3017 return 0;
3018}
3019
3020static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
3021 struct b43legacy_phy *phy)
3022{
3023 struct b43legacy_lopair *lo;
3024 int i;
3025
3026 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3027 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3028
1065de15
LF		 3029 /* Assume the radio is enabled. If it's not enabled, the state will
3030 * immediately get fixed on the first periodic work run. */
3031 dev->radio_hw_enable = 1;
75388acd
LF		 3032
3033 phy->savedpctlreg = 0xFFFF;
3034 phy->aci_enable = 0;
3035 phy->aci_wlan_automatic = 0;
3036 phy->aci_hw_rssi = 0;
3037
3038 lo = phy->_lo_pairs;
3039 if (lo)
3040 memset(lo, 0, sizeof(struct b43legacy_lopair) *
3041 B43legacy_LO_COUNT);
3042 phy->max_lb_gain = 0;
3043 phy->trsw_rx_gain = 0;
3044
3045 /* Set default attenuation values. */
3046 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3047 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3048 phy->txctl1 = b43legacy_default_txctl1(dev);
3049 phy->txpwr_offset = 0;
3050
3051 /* NRSSI */
3052 phy->nrssislope = 0;
3053 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3054 phy->nrssi[i] = -1000;
3055 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3056 phy->nrssi_lt[i] = i;
3057
3058 phy->lofcal = 0xFFFF;
3059 phy->initval = 0xFFFF;
3060
75388acd
LF		 3061 phy->interfmode = B43legacy_INTERFMODE_NONE;
3062 phy->channel = 0xFF;
3063}
3064
3065static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
3066{
3067 /* Flags */
eed0fd21 3068 dev->dfq_valid = 0;
75388acd
LF		 3069
3070 /* Stats */
3071 memset(&dev->stats, 0, sizeof(dev->stats));
3072
3073 setup_struct_phy_for_init(dev, &dev->phy);
3074
3075 /* IRQ related flags */
3076 dev->irq_reason = 0;
3077 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3078 dev->irq_savedstate = B43legacy_IRQ_MASKTEMPLATE;
3079
3080 dev->mac_suspended = 1;
3081
3082 /* Noise calculation context */
3083 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3084}
3085
3086static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
3087{
3088#ifdef CONFIG_SSB_DRIVER_PCICORE
3089 struct ssb_bus *bus = dev->dev->bus;
3090 u32 tmp;
3091
3092 if (bus->pcicore.dev &&
3093 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3094 bus->pcicore.dev->id.revision <= 5) {
3095 /* IMCFGLO timeouts workaround. */
3096 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3097 tmp &= ~SSB_IMCFGLO_REQTO;
3098 tmp &= ~SSB_IMCFGLO_SERTO;
3099 switch (bus->bustype) {
3100 case SSB_BUSTYPE_PCI:
3101 case SSB_BUSTYPE_PCMCIA:
3102 tmp |= 0x32;
3103 break;
3104 case SSB_BUSTYPE_SSB:
3105 tmp |= 0x53;
3106 break;
3107 }
3108 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3109 }
3110#endif /* CONFIG_SSB_DRIVER_PCICORE */
3111}
3112
3e2c40ef
SB		 3113static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,
3114 bool idle) {
3115 u16 pu_delay = 1050;
3116
05c914fe 3117 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3e2c40ef
SB		 3118 pu_delay = 500;
3119 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3120 pu_delay = max(pu_delay, (u16)2400);
3121
3122 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3123 B43legacy_SHM_SH_SPUWKUP, pu_delay);
3124}
3125
3126/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3127static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev)
3128{
3129 u16 pretbtt;
3130
3131 /* The time value is in microseconds. */
05c914fe 3132 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3e2c40ef
SB		 3133 pretbtt = 2;
3134 else
3135 pretbtt = 250;
3136 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3137 B43legacy_SHM_SH_PRETBTT, pretbtt);
3138 b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt);
3139}
3140
75388acd
LF		 3141/* Shutdown a wireless core */
3142/* Locking: wl->mutex */
3143static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
3144{
75388acd 3145 struct b43legacy_phy *phy = &dev->phy;
e78c9d28 3146 u32 macctl;
75388acd
LF		 3147
3148 B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
3149 if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
3150 return;
3151 b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3152
e78c9d28
SB		 3153 /* Stop the microcode PSM. */
3154 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3155 macctl &= ~B43legacy_MACCTL_PSM_RUN;
3156 macctl |= B43legacy_MACCTL_PSM_JMP0;
3157 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3158
4ad36d78 3159 b43legacy_leds_exit(dev);
75388acd
LF		 3160 b43legacy_rng_exit(dev->wl);
3161 b43legacy_pio_free(dev);
3162 b43legacy_dma_free(dev);
3163 b43legacy_chip_exit(dev);
93bb7f3a 3164 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 3165 b43legacy_switch_analog(dev, 0);
3166 if (phy->dyn_tssi_tbl)
3167 kfree(phy->tssi2dbm);
3168 kfree(phy->lo_control);
3169 phy->lo_control = NULL;
a297170d
SB		 3170 if (dev->wl->current_beacon) {
3171 dev_kfree_skb_any(dev->wl->current_beacon);
3172 dev->wl->current_beacon = NULL;
3173 }
3174
75388acd
LF		 3175 ssb_device_disable(dev->dev, 0);
3176 ssb_bus_may_powerdown(dev->dev->bus);
3177}
3178
3179static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3180{
3181 struct b43legacy_phy *phy = &dev->phy;
3182 int i;
3183
3184 /* Set default attenuation values. */
3185 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3186 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3187 phy->txctl1 = b43legacy_default_txctl1(dev);
3188 phy->txctl2 = 0xFFFF;
3189 phy->txpwr_offset = 0;
3190
3191 /* NRSSI */
3192 phy->nrssislope = 0;
3193 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3194 phy->nrssi[i] = -1000;
3195 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3196 phy->nrssi_lt[i] = i;
3197
3198 phy->lofcal = 0xFFFF;
3199 phy->initval = 0xFFFF;
3200
3201 phy->aci_enable = 0;
3202 phy->aci_wlan_automatic = 0;
3203 phy->aci_hw_rssi = 0;
3204
3205 phy->antenna_diversity = 0xFFFF;
3206 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3207 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3208
3209 /* Flags */
3210 phy->calibrated = 0;
75388acd
LF		 3211
3212 if (phy->_lo_pairs)
3213 memset(phy->_lo_pairs, 0,
3214 sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3215 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3216}
3217
3218/* Initialize a wireless core */
3219static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3220{
3221 struct b43legacy_wl *wl = dev->wl;
3222 struct ssb_bus *bus = dev->dev->bus;
3223 struct b43legacy_phy *phy = &dev->phy;
3224 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3225 int err;
3226 u32 hf;
3227 u32 tmp;
3228
3229 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3230
3231 err = ssb_bus_powerup(bus, 0);
3232 if (err)
3233 goto out;
3234 if (!ssb_device_is_enabled(dev->dev)) {
3235 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3236 b43legacy_wireless_core_reset(dev, tmp);
3237 }
3238
3239 if ((phy->type == B43legacy_PHYTYPE_B) ||
3240 (phy->type == B43legacy_PHYTYPE_G)) {
3241 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3242 * B43legacy_LO_COUNT,
3243 GFP_KERNEL);
3244 if (!phy->_lo_pairs)
3245 return -ENOMEM;
3246 }
3247 setup_struct_wldev_for_init(dev);
3248
3249 err = b43legacy_phy_init_tssi2dbm_table(dev);
3250 if (err)
3251 goto err_kfree_lo_control;
3252
3253 /* Enable IRQ routing to this device. */
3254 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3255
3256 b43legacy_imcfglo_timeouts_workaround(dev);
3257 prepare_phy_data_for_init(dev);
3258 b43legacy_phy_calibrate(dev);
3259 err = b43legacy_chip_init(dev);
3260 if (err)
3261 goto err_kfree_tssitbl;
3262 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3263 B43legacy_SHM_SH_WLCOREREV,
3264 dev->dev->id.revision);
3265 hf = b43legacy_hf_read(dev);
3266 if (phy->type == B43legacy_PHYTYPE_G) {
3267 hf |= B43legacy_HF_SYMW;
3268 if (phy->rev == 1)
3269 hf |= B43legacy_HF_GDCW;
7797aa38 3270 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
75388acd
LF		 3271 hf |= B43legacy_HF_OFDMPABOOST;
3272 } else if (phy->type == B43legacy_PHYTYPE_B) {
3273 hf |= B43legacy_HF_SYMW;
3274 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3275 hf &= ~B43legacy_HF_GDCW;
3276 }
3277 b43legacy_hf_write(dev, hf);
3278
0a6e1bee
SB		 3279 b43legacy_set_retry_limits(dev,
3280 B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3281 B43legacy_DEFAULT_LONG_RETRY_LIMIT);
75388acd
LF		 3282
3283 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3284 0x0044, 3);
3285 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3286 0x0046, 2);
3287
3288 /* Disable sending probe responses from firmware.
3289 * Setting the MaxTime to one usec will always trigger
3290 * a timeout, so we never send any probe resp.
3291 * A timeout of zero is infinite. */
3292 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3293 B43legacy_SHM_SH_PRMAXTIME, 1);
3294
3295 b43legacy_rate_memory_init(dev);
3296
3297 /* Minimum Contention Window */
3298 if (phy->type == B43legacy_PHYTYPE_B)
3299 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3300 0x0003, 31);
3301 else
3302 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3303 0x0003, 15);
3304 /* Maximum Contention Window */
3305 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3306 0x0004, 1023);
3307
3308 do {
3309 if (b43legacy_using_pio(dev))
3310 err = b43legacy_pio_init(dev);
3311 else {
3312 err = b43legacy_dma_init(dev);
3313 if (!err)
3314 b43legacy_qos_init(dev);
3315 }
3316 } while (err == -EAGAIN);
3317 if (err)
3318 goto err_chip_exit;
3319
3e2c40ef 3320 b43legacy_set_synth_pu_delay(dev, 1);
75388acd
LF		 3321
3322 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4150c572 3323 b43legacy_upload_card_macaddress(dev);
75388acd
LF		 3324 b43legacy_security_init(dev);
3325 b43legacy_rng_init(wl);
3326
3327 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3328
4ad36d78 3329 b43legacy_leds_init(dev);
75388acd
LF		 3330out:
3331 return err;
3332
3333err_chip_exit:
3334 b43legacy_chip_exit(dev);
3335err_kfree_tssitbl:
3336 if (phy->dyn_tssi_tbl)
3337 kfree(phy->tssi2dbm);
3338err_kfree_lo_control:
3339 kfree(phy->lo_control);
3340 phy->lo_control = NULL;
3341 ssb_bus_may_powerdown(bus);
3342 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3343 return err;
3344}
3345
33a3dc93
SB		 3346static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
3347 struct ieee80211_if_init_conf *conf)
75388acd
LF		 3348{
3349 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3350 struct b43legacy_wldev *dev;
3351 unsigned long flags;
3352 int err = -EOPNOTSUPP;
4150c572
JB		 3353
3354 /* TODO: allow WDS/AP devices to coexist */
3355
05c914fe
JB		 3356 if (conf->type != NL80211_IFTYPE_AP &&
3357 conf->type != NL80211_IFTYPE_STATION &&
3358 conf->type != NL80211_IFTYPE_WDS &&
3359 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 3360 return -EOPNOTSUPP;
75388acd
LF		 3361
3362 mutex_lock(&wl->mutex);
4150c572 3363 if (wl->operating)
75388acd
LF		 3364 goto out_mutex_unlock;
3365
3366 b43legacydbg(wl, "Adding Interface type %d\n", conf->type);
3367
3368 dev = wl->current_dev;
4150c572 3369 wl->operating = 1;
32bfd35d 3370 wl->vif = conf->vif;
4150c572
JB		 3371 wl->if_type = conf->type;
3372 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3373
3374 spin_lock_irqsave(&wl->irq_lock, flags);
3375 b43legacy_adjust_opmode(dev);
3e2c40ef
SB		 3376 b43legacy_set_pretbtt(dev);
3377 b43legacy_set_synth_pu_delay(dev, 0);
4150c572
JB		 3378 b43legacy_upload_card_macaddress(dev);
3379 spin_unlock_irqrestore(&wl->irq_lock, flags);
3380
3381 err = 0;
3382 out_mutex_unlock:
3383 mutex_unlock(&wl->mutex);
3384
3385 return err;
3386}
3387
33a3dc93
SB		 3388static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
3389 struct ieee80211_if_init_conf *conf)
4150c572
JB		 3390{
3391 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3392 struct b43legacy_wldev *dev = wl->current_dev;
3393 unsigned long flags;
3394
3395 b43legacydbg(wl, "Removing Interface type %d\n", conf->type);
3396
3397 mutex_lock(&wl->mutex);
3398
3399 B43legacy_WARN_ON(!wl->operating);
32bfd35d
JB		 3400 B43legacy_WARN_ON(wl->vif != conf->vif);
3401 wl->vif = NULL;
4150c572
JB		 3402
3403 wl->operating = 0;
3404
3405 spin_lock_irqsave(&wl->irq_lock, flags);
3406 b43legacy_adjust_opmode(dev);
3407 memset(wl->mac_addr, 0, ETH_ALEN);
3408 b43legacy_upload_card_macaddress(dev);
3409 spin_unlock_irqrestore(&wl->irq_lock, flags);
3410
3411 mutex_unlock(&wl->mutex);
3412}
3413
33a3dc93 3414static int b43legacy_op_start(struct ieee80211_hw *hw)
4150c572
JB		 3415{
3416 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3417 struct b43legacy_wldev *dev = wl->current_dev;
3418 int did_init = 0;
208eec88 3419 int err = 0;
8712f276 3420 bool do_rfkill_exit = 0;
4150c572 3421
4ad36d78
LF		 3422 /* First register RFkill.
3423 * LEDs that are registered later depend on it. */
3424 b43legacy_rfkill_init(dev);
3425
ada50731
SB		 3426 /* Kill all old instance specific information to make sure
3427 * the card won't use it in the short timeframe between start
3428 * and mac80211 reconfiguring it. */
3429 memset(wl->bssid, 0, ETH_ALEN);
3430 memset(wl->mac_addr, 0, ETH_ALEN);
3431 wl->filter_flags = 0;
3432
4150c572
JB		 3433 mutex_lock(&wl->mutex);
3434
75388acd
LF		 3435 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
3436 err = b43legacy_wireless_core_init(dev);
8712f276
MB		 3437 if (err) {
3438 do_rfkill_exit = 1;
75388acd 3439 goto out_mutex_unlock;
8712f276 3440 }
75388acd
LF		 3441 did_init = 1;
3442 }
4150c572 3443
75388acd
LF		 3444 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
3445 err = b43legacy_wireless_core_start(dev);
3446 if (err) {
3447 if (did_init)
3448 b43legacy_wireless_core_exit(dev);
8712f276 3449 do_rfkill_exit = 1;
75388acd
LF		 3450 goto out_mutex_unlock;
3451 }
3452 }
3453
75388acd
LF		 3454out_mutex_unlock:
3455 mutex_unlock(&wl->mutex);
3456
8712f276
MB		 3457 if (do_rfkill_exit)
3458 b43legacy_rfkill_exit(dev);
3459
75388acd
LF		 3460 return err;
3461}
3462
33a3dc93 3463static void b43legacy_op_stop(struct ieee80211_hw *hw)
75388acd
LF		 3464{
3465 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
4150c572 3466 struct b43legacy_wldev *dev = wl->current_dev;
75388acd 3467
4ad36d78 3468 b43legacy_rfkill_exit(dev);
7858e07b 3469 cancel_work_sync(&(wl->beacon_update_trigger));
4ad36d78 3470
75388acd 3471 mutex_lock(&wl->mutex);
4150c572
JB		 3472 if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
3473 b43legacy_wireless_core_stop(dev);
3474 b43legacy_wireless_core_exit(dev);
75388acd
LF		 3475 mutex_unlock(&wl->mutex);
3476}
3477
a297170d 3478static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw,
17741cdc 3479 struct ieee80211_sta *sta, bool set)
a297170d
SB		 3480{
3481 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3482 unsigned long flags;
3483
3484 spin_lock_irqsave(&wl->irq_lock, flags);
9d139c81 3485 b43legacy_update_templates(wl);
a297170d
SB		 3486 spin_unlock_irqrestore(&wl->irq_lock, flags);
3487
3488 return 0;
3489}
3490
75388acd 3491static const struct ieee80211_ops b43legacy_hw_ops = {
33a3dc93
SB		 3492 .tx = b43legacy_op_tx,
3493 .conf_tx = b43legacy_op_conf_tx,
3494 .add_interface = b43legacy_op_add_interface,
3495 .remove_interface = b43legacy_op_remove_interface,
3496 .config = b43legacy_op_dev_config,
7f3704e9 3497 .bss_info_changed = b43legacy_op_bss_info_changed,
33a3dc93
SB		 3498 .config_interface = b43legacy_op_config_interface,
3499 .configure_filter = b43legacy_op_configure_filter,
3500 .get_stats = b43legacy_op_get_stats,
3501 .get_tx_stats = b43legacy_op_get_tx_stats,
3502 .start = b43legacy_op_start,
3503 .stop = b43legacy_op_stop,
a297170d 3504 .set_tim = b43legacy_op_beacon_set_tim,
75388acd
LF		 3505};
3506
3507/* Hard-reset the chip. Do not call this directly.
3508 * Use b43legacy_controller_restart()
3509 */
3510static void b43legacy_chip_reset(struct work_struct *work)
3511{
3512 struct b43legacy_wldev *dev =
3513 container_of(work, struct b43legacy_wldev, restart_work);
3514 struct b43legacy_wl *wl = dev->wl;
3515 int err = 0;
3516 int prev_status;
3517
3518 mutex_lock(&wl->mutex);
3519
3520 prev_status = b43legacy_status(dev);
3521 /* Bring the device down... */
3522 if (prev_status >= B43legacy_STAT_STARTED)
3523 b43legacy_wireless_core_stop(dev);
3524 if (prev_status >= B43legacy_STAT_INITIALIZED)
3525 b43legacy_wireless_core_exit(dev);
3526
3527 /* ...and up again. */
3528 if (prev_status >= B43legacy_STAT_INITIALIZED) {
3529 err = b43legacy_wireless_core_init(dev);
3530 if (err)
3531 goto out;
3532 }
3533 if (prev_status >= B43legacy_STAT_STARTED) {
3534 err = b43legacy_wireless_core_start(dev);
3535 if (err) {
3536 b43legacy_wireless_core_exit(dev);
3537 goto out;
3538 }
3539 }
3540out:
48e6c51b
MB		 3541 if (err)
3542 wl->current_dev = NULL; /* Failed to init the dev. */
75388acd
LF		 3543 mutex_unlock(&wl->mutex);
3544 if (err)
3545 b43legacyerr(wl, "Controller restart FAILED\n");
3546 else
3547 b43legacyinfo(wl, "Controller restarted\n");
3548}
3549
3550static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
3551 int have_bphy,
3552 int have_gphy)
3553{
3554 struct ieee80211_hw *hw = dev->wl->hw;
75388acd 3555 struct b43legacy_phy *phy = &dev->phy;
75388acd
LF		 3556
3557 phy->possible_phymodes = 0;
8318d78a
JB		 3558 if (have_bphy) {
3559 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3560 &b43legacy_band_2GHz_BPHY;
3561 phy->possible_phymodes |= B43legacy_PHYMODE_B;
3562 }
3563
3564 if (have_gphy) {
3565 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3566 &b43legacy_band_2GHz_GPHY;
3567 phy->possible_phymodes |= B43legacy_PHYMODE_G;
75388acd
LF		 3568 }
3569
3570 return 0;
3571}
3572
3573static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
3574{
3575 /* We release firmware that late to not be required to re-request
3576 * is all the time when we reinit the core. */
3577 b43legacy_release_firmware(dev);
3578}
3579
3580static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
3581{
3582 struct b43legacy_wl *wl = dev->wl;
3583 struct ssb_bus *bus = dev->dev->bus;
3584 struct pci_dev *pdev = bus->host_pci;
3585 int err;
3586 int have_bphy = 0;
3587 int have_gphy = 0;
3588 u32 tmp;
3589
3590 /* Do NOT do any device initialization here.
3591 * Do it in wireless_core_init() instead.
3592 * This function is for gathering basic information about the HW, only.
3593 * Also some structs may be set up here. But most likely you want to
3594 * have that in core_init(), too.
3595 */
3596
3597 err = ssb_bus_powerup(bus, 0);
3598 if (err) {
3599 b43legacyerr(wl, "Bus powerup failed\n");
3600 goto out;
3601 }
3602 /* Get the PHY type. */
3603 if (dev->dev->id.revision >= 5) {
3604 u32 tmshigh;
3605
3606 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3607 have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
3608 if (!have_gphy)
3609 have_bphy = 1;
3610 } else if (dev->dev->id.revision == 4)
3611 have_gphy = 1;
3612 else
3613 have_bphy = 1;
3614
75388acd
LF		 3615 dev->phy.gmode = (have_gphy || have_bphy);
3616 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3617 b43legacy_wireless_core_reset(dev, tmp);
3618
3619 err = b43legacy_phy_versioning(dev);
3620 if (err)
ba48f7bb 3621 goto err_powerdown;
75388acd
LF		 3622 /* Check if this device supports multiband. */
3623 if (!pdev ||
3624 (pdev->device != 0x4312 &&
3625 pdev->device != 0x4319 &&
3626 pdev->device != 0x4324)) {
3627 /* No multiband support. */
3628 have_bphy = 0;
3629 have_gphy = 0;
3630 switch (dev->phy.type) {
3631 case B43legacy_PHYTYPE_B:
3632 have_bphy = 1;
3633 break;
3634 case B43legacy_PHYTYPE_G:
3635 have_gphy = 1;
3636 break;
3637 default:
3638 B43legacy_BUG_ON(1);
3639 }
3640 }
3641 dev->phy.gmode = (have_gphy || have_bphy);
3642 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3643 b43legacy_wireless_core_reset(dev, tmp);
3644
3645 err = b43legacy_validate_chipaccess(dev);
3646 if (err)
ba48f7bb 3647 goto err_powerdown;
75388acd
LF		 3648 err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
3649 if (err)
ba48f7bb 3650 goto err_powerdown;
75388acd
LF		 3651
3652 /* Now set some default "current_dev" */
3653 if (!wl->current_dev)
3654 wl->current_dev = dev;
3655 INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
3656
93bb7f3a 3657 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 3658 b43legacy_switch_analog(dev, 0);
3659 ssb_device_disable(dev->dev, 0);
3660 ssb_bus_may_powerdown(bus);
3661
3662out:
3663 return err;
3664
75388acd
LF		 3665err_powerdown:
3666 ssb_bus_may_powerdown(bus);
3667 return err;
3668}
3669
3670static void b43legacy_one_core_detach(struct ssb_device *dev)
3671{
3672 struct b43legacy_wldev *wldev;
3673 struct b43legacy_wl *wl;
3674
48e6c51b
MB		 3675 /* Do not cancel ieee80211-workqueue based work here.
3676 * See comment in b43legacy_remove(). */
3677
75388acd
LF		 3678 wldev = ssb_get_drvdata(dev);
3679 wl = wldev->wl;
75388acd
LF		 3680 b43legacy_debugfs_remove_device(wldev);
3681 b43legacy_wireless_core_detach(wldev);
3682 list_del(&wldev->list);
3683 wl->nr_devs--;
3684 ssb_set_drvdata(dev, NULL);
3685 kfree(wldev);
3686}
3687
3688static int b43legacy_one_core_attach(struct ssb_device *dev,
3689 struct b43legacy_wl *wl)
3690{
3691 struct b43legacy_wldev *wldev;
3692 struct pci_dev *pdev;
3693 int err = -ENOMEM;
3694
3695 if (!list_empty(&wl->devlist)) {
3696 /* We are not the first core on this chip. */
3697 pdev = dev->bus->host_pci;
3698 /* Only special chips support more than one wireless
3699 * core, although some of the other chips have more than
3700 * one wireless core as well. Check for this and
3701 * bail out early.
3702 */
3703 if (!pdev ||
3704 ((pdev->device != 0x4321) &&
3705 (pdev->device != 0x4313) &&
3706 (pdev->device != 0x431A))) {
3707 b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
3708 return -ENODEV;
3709 }
3710 }
3711
3712 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3713 if (!wldev)
3714 goto out;
3715
3716 wldev->dev = dev;
3717 wldev->wl = wl;
3718 b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
3719 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3720 tasklet_init(&wldev->isr_tasklet,
3721 (void (*)(unsigned long))b43legacy_interrupt_tasklet,
3722 (unsigned long)wldev);
3723 if (modparam_pio)
3724 wldev->__using_pio = 1;
3725 INIT_LIST_HEAD(&wldev->list);
3726
3727 err = b43legacy_wireless_core_attach(wldev);
3728 if (err)
3729 goto err_kfree_wldev;
3730
3731 list_add(&wldev->list, &wl->devlist);
3732 wl->nr_devs++;
3733 ssb_set_drvdata(dev, wldev);
3734 b43legacy_debugfs_add_device(wldev);
3735out:
3736 return err;
3737
3738err_kfree_wldev:
3739 kfree(wldev);
3740 return err;
3741}
3742
3743static void b43legacy_sprom_fixup(struct ssb_bus *bus)
3744{
3745 /* boardflags workarounds */
3746 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3747 bus->boardinfo.type == 0x4E &&
3748 bus->boardinfo.rev > 0x40)
7797aa38 3749 bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
75388acd
LF		 3750}
3751
3752static void b43legacy_wireless_exit(struct ssb_device *dev,
3753 struct b43legacy_wl *wl)
3754{
3755 struct ieee80211_hw *hw = wl->hw;
3756
3757 ssb_set_devtypedata(dev, NULL);
3758 ieee80211_free_hw(hw);
3759}
3760
3761static int b43legacy_wireless_init(struct ssb_device *dev)
3762{
3763 struct ssb_sprom *sprom = &dev->bus->sprom;
3764 struct ieee80211_hw *hw;
3765 struct b43legacy_wl *wl;
3766 int err = -ENOMEM;
3767
3768 b43legacy_sprom_fixup(dev->bus);
3769
3770 hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
3771 if (!hw) {
3772 b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
3773 goto out;
3774 }
3775
3776 /* fill hw info */
605a0bd6 3777 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 3778 IEEE80211_HW_SIGNAL_DBM |
3779 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 3780 hw->wiphy->interface_modes =
3781 BIT(NL80211_IFTYPE_AP) |
3782 BIT(NL80211_IFTYPE_STATION) |
3783 BIT(NL80211_IFTYPE_WDS) |
3784 BIT(NL80211_IFTYPE_ADHOC);
75388acd 3785 hw->queues = 1; /* FIXME: hardware has more queues */
e6a9854b 3786 hw->max_rates = 2;
75388acd 3787 SET_IEEE80211_DEV(hw, dev->dev);
7797aa38
LF		 3788 if (is_valid_ether_addr(sprom->et1mac))
3789 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
75388acd 3790 else
7797aa38 3791 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
75388acd
LF		 3792
3793 /* Get and initialize struct b43legacy_wl */
3794 wl = hw_to_b43legacy_wl(hw);
3795 memset(wl, 0, sizeof(*wl));
3796 wl->hw = hw;
3797 spin_lock_init(&wl->irq_lock);
3798 spin_lock_init(&wl->leds_lock);
3799 mutex_init(&wl->mutex);
3800 INIT_LIST_HEAD(&wl->devlist);
7858e07b 3801 INIT_WORK(&wl->beacon_update_trigger, b43legacy_beacon_update_trigger_work);
75388acd
LF		 3802
3803 ssb_set_devtypedata(dev, wl);
3804 b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3805 err = 0;
3806out:
3807 return err;
3808}
3809
3810static int b43legacy_probe(struct ssb_device *dev,
3811 const struct ssb_device_id *id)
3812{
3813 struct b43legacy_wl *wl;
3814 int err;
3815 int first = 0;
3816
3817 wl = ssb_get_devtypedata(dev);
3818 if (!wl) {
3819 /* Probing the first core - setup common struct b43legacy_wl */
3820 first = 1;
3821 err = b43legacy_wireless_init(dev);
3822 if (err)
3823 goto out;
3824 wl = ssb_get_devtypedata(dev);
3825 B43legacy_WARN_ON(!wl);
3826 }
3827 err = b43legacy_one_core_attach(dev, wl);
3828 if (err)
3829 goto err_wireless_exit;
3830
3831 if (first) {
3832 err = ieee80211_register_hw(wl->hw);
3833 if (err)
3834 goto err_one_core_detach;
3835 }
3836
3837out:
3838 return err;
3839
3840err_one_core_detach:
3841 b43legacy_one_core_detach(dev);
3842err_wireless_exit:
3843 if (first)
3844 b43legacy_wireless_exit(dev, wl);
3845 return err;
3846}
3847
3848static void b43legacy_remove(struct ssb_device *dev)
3849{
3850 struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
3851 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3852
48e6c51b
MB		 3853 /* We must cancel any work here before unregistering from ieee80211,
3854 * as the ieee80211 unreg will destroy the workqueue. */
3855 cancel_work_sync(&wldev->restart_work);
3856
75388acd
LF		 3857 B43legacy_WARN_ON(!wl);
3858 if (wl->current_dev == wldev)
3859 ieee80211_unregister_hw(wl->hw);
3860
3861 b43legacy_one_core_detach(dev);
3862
3863 if (list_empty(&wl->devlist))
3864 /* Last core on the chip unregistered.
3865 * We can destroy common struct b43legacy_wl.
3866 */
3867 b43legacy_wireless_exit(dev, wl);
3868}
3869
3870/* Perform a hardware reset. This can be called from any context. */
3871void b43legacy_controller_restart(struct b43legacy_wldev *dev,
3872 const char *reason)
3873{
3874 /* Must avoid requeueing, if we are in shutdown. */
3875 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
3876 return;
3877 b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
3878 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3879}
3880
3881#ifdef CONFIG_PM
3882
3883static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
3884{
3885 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3886 struct b43legacy_wl *wl = wldev->wl;
3887
3888 b43legacydbg(wl, "Suspending...\n");
3889
3890 mutex_lock(&wl->mutex);
3891 wldev->suspend_init_status = b43legacy_status(wldev);
3892 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
3893 b43legacy_wireless_core_stop(wldev);
3894 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
3895 b43legacy_wireless_core_exit(wldev);
3896 mutex_unlock(&wl->mutex);
3897
3898 b43legacydbg(wl, "Device suspended.\n");
3899
3900 return 0;
3901}
3902
3903static int b43legacy_resume(struct ssb_device *dev)
3904{
3905 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3906 struct b43legacy_wl *wl = wldev->wl;
3907 int err = 0;
3908
3909 b43legacydbg(wl, "Resuming...\n");
3910
3911 mutex_lock(&wl->mutex);
3912 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
3913 err = b43legacy_wireless_core_init(wldev);
3914 if (err) {
3915 b43legacyerr(wl, "Resume failed at core init\n");
3916 goto out;
3917 }
3918 }
3919 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
3920 err = b43legacy_wireless_core_start(wldev);
3921 if (err) {
3922 b43legacy_wireless_core_exit(wldev);
3923 b43legacyerr(wl, "Resume failed at core start\n");
3924 goto out;
3925 }
3926 }
75388acd
LF		 3927
3928 b43legacydbg(wl, "Device resumed.\n");
3929out:
4104863f 3930 mutex_unlock(&wl->mutex);
75388acd
LF		 3931 return err;
3932}
3933
3934#else /* CONFIG_PM */
3935# define b43legacy_suspend NULL
3936# define b43legacy_resume NULL
3937#endif /* CONFIG_PM */
3938
3939static struct ssb_driver b43legacy_ssb_driver = {
3940 .name = KBUILD_MODNAME,
3941 .id_table = b43legacy_ssb_tbl,
3942 .probe = b43legacy_probe,
3943 .remove = b43legacy_remove,
3944 .suspend = b43legacy_suspend,
3945 .resume = b43legacy_resume,
3946};
3947
6fff1c64
SB		 3948static void b43legacy_print_driverinfo(void)
3949{
3950 const char *feat_pci = "", *feat_leds = "", *feat_rfkill = "",
3951 *feat_pio = "", *feat_dma = "";
3952
3953#ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
3954 feat_pci = "P";
3955#endif
3956#ifdef CONFIG_B43LEGACY_LEDS
3957 feat_leds = "L";
3958#endif
3959#ifdef CONFIG_B43LEGACY_RFKILL
3960 feat_rfkill = "R";
3961#endif
3962#ifdef CONFIG_B43LEGACY_PIO
3963 feat_pio = "I";
3964#endif
3965#ifdef CONFIG_B43LEGACY_DMA
3966 feat_dma = "D";
3967#endif
c256e05b 3968 printk(KERN_INFO "Broadcom 43xx-legacy driver loaded "
6fff1c64
SB		 3969 "[ Features: %s%s%s%s%s, Firmware-ID: "
3970 B43legacy_SUPPORTED_FIRMWARE_ID " ]\n",
3971 feat_pci, feat_leds, feat_rfkill, feat_pio, feat_dma);
3972}
3973
75388acd
LF		 3974static int __init b43legacy_init(void)
3975{
3976 int err;
3977
3978 b43legacy_debugfs_init();
3979
3980 err = ssb_driver_register(&b43legacy_ssb_driver);
3981 if (err)
3982 goto err_dfs_exit;
3983
6fff1c64
SB		 3984 b43legacy_print_driverinfo();
3985
75388acd
LF		 3986 return err;
3987
3988err_dfs_exit:
3989 b43legacy_debugfs_exit();
3990 return err;
3991}
3992
3993static void __exit b43legacy_exit(void)
3994{
3995 ssb_driver_unregister(&b43legacy_ssb_driver);
3996 b43legacy_debugfs_exit();
3997}
3998
3999module_init(b43legacy_init)
4000module_exit(b43legacy_exit)
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