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b43/b43legacy: Wake queues in wireless_core_start
[net-next-2.6.git] / drivers / net / wireless / b43legacy / main.c
CommitLineData
75388acd
LF		 1/*
2 *
3 * Broadcom B43legacy wireless driver
4 *
5 * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6fff1c64 6 * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
75388acd
LF		 7 * Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11 *
12 * Some parts of the code in this file are derived from the ipw2200
13 * driver Copyright(c) 2003 - 2004 Intel Corporation.
14
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING. If not, write to
27 * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28 * Boston, MA 02110-1301, USA.
29 *
30 */
31
32#include <linux/delay.h>
33#include <linux/init.h>
34#include <linux/moduleparam.h>
35#include <linux/if_arp.h>
36#include <linux/etherdevice.h>
75388acd
LF		 37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
d43c36dc 40#include <linux/sched.h>
75388acd
LF		 41#include <linux/skbuff.h>
42#include <linux/dma-mapping.h>
43#include <net/dst.h>
44#include <asm/unaligned.h>
45
46#include "b43legacy.h"
47#include "main.h"
48#include "debugfs.h"
49#include "phy.h"
50#include "dma.h"
51#include "pio.h"
52#include "sysfs.h"
53#include "xmit.h"
54#include "radio.h"
55
56
57MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
61MODULE_LICENSE("GPL");
62
1a1c360d 63MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
c2f4f527
TG		 64MODULE_FIRMWARE("b43legacy/ucode2.fw");
65MODULE_FIRMWARE("b43legacy/ucode4.fw");
1a1c360d 66
75388acd
LF		 67#if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
68static int modparam_pio;
69module_param_named(pio, modparam_pio, int, 0444);
70MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
71#elif defined(CONFIG_B43LEGACY_DMA)
72# define modparam_pio 0
73#elif defined(CONFIG_B43LEGACY_PIO)
74# define modparam_pio 1
75#endif
76
77static int modparam_bad_frames_preempt;
78module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
79MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
80 " Preemption");
81
75388acd
LF		 82static char modparam_fwpostfix[16];
83module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
84MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
85
75388acd
LF		 86/* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
87static const struct ssb_device_id b43legacy_ssb_tbl[] = {
88 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
89 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
90 SSB_DEVTABLE_END
91};
92MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
93
94
95/* Channel and ratetables are shared for all devices.
96 * They can't be const, because ieee80211 puts some precalculated
97 * data in there. This data is the same for all devices, so we don't
98 * get concurrency issues */
99#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 100 { \
101 .bitrate = B43legacy_RATE_TO_100KBPS(_rateid), \
102 .hw_value = (_rateid), \
103 .flags = (_flags), \
75388acd 104 }
8318d78a
JB		 105/*
106 * NOTE: When changing this, sync with xmit.c's
107 * b43legacy_plcp_get_bitrate_idx_* functions!
108 */
75388acd 109static struct ieee80211_rate __b43legacy_ratetable[] = {
8318d78a
JB		 110 RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
111 RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
112 RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
113 RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
114 RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
115 RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
116 RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
117 RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
118 RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
119 RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
120 RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
121 RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
75388acd 122};
75388acd
LF		 123#define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
124#define b43legacy_b_ratetable_size 4
125#define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
126#define b43legacy_g_ratetable_size 12
127
128#define CHANTAB_ENT(_chanid, _freq) \
129 { \
8318d78a
JB		 130 .center_freq = (_freq), \
131 .hw_value = (_chanid), \
75388acd
LF		 132 }
133static struct ieee80211_channel b43legacy_bg_chantable[] = {
134 CHANTAB_ENT(1, 2412),
135 CHANTAB_ENT(2, 2417),
136 CHANTAB_ENT(3, 2422),
137 CHANTAB_ENT(4, 2427),
138 CHANTAB_ENT(5, 2432),
139 CHANTAB_ENT(6, 2437),
140 CHANTAB_ENT(7, 2442),
141 CHANTAB_ENT(8, 2447),
142 CHANTAB_ENT(9, 2452),
143 CHANTAB_ENT(10, 2457),
144 CHANTAB_ENT(11, 2462),
145 CHANTAB_ENT(12, 2467),
146 CHANTAB_ENT(13, 2472),
147 CHANTAB_ENT(14, 2484),
148};
8318d78a
JB		 149
150static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
151 .channels = b43legacy_bg_chantable,
152 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
153 .bitrates = b43legacy_b_ratetable,
154 .n_bitrates = b43legacy_b_ratetable_size,
155};
156
157static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
158 .channels = b43legacy_bg_chantable,
159 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
160 .bitrates = b43legacy_g_ratetable,
161 .n_bitrates = b43legacy_g_ratetable_size,
162};
75388acd
LF		 163
164static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
165static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
166static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
167static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
168
169
170static int b43legacy_ratelimit(struct b43legacy_wl *wl)
171{
172 if (!wl || !wl->current_dev)
173 return 1;
174 if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
175 return 1;
176 /* We are up and running.
177 * Ratelimit the messages to avoid DoS over the net. */
178 return net_ratelimit();
179}
180
181void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
182{
183 va_list args;
184
185 if (!b43legacy_ratelimit(wl))
186 return;
187 va_start(args, fmt);
188 printk(KERN_INFO "b43legacy-%s: ",
189 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
190 vprintk(fmt, args);
191 va_end(args);
192}
193
194void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
195{
196 va_list args;
197
198 if (!b43legacy_ratelimit(wl))
199 return;
200 va_start(args, fmt);
201 printk(KERN_ERR "b43legacy-%s ERROR: ",
202 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
203 vprintk(fmt, args);
204 va_end(args);
205}
206
207void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
208{
209 va_list args;
210
211 if (!b43legacy_ratelimit(wl))
212 return;
213 va_start(args, fmt);
214 printk(KERN_WARNING "b43legacy-%s warning: ",
215 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
216 vprintk(fmt, args);
217 va_end(args);
218}
219
220#if B43legacy_DEBUG
221void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
222{
223 va_list args;
224
225 va_start(args, fmt);
226 printk(KERN_DEBUG "b43legacy-%s debug: ",
227 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
228 vprintk(fmt, args);
229 va_end(args);
230}
231#endif /* DEBUG */
232
233static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
234 u32 val)
235{
236 u32 status;
237
238 B43legacy_WARN_ON(offset % 4 != 0);
239
e78c9d28
SB		 240 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
241 if (status & B43legacy_MACCTL_BE)
75388acd
LF		 242 val = swab32(val);
243
244 b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
245 mmiowb();
246 b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
247}
248
249static inline
250void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
251 u16 routing, u16 offset)
252{
253 u32 control;
254
255 /* "offset" is the WORD offset. */
256
257 control = routing;
258 control <<= 16;
259 control |= offset;
260 b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
261}
262
263u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
264 u16 routing, u16 offset)
265{
266 u32 ret;
267
268 if (routing == B43legacy_SHM_SHARED) {
269 B43legacy_WARN_ON((offset & 0x0001) != 0);
270 if (offset & 0x0003) {
271 /* Unaligned access */
272 b43legacy_shm_control_word(dev, routing, offset >> 2);
273 ret = b43legacy_read16(dev,
274 B43legacy_MMIO_SHM_DATA_UNALIGNED);
275 ret <<= 16;
276 b43legacy_shm_control_word(dev, routing,
277 (offset >> 2) + 1);
278 ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
279
280 return ret;
281 }
282 offset >>= 2;
283 }
284 b43legacy_shm_control_word(dev, routing, offset);
285 ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
286
287 return ret;
288}
289
290u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
291 u16 routing, u16 offset)
292{
293 u16 ret;
294
295 if (routing == B43legacy_SHM_SHARED) {
296 B43legacy_WARN_ON((offset & 0x0001) != 0);
297 if (offset & 0x0003) {
298 /* Unaligned access */
299 b43legacy_shm_control_word(dev, routing, offset >> 2);
300 ret = b43legacy_read16(dev,
301 B43legacy_MMIO_SHM_DATA_UNALIGNED);
302
303 return ret;
304 }
305 offset >>= 2;
306 }
307 b43legacy_shm_control_word(dev, routing, offset);
308 ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
309
310 return ret;
311}
312
313void b43legacy_shm_write32(struct b43legacy_wldev *dev,
314 u16 routing, u16 offset,
315 u32 value)
316{
317 if (routing == B43legacy_SHM_SHARED) {
318 B43legacy_WARN_ON((offset & 0x0001) != 0);
319 if (offset & 0x0003) {
320 /* Unaligned access */
321 b43legacy_shm_control_word(dev, routing, offset >> 2);
322 mmiowb();
323 b43legacy_write16(dev,
324 B43legacy_MMIO_SHM_DATA_UNALIGNED,
325 (value >> 16) & 0xffff);
326 mmiowb();
327 b43legacy_shm_control_word(dev, routing,
328 (offset >> 2) + 1);
329 mmiowb();
330 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
331 value & 0xffff);
332 return;
333 }
334 offset >>= 2;
335 }
336 b43legacy_shm_control_word(dev, routing, offset);
337 mmiowb();
338 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
339}
340
341void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
342 u16 value)
343{
344 if (routing == B43legacy_SHM_SHARED) {
345 B43legacy_WARN_ON((offset & 0x0001) != 0);
346 if (offset & 0x0003) {
347 /* Unaligned access */
348 b43legacy_shm_control_word(dev, routing, offset >> 2);
349 mmiowb();
350 b43legacy_write16(dev,
351 B43legacy_MMIO_SHM_DATA_UNALIGNED,
352 value);
353 return;
354 }
355 offset >>= 2;
356 }
357 b43legacy_shm_control_word(dev, routing, offset);
358 mmiowb();
359 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
360}
361
362/* Read HostFlags */
363u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
364{
365 u32 ret;
366
367 ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
368 B43legacy_SHM_SH_HOSTFHI);
369 ret <<= 16;
370 ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
371 B43legacy_SHM_SH_HOSTFLO);
372
373 return ret;
374}
375
376/* Write HostFlags */
377void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
378{
379 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
380 B43legacy_SHM_SH_HOSTFLO,
381 (value & 0x0000FFFF));
382 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
383 B43legacy_SHM_SH_HOSTFHI,
384 ((value & 0xFFFF0000) >> 16));
385}
386
387void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
388{
389 /* We need to be careful. As we read the TSF from multiple
390 * registers, we should take care of register overflows.
391 * In theory, the whole tsf read process should be atomic.
392 * We try to be atomic here, by restaring the read process,
393 * if any of the high registers changed (overflew).
394 */
395 if (dev->dev->id.revision >= 3) {
396 u32 low;
397 u32 high;
398 u32 high2;
399
400 do {
401 high = b43legacy_read32(dev,
402 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
403 low = b43legacy_read32(dev,
404 B43legacy_MMIO_REV3PLUS_TSF_LOW);
405 high2 = b43legacy_read32(dev,
406 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
407 } while (unlikely(high != high2));
408
409 *tsf = high;
410 *tsf <<= 32;
411 *tsf |= low;
412 } else {
413 u64 tmp;
414 u16 v0;
415 u16 v1;
416 u16 v2;
417 u16 v3;
418 u16 test1;
419 u16 test2;
420 u16 test3;
421
422 do {
423 v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
424 v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
425 v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
426 v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
427
428 test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
429 test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
430 test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
431 } while (v3 != test3 || v2 != test2 || v1 != test1);
432
433 *tsf = v3;
434 *tsf <<= 48;
435 tmp = v2;
436 tmp <<= 32;
437 *tsf |= tmp;
438 tmp = v1;
439 tmp <<= 16;
440 *tsf |= tmp;
441 *tsf |= v0;
442 }
443}
444
445static void b43legacy_time_lock(struct b43legacy_wldev *dev)
446{
447 u32 status;
448
e78c9d28
SB		 449 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
450 status |= B43legacy_MACCTL_TBTTHOLD;
451 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
75388acd
LF		 452 mmiowb();
453}
454
455static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
456{
457 u32 status;
458
e78c9d28
SB		 459 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
460 status &= ~B43legacy_MACCTL_TBTTHOLD;
461 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
75388acd
LF		 462}
463
464static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
465{
466 /* Be careful with the in-progress timer.
467 * First zero out the low register, so we have a full
468 * register-overflow duration to complete the operation.
469 */
470 if (dev->dev->id.revision >= 3) {
471 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
472 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
473
474 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
475 mmiowb();
476 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
477 hi);
478 mmiowb();
479 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
480 lo);
481 } else {
482 u16 v0 = (tsf & 0x000000000000FFFFULL);
483 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
484 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
485 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
486
487 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
488 mmiowb();
489 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
490 mmiowb();
491 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
492 mmiowb();
493 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
494 mmiowb();
495 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
496 }
497}
498
499void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
500{
501 b43legacy_time_lock(dev);
502 b43legacy_tsf_write_locked(dev, tsf);
503 b43legacy_time_unlock(dev);
504}
505
506static
507void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
508 u16 offset, const u8 *mac)
509{
510 static const u8 zero_addr[ETH_ALEN] = { 0 };
511 u16 data;
512
513 if (!mac)
514 mac = zero_addr;
515
516 offset |= 0x0020;
517 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
518
519 data = mac[0];
520 data |= mac[1] << 8;
521 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
522 data = mac[2];
523 data |= mac[3] << 8;
524 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
525 data = mac[4];
526 data |= mac[5] << 8;
527 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
528}
529
530static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
531{
532 static const u8 zero_addr[ETH_ALEN] = { 0 };
533 const u8 *mac = dev->wl->mac_addr;
534 const u8 *bssid = dev->wl->bssid;
535 u8 mac_bssid[ETH_ALEN * 2];
536 int i;
537 u32 tmp;
538
539 if (!bssid)
540 bssid = zero_addr;
541 if (!mac)
542 mac = zero_addr;
543
544 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
545
546 memcpy(mac_bssid, mac, ETH_ALEN);
547 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
548
549 /* Write our MAC address and BSSID to template ram */
550 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
551 tmp = (u32)(mac_bssid[i + 0]);
552 tmp |= (u32)(mac_bssid[i + 1]) << 8;
553 tmp |= (u32)(mac_bssid[i + 2]) << 16;
554 tmp |= (u32)(mac_bssid[i + 3]) << 24;
555 b43legacy_ram_write(dev, 0x20 + i, tmp);
556 b43legacy_ram_write(dev, 0x78 + i, tmp);
557 b43legacy_ram_write(dev, 0x478 + i, tmp);
558 }
559}
560
4150c572 561static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
75388acd 562{
75388acd 563 b43legacy_write_mac_bssid_templates(dev);
4150c572
JB		 564 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
565 dev->wl->mac_addr);
75388acd
LF		 566}
567
568static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
569 u16 slot_time)
570{
571 /* slot_time is in usec. */
572 if (dev->phy.type != B43legacy_PHYTYPE_G)
573 return;
574 b43legacy_write16(dev, 0x684, 510 + slot_time);
575 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
576 slot_time);
577}
578
579static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
580{
581 b43legacy_set_slot_time(dev, 9);
75388acd
LF		 582}
583
584static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
585{
586 b43legacy_set_slot_time(dev, 20);
75388acd
LF		 587}
588
75388acd
LF		 589/* Synchronize IRQ top- and bottom-half.
590 * IRQs must be masked before calling this.
591 * This must not be called with the irq_lock held.
592 */
593static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
594{
595 synchronize_irq(dev->dev->irq);
596 tasklet_kill(&dev->isr_tasklet);
597}
598
599/* DummyTransmission function, as documented on
600 * http://bcm-specs.sipsolutions.net/DummyTransmission
601 */
602void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
603{
604 struct b43legacy_phy *phy = &dev->phy;
605 unsigned int i;
606 unsigned int max_loop;
607 u16 value;
608 u32 buffer[5] = {
609 0x00000000,
610 0x00D40000,
611 0x00000000,
612 0x01000000,
613 0x00000000,
614 };
615
616 switch (phy->type) {
617 case B43legacy_PHYTYPE_B:
618 case B43legacy_PHYTYPE_G:
619 max_loop = 0xFA;
620 buffer[0] = 0x000B846E;
621 break;
622 default:
623 B43legacy_BUG_ON(1);
624 return;
625 }
626
627 for (i = 0; i < 5; i++)
628 b43legacy_ram_write(dev, i * 4, buffer[i]);
629
630 /* dummy read follows */
e78c9d28 631 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
75388acd
LF		 632
633 b43legacy_write16(dev, 0x0568, 0x0000);
634 b43legacy_write16(dev, 0x07C0, 0x0000);
635 b43legacy_write16(dev, 0x050C, 0x0000);
636 b43legacy_write16(dev, 0x0508, 0x0000);
637 b43legacy_write16(dev, 0x050A, 0x0000);
638 b43legacy_write16(dev, 0x054C, 0x0000);
639 b43legacy_write16(dev, 0x056A, 0x0014);
640 b43legacy_write16(dev, 0x0568, 0x0826);
641 b43legacy_write16(dev, 0x0500, 0x0000);
642 b43legacy_write16(dev, 0x0502, 0x0030);
643
644 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
645 b43legacy_radio_write16(dev, 0x0051, 0x0017);
646 for (i = 0x00; i < max_loop; i++) {
647 value = b43legacy_read16(dev, 0x050E);
648 if (value & 0x0080)
649 break;
650 udelay(10);
651 }
652 for (i = 0x00; i < 0x0A; i++) {
653 value = b43legacy_read16(dev, 0x050E);
654 if (value & 0x0400)
655 break;
656 udelay(10);
657 }
658 for (i = 0x00; i < 0x0A; i++) {
659 value = b43legacy_read16(dev, 0x0690);
660 if (!(value & 0x0100))
661 break;
662 udelay(10);
663 }
664 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
665 b43legacy_radio_write16(dev, 0x0051, 0x0037);
666}
667
668/* Turn the Analog ON/OFF */
669static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
670{
671 b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
672}
673
674void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
675{
676 u32 tmslow;
677 u32 macctl;
678
679 flags |= B43legacy_TMSLOW_PHYCLKEN;
680 flags |= B43legacy_TMSLOW_PHYRESET;
681 ssb_device_enable(dev->dev, flags);
682 msleep(2); /* Wait for the PLL to turn on. */
683
684 /* Now take the PHY out of Reset again */
685 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
686 tmslow |= SSB_TMSLOW_FGC;
687 tmslow &= ~B43legacy_TMSLOW_PHYRESET;
688 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
689 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
690 msleep(1);
691 tmslow &= ~SSB_TMSLOW_FGC;
692 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
693 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
694 msleep(1);
695
696 /* Turn Analog ON */
697 b43legacy_switch_analog(dev, 1);
698
699 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
700 macctl &= ~B43legacy_MACCTL_GMODE;
701 if (flags & B43legacy_TMSLOW_GMODE) {
702 macctl |= B43legacy_MACCTL_GMODE;
703 dev->phy.gmode = 1;
704 } else
705 dev->phy.gmode = 0;
706 macctl |= B43legacy_MACCTL_IHR_ENABLED;
707 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
708}
709
710static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
711{
712 u32 v0;
713 u32 v1;
714 u16 tmp;
715 struct b43legacy_txstatus stat;
716
717 while (1) {
718 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
719 if (!(v0 & 0x00000001))
720 break;
721 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
722
723 stat.cookie = (v0 >> 16);
724 stat.seq = (v1 & 0x0000FFFF);
725 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
726 tmp = (v0 & 0x0000FFFF);
727 stat.frame_count = ((tmp & 0xF000) >> 12);
728 stat.rts_count = ((tmp & 0x0F00) >> 8);
729 stat.supp_reason = ((tmp & 0x001C) >> 2);
730 stat.pm_indicated = !!(tmp & 0x0080);
731 stat.intermediate = !!(tmp & 0x0040);
732 stat.for_ampdu = !!(tmp & 0x0020);
733 stat.acked = !!(tmp & 0x0002);
734
735 b43legacy_handle_txstatus(dev, &stat);
736 }
737}
738
739static void drain_txstatus_queue(struct b43legacy_wldev *dev)
740{
741 u32 dummy;
742
743 if (dev->dev->id.revision < 5)
744 return;
745 /* Read all entries from the microcode TXstatus FIFO
746 * and throw them away.
747 */
748 while (1) {
749 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
750 if (!(dummy & 0x00000001))
751 break;
752 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
753 }
754}
755
756static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
757{
758 u32 val = 0;
759
760 val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
761 val <<= 16;
762 val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
763
764 return val;
765}
766
767static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
768{
769 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
770 (jssi & 0x0000FFFF));
771 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
772 (jssi & 0xFFFF0000) >> 16);
773}
774
775static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
776{
777 b43legacy_jssi_write(dev, 0x7F7F7F7F);
e78c9d28 778 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
eed0fd21
SB		 779 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
780 | B43legacy_MACCMD_BGNOISE);
75388acd
LF		 781 B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
782 dev->phy.channel);
783}
784
785static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
786{
787 /* Top half of Link Quality calculation. */
788
789 if (dev->noisecalc.calculation_running)
790 return;
791 dev->noisecalc.channel_at_start = dev->phy.channel;
792 dev->noisecalc.calculation_running = 1;
793 dev->noisecalc.nr_samples = 0;
794
795 b43legacy_generate_noise_sample(dev);
796}
797
798static void handle_irq_noise(struct b43legacy_wldev *dev)
799{
800 struct b43legacy_phy *phy = &dev->phy;
801 u16 tmp;
802 u8 noise[4];
803 u8 i;
804 u8 j;
805 s32 average;
806
807 /* Bottom half of Link Quality calculation. */
808
809 B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
810 if (dev->noisecalc.channel_at_start != phy->channel)
811 goto drop_calculation;
812 *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
813 if (noise[0] == 0x7F || noise[1] == 0x7F ||
814 noise[2] == 0x7F || noise[3] == 0x7F)
815 goto generate_new;
816
817 /* Get the noise samples. */
818 B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
819 i = dev->noisecalc.nr_samples;
ca21614d
HH		 820 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
821 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
822 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
823 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
75388acd
LF		 824 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
825 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
826 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
827 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
828 dev->noisecalc.nr_samples++;
829 if (dev->noisecalc.nr_samples == 8) {
830 /* Calculate the Link Quality by the noise samples. */
831 average = 0;
832 for (i = 0; i < 8; i++) {
833 for (j = 0; j < 4; j++)
834 average += dev->noisecalc.samples[i][j];
835 }
836 average /= (8 * 4);
837 average *= 125;
838 average += 64;
839 average /= 128;
840 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
841 0x40C);
842 tmp = (tmp / 128) & 0x1F;
843 if (tmp >= 8)
844 average += 2;
845 else
846 average -= 25;
847 if (tmp == 8)
848 average -= 72;
849 else
850 average -= 48;
851
852 dev->stats.link_noise = average;
853drop_calculation:
854 dev->noisecalc.calculation_running = 0;
855 return;
856 }
857generate_new:
858 b43legacy_generate_noise_sample(dev);
859}
860
861static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
862{
05c914fe 863 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
75388acd
LF		 864 /* TODO: PS TBTT */
865 } else {
866 if (1/*FIXME: the last PSpoll frame was sent successfully */)
867 b43legacy_power_saving_ctl_bits(dev, -1, -1);
868 }
05c914fe 869 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
eed0fd21 870 dev->dfq_valid = 1;
75388acd
LF		 871}
872
873static void handle_irq_atim_end(struct b43legacy_wldev *dev)
874{
eed0fd21
SB		 875 if (dev->dfq_valid) {
876 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
877 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
878 | B43legacy_MACCMD_DFQ_VALID);
879 dev->dfq_valid = 0;
880 }
75388acd
LF		 881}
882
883static void handle_irq_pmq(struct b43legacy_wldev *dev)
884{
885 u32 tmp;
886
887 /* TODO: AP mode. */
888
889 while (1) {
890 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
891 if (!(tmp & 0x00000008))
892 break;
893 }
894 /* 16bit write is odd, but correct. */
895 b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
896}
897
898static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
899 const u8 *data, u16 size,
900 u16 ram_offset,
901 u16 shm_size_offset, u8 rate)
902{
903 u32 i;
904 u32 tmp;
905 struct b43legacy_plcp_hdr4 plcp;
906
907 plcp.data = 0;
908 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
909 b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
910 ram_offset += sizeof(u32);
911 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
912 * So leave the first two bytes of the next write blank.
913 */
914 tmp = (u32)(data[0]) << 16;
915 tmp |= (u32)(data[1]) << 24;
916 b43legacy_ram_write(dev, ram_offset, tmp);
917 ram_offset += sizeof(u32);
918 for (i = 2; i < size; i += sizeof(u32)) {
919 tmp = (u32)(data[i + 0]);
920 if (i + 1 < size)
921 tmp |= (u32)(data[i + 1]) << 8;
922 if (i + 2 < size)
923 tmp |= (u32)(data[i + 2]) << 16;
924 if (i + 3 < size)
925 tmp |= (u32)(data[i + 3]) << 24;
926 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
927 }
928 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
929 size + sizeof(struct b43legacy_plcp_hdr6));
930}
931
2d1f96dd
LF		 932/* Convert a b43legacy antenna number value to the PHY TX control value. */
933static u16 b43legacy_antenna_to_phyctl(int antenna)
934{
935 switch (antenna) {
936 case B43legacy_ANTENNA0:
937 return B43legacy_TX4_PHY_ANT0;
938 case B43legacy_ANTENNA1:
939 return B43legacy_TX4_PHY_ANT1;
940 }
941 return B43legacy_TX4_PHY_ANTLAST;
942}
943
75388acd
LF		 944static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
945 u16 ram_offset,
2d1f96dd 946 u16 shm_size_offset)
75388acd 947{
75388acd 948
a297170d
SB		 949 unsigned int i, len, variable_len;
950 const struct ieee80211_mgmt *bcn;
951 const u8 *ie;
952 bool tim_found = 0;
2d1f96dd
LF		 953 unsigned int rate;
954 u16 ctl;
955 int antenna;
956 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
a297170d
SB		 957
958 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
959 len = min((size_t)dev->wl->current_beacon->len,
75388acd 960 0x200 - sizeof(struct b43legacy_plcp_hdr6));
2d1f96dd 961 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
a297170d
SB		 962
963 b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
75388acd 964 shm_size_offset, rate);
a297170d 965
2d1f96dd
LF		 966 /* Write the PHY TX control parameters. */
967 antenna = B43legacy_ANTENNA_DEFAULT;
968 antenna = b43legacy_antenna_to_phyctl(antenna);
969 ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
970 B43legacy_SHM_SH_BEACPHYCTL);
971 /* We can't send beacons with short preamble. Would get PHY errors. */
972 ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
973 ctl &= ~B43legacy_TX4_PHY_ANT;
974 ctl &= ~B43legacy_TX4_PHY_ENC;
975 ctl |= antenna;
976 ctl |= B43legacy_TX4_PHY_ENC_CCK;
977 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
978 B43legacy_SHM_SH_BEACPHYCTL, ctl);
979
a297170d
SB		 980 /* Find the position of the TIM and the DTIM_period value
981 * and write them to SHM. */
982 ie = bcn->u.beacon.variable;
983 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
984 for (i = 0; i < variable_len - 2; ) {
985 uint8_t ie_id, ie_len;
986
987 ie_id = ie[i];
988 ie_len = ie[i + 1];
989 if (ie_id == 5) {
990 u16 tim_position;
991 u16 dtim_period;
992 /* This is the TIM Information Element */
993
994 /* Check whether the ie_len is in the beacon data range. */
995 if (variable_len < ie_len + 2 + i)
996 break;
997 /* A valid TIM is at least 4 bytes long. */
998 if (ie_len < 4)
999 break;
1000 tim_found = 1;
1001
1002 tim_position = sizeof(struct b43legacy_plcp_hdr6);
1003 tim_position += offsetof(struct ieee80211_mgmt,
1004 u.beacon.variable);
1005 tim_position += i;
1006
1007 dtim_period = ie[i + 3];
1008
1009 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1010 B43legacy_SHM_SH_TIMPOS, tim_position);
1011 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1012 B43legacy_SHM_SH_DTIMP, dtim_period);
1013 break;
1014 }
1015 i += ie_len + 2;
1016 }
1017 if (!tim_found) {
1018 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1019 "beacon template packet. AP or IBSS operation "
1020 "may be broken.\n");
7858e07b
LF		 1021 } else
1022 b43legacydbg(dev->wl, "Updated beacon template\n");
75388acd
LF		 1023}
1024
1025static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1026 u16 shm_offset, u16 size,
8318d78a 1027 struct ieee80211_rate *rate)
75388acd
LF		 1028{
1029 struct b43legacy_plcp_hdr4 plcp;
1030 u32 tmp;
1031 __le16 dur;
1032
1033 plcp.data = 0;
2d1f96dd 1034 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
75388acd 1035 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1036 dev->wl->vif,
75388acd 1037 size,
8318d78a 1038 rate);
75388acd
LF		 1039 /* Write PLCP in two parts and timing for packet transfer */
1040 tmp = le32_to_cpu(plcp.data);
1041 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1042 tmp & 0xFFFF);
1043 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1044 tmp >> 16);
1045 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1046 le16_to_cpu(dur));
1047}
1048
1049/* Instead of using custom probe response template, this function
1050 * just patches custom beacon template by:
1051 * 1) Changing packet type
1052 * 2) Patching duration field
1053 * 3) Stripping TIM
1054 */
a297170d
SB		 1055static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1056 u16 *dest_size,
1057 struct ieee80211_rate *rate)
75388acd
LF		 1058{
1059 const u8 *src_data;
1060 u8 *dest_data;
a297170d 1061 u16 src_size, elem_size, src_pos, dest_pos;
75388acd
LF		 1062 __le16 dur;
1063 struct ieee80211_hdr *hdr;
a297170d
SB		 1064 size_t ie_start;
1065
1066 src_size = dev->wl->current_beacon->len;
1067 src_data = (const u8 *)dev->wl->current_beacon->data;
75388acd 1068
a297170d
SB		 1069 /* Get the start offset of the variable IEs in the packet. */
1070 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1071 B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1072 u.beacon.variable));
75388acd 1073
4688be30 1074 if (B43legacy_WARN_ON(src_size < ie_start))
75388acd 1075 return NULL;
75388acd
LF		 1076
1077 dest_data = kmalloc(src_size, GFP_ATOMIC);
1078 if (unlikely(!dest_data))
1079 return NULL;
1080
a297170d
SB		 1081 /* Copy the static data and all Information Elements, except the TIM. */
1082 memcpy(dest_data, src_data, ie_start);
1083 src_pos = ie_start;
1084 dest_pos = ie_start;
1085 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
75388acd 1086 elem_size = src_data[src_pos + 1] + 2;
a297170d
SB		 1087 if (src_data[src_pos] == 5) {
1088 /* This is the TIM. */
1089 continue;
75388acd 1090 }
a297170d
SB		 1091 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1092 dest_pos += elem_size;
75388acd
LF		 1093 }
1094 *dest_size = dest_pos;
1095 hdr = (struct ieee80211_hdr *)dest_data;
1096
1097 /* Set the frame control. */
1098 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1099 IEEE80211_STYPE_PROBE_RESP);
1100 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1101 dev->wl->vif,
75388acd 1102 *dest_size,
8318d78a 1103 rate);
75388acd
LF		 1104 hdr->duration_id = dur;
1105
1106 return dest_data;
1107}
1108
1109static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1110 u16 ram_offset,
8318d78a
JB		 1111 u16 shm_size_offset,
1112 struct ieee80211_rate *rate)
75388acd 1113{
a297170d 1114 const u8 *probe_resp_data;
75388acd
LF		 1115 u16 size;
1116
a297170d 1117 size = dev->wl->current_beacon->len;
75388acd
LF		 1118 probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1119 if (unlikely(!probe_resp_data))
1120 return;
1121
1122 /* Looks like PLCP headers plus packet timings are stored for
1123 * all possible basic rates
1124 */
1125 b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
8318d78a 1126 &b43legacy_b_ratetable[0]);
75388acd 1127 b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
8318d78a 1128 &b43legacy_b_ratetable[1]);
75388acd 1129 b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
8318d78a 1130 &b43legacy_b_ratetable[2]);
75388acd 1131 b43legacy_write_probe_resp_plcp(dev, 0x350, size,
8318d78a 1132 &b43legacy_b_ratetable[3]);
75388acd
LF		 1133
1134 size = min((size_t)size,
1135 0x200 - sizeof(struct b43legacy_plcp_hdr6));
1136 b43legacy_write_template_common(dev, probe_resp_data,
1137 size, ram_offset,
2d1f96dd 1138 shm_size_offset, rate->hw_value);
75388acd
LF		 1139 kfree(probe_resp_data);
1140}
1141
2d1f96dd
LF		 1142static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1143{
1144 struct b43legacy_wl *wl = dev->wl;
1145
1146 if (wl->beacon0_uploaded)
1147 return;
1148 b43legacy_write_beacon_template(dev, 0x68, 0x18);
1149 /* FIXME: Probe resp upload doesn't really belong here,
1150 * but we don't use that feature anyway. */
1151 b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1152 &__b43legacy_ratetable[3]);
1153 wl->beacon0_uploaded = 1;
1154}
1155
1156static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1157{
1158 struct b43legacy_wl *wl = dev->wl;
1159
1160 if (wl->beacon1_uploaded)
1161 return;
1162 b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1163 wl->beacon1_uploaded = 1;
1164}
1165
1166static void handle_irq_beacon(struct b43legacy_wldev *dev)
1167{
1168 struct b43legacy_wl *wl = dev->wl;
1169 u32 cmd, beacon0_valid, beacon1_valid;
1170
1171 if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1172 return;
1173
1174 /* This is the bottom half of the asynchronous beacon update. */
1175
1176 /* Ignore interrupt in the future. */
44710bbc 1177 dev->irq_mask &= ~B43legacy_IRQ_BEACON;
2d1f96dd
LF		 1178
1179 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1180 beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1181 beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1182
1183 /* Schedule interrupt manually, if busy. */
1184 if (beacon0_valid && beacon1_valid) {
1185 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
44710bbc 1186 dev->irq_mask |= B43legacy_IRQ_BEACON;
2d1f96dd
LF		 1187 return;
1188 }
1189
1190 if (unlikely(wl->beacon_templates_virgin)) {
1191 /* We never uploaded a beacon before.
1192 * Upload both templates now, but only mark one valid. */
1193 wl->beacon_templates_virgin = 0;
1194 b43legacy_upload_beacon0(dev);
1195 b43legacy_upload_beacon1(dev);
1196 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1197 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1198 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1199 } else {
1200 if (!beacon0_valid) {
1201 b43legacy_upload_beacon0(dev);
1202 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1203 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1204 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1205 } else if (!beacon1_valid) {
1206 b43legacy_upload_beacon1(dev);
1207 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1208 cmd |= B43legacy_MACCMD_BEACON1_VALID;
1209 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1210 }
1211 }
1212}
1213
7858e07b
LF		 1214static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1215{
1216 struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1217 beacon_update_trigger);
1218 struct b43legacy_wldev *dev;
1219
1220 mutex_lock(&wl->mutex);
1221 dev = wl->current_dev;
1222 if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
7858e07b 1223 spin_lock_irq(&wl->irq_lock);
44710bbc 1224 /* Update beacon right away or defer to IRQ. */
2d1f96dd
LF		 1225 handle_irq_beacon(dev);
1226 /* The handler might have updated the IRQ mask. */
1227 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
44710bbc 1228 dev->irq_mask);
2d1f96dd 1229 mmiowb();
7858e07b
LF		 1230 spin_unlock_irq(&wl->irq_lock);
1231 }
1232 mutex_unlock(&wl->mutex);
1233}
1234
a297170d
SB		 1235/* Asynchronously update the packet templates in template RAM.
1236 * Locking: Requires wl->irq_lock to be locked. */
9d139c81 1237static void b43legacy_update_templates(struct b43legacy_wl *wl)
75388acd 1238{
9d139c81 1239 struct sk_buff *beacon;
a297170d
SB		 1240 /* This is the top half of the ansynchronous beacon update. The bottom
1241 * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1242 * sending an invalid beacon. This can happen for example, if the
1243 * firmware transmits a beacon while we are updating it. */
75388acd 1244
9d139c81
JB		 1245 /* We could modify the existing beacon and set the aid bit in the TIM
1246 * field, but that would probably require resizing and moving of data
1247 * within the beacon template. Simply request a new beacon and let
1248 * mac80211 do the hard work. */
1249 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1250 if (unlikely(!beacon))
1251 return;
1252
a297170d
SB		 1253 if (wl->current_beacon)
1254 dev_kfree_skb_any(wl->current_beacon);
1255 wl->current_beacon = beacon;
1256 wl->beacon0_uploaded = 0;
1257 wl->beacon1_uploaded = 0;
42935eca 1258 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
75388acd
LF		 1259}
1260
75388acd
LF		 1261static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1262 u16 beacon_int)
1263{
1264 b43legacy_time_lock(dev);
7858e07b
LF		 1265 if (dev->dev->id.revision >= 3) {
1266 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1267 (beacon_int << 16));
1268 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1269 (beacon_int << 10));
1270 } else {
75388acd
LF		 1271 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1272 b43legacy_write16(dev, 0x610, beacon_int);
1273 }
1274 b43legacy_time_unlock(dev);
7858e07b 1275 b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
75388acd
LF		 1276}
1277
75388acd
LF		 1278static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1279{
1280}
1281
1282/* Interrupt handler bottom-half */
1283static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1284{
1285 u32 reason;
1286 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1287 u32 merged_dma_reason = 0;
1288 int i;
75388acd
LF		 1289 unsigned long flags;
1290
1291 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1292
1293 B43legacy_WARN_ON(b43legacy_status(dev) <
1294 B43legacy_STAT_INITIALIZED);
1295
1296 reason = dev->irq_reason;
1297 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1298 dma_reason[i] = dev->dma_reason[i];
1299 merged_dma_reason |= dma_reason[i];
1300 }
1301
1302 if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1303 b43legacyerr(dev->wl, "MAC transmission error\n");
1304
a293ee99 1305 if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
75388acd 1306 b43legacyerr(dev->wl, "PHY transmission error\n");
a293ee99
SB		 1307 rmb();
1308 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1309 b43legacyerr(dev->wl, "Too many PHY TX errors, "
1310 "restarting the controller\n");
1311 b43legacy_controller_restart(dev, "PHY TX errors");
1312 }
1313 }
75388acd
LF		 1314
1315 if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1316 B43legacy_DMAIRQ_NONFATALMASK))) {
1317 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1318 b43legacyerr(dev->wl, "Fatal DMA error: "
1319 "0x%08X, 0x%08X, 0x%08X, "
1320 "0x%08X, 0x%08X, 0x%08X\n",
1321 dma_reason[0], dma_reason[1],
1322 dma_reason[2], dma_reason[3],
1323 dma_reason[4], dma_reason[5]);
1324 b43legacy_controller_restart(dev, "DMA error");
1325 mmiowb();
1326 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1327 return;
1328 }
1329 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1330 b43legacyerr(dev->wl, "DMA error: "
1331 "0x%08X, 0x%08X, 0x%08X, "
1332 "0x%08X, 0x%08X, 0x%08X\n",
1333 dma_reason[0], dma_reason[1],
1334 dma_reason[2], dma_reason[3],
1335 dma_reason[4], dma_reason[5]);
1336 }
1337
1338 if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1339 handle_irq_ucode_debug(dev);
1340 if (reason & B43legacy_IRQ_TBTT_INDI)
1341 handle_irq_tbtt_indication(dev);
1342 if (reason & B43legacy_IRQ_ATIM_END)
1343 handle_irq_atim_end(dev);
1344 if (reason & B43legacy_IRQ_BEACON)
1345 handle_irq_beacon(dev);
1346 if (reason & B43legacy_IRQ_PMQ)
1347 handle_irq_pmq(dev);
1348 if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1349 ;/*TODO*/
1350 if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1351 handle_irq_noise(dev);
1352
1353 /* Check the DMA reason registers for received data. */
1354 if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1355 if (b43legacy_using_pio(dev))
1356 b43legacy_pio_rx(dev->pio.queue0);
1357 else
1358 b43legacy_dma_rx(dev->dma.rx_ring0);
75388acd
LF		 1359 }
1360 B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1361 B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1362 if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1363 if (b43legacy_using_pio(dev))
1364 b43legacy_pio_rx(dev->pio.queue3);
1365 else
1366 b43legacy_dma_rx(dev->dma.rx_ring3);
75388acd
LF		 1367 }
1368 B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1369 B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1370
ba48f7bb 1371 if (reason & B43legacy_IRQ_TX_OK)
75388acd 1372 handle_irq_transmit_status(dev);
75388acd 1373
44710bbc 1374 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
75388acd
LF		 1375 mmiowb();
1376 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1377}
1378
1379static void pio_irq_workaround(struct b43legacy_wldev *dev,
1380 u16 base, int queueidx)
1381{
1382 u16 rxctl;
1383
1384 rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1385 if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1386 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1387 else
1388 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1389}
1390
1391static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1392{
1393 if (b43legacy_using_pio(dev) &&
1394 (dev->dev->id.revision < 3) &&
1395 (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1396 /* Apply a PIO specific workaround to the dma_reasons */
1397 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1398 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1399 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1400 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1401 }
1402
1403 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1404
1405 b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1406 dev->dma_reason[0]);
1407 b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1408 dev->dma_reason[1]);
1409 b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1410 dev->dma_reason[2]);
1411 b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1412 dev->dma_reason[3]);
1413 b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1414 dev->dma_reason[4]);
1415 b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1416 dev->dma_reason[5]);
1417}
1418
1419/* Interrupt handler top-half */
1420static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1421{
1422 irqreturn_t ret = IRQ_NONE;
1423 struct b43legacy_wldev *dev = dev_id;
1424 u32 reason;
1425
44710bbc 1426 B43legacy_WARN_ON(!dev);
75388acd
LF		 1427
1428 spin_lock(&dev->wl->irq_lock);
1429
44710bbc
SB		 1430 if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
1431 /* This can only happen on shared IRQ lines. */
75388acd
LF		 1432 goto out;
1433 reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1434 if (reason == 0xffffffff) /* shared IRQ */
1435 goto out;
1436 ret = IRQ_HANDLED;
44710bbc 1437 reason &= dev->irq_mask;
75388acd
LF		 1438 if (!reason)
1439 goto out;
1440
1441 dev->dma_reason[0] = b43legacy_read32(dev,
1442 B43legacy_MMIO_DMA0_REASON)
1443 & 0x0001DC00;
1444 dev->dma_reason[1] = b43legacy_read32(dev,
1445 B43legacy_MMIO_DMA1_REASON)
1446 & 0x0000DC00;
1447 dev->dma_reason[2] = b43legacy_read32(dev,
1448 B43legacy_MMIO_DMA2_REASON)
1449 & 0x0000DC00;
1450 dev->dma_reason[3] = b43legacy_read32(dev,
1451 B43legacy_MMIO_DMA3_REASON)
1452 & 0x0001DC00;
1453 dev->dma_reason[4] = b43legacy_read32(dev,
1454 B43legacy_MMIO_DMA4_REASON)
1455 & 0x0000DC00;
1456 dev->dma_reason[5] = b43legacy_read32(dev,
1457 B43legacy_MMIO_DMA5_REASON)
1458 & 0x0000DC00;
1459
1460 b43legacy_interrupt_ack(dev, reason);
44710bbc
SB		 1461 /* Disable all IRQs. They are enabled again in the bottom half. */
1462 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1463 /* Save the reason code and call our bottom half. */
75388acd
LF		 1464 dev->irq_reason = reason;
1465 tasklet_schedule(&dev->isr_tasklet);
1466out:
1467 mmiowb();
1468 spin_unlock(&dev->wl->irq_lock);
1469
1470 return ret;
1471}
1472
1473static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1474{
1475 release_firmware(dev->fw.ucode);
1476 dev->fw.ucode = NULL;
1477 release_firmware(dev->fw.pcm);
1478 dev->fw.pcm = NULL;
1479 release_firmware(dev->fw.initvals);
1480 dev->fw.initvals = NULL;
1481 release_firmware(dev->fw.initvals_band);
1482 dev->fw.initvals_band = NULL;
1483}
1484
1485static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1486{
1487 b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
354807e0 1488 "Drivers/b43#devicefirmware "
75388acd
LF		 1489 "and download the correct firmware (version 3).\n");
1490}
1491
1492static int do_request_fw(struct b43legacy_wldev *dev,
1493 const char *name,
1494 const struct firmware **fw)
1495{
1496 char path[sizeof(modparam_fwpostfix) + 32];
1497 struct b43legacy_fw_header *hdr;
1498 u32 size;
1499 int err;
1500
1501 if (!name)
1502 return 0;
1503
1504 snprintf(path, ARRAY_SIZE(path),
1505 "b43legacy%s/%s.fw",
1506 modparam_fwpostfix, name);
1507 err = request_firmware(fw, path, dev->dev->dev);
1508 if (err) {
1509 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1510 "or load failed.\n", path);
1511 return err;
1512 }
1513 if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1514 goto err_format;
1515 hdr = (struct b43legacy_fw_header *)((*fw)->data);
1516 switch (hdr->type) {
1517 case B43legacy_FW_TYPE_UCODE:
1518 case B43legacy_FW_TYPE_PCM:
1519 size = be32_to_cpu(hdr->size);
1520 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1521 goto err_format;
1522 /* fallthrough */
1523 case B43legacy_FW_TYPE_IV:
1524 if (hdr->ver != 1)
1525 goto err_format;
1526 break;
1527 default:
1528 goto err_format;
1529 }
1530
1531 return err;
1532
1533err_format:
1534 b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1535 return -EPROTO;
1536}
1537
1538static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1539{
1540 struct b43legacy_firmware *fw = &dev->fw;
1541 const u8 rev = dev->dev->id.revision;
1542 const char *filename;
1543 u32 tmshigh;
1544 int err;
1545
1546 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1547 if (!fw->ucode) {
1548 if (rev == 2)
1549 filename = "ucode2";
1550 else if (rev == 4)
1551 filename = "ucode4";
1552 else
1553 filename = "ucode5";
1554 err = do_request_fw(dev, filename, &fw->ucode);
1555 if (err)
1556 goto err_load;
1557 }
1558 if (!fw->pcm) {
1559 if (rev < 5)
1560 filename = "pcm4";
1561 else
1562 filename = "pcm5";
1563 err = do_request_fw(dev, filename, &fw->pcm);
1564 if (err)
1565 goto err_load;
1566 }
1567 if (!fw->initvals) {
1568 switch (dev->phy.type) {
385f848a 1569 case B43legacy_PHYTYPE_B:
75388acd
LF		 1570 case B43legacy_PHYTYPE_G:
1571 if ((rev >= 5) && (rev <= 10))
1572 filename = "b0g0initvals5";
1573 else if (rev == 2 || rev == 4)
1574 filename = "b0g0initvals2";
1575 else
1576 goto err_no_initvals;
1577 break;
1578 default:
1579 goto err_no_initvals;
1580 }
1581 err = do_request_fw(dev, filename, &fw->initvals);
1582 if (err)
1583 goto err_load;
1584 }
1585 if (!fw->initvals_band) {
1586 switch (dev->phy.type) {
385f848a 1587 case B43legacy_PHYTYPE_B:
75388acd
LF		 1588 case B43legacy_PHYTYPE_G:
1589 if ((rev >= 5) && (rev <= 10))
1590 filename = "b0g0bsinitvals5";
1591 else if (rev >= 11)
1592 filename = NULL;
1593 else if (rev == 2 || rev == 4)
1594 filename = NULL;
1595 else
1596 goto err_no_initvals;
1597 break;
1598 default:
1599 goto err_no_initvals;
1600 }
1601 err = do_request_fw(dev, filename, &fw->initvals_band);
1602 if (err)
1603 goto err_load;
1604 }
1605
1606 return 0;
1607
1608err_load:
1609 b43legacy_print_fw_helptext(dev->wl);
1610 goto error;
1611
1612err_no_initvals:
1613 err = -ENODEV;
1614 b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1615 "core rev %u\n", dev->phy.type, rev);
1616 goto error;
1617
1618error:
1619 b43legacy_release_firmware(dev);
1620 return err;
1621}
1622
1623static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1624{
1625 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1626 const __be32 *data;
1627 unsigned int i;
1628 unsigned int len;
1629 u16 fwrev;
1630 u16 fwpatch;
1631 u16 fwdate;
1632 u16 fwtime;
e78c9d28 1633 u32 tmp, macctl;
75388acd
LF		 1634 int err = 0;
1635
e78c9d28
SB		 1636 /* Jump the microcode PSM to offset 0 */
1637 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1638 B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1639 macctl |= B43legacy_MACCTL_PSM_JMP0;
1640 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1641 /* Zero out all microcode PSM registers and shared memory. */
1642 for (i = 0; i < 64; i++)
1643 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1644 for (i = 0; i < 4096; i += 2)
1645 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1646
75388acd
LF		 1647 /* Upload Microcode. */
1648 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1649 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1650 b43legacy_shm_control_word(dev,
1651 B43legacy_SHM_UCODE |
1652 B43legacy_SHM_AUTOINC_W,
1653 0x0000);
1654 for (i = 0; i < len; i++) {
1655 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1656 be32_to_cpu(data[i]));
1657 udelay(10);
1658 }
1659
1660 if (dev->fw.pcm) {
1661 /* Upload PCM data. */
1662 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1663 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1664 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1665 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1666 /* No need for autoinc bit in SHM_HW */
1667 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1668 for (i = 0; i < len; i++) {
1669 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1670 be32_to_cpu(data[i]));
1671 udelay(10);
1672 }
1673 }
1674
1675 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1676 B43legacy_IRQ_ALL);
e78c9d28
SB		 1677
1678 /* Start the microcode PSM */
1679 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1680 macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1681 macctl |= B43legacy_MACCTL_PSM_RUN;
1682 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
75388acd
LF		 1683
1684 /* Wait for the microcode to load and respond */
1685 i = 0;
1686 while (1) {
1687 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1688 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1689 break;
1690 i++;
1691 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1692 b43legacyerr(dev->wl, "Microcode not responding\n");
1693 b43legacy_print_fw_helptext(dev->wl);
1694 err = -ENODEV;
e78c9d28
SB		 1695 goto error;
1696 }
1697 msleep_interruptible(50);
1698 if (signal_pending(current)) {
1699 err = -EINTR;
1700 goto error;
75388acd 1701 }
75388acd
LF		 1702 }
1703 /* dummy read follows */
1704 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1705
1706 /* Get and check the revisions. */
1707 fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1708 B43legacy_SHM_SH_UCODEREV);
1709 fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1710 B43legacy_SHM_SH_UCODEPATCH);
1711 fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1712 B43legacy_SHM_SH_UCODEDATE);
1713 fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1714 B43legacy_SHM_SH_UCODETIME);
1715
1716 if (fwrev > 0x128) {
1717 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1718 " Only firmware from binary drivers version 3.x"
1719 " is supported. You must change your firmware"
1720 " files.\n");
1721 b43legacy_print_fw_helptext(dev->wl);
75388acd 1722 err = -EOPNOTSUPP;
e78c9d28 1723 goto error;
75388acd 1724 }
cfbc35b6
SB		 1725 b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1726 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1727 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1728 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1729 fwtime & 0x1F);
75388acd
LF		 1730
1731 dev->fw.rev = fwrev;
1732 dev->fw.patch = fwpatch;
1733
e78c9d28
SB		 1734 return 0;
1735
1736error:
1737 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1738 macctl &= ~B43legacy_MACCTL_PSM_RUN;
1739 macctl |= B43legacy_MACCTL_PSM_JMP0;
1740 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1741
75388acd
LF		 1742 return err;
1743}
1744
1745static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1746 const struct b43legacy_iv *ivals,
1747 size_t count,
1748 size_t array_size)
1749{
1750 const struct b43legacy_iv *iv;
1751 u16 offset;
1752 size_t i;
1753 bool bit32;
1754
1755 BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1756 iv = ivals;
1757 for (i = 0; i < count; i++) {
1758 if (array_size < sizeof(iv->offset_size))
1759 goto err_format;
1760 array_size -= sizeof(iv->offset_size);
1761 offset = be16_to_cpu(iv->offset_size);
1762 bit32 = !!(offset & B43legacy_IV_32BIT);
1763 offset &= B43legacy_IV_OFFSET_MASK;
1764 if (offset >= 0x1000)
1765 goto err_format;
1766 if (bit32) {
1767 u32 value;
1768
1769 if (array_size < sizeof(iv->data.d32))
1770 goto err_format;
1771 array_size -= sizeof(iv->data.d32);
1772
533dd1b0 1773 value = get_unaligned_be32(&iv->data.d32);
75388acd
LF		 1774 b43legacy_write32(dev, offset, value);
1775
1776 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1777 sizeof(__be16) +
1778 sizeof(__be32));
1779 } else {
1780 u16 value;
1781
1782 if (array_size < sizeof(iv->data.d16))
1783 goto err_format;
1784 array_size -= sizeof(iv->data.d16);
1785
1786 value = be16_to_cpu(iv->data.d16);
1787 b43legacy_write16(dev, offset, value);
1788
1789 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1790 sizeof(__be16) +
1791 sizeof(__be16));
1792 }
1793 }
1794 if (array_size)
1795 goto err_format;
1796
1797 return 0;
1798
1799err_format:
1800 b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1801 b43legacy_print_fw_helptext(dev->wl);
1802
1803 return -EPROTO;
1804}
1805
1806static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1807{
1808 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1809 const struct b43legacy_fw_header *hdr;
1810 struct b43legacy_firmware *fw = &dev->fw;
1811 const struct b43legacy_iv *ivals;
1812 size_t count;
1813 int err;
1814
1815 hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1816 ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1817 count = be32_to_cpu(hdr->size);
1818 err = b43legacy_write_initvals(dev, ivals, count,
1819 fw->initvals->size - hdr_len);
1820 if (err)
1821 goto out;
1822 if (fw->initvals_band) {
1823 hdr = (const struct b43legacy_fw_header *)
1824 (fw->initvals_band->data);
1825 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1826 + hdr_len);
1827 count = be32_to_cpu(hdr->size);
1828 err = b43legacy_write_initvals(dev, ivals, count,
1829 fw->initvals_band->size - hdr_len);
1830 if (err)
1831 goto out;
1832 }
1833out:
1834
1835 return err;
1836}
1837
1838/* Initialize the GPIOs
1839 * http://bcm-specs.sipsolutions.net/GPIO
1840 */
1841static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1842{
1843 struct ssb_bus *bus = dev->dev->bus;
1844 struct ssb_device *gpiodev, *pcidev = NULL;
1845 u32 mask;
1846 u32 set;
1847
e78c9d28 1848 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1849 b43legacy_read32(dev,
e78c9d28 1850 B43legacy_MMIO_MACCTL)
75388acd
LF		 1851 & 0xFFFF3FFF);
1852
75388acd
LF		 1853 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1854 b43legacy_read16(dev,
1855 B43legacy_MMIO_GPIO_MASK)
1856 | 0x000F);
1857
1858 mask = 0x0000001F;
1859 set = 0x0000000F;
1860 if (dev->dev->bus->chip_id == 0x4301) {
1861 mask |= 0x0060;
1862 set |= 0x0060;
1863 }
7797aa38 1864 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
75388acd
LF		 1865 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1866 b43legacy_read16(dev,
1867 B43legacy_MMIO_GPIO_MASK)
1868 | 0x0200);
1869 mask |= 0x0200;
1870 set |= 0x0200;
1871 }
1872 if (dev->dev->id.revision >= 2)
1873 mask |= 0x0010; /* FIXME: This is redundant. */
1874
1875#ifdef CONFIG_SSB_DRIVER_PCICORE
1876 pcidev = bus->pcicore.dev;
1877#endif
1878 gpiodev = bus->chipco.dev ? : pcidev;
1879 if (!gpiodev)
1880 return 0;
1881 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1882 (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1883 & mask) | set);
1884
1885 return 0;
1886}
1887
1888/* Turn off all GPIO stuff. Call this on module unload, for example. */
1889static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1890{
1891 struct ssb_bus *bus = dev->dev->bus;
1892 struct ssb_device *gpiodev, *pcidev = NULL;
1893
1894#ifdef CONFIG_SSB_DRIVER_PCICORE
1895 pcidev = bus->pcicore.dev;
1896#endif
1897 gpiodev = bus->chipco.dev ? : pcidev;
1898 if (!gpiodev)
1899 return;
1900 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1901}
1902
1903/* http://bcm-specs.sipsolutions.net/EnableMac */
1904void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1905{
1906 dev->mac_suspended--;
1907 B43legacy_WARN_ON(dev->mac_suspended < 0);
f34eb692 1908 B43legacy_WARN_ON(irqs_disabled());
75388acd 1909 if (dev->mac_suspended == 0) {
e78c9d28 1910 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1911 b43legacy_read32(dev,
e78c9d28
SB		 1912 B43legacy_MMIO_MACCTL)
1913 | B43legacy_MACCTL_ENABLED);
75388acd
LF		 1914 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1915 B43legacy_IRQ_MAC_SUSPENDED);
1916 /* the next two are dummy reads */
e78c9d28 1917 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
75388acd
LF		 1918 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1919 b43legacy_power_saving_ctl_bits(dev, -1, -1);
f34eb692
LF		 1920
1921 /* Re-enable IRQs. */
1922 spin_lock_irq(&dev->wl->irq_lock);
44710bbc
SB		 1923 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1924 dev->irq_mask);
f34eb692 1925 spin_unlock_irq(&dev->wl->irq_lock);
75388acd
LF		 1926 }
1927}
1928
1929/* http://bcm-specs.sipsolutions.net/SuspendMAC */
1930void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1931{
1932 int i;
1933 u32 tmp;
1934
f34eb692
LF		 1935 might_sleep();
1936 B43legacy_WARN_ON(irqs_disabled());
75388acd 1937 B43legacy_WARN_ON(dev->mac_suspended < 0);
f34eb692 1938
75388acd 1939 if (dev->mac_suspended == 0) {
f34eb692
LF		 1940 /* Mask IRQs before suspending MAC. Otherwise
1941 * the MAC stays busy and won't suspend. */
1942 spin_lock_irq(&dev->wl->irq_lock);
44710bbc 1943 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
f34eb692
LF		 1944 spin_unlock_irq(&dev->wl->irq_lock);
1945 b43legacy_synchronize_irq(dev);
f34eb692 1946
75388acd 1947 b43legacy_power_saving_ctl_bits(dev, -1, 1);
e78c9d28 1948 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1949 b43legacy_read32(dev,
e78c9d28
SB		 1950 B43legacy_MMIO_MACCTL)
1951 & ~B43legacy_MACCTL_ENABLED);
75388acd 1952 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
f34eb692 1953 for (i = 40; i; i--) {
75388acd
LF		 1954 tmp = b43legacy_read32(dev,
1955 B43legacy_MMIO_GEN_IRQ_REASON);
1956 if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1957 goto out;
f34eb692 1958 msleep(1);
75388acd
LF		 1959 }
1960 b43legacyerr(dev->wl, "MAC suspend failed\n");
1961 }
1962out:
1963 dev->mac_suspended++;
1964}
1965
1966static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1967{
1968 struct b43legacy_wl *wl = dev->wl;
1969 u32 ctl;
1970 u16 cfp_pretbtt;
1971
1972 ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1973 /* Reset status to STA infrastructure mode. */
1974 ctl &= ~B43legacy_MACCTL_AP;
1975 ctl &= ~B43legacy_MACCTL_KEEP_CTL;
1976 ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
1977 ctl &= ~B43legacy_MACCTL_KEEP_BAD;
1978 ctl &= ~B43legacy_MACCTL_PROMISC;
4150c572 1979 ctl &= ~B43legacy_MACCTL_BEACPROMISC;
75388acd
LF		 1980 ctl |= B43legacy_MACCTL_INFRA;
1981
05c914fe 1982 if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
4150c572 1983 ctl |= B43legacy_MACCTL_AP;
05c914fe 1984 else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 1985 ctl &= ~B43legacy_MACCTL_INFRA;
1986
1987 if (wl->filter_flags & FIF_CONTROL)
75388acd 1988 ctl |= B43legacy_MACCTL_KEEP_CTL;
4150c572
JB		 1989 if (wl->filter_flags & FIF_FCSFAIL)
1990 ctl |= B43legacy_MACCTL_KEEP_BAD;
1991 if (wl->filter_flags & FIF_PLCPFAIL)
1992 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
1993 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
75388acd 1994 ctl |= B43legacy_MACCTL_PROMISC;
4150c572
JB		 1995 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
1996 ctl |= B43legacy_MACCTL_BEACPROMISC;
1997
75388acd
LF		 1998 /* Workaround: On old hardware the HW-MAC-address-filter
1999 * doesn't work properly, so always run promisc in filter
2000 * it in software. */
2001 if (dev->dev->id.revision <= 4)
2002 ctl |= B43legacy_MACCTL_PROMISC;
2003
2004 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2005
2006 cfp_pretbtt = 2;
2007 if ((ctl & B43legacy_MACCTL_INFRA) &&
2008 !(ctl & B43legacy_MACCTL_AP)) {
2009 if (dev->dev->bus->chip_id == 0x4306 &&
2010 dev->dev->bus->chip_rev == 3)
2011 cfp_pretbtt = 100;
2012 else
2013 cfp_pretbtt = 50;
2014 }
2015 b43legacy_write16(dev, 0x612, cfp_pretbtt);
2016}
2017
2018static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2019 u16 rate,
2020 int is_ofdm)
2021{
2022 u16 offset;
2023
2024 if (is_ofdm) {
2025 offset = 0x480;
2026 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2027 } else {
2028 offset = 0x4C0;
2029 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2030 }
2031 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2032 b43legacy_shm_read16(dev,
2033 B43legacy_SHM_SHARED, offset));
2034}
2035
2036static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2037{
2038 switch (dev->phy.type) {
2039 case B43legacy_PHYTYPE_G:
2040 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2041 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2042 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2043 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2044 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2045 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2046 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2047 /* fallthrough */
2048 case B43legacy_PHYTYPE_B:
2049 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2050 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2051 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2052 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2053 break;
2054 default:
2055 B43legacy_BUG_ON(1);
2056 }
2057}
2058
2059/* Set the TX-Antenna for management frames sent by firmware. */
2060static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2061 int antenna)
2062{
2063 u16 ant = 0;
2064 u16 tmp;
2065
2066 switch (antenna) {
2067 case B43legacy_ANTENNA0:
2068 ant |= B43legacy_TX4_PHY_ANT0;
2069 break;
2070 case B43legacy_ANTENNA1:
2071 ant |= B43legacy_TX4_PHY_ANT1;
2072 break;
2073 case B43legacy_ANTENNA_AUTO:
2074 ant |= B43legacy_TX4_PHY_ANTLAST;
2075 break;
2076 default:
2077 B43legacy_BUG_ON(1);
2078 }
2079
2080 /* FIXME We also need to set the other flags of the PHY control
2081 * field somewhere. */
2082
2083 /* For Beacons */
2084 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2085 B43legacy_SHM_SH_BEACPHYCTL);
2086 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2087 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2088 B43legacy_SHM_SH_BEACPHYCTL, tmp);
2089 /* For ACK/CTS */
2090 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2091 B43legacy_SHM_SH_ACKCTSPHYCTL);
2092 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2093 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2094 B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2095 /* For Probe Resposes */
2096 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2097 B43legacy_SHM_SH_PRPHYCTL);
2098 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2099 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2100 B43legacy_SHM_SH_PRPHYCTL, tmp);
2101}
2102
2103/* This is the opposite of b43legacy_chip_init() */
2104static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2105{
93bb7f3a 2106 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 2107 b43legacy_gpio_cleanup(dev);
2108 /* firmware is released later */
2109}
2110
2111/* Initialize the chip
2112 * http://bcm-specs.sipsolutions.net/ChipInit
2113 */
2114static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2115{
2116 struct b43legacy_phy *phy = &dev->phy;
2117 int err;
2118 int tmp;
e78c9d28 2119 u32 value32, macctl;
75388acd
LF		 2120 u16 value16;
2121
e78c9d28
SB		 2122 /* Initialize the MAC control */
2123 macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2124 if (dev->phy.gmode)
2125 macctl |= B43legacy_MACCTL_GMODE;
2126 macctl |= B43legacy_MACCTL_INFRA;
2127 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
75388acd
LF		 2128
2129 err = b43legacy_request_firmware(dev);
2130 if (err)
2131 goto out;
2132 err = b43legacy_upload_microcode(dev);
2133 if (err)
2134 goto out; /* firmware is released later */
2135
2136 err = b43legacy_gpio_init(dev);
2137 if (err)
2138 goto out; /* firmware is released later */
ba48f7bb 2139
75388acd
LF		 2140 err = b43legacy_upload_initvals(dev);
2141 if (err)
4ad36d78 2142 goto err_gpio_clean;
75388acd 2143 b43legacy_radio_turn_on(dev);
75388acd
LF		 2144
2145 b43legacy_write16(dev, 0x03E6, 0x0000);
2146 err = b43legacy_phy_init(dev);
2147 if (err)
2148 goto err_radio_off;
2149
2150 /* Select initial Interference Mitigation. */
2151 tmp = phy->interfmode;
2152 phy->interfmode = B43legacy_INTERFMODE_NONE;
2153 b43legacy_radio_set_interference_mitigation(dev, tmp);
2154
2155 b43legacy_phy_set_antenna_diversity(dev);
2156 b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2157
2158 if (phy->type == B43legacy_PHYTYPE_B) {
2159 value16 = b43legacy_read16(dev, 0x005E);
2160 value16 |= 0x0004;
2161 b43legacy_write16(dev, 0x005E, value16);
2162 }
2163 b43legacy_write32(dev, 0x0100, 0x01000000);
2164 if (dev->dev->id.revision < 5)
2165 b43legacy_write32(dev, 0x010C, 0x01000000);
2166
e78c9d28
SB		 2167 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2168 value32 &= ~B43legacy_MACCTL_INFRA;
2169 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2170 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2171 value32 |= B43legacy_MACCTL_INFRA;
2172 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
75388acd 2173
75388acd
LF		 2174 if (b43legacy_using_pio(dev)) {
2175 b43legacy_write32(dev, 0x0210, 0x00000100);
2176 b43legacy_write32(dev, 0x0230, 0x00000100);
2177 b43legacy_write32(dev, 0x0250, 0x00000100);
2178 b43legacy_write32(dev, 0x0270, 0x00000100);
2179 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2180 0x0000);
2181 }
2182
2183 /* Probe Response Timeout value */
2184 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2185 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2186
2187 /* Initially set the wireless operation mode. */
2188 b43legacy_adjust_opmode(dev);
2189
2190 if (dev->dev->id.revision < 3) {
2191 b43legacy_write16(dev, 0x060E, 0x0000);
2192 b43legacy_write16(dev, 0x0610, 0x8000);
2193 b43legacy_write16(dev, 0x0604, 0x0000);
2194 b43legacy_write16(dev, 0x0606, 0x0200);
2195 } else {
2196 b43legacy_write32(dev, 0x0188, 0x80000000);
2197 b43legacy_write32(dev, 0x018C, 0x02000000);
2198 }
2199 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2200 b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2201 b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2202 b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2203 b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2204 b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2205 b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2206
2207 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2208 value32 |= 0x00100000;
2209 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2210
2211 b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2212 dev->dev->bus->chipco.fast_pwrup_delay);
2213
a293ee99
SB		 2214 /* PHY TX errors counter. */
2215 atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2216
75388acd
LF		 2217 B43legacy_WARN_ON(err != 0);
2218 b43legacydbg(dev->wl, "Chip initialized\n");
2219out:
2220 return err;
2221
2222err_radio_off:
93bb7f3a 2223 b43legacy_radio_turn_off(dev, 1);
4ad36d78 2224err_gpio_clean:
75388acd
LF		 2225 b43legacy_gpio_cleanup(dev);
2226 goto out;
2227}
2228
2229static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2230{
2231 struct b43legacy_phy *phy = &dev->phy;
2232
2233 if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2234 return;
2235
2236 b43legacy_mac_suspend(dev);
2237 b43legacy_phy_lo_g_measure(dev);
2238 b43legacy_mac_enable(dev);
2239}
2240
2241static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2242{
2243 b43legacy_phy_lo_mark_all_unused(dev);
7797aa38 2244 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
75388acd
LF		 2245 b43legacy_mac_suspend(dev);
2246 b43legacy_calc_nrssi_slope(dev);
2247 b43legacy_mac_enable(dev);
2248 }
2249}
2250
2251static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2252{
2253 /* Update device statistics. */
2254 b43legacy_calculate_link_quality(dev);
2255}
2256
2257static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2258{
2259 b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
a293ee99
SB		 2260
2261 atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2262 wmb();
75388acd
LF		 2263}
2264
75388acd
LF		 2265static void do_periodic_work(struct b43legacy_wldev *dev)
2266{
2267 unsigned int state;
2268
2269 state = dev->periodic_state;
6be50837 2270 if (state % 8 == 0)
75388acd 2271 b43legacy_periodic_every120sec(dev);
6be50837 2272 if (state % 4 == 0)
75388acd 2273 b43legacy_periodic_every60sec(dev);
6be50837 2274 if (state % 2 == 0)
75388acd 2275 b43legacy_periodic_every30sec(dev);
6be50837 2276 b43legacy_periodic_every15sec(dev);
75388acd
LF		 2277}
2278
f34eb692
LF		 2279/* Periodic work locking policy:
2280 * The whole periodic work handler is protected by
2281 * wl->mutex. If another lock is needed somewhere in the
2282 * pwork callchain, it's aquired in-place, where it's needed.
75388acd 2283 */
75388acd
LF		 2284static void b43legacy_periodic_work_handler(struct work_struct *work)
2285{
f34eb692
LF		 2286 struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2287 periodic_work.work);
2288 struct b43legacy_wl *wl = dev->wl;
75388acd 2289 unsigned long delay;
75388acd 2290
f34eb692 2291 mutex_lock(&wl->mutex);
75388acd
LF		 2292
2293 if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2294 goto out;
2295 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2296 goto out_requeue;
2297
f34eb692 2298 do_periodic_work(dev);
75388acd 2299
75388acd
LF		 2300 dev->periodic_state++;
2301out_requeue:
2302 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2303 delay = msecs_to_jiffies(50);
2304 else
6be50837 2305 delay = round_jiffies_relative(HZ * 15);
42935eca 2306 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
75388acd 2307out:
f34eb692 2308 mutex_unlock(&wl->mutex);
75388acd
LF		 2309}
2310
2311static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2312{
2313 struct delayed_work *work = &dev->periodic_work;
2314
2315 dev->periodic_state = 0;
2316 INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
42935eca 2317 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
75388acd
LF		 2318}
2319
2320/* Validate access to the chip (SHM) */
2321static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2322{
2323 u32 value;
2324 u32 shm_backup;
2325
2326 shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2327 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2328 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2329 0xAA5555AA)
2330 goto error;
2331 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2332 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2333 0x55AAAA55)
2334 goto error;
2335 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2336
2337 value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2338 if ((value | B43legacy_MACCTL_GMODE) !=
2339 (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2340 goto error;
2341
2342 value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2343 if (value)
2344 goto error;
2345
2346 return 0;
2347error:
2348 b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2349 return -ENODEV;
2350}
2351
2352static void b43legacy_security_init(struct b43legacy_wldev *dev)
2353{
2354 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2355 B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2356 dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2357 0x0056);
2358 /* KTP is a word address, but we address SHM bytewise.
2359 * So multiply by two.
2360 */
2361 dev->ktp *= 2;
2362 if (dev->dev->id.revision >= 5)
2363 /* Number of RCMTA address slots */
2364 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2365 dev->max_nr_keys - 8);
2366}
2367
910cfee3 2368#ifdef CONFIG_B43LEGACY_HWRNG
75388acd
LF		 2369static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2370{
2371 struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2372 unsigned long flags;
2373
2374 /* Don't take wl->mutex here, as it could deadlock with
2375 * hwrng internal locking. It's not needed to take
2376 * wl->mutex here, anyway. */
2377
2378 spin_lock_irqsave(&wl->irq_lock, flags);
2379 *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2380 spin_unlock_irqrestore(&wl->irq_lock, flags);
2381
2382 return (sizeof(u16));
2383}
910cfee3 2384#endif
75388acd
LF		 2385
2386static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2387{
910cfee3 2388#ifdef CONFIG_B43LEGACY_HWRNG
75388acd
LF		 2389 if (wl->rng_initialized)
2390 hwrng_unregister(&wl->rng);
910cfee3 2391#endif
75388acd
LF		 2392}
2393
2394static int b43legacy_rng_init(struct b43legacy_wl *wl)
2395{
910cfee3 2396 int err = 0;
75388acd 2397
910cfee3 2398#ifdef CONFIG_B43LEGACY_HWRNG
75388acd
LF		 2399 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2400 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2401 wl->rng.name = wl->rng_name;
2402 wl->rng.data_read = b43legacy_rng_read;
2403 wl->rng.priv = (unsigned long)wl;
2404 wl->rng_initialized = 1;
2405 err = hwrng_register(&wl->rng);
2406 if (err) {
2407 wl->rng_initialized = 0;
2408 b43legacyerr(wl, "Failed to register the random "
2409 "number generator (%d)\n", err);
2410 }
2411
910cfee3 2412#endif
75388acd
LF		 2413 return err;
2414}
2415
33a3dc93 2416static int b43legacy_op_tx(struct ieee80211_hw *hw,
e039fa4a 2417 struct sk_buff *skb)
75388acd
LF		 2418{
2419 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2420 struct b43legacy_wldev *dev = wl->current_dev;
2421 int err = -ENODEV;
2422 unsigned long flags;
2423
2424 if (unlikely(!dev))
2425 goto out;
2426 if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2427 goto out;
2428 /* DMA-TX is done without a global lock. */
2429 if (b43legacy_using_pio(dev)) {
2430 spin_lock_irqsave(&wl->irq_lock, flags);
e039fa4a 2431 err = b43legacy_pio_tx(dev, skb);
75388acd
LF		 2432 spin_unlock_irqrestore(&wl->irq_lock, flags);
2433 } else
e039fa4a 2434 err = b43legacy_dma_tx(dev, skb);
75388acd 2435out:
664f2006
MB		 2436 if (unlikely(err)) {
2437 /* Drop the packet. */
2438 dev_kfree_skb_any(skb);
2439 }
75388acd
LF		 2440 return NETDEV_TX_OK;
2441}
2442
e100bb64 2443static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
33a3dc93 2444 const struct ieee80211_tx_queue_params *params)
75388acd
LF		 2445{
2446 return 0;
2447}
2448
33a3dc93
SB		 2449static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
2450 struct ieee80211_tx_queue_stats *stats)
75388acd
LF		 2451{
2452 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2453 struct b43legacy_wldev *dev = wl->current_dev;
2454 unsigned long flags;
2455 int err = -ENODEV;
2456
2457 if (!dev)
2458 goto out;
2459 spin_lock_irqsave(&wl->irq_lock, flags);
2460 if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
2461 if (b43legacy_using_pio(dev))
2462 b43legacy_pio_get_tx_stats(dev, stats);
2463 else
2464 b43legacy_dma_get_tx_stats(dev, stats);
2465 err = 0;
2466 }
2467 spin_unlock_irqrestore(&wl->irq_lock, flags);
2468out:
2469 return err;
2470}
2471
33a3dc93
SB		 2472static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2473 struct ieee80211_low_level_stats *stats)
75388acd
LF		 2474{
2475 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2476 unsigned long flags;
2477
2478 spin_lock_irqsave(&wl->irq_lock, flags);
2479 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2480 spin_unlock_irqrestore(&wl->irq_lock, flags);
2481
2482 return 0;
2483}
2484
2485static const char *phymode_to_string(unsigned int phymode)
2486{
2487 switch (phymode) {
2488 case B43legacy_PHYMODE_B:
2489 return "B";
2490 case B43legacy_PHYMODE_G:
2491 return "G";
2492 default:
2493 B43legacy_BUG_ON(1);
2494 }
2495 return "";
2496}
2497
2498static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2499 unsigned int phymode,
2500 struct b43legacy_wldev **dev,
2501 bool *gmode)
2502{
2503 struct b43legacy_wldev *d;
2504
2505 list_for_each_entry(d, &wl->devlist, list) {
2506 if (d->phy.possible_phymodes & phymode) {
2507 /* Ok, this device supports the PHY-mode.
2508 * Set the gmode bit. */
2509 *gmode = 1;
2510 *dev = d;
2511
2512 return 0;
2513 }
2514 }
2515
2516 return -ESRCH;
2517}
2518
2519static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2520{
2521 struct ssb_device *sdev = dev->dev;
2522 u32 tmslow;
2523
2524 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2525 tmslow &= ~B43legacy_TMSLOW_GMODE;
2526 tmslow |= B43legacy_TMSLOW_PHYRESET;
2527 tmslow |= SSB_TMSLOW_FGC;
2528 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2529 msleep(1);
2530
2531 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2532 tmslow &= ~SSB_TMSLOW_FGC;
2533 tmslow |= B43legacy_TMSLOW_PHYRESET;
2534 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2535 msleep(1);
2536}
2537
2538/* Expects wl->mutex locked */
2539static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2540 unsigned int new_mode)
2541{
08cb7e01 2542 struct b43legacy_wldev *uninitialized_var(up_dev);
75388acd
LF		 2543 struct b43legacy_wldev *down_dev;
2544 int err;
2545 bool gmode = 0;
2546 int prev_status;
2547
2548 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2549 if (err) {
2550 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2551 phymode_to_string(new_mode));
2552 return err;
2553 }
2554 if ((up_dev == wl->current_dev) &&
2555 (!!wl->current_dev->phy.gmode == !!gmode))
2556 /* This device is already running. */
2557 return 0;
2558 b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2559 phymode_to_string(new_mode));
2560 down_dev = wl->current_dev;
2561
2562 prev_status = b43legacy_status(down_dev);
2563 /* Shutdown the currently running core. */
2564 if (prev_status >= B43legacy_STAT_STARTED)
2565 b43legacy_wireless_core_stop(down_dev);
2566 if (prev_status >= B43legacy_STAT_INITIALIZED)
2567 b43legacy_wireless_core_exit(down_dev);
2568
2569 if (down_dev != up_dev)
2570 /* We switch to a different core, so we put PHY into
2571 * RESET on the old core. */
2572 b43legacy_put_phy_into_reset(down_dev);
2573
2574 /* Now start the new core. */
2575 up_dev->phy.gmode = gmode;
2576 if (prev_status >= B43legacy_STAT_INITIALIZED) {
2577 err = b43legacy_wireless_core_init(up_dev);
2578 if (err) {
2579 b43legacyerr(wl, "Fatal: Could not initialize device"
2580 " for newly selected %s-PHY mode\n",
2581 phymode_to_string(new_mode));
2582 goto init_failure;
2583 }
2584 }
2585 if (prev_status >= B43legacy_STAT_STARTED) {
2586 err = b43legacy_wireless_core_start(up_dev);
2587 if (err) {
2588 b43legacyerr(wl, "Fatal: Coult not start device for "
2589 "newly selected %s-PHY mode\n",
2590 phymode_to_string(new_mode));
2591 b43legacy_wireless_core_exit(up_dev);
2592 goto init_failure;
2593 }
2594 }
2595 B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2596
2597 b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2598
2599 wl->current_dev = up_dev;
2600
2601 return 0;
2602init_failure:
2603 /* Whoops, failed to init the new core. No core is operating now. */
2604 wl->current_dev = NULL;
2605 return err;
2606}
2607
9124b077
JB		 2608/* Write the short and long frame retry limit values. */
2609static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2610 unsigned int short_retry,
2611 unsigned int long_retry)
2612{
2613 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2614 * the chip-internal counter. */
2615 short_retry = min(short_retry, (unsigned int)0xF);
2616 long_retry = min(long_retry, (unsigned int)0xF);
2617
2618 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2619 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2620}
2621
33a3dc93 2622static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
e8975581 2623 u32 changed)
75388acd
LF		 2624{
2625 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2626 struct b43legacy_wldev *dev;
2627 struct b43legacy_phy *phy;
e8975581 2628 struct ieee80211_conf *conf = &hw->conf;
75388acd
LF		 2629 unsigned long flags;
2630 unsigned int new_phymode = 0xFFFF;
2631 int antenna_tx;
2632 int antenna_rx;
2633 int err = 0;
75388acd 2634
0f4ac38b
JB		 2635 antenna_tx = B43legacy_ANTENNA_DEFAULT;
2636 antenna_rx = B43legacy_ANTENNA_DEFAULT;
75388acd
LF		 2637
2638 mutex_lock(&wl->mutex);
8318d78a
JB		 2639 dev = wl->current_dev;
2640 phy = &dev->phy;
75388acd 2641
9124b077
JB		 2642 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2643 b43legacy_set_retry_limits(dev,
2644 conf->short_frame_max_tx_count,
2645 conf->long_frame_max_tx_count);
2646 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2647 if (!changed)
2648 goto out_unlock_mutex;
2649
75388acd 2650 /* Switch the PHY mode (if necessary). */
8318d78a
JB		 2651 switch (conf->channel->band) {
2652 case IEEE80211_BAND_2GHZ:
2653 if (phy->type == B43legacy_PHYTYPE_B)
2654 new_phymode = B43legacy_PHYMODE_B;
2655 else
2656 new_phymode = B43legacy_PHYMODE_G;
75388acd
LF		 2657 break;
2658 default:
2659 B43legacy_WARN_ON(1);
2660 }
2661 err = b43legacy_switch_phymode(wl, new_phymode);
2662 if (err)
2663 goto out_unlock_mutex;
75388acd
LF		 2664
2665 /* Disable IRQs while reconfiguring the device.
2666 * This makes it possible to drop the spinlock throughout
2667 * the reconfiguration process. */
2668 spin_lock_irqsave(&wl->irq_lock, flags);
2669 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2670 spin_unlock_irqrestore(&wl->irq_lock, flags);
2671 goto out_unlock_mutex;
2672 }
44710bbc 2673 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
75388acd
LF		 2674 spin_unlock_irqrestore(&wl->irq_lock, flags);
2675 b43legacy_synchronize_irq(dev);
2676
2677 /* Switch to the requested channel.
2678 * The firmware takes care of races with the TX handler. */
8318d78a
JB		 2679 if (conf->channel->hw_value != phy->channel)
2680 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
75388acd 2681
0869aea0 2682 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
5be3bda8 2683
75388acd
LF		 2684 /* Adjust the desired TX power level. */
2685 if (conf->power_level != 0) {
2686 if (conf->power_level != phy->power_level) {
2687 phy->power_level = conf->power_level;
2688 b43legacy_phy_xmitpower(dev);
2689 }
2690 }
2691
2692 /* Antennas for RX and management frame TX. */
2693 b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2694
fd4973c5
LF		 2695 if (wl->radio_enabled != phy->radio_on) {
2696 if (wl->radio_enabled) {
42a9174f
LF		 2697 b43legacy_radio_turn_on(dev);
2698 b43legacyinfo(dev->wl, "Radio turned on by software\n");
2699 if (!dev->radio_hw_enable)
2700 b43legacyinfo(dev->wl, "The hardware RF-kill"
2701 " button still turns the radio"
2702 " physically off. Press the"
2703 " button to turn it on.\n");
2704 } else {
93bb7f3a 2705 b43legacy_radio_turn_off(dev, 0);
42a9174f
LF		 2706 b43legacyinfo(dev->wl, "Radio turned off by"
2707 " software\n");
2708 }
2709 }
2710
75388acd 2711 spin_lock_irqsave(&wl->irq_lock, flags);
44710bbc 2712 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
75388acd
LF		 2713 mmiowb();
2714 spin_unlock_irqrestore(&wl->irq_lock, flags);
2715out_unlock_mutex:
2716 mutex_unlock(&wl->mutex);
2717
2718 return err;
2719}
2720
881d948c 2721static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
7f3704e9
JB		 2722{
2723 struct ieee80211_supported_band *sband =
2724 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2725 struct ieee80211_rate *rate;
2726 int i;
2727 u16 basic, direct, offset, basic_offset, rateptr;
2728
2729 for (i = 0; i < sband->n_bitrates; i++) {
2730 rate = &sband->bitrates[i];
2731
2732 if (b43legacy_is_cck_rate(rate->hw_value)) {
2733 direct = B43legacy_SHM_SH_CCKDIRECT;
2734 basic = B43legacy_SHM_SH_CCKBASIC;
2735 offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2736 offset &= 0xF;
2737 } else {
2738 direct = B43legacy_SHM_SH_OFDMDIRECT;
2739 basic = B43legacy_SHM_SH_OFDMBASIC;
2740 offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2741 offset &= 0xF;
2742 }
2743
2744 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2745
2746 if (b43legacy_is_cck_rate(rate->hw_value)) {
2747 basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2748 basic_offset &= 0xF;
2749 } else {
2750 basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2751 basic_offset &= 0xF;
2752 }
2753
2754 /*
2755 * Get the pointer that we need to point to
2756 * from the direct map
2757 */
2758 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2759 direct + 2 * basic_offset);
2760 /* and write it to the basic map */
2761 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2762 basic + 2 * offset, rateptr);
2763 }
2764}
2765
2766static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2767 struct ieee80211_vif *vif,
2768 struct ieee80211_bss_conf *conf,
2769 u32 changed)
2770{
2771 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2772 struct b43legacy_wldev *dev;
2773 struct b43legacy_phy *phy;
2774 unsigned long flags;
7f3704e9
JB		 2775
2776 mutex_lock(&wl->mutex);
2d0ddec5 2777 B43legacy_WARN_ON(wl->vif != vif);
7f3704e9
JB		 2778
2779 dev = wl->current_dev;
2780 phy = &dev->phy;
2781
2782 /* Disable IRQs while reconfiguring the device.
2783 * This makes it possible to drop the spinlock throughout
2784 * the reconfiguration process. */
2785 spin_lock_irqsave(&wl->irq_lock, flags);
2786 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2787 spin_unlock_irqrestore(&wl->irq_lock, flags);
2788 goto out_unlock_mutex;
2789 }
44710bbc 2790 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2d0ddec5
JB		 2791
2792 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 2793 b43legacy_synchronize_irq(dev);
2794
2795 if (conf->bssid)
2796 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2797 else
2798 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b
JB		 2799 }
2800
2801 if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2802 if (changed & BSS_CHANGED_BEACON &&
2803 (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2804 b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2805 b43legacy_update_templates(wl);
2d0ddec5 2806
3f0d843b 2807 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 2808 b43legacy_write_mac_bssid_templates(dev);
2d0ddec5 2809 }
3f0d843b 2810 spin_unlock_irqrestore(&wl->irq_lock, flags);
7f3704e9
JB		 2811
2812 b43legacy_mac_suspend(dev);
2813
57c4d7b4
JB		 2814 if (changed & BSS_CHANGED_BEACON_INT &&
2815 (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2816 b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2817 b43legacy_set_beacon_int(dev, conf->beacon_int);
2818
7f3704e9
JB		 2819 if (changed & BSS_CHANGED_BASIC_RATES)
2820 b43legacy_update_basic_rates(dev, conf->basic_rates);
2821
2822 if (changed & BSS_CHANGED_ERP_SLOT) {
2823 if (conf->use_short_slot)
2824 b43legacy_short_slot_timing_enable(dev);
2825 else
2826 b43legacy_short_slot_timing_disable(dev);
2827 }
2828
2829 b43legacy_mac_enable(dev);
2830
2831 spin_lock_irqsave(&wl->irq_lock, flags);
44710bbc 2832 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
7f3704e9
JB		 2833 /* XXX: why? */
2834 mmiowb();
2835 spin_unlock_irqrestore(&wl->irq_lock, flags);
2836 out_unlock_mutex:
2837 mutex_unlock(&wl->mutex);
7f3704e9
JB		 2838}
2839
33a3dc93
SB		 2840static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2841 unsigned int changed,
3ac64bee 2842 unsigned int *fflags,u64 multicast)
75388acd
LF		 2843{
2844 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2845 struct b43legacy_wldev *dev = wl->current_dev;
2846 unsigned long flags;
2847
4150c572
JB		 2848 if (!dev) {
2849 *fflags = 0;
75388acd 2850 return;
75388acd 2851 }
4150c572
JB		 2852
2853 spin_lock_irqsave(&wl->irq_lock, flags);
2854 *fflags &= FIF_PROMISC_IN_BSS |
2855 FIF_ALLMULTI |
2856 FIF_FCSFAIL |
2857 FIF_PLCPFAIL |
2858 FIF_CONTROL |
2859 FIF_OTHER_BSS |
2860 FIF_BCN_PRBRESP_PROMISC;
2861
2862 changed &= FIF_PROMISC_IN_BSS |
2863 FIF_ALLMULTI |
2864 FIF_FCSFAIL |
2865 FIF_PLCPFAIL |
2866 FIF_CONTROL |
2867 FIF_OTHER_BSS |
2868 FIF_BCN_PRBRESP_PROMISC;
2869
2870 wl->filter_flags = *fflags;
2871
2872 if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2873 b43legacy_adjust_opmode(dev);
75388acd
LF		 2874 spin_unlock_irqrestore(&wl->irq_lock, flags);
2875}
2876
75388acd
LF		 2877/* Locking: wl->mutex */
2878static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2879{
2880 struct b43legacy_wl *wl = dev->wl;
2881 unsigned long flags;
2882
2883 if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2884 return;
440cb58a
SB		 2885
2886 /* Disable and sync interrupts. We must do this before than
2887 * setting the status to INITIALIZED, as the interrupt handler
2888 * won't care about IRQs then. */
2889 spin_lock_irqsave(&wl->irq_lock, flags);
44710bbc 2890 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
440cb58a
SB		 2891 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2892 spin_unlock_irqrestore(&wl->irq_lock, flags);
2893 b43legacy_synchronize_irq(dev);
2894
75388acd
LF		 2895 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2896
2897 mutex_unlock(&wl->mutex);
2898 /* Must unlock as it would otherwise deadlock. No races here.
2899 * Cancel the possibly running self-rearming periodic work. */
2900 cancel_delayed_work_sync(&dev->periodic_work);
2901 mutex_lock(&wl->mutex);
2902
2903 ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2904
75388acd
LF		 2905 b43legacy_mac_suspend(dev);
2906 free_irq(dev->dev->irq, dev);
2907 b43legacydbg(wl, "Wireless interface stopped\n");
2908}
2909
2910/* Locking: wl->mutex */
2911static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2912{
2913 int err;
2914
2915 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2916
2917 drain_txstatus_queue(dev);
2918 err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2919 IRQF_SHARED, KBUILD_MODNAME, dev);
2920 if (err) {
2921 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2922 dev->dev->irq);
2923 goto out;
2924 }
2925 /* We are ready to run. */
0866b03c 2926 ieee80211_wake_queues(dev->wl->hw);
75388acd
LF		 2927 b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2928
2929 /* Start data flow (TX/RX) */
2930 b43legacy_mac_enable(dev);
44710bbc 2931 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
75388acd
LF		 2932
2933 /* Start maintenance work */
2934 b43legacy_periodic_tasks_setup(dev);
2935
2936 b43legacydbg(dev->wl, "Wireless interface started\n");
2937out:
2938 return err;
2939}
2940
2941/* Get PHY and RADIO versioning numbers */
2942static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2943{
2944 struct b43legacy_phy *phy = &dev->phy;
2945 u32 tmp;
2946 u8 analog_type;
2947 u8 phy_type;
2948 u8 phy_rev;
2949 u16 radio_manuf;
2950 u16 radio_ver;
2951 u16 radio_rev;
2952 int unsupported = 0;
2953
2954 /* Get PHY versioning */
2955 tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2956 analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2957 >> B43legacy_PHYVER_ANALOG_SHIFT;
2958 phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2959 phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2960 switch (phy_type) {
2961 case B43legacy_PHYTYPE_B:
2962 if (phy_rev != 2 && phy_rev != 4
2963 && phy_rev != 6 && phy_rev != 7)
2964 unsupported = 1;
2965 break;
2966 case B43legacy_PHYTYPE_G:
2967 if (phy_rev > 8)
2968 unsupported = 1;
2969 break;
2970 default:
2971 unsupported = 1;
2972 };
2973 if (unsupported) {
2974 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2975 "(Analog %u, Type %u, Revision %u)\n",
2976 analog_type, phy_type, phy_rev);
2977 return -EOPNOTSUPP;
2978 }
2979 b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2980 analog_type, phy_type, phy_rev);
2981
2982
2983 /* Get RADIO versioning */
2984 if (dev->dev->bus->chip_id == 0x4317) {
2985 if (dev->dev->bus->chip_rev == 0)
2986 tmp = 0x3205017F;
2987 else if (dev->dev->bus->chip_rev == 1)
2988 tmp = 0x4205017F;
2989 else
2990 tmp = 0x5205017F;
2991 } else {
2992 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2993 B43legacy_RADIOCTL_ID);
2994 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
2995 tmp <<= 16;
2996 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2997 B43legacy_RADIOCTL_ID);
2998 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
2999 }
3000 radio_manuf = (tmp & 0x00000FFF);
3001 radio_ver = (tmp & 0x0FFFF000) >> 12;
3002 radio_rev = (tmp & 0xF0000000) >> 28;
3003 switch (phy_type) {
3004 case B43legacy_PHYTYPE_B:
3005 if ((radio_ver & 0xFFF0) != 0x2050)
3006 unsupported = 1;
3007 break;
3008 case B43legacy_PHYTYPE_G:
3009 if (radio_ver != 0x2050)
3010 unsupported = 1;
3011 break;
3012 default:
3013 B43legacy_BUG_ON(1);
3014 }
3015 if (unsupported) {
3016 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
3017 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3018 radio_manuf, radio_ver, radio_rev);
3019 return -EOPNOTSUPP;
3020 }
3021 b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
3022 " Revision %u\n", radio_manuf, radio_ver, radio_rev);
3023
3024
3025 phy->radio_manuf = radio_manuf;
3026 phy->radio_ver = radio_ver;
3027 phy->radio_rev = radio_rev;
3028
3029 phy->analog = analog_type;
3030 phy->type = phy_type;
3031 phy->rev = phy_rev;
3032
3033 return 0;
3034}
3035
3036static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
3037 struct b43legacy_phy *phy)
3038{
3039 struct b43legacy_lopair *lo;
3040 int i;
3041
3042 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3043 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3044
1065de15
LF		 3045 /* Assume the radio is enabled. If it's not enabled, the state will
3046 * immediately get fixed on the first periodic work run. */
3047 dev->radio_hw_enable = 1;
75388acd
LF		 3048
3049 phy->savedpctlreg = 0xFFFF;
3050 phy->aci_enable = 0;
3051 phy->aci_wlan_automatic = 0;
3052 phy->aci_hw_rssi = 0;
3053
3054 lo = phy->_lo_pairs;
3055 if (lo)
3056 memset(lo, 0, sizeof(struct b43legacy_lopair) *
3057 B43legacy_LO_COUNT);
3058 phy->max_lb_gain = 0;
3059 phy->trsw_rx_gain = 0;
3060
3061 /* Set default attenuation values. */
3062 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3063 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3064 phy->txctl1 = b43legacy_default_txctl1(dev);
3065 phy->txpwr_offset = 0;
3066
3067 /* NRSSI */
3068 phy->nrssislope = 0;
3069 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3070 phy->nrssi[i] = -1000;
3071 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3072 phy->nrssi_lt[i] = i;
3073
3074 phy->lofcal = 0xFFFF;
3075 phy->initval = 0xFFFF;
3076
75388acd
LF		 3077 phy->interfmode = B43legacy_INTERFMODE_NONE;
3078 phy->channel = 0xFF;
3079}
3080
3081static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
3082{
3083 /* Flags */
eed0fd21 3084 dev->dfq_valid = 0;
75388acd
LF		 3085
3086 /* Stats */
3087 memset(&dev->stats, 0, sizeof(dev->stats));
3088
3089 setup_struct_phy_for_init(dev, &dev->phy);
3090
3091 /* IRQ related flags */
3092 dev->irq_reason = 0;
3093 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
44710bbc 3094 dev->irq_mask = B43legacy_IRQ_MASKTEMPLATE;
75388acd
LF		 3095
3096 dev->mac_suspended = 1;
3097
3098 /* Noise calculation context */
3099 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3100}
3101
3102static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
3103{
3104#ifdef CONFIG_SSB_DRIVER_PCICORE
3105 struct ssb_bus *bus = dev->dev->bus;
3106 u32 tmp;
3107
3108 if (bus->pcicore.dev &&
3109 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3110 bus->pcicore.dev->id.revision <= 5) {
3111 /* IMCFGLO timeouts workaround. */
3112 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
75388acd
LF		 3113 switch (bus->bustype) {
3114 case SSB_BUSTYPE_PCI:
3115 case SSB_BUSTYPE_PCMCIA:
98a1e2a9
MB		 3116 tmp &= ~SSB_IMCFGLO_REQTO;
3117 tmp &= ~SSB_IMCFGLO_SERTO;
75388acd
LF		 3118 tmp |= 0x32;
3119 break;
3120 case SSB_BUSTYPE_SSB:
98a1e2a9
MB		 3121 tmp &= ~SSB_IMCFGLO_REQTO;
3122 tmp &= ~SSB_IMCFGLO_SERTO;
75388acd
LF		 3123 tmp |= 0x53;
3124 break;
98a1e2a9
MB		 3125 default:
3126 break;
75388acd
LF		 3127 }
3128 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3129 }
3130#endif /* CONFIG_SSB_DRIVER_PCICORE */
3131}
3132
3e2c40ef
SB		 3133static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,
3134 bool idle) {
3135 u16 pu_delay = 1050;
3136
05c914fe 3137 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3e2c40ef
SB		 3138 pu_delay = 500;
3139 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3140 pu_delay = max(pu_delay, (u16)2400);
3141
3142 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3143 B43legacy_SHM_SH_SPUWKUP, pu_delay);
3144}
3145
3146/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3147static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev)
3148{
3149 u16 pretbtt;
3150
3151 /* The time value is in microseconds. */
05c914fe 3152 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3e2c40ef
SB		 3153 pretbtt = 2;
3154 else
3155 pretbtt = 250;
3156 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3157 B43legacy_SHM_SH_PRETBTT, pretbtt);
3158 b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt);
3159}
3160
75388acd
LF		 3161/* Shutdown a wireless core */
3162/* Locking: wl->mutex */
3163static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
3164{
75388acd 3165 struct b43legacy_phy *phy = &dev->phy;
e78c9d28 3166 u32 macctl;
75388acd
LF		 3167
3168 B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
3169 if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
3170 return;
3171 b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3172
e78c9d28
SB		 3173 /* Stop the microcode PSM. */
3174 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3175 macctl &= ~B43legacy_MACCTL_PSM_RUN;
3176 macctl |= B43legacy_MACCTL_PSM_JMP0;
3177 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3178
4ad36d78 3179 b43legacy_leds_exit(dev);
75388acd
LF		 3180 b43legacy_rng_exit(dev->wl);
3181 b43legacy_pio_free(dev);
3182 b43legacy_dma_free(dev);
3183 b43legacy_chip_exit(dev);
93bb7f3a 3184 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 3185 b43legacy_switch_analog(dev, 0);
3186 if (phy->dyn_tssi_tbl)
3187 kfree(phy->tssi2dbm);
3188 kfree(phy->lo_control);
3189 phy->lo_control = NULL;
a297170d
SB		 3190 if (dev->wl->current_beacon) {
3191 dev_kfree_skb_any(dev->wl->current_beacon);
3192 dev->wl->current_beacon = NULL;
3193 }
3194
75388acd
LF		 3195 ssb_device_disable(dev->dev, 0);
3196 ssb_bus_may_powerdown(dev->dev->bus);
3197}
3198
3199static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3200{
3201 struct b43legacy_phy *phy = &dev->phy;
3202 int i;
3203
3204 /* Set default attenuation values. */
3205 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3206 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3207 phy->txctl1 = b43legacy_default_txctl1(dev);
3208 phy->txctl2 = 0xFFFF;
3209 phy->txpwr_offset = 0;
3210
3211 /* NRSSI */
3212 phy->nrssislope = 0;
3213 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3214 phy->nrssi[i] = -1000;
3215 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3216 phy->nrssi_lt[i] = i;
3217
3218 phy->lofcal = 0xFFFF;
3219 phy->initval = 0xFFFF;
3220
3221 phy->aci_enable = 0;
3222 phy->aci_wlan_automatic = 0;
3223 phy->aci_hw_rssi = 0;
3224
3225 phy->antenna_diversity = 0xFFFF;
3226 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3227 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3228
3229 /* Flags */
3230 phy->calibrated = 0;
75388acd
LF		 3231
3232 if (phy->_lo_pairs)
3233 memset(phy->_lo_pairs, 0,
3234 sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3235 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3236}
3237
3238/* Initialize a wireless core */
3239static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3240{
3241 struct b43legacy_wl *wl = dev->wl;
3242 struct ssb_bus *bus = dev->dev->bus;
3243 struct b43legacy_phy *phy = &dev->phy;
3244 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3245 int err;
3246 u32 hf;
3247 u32 tmp;
3248
3249 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3250
3251 err = ssb_bus_powerup(bus, 0);
3252 if (err)
3253 goto out;
3254 if (!ssb_device_is_enabled(dev->dev)) {
3255 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3256 b43legacy_wireless_core_reset(dev, tmp);
3257 }
3258
3259 if ((phy->type == B43legacy_PHYTYPE_B) ||
3260 (phy->type == B43legacy_PHYTYPE_G)) {
3261 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3262 * B43legacy_LO_COUNT,
3263 GFP_KERNEL);
3264 if (!phy->_lo_pairs)
3265 return -ENOMEM;
3266 }
3267 setup_struct_wldev_for_init(dev);
3268
3269 err = b43legacy_phy_init_tssi2dbm_table(dev);
3270 if (err)
3271 goto err_kfree_lo_control;
3272
3273 /* Enable IRQ routing to this device. */
3274 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3275
3276 b43legacy_imcfglo_timeouts_workaround(dev);
3277 prepare_phy_data_for_init(dev);
3278 b43legacy_phy_calibrate(dev);
3279 err = b43legacy_chip_init(dev);
3280 if (err)
3281 goto err_kfree_tssitbl;
3282 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3283 B43legacy_SHM_SH_WLCOREREV,
3284 dev->dev->id.revision);
3285 hf = b43legacy_hf_read(dev);
3286 if (phy->type == B43legacy_PHYTYPE_G) {
3287 hf |= B43legacy_HF_SYMW;
3288 if (phy->rev == 1)
3289 hf |= B43legacy_HF_GDCW;
7797aa38 3290 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
75388acd
LF		 3291 hf |= B43legacy_HF_OFDMPABOOST;
3292 } else if (phy->type == B43legacy_PHYTYPE_B) {
3293 hf |= B43legacy_HF_SYMW;
3294 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3295 hf &= ~B43legacy_HF_GDCW;
3296 }
3297 b43legacy_hf_write(dev, hf);
3298
0a6e1bee
SB		 3299 b43legacy_set_retry_limits(dev,
3300 B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3301 B43legacy_DEFAULT_LONG_RETRY_LIMIT);
75388acd
LF		 3302
3303 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3304 0x0044, 3);
3305 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3306 0x0046, 2);
3307
3308 /* Disable sending probe responses from firmware.
3309 * Setting the MaxTime to one usec will always trigger
3310 * a timeout, so we never send any probe resp.
3311 * A timeout of zero is infinite. */
3312 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3313 B43legacy_SHM_SH_PRMAXTIME, 1);
3314
3315 b43legacy_rate_memory_init(dev);
3316
3317 /* Minimum Contention Window */
3318 if (phy->type == B43legacy_PHYTYPE_B)
3319 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3320 0x0003, 31);
3321 else
3322 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3323 0x0003, 15);
3324 /* Maximum Contention Window */
3325 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3326 0x0004, 1023);
3327
3328 do {
3329 if (b43legacy_using_pio(dev))
3330 err = b43legacy_pio_init(dev);
3331 else {
3332 err = b43legacy_dma_init(dev);
3333 if (!err)
3334 b43legacy_qos_init(dev);
3335 }
3336 } while (err == -EAGAIN);
3337 if (err)
3338 goto err_chip_exit;
3339
3e2c40ef 3340 b43legacy_set_synth_pu_delay(dev, 1);
75388acd
LF		 3341
3342 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4150c572 3343 b43legacy_upload_card_macaddress(dev);
75388acd
LF		 3344 b43legacy_security_init(dev);
3345 b43legacy_rng_init(wl);
3346
0866b03c 3347 ieee80211_wake_queues(dev->wl->hw);
75388acd
LF		 3348 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3349
4ad36d78 3350 b43legacy_leds_init(dev);
75388acd
LF		 3351out:
3352 return err;
3353
3354err_chip_exit:
3355 b43legacy_chip_exit(dev);
3356err_kfree_tssitbl:
3357 if (phy->dyn_tssi_tbl)
3358 kfree(phy->tssi2dbm);
3359err_kfree_lo_control:
3360 kfree(phy->lo_control);
3361 phy->lo_control = NULL;
3362 ssb_bus_may_powerdown(bus);
3363 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3364 return err;
3365}
3366
33a3dc93 3367static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 3368 struct ieee80211_vif *vif)
75388acd
LF		 3369{
3370 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3371 struct b43legacy_wldev *dev;
3372 unsigned long flags;
3373 int err = -EOPNOTSUPP;
4150c572
JB		 3374
3375 /* TODO: allow WDS/AP devices to coexist */
3376
1ed32e4f
JB		 3377 if (vif->type != NL80211_IFTYPE_AP &&
3378 vif->type != NL80211_IFTYPE_STATION &&
3379 vif->type != NL80211_IFTYPE_WDS &&
3380 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 3381 return -EOPNOTSUPP;
75388acd
LF		 3382
3383 mutex_lock(&wl->mutex);
4150c572 3384 if (wl->operating)
75388acd
LF		 3385 goto out_mutex_unlock;
3386
1ed32e4f 3387 b43legacydbg(wl, "Adding Interface type %d\n", vif->type);
75388acd
LF		 3388
3389 dev = wl->current_dev;
4150c572 3390 wl->operating = 1;
1ed32e4f
JB		 3391 wl->vif = vif;
3392 wl->if_type = vif->type;
3393 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572
JB		 3394
3395 spin_lock_irqsave(&wl->irq_lock, flags);
3396 b43legacy_adjust_opmode(dev);
3e2c40ef
SB		 3397 b43legacy_set_pretbtt(dev);
3398 b43legacy_set_synth_pu_delay(dev, 0);
4150c572
JB		 3399 b43legacy_upload_card_macaddress(dev);
3400 spin_unlock_irqrestore(&wl->irq_lock, flags);
3401
3402 err = 0;
3403 out_mutex_unlock:
3404 mutex_unlock(&wl->mutex);
3405
3406 return err;
3407}
3408
33a3dc93 3409static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3410 struct ieee80211_vif *vif)
4150c572
JB		 3411{
3412 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3413 struct b43legacy_wldev *dev = wl->current_dev;
3414 unsigned long flags;
3415
1ed32e4f 3416 b43legacydbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 3417
3418 mutex_lock(&wl->mutex);
3419
3420 B43legacy_WARN_ON(!wl->operating);
1ed32e4f 3421 B43legacy_WARN_ON(wl->vif != vif);
32bfd35d 3422 wl->vif = NULL;
4150c572
JB		 3423
3424 wl->operating = 0;
3425
3426 spin_lock_irqsave(&wl->irq_lock, flags);
3427 b43legacy_adjust_opmode(dev);
3428 memset(wl->mac_addr, 0, ETH_ALEN);
3429 b43legacy_upload_card_macaddress(dev);
3430 spin_unlock_irqrestore(&wl->irq_lock, flags);
3431
3432 mutex_unlock(&wl->mutex);
3433}
3434
33a3dc93 3435static int b43legacy_op_start(struct ieee80211_hw *hw)
4150c572
JB		 3436{
3437 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3438 struct b43legacy_wldev *dev = wl->current_dev;
3439 int did_init = 0;
208eec88 3440 int err = 0;
4ad36d78 3441
ada50731
SB		 3442 /* Kill all old instance specific information to make sure
3443 * the card won't use it in the short timeframe between start
3444 * and mac80211 reconfiguring it. */
3445 memset(wl->bssid, 0, ETH_ALEN);
3446 memset(wl->mac_addr, 0, ETH_ALEN);
3447 wl->filter_flags = 0;
2d1f96dd
LF		 3448 wl->beacon0_uploaded = 0;
3449 wl->beacon1_uploaded = 0;
3450 wl->beacon_templates_virgin = 1;
fd4973c5 3451 wl->radio_enabled = 1;
ada50731 3452
4150c572
JB		 3453 mutex_lock(&wl->mutex);
3454
75388acd
LF		 3455 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
3456 err = b43legacy_wireless_core_init(dev);
f41f3f37 3457 if (err)
75388acd
LF		 3458 goto out_mutex_unlock;
3459 did_init = 1;
3460 }
4150c572 3461
75388acd
LF		 3462 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
3463 err = b43legacy_wireless_core_start(dev);
3464 if (err) {
3465 if (did_init)
3466 b43legacy_wireless_core_exit(dev);
3467 goto out_mutex_unlock;
3468 }
3469 }
3470
f41f3f37
JB		 3471 wiphy_rfkill_start_polling(hw->wiphy);
3472
75388acd
LF		 3473out_mutex_unlock:
3474 mutex_unlock(&wl->mutex);
3475
3476 return err;
3477}
3478
33a3dc93 3479static void b43legacy_op_stop(struct ieee80211_hw *hw)
75388acd
LF		 3480{
3481 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
4150c572 3482 struct b43legacy_wldev *dev = wl->current_dev;
75388acd 3483
7858e07b 3484 cancel_work_sync(&(wl->beacon_update_trigger));
4ad36d78 3485
75388acd 3486 mutex_lock(&wl->mutex);
4150c572
JB		 3487 if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
3488 b43legacy_wireless_core_stop(dev);
3489 b43legacy_wireless_core_exit(dev);
fd4973c5 3490 wl->radio_enabled = 0;
75388acd
LF		 3491 mutex_unlock(&wl->mutex);
3492}
3493
a297170d 3494static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw,
17741cdc 3495 struct ieee80211_sta *sta, bool set)
a297170d
SB		 3496{
3497 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3498 unsigned long flags;
3499
3500 spin_lock_irqsave(&wl->irq_lock, flags);
9d139c81 3501 b43legacy_update_templates(wl);
a297170d
SB		 3502 spin_unlock_irqrestore(&wl->irq_lock, flags);
3503
3504 return 0;
3505}
3506
75388acd 3507static const struct ieee80211_ops b43legacy_hw_ops = {
33a3dc93
SB		 3508 .tx = b43legacy_op_tx,
3509 .conf_tx = b43legacy_op_conf_tx,
3510 .add_interface = b43legacy_op_add_interface,
3511 .remove_interface = b43legacy_op_remove_interface,
3512 .config = b43legacy_op_dev_config,
7f3704e9 3513 .bss_info_changed = b43legacy_op_bss_info_changed,
33a3dc93
SB		 3514 .configure_filter = b43legacy_op_configure_filter,
3515 .get_stats = b43legacy_op_get_stats,
3516 .get_tx_stats = b43legacy_op_get_tx_stats,
3517 .start = b43legacy_op_start,
3518 .stop = b43legacy_op_stop,
a297170d 3519 .set_tim = b43legacy_op_beacon_set_tim,
f41f3f37 3520 .rfkill_poll = b43legacy_rfkill_poll,
75388acd
LF		 3521};
3522
3523/* Hard-reset the chip. Do not call this directly.
3524 * Use b43legacy_controller_restart()
3525 */
3526static void b43legacy_chip_reset(struct work_struct *work)
3527{
3528 struct b43legacy_wldev *dev =
3529 container_of(work, struct b43legacy_wldev, restart_work);
3530 struct b43legacy_wl *wl = dev->wl;
3531 int err = 0;
3532 int prev_status;
3533
3534 mutex_lock(&wl->mutex);
3535
3536 prev_status = b43legacy_status(dev);
3537 /* Bring the device down... */
3538 if (prev_status >= B43legacy_STAT_STARTED)
3539 b43legacy_wireless_core_stop(dev);
3540 if (prev_status >= B43legacy_STAT_INITIALIZED)
3541 b43legacy_wireless_core_exit(dev);
3542
3543 /* ...and up again. */
3544 if (prev_status >= B43legacy_STAT_INITIALIZED) {
3545 err = b43legacy_wireless_core_init(dev);
3546 if (err)
3547 goto out;
3548 }
3549 if (prev_status >= B43legacy_STAT_STARTED) {
3550 err = b43legacy_wireless_core_start(dev);
3551 if (err) {
3552 b43legacy_wireless_core_exit(dev);
3553 goto out;
3554 }
3555 }
3556out:
48e6c51b
MB		 3557 if (err)
3558 wl->current_dev = NULL; /* Failed to init the dev. */
75388acd
LF		 3559 mutex_unlock(&wl->mutex);
3560 if (err)
3561 b43legacyerr(wl, "Controller restart FAILED\n");
3562 else
3563 b43legacyinfo(wl, "Controller restarted\n");
3564}
3565
3566static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
3567 int have_bphy,
3568 int have_gphy)
3569{
3570 struct ieee80211_hw *hw = dev->wl->hw;
75388acd 3571 struct b43legacy_phy *phy = &dev->phy;
75388acd
LF		 3572
3573 phy->possible_phymodes = 0;
8318d78a
JB		 3574 if (have_bphy) {
3575 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3576 &b43legacy_band_2GHz_BPHY;
3577 phy->possible_phymodes |= B43legacy_PHYMODE_B;
3578 }
3579
3580 if (have_gphy) {
3581 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3582 &b43legacy_band_2GHz_GPHY;
3583 phy->possible_phymodes |= B43legacy_PHYMODE_G;
75388acd
LF		 3584 }
3585
3586 return 0;
3587}
3588
3589static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
3590{
3591 /* We release firmware that late to not be required to re-request
3592 * is all the time when we reinit the core. */
3593 b43legacy_release_firmware(dev);
3594}
3595
3596static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
3597{
3598 struct b43legacy_wl *wl = dev->wl;
3599 struct ssb_bus *bus = dev->dev->bus;
899110fe 3600 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
75388acd
LF		 3601 int err;
3602 int have_bphy = 0;
3603 int have_gphy = 0;
3604 u32 tmp;
3605
3606 /* Do NOT do any device initialization here.
3607 * Do it in wireless_core_init() instead.
3608 * This function is for gathering basic information about the HW, only.
3609 * Also some structs may be set up here. But most likely you want to
3610 * have that in core_init(), too.
3611 */
3612
3613 err = ssb_bus_powerup(bus, 0);
3614 if (err) {
3615 b43legacyerr(wl, "Bus powerup failed\n");
3616 goto out;
3617 }
3618 /* Get the PHY type. */
3619 if (dev->dev->id.revision >= 5) {
3620 u32 tmshigh;
3621
3622 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3623 have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
3624 if (!have_gphy)
3625 have_bphy = 1;
3626 } else if (dev->dev->id.revision == 4)
3627 have_gphy = 1;
3628 else
3629 have_bphy = 1;
3630
75388acd 3631 dev->phy.gmode = (have_gphy || have_bphy);
fd4973c5 3632 dev->phy.radio_on = 1;
75388acd
LF		 3633 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3634 b43legacy_wireless_core_reset(dev, tmp);
3635
3636 err = b43legacy_phy_versioning(dev);
3637 if (err)
ba48f7bb 3638 goto err_powerdown;
75388acd
LF		 3639 /* Check if this device supports multiband. */
3640 if (!pdev ||
3641 (pdev->device != 0x4312 &&
3642 pdev->device != 0x4319 &&
3643 pdev->device != 0x4324)) {
3644 /* No multiband support. */
3645 have_bphy = 0;
3646 have_gphy = 0;
3647 switch (dev->phy.type) {
3648 case B43legacy_PHYTYPE_B:
3649 have_bphy = 1;
3650 break;
3651 case B43legacy_PHYTYPE_G:
3652 have_gphy = 1;
3653 break;
3654 default:
3655 B43legacy_BUG_ON(1);
3656 }
3657 }
3658 dev->phy.gmode = (have_gphy || have_bphy);
3659 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3660 b43legacy_wireless_core_reset(dev, tmp);
3661
3662 err = b43legacy_validate_chipaccess(dev);
3663 if (err)
ba48f7bb 3664 goto err_powerdown;
75388acd
LF		 3665 err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
3666 if (err)
ba48f7bb 3667 goto err_powerdown;
75388acd
LF		 3668
3669 /* Now set some default "current_dev" */
3670 if (!wl->current_dev)
3671 wl->current_dev = dev;
3672 INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
3673
93bb7f3a 3674 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 3675 b43legacy_switch_analog(dev, 0);
3676 ssb_device_disable(dev->dev, 0);
3677 ssb_bus_may_powerdown(bus);
3678
3679out:
3680 return err;
3681
75388acd
LF		 3682err_powerdown:
3683 ssb_bus_may_powerdown(bus);
3684 return err;
3685}
3686
3687static void b43legacy_one_core_detach(struct ssb_device *dev)
3688{
3689 struct b43legacy_wldev *wldev;
3690 struct b43legacy_wl *wl;
3691
48e6c51b
MB		 3692 /* Do not cancel ieee80211-workqueue based work here.
3693 * See comment in b43legacy_remove(). */
3694
75388acd
LF		 3695 wldev = ssb_get_drvdata(dev);
3696 wl = wldev->wl;
75388acd
LF		 3697 b43legacy_debugfs_remove_device(wldev);
3698 b43legacy_wireless_core_detach(wldev);
3699 list_del(&wldev->list);
3700 wl->nr_devs--;
3701 ssb_set_drvdata(dev, NULL);
3702 kfree(wldev);
3703}
3704
3705static int b43legacy_one_core_attach(struct ssb_device *dev,
3706 struct b43legacy_wl *wl)
3707{
3708 struct b43legacy_wldev *wldev;
3709 struct pci_dev *pdev;
3710 int err = -ENOMEM;
3711
3712 if (!list_empty(&wl->devlist)) {
3713 /* We are not the first core on this chip. */
899110fe 3714 pdev = (dev->bus->bustype == SSB_BUSTYPE_PCI) ? dev->bus->host_pci : NULL;
75388acd
LF		 3715 /* Only special chips support more than one wireless
3716 * core, although some of the other chips have more than
3717 * one wireless core as well. Check for this and
3718 * bail out early.
3719 */
3720 if (!pdev ||
3721 ((pdev->device != 0x4321) &&
3722 (pdev->device != 0x4313) &&
3723 (pdev->device != 0x431A))) {
3724 b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
3725 return -ENODEV;
3726 }
3727 }
3728
3729 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3730 if (!wldev)
3731 goto out;
3732
3733 wldev->dev = dev;
3734 wldev->wl = wl;
3735 b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
3736 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3737 tasklet_init(&wldev->isr_tasklet,
3738 (void (*)(unsigned long))b43legacy_interrupt_tasklet,
3739 (unsigned long)wldev);
3740 if (modparam_pio)
3741 wldev->__using_pio = 1;
3742 INIT_LIST_HEAD(&wldev->list);
3743
3744 err = b43legacy_wireless_core_attach(wldev);
3745 if (err)
3746 goto err_kfree_wldev;
3747
3748 list_add(&wldev->list, &wl->devlist);
3749 wl->nr_devs++;
3750 ssb_set_drvdata(dev, wldev);
3751 b43legacy_debugfs_add_device(wldev);
3752out:
3753 return err;
3754
3755err_kfree_wldev:
3756 kfree(wldev);
3757 return err;
3758}
3759
3760static void b43legacy_sprom_fixup(struct ssb_bus *bus)
3761{
3762 /* boardflags workarounds */
3763 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3764 bus->boardinfo.type == 0x4E &&
3765 bus->boardinfo.rev > 0x40)
7797aa38 3766 bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
75388acd
LF		 3767}
3768
3769static void b43legacy_wireless_exit(struct ssb_device *dev,
3770 struct b43legacy_wl *wl)
3771{
3772 struct ieee80211_hw *hw = wl->hw;
3773
3774 ssb_set_devtypedata(dev, NULL);
3775 ieee80211_free_hw(hw);
3776}
3777
3778static int b43legacy_wireless_init(struct ssb_device *dev)
3779{
3780 struct ssb_sprom *sprom = &dev->bus->sprom;
3781 struct ieee80211_hw *hw;
3782 struct b43legacy_wl *wl;
3783 int err = -ENOMEM;
3784
3785 b43legacy_sprom_fixup(dev->bus);
3786
3787 hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
3788 if (!hw) {
3789 b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
3790 goto out;
3791 }
3792
3793 /* fill hw info */
605a0bd6 3794 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 3795 IEEE80211_HW_SIGNAL_DBM |
3796 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 3797 hw->wiphy->interface_modes =
3798 BIT(NL80211_IFTYPE_AP) |
3799 BIT(NL80211_IFTYPE_STATION) |
3800 BIT(NL80211_IFTYPE_WDS) |
3801 BIT(NL80211_IFTYPE_ADHOC);
75388acd 3802 hw->queues = 1; /* FIXME: hardware has more queues */
e6a9854b 3803 hw->max_rates = 2;
75388acd 3804 SET_IEEE80211_DEV(hw, dev->dev);
7797aa38
LF		 3805 if (is_valid_ether_addr(sprom->et1mac))
3806 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
75388acd 3807 else
7797aa38 3808 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
75388acd
LF		 3809
3810 /* Get and initialize struct b43legacy_wl */
3811 wl = hw_to_b43legacy_wl(hw);
3812 memset(wl, 0, sizeof(*wl));
3813 wl->hw = hw;
3814 spin_lock_init(&wl->irq_lock);
3815 spin_lock_init(&wl->leds_lock);
3816 mutex_init(&wl->mutex);
3817 INIT_LIST_HEAD(&wl->devlist);
7858e07b 3818 INIT_WORK(&wl->beacon_update_trigger, b43legacy_beacon_update_trigger_work);
75388acd
LF		 3819
3820 ssb_set_devtypedata(dev, wl);
3821 b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3822 err = 0;
3823out:
3824 return err;
3825}
3826
3827static int b43legacy_probe(struct ssb_device *dev,
3828 const struct ssb_device_id *id)
3829{
3830 struct b43legacy_wl *wl;
3831 int err;
3832 int first = 0;
3833
3834 wl = ssb_get_devtypedata(dev);
3835 if (!wl) {
3836 /* Probing the first core - setup common struct b43legacy_wl */
3837 first = 1;
3838 err = b43legacy_wireless_init(dev);
3839 if (err)
3840 goto out;
3841 wl = ssb_get_devtypedata(dev);
3842 B43legacy_WARN_ON(!wl);
3843 }
3844 err = b43legacy_one_core_attach(dev, wl);
3845 if (err)
3846 goto err_wireless_exit;
3847
3848 if (first) {
3849 err = ieee80211_register_hw(wl->hw);
3850 if (err)
3851 goto err_one_core_detach;
3852 }
3853
3854out:
3855 return err;
3856
3857err_one_core_detach:
3858 b43legacy_one_core_detach(dev);
3859err_wireless_exit:
3860 if (first)
3861 b43legacy_wireless_exit(dev, wl);
3862 return err;
3863}
3864
3865static void b43legacy_remove(struct ssb_device *dev)
3866{
3867 struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
3868 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3869
48e6c51b
MB		 3870 /* We must cancel any work here before unregistering from ieee80211,
3871 * as the ieee80211 unreg will destroy the workqueue. */
3872 cancel_work_sync(&wldev->restart_work);
3873
75388acd
LF		 3874 B43legacy_WARN_ON(!wl);
3875 if (wl->current_dev == wldev)
3876 ieee80211_unregister_hw(wl->hw);
3877
3878 b43legacy_one_core_detach(dev);
3879
3880 if (list_empty(&wl->devlist))
3881 /* Last core on the chip unregistered.
3882 * We can destroy common struct b43legacy_wl.
3883 */
3884 b43legacy_wireless_exit(dev, wl);
3885}
3886
3887/* Perform a hardware reset. This can be called from any context. */
3888void b43legacy_controller_restart(struct b43legacy_wldev *dev,
3889 const char *reason)
3890{
3891 /* Must avoid requeueing, if we are in shutdown. */
3892 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
3893 return;
3894 b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 3895 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
75388acd
LF		 3896}
3897
3898#ifdef CONFIG_PM
3899
3900static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
3901{
3902 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3903 struct b43legacy_wl *wl = wldev->wl;
3904
3905 b43legacydbg(wl, "Suspending...\n");
3906
3907 mutex_lock(&wl->mutex);
3908 wldev->suspend_init_status = b43legacy_status(wldev);
3909 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
3910 b43legacy_wireless_core_stop(wldev);
3911 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
3912 b43legacy_wireless_core_exit(wldev);
3913 mutex_unlock(&wl->mutex);
3914
3915 b43legacydbg(wl, "Device suspended.\n");
3916
3917 return 0;
3918}
3919
3920static int b43legacy_resume(struct ssb_device *dev)
3921{
3922 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3923 struct b43legacy_wl *wl = wldev->wl;
3924 int err = 0;
3925
3926 b43legacydbg(wl, "Resuming...\n");
3927
3928 mutex_lock(&wl->mutex);
3929 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
3930 err = b43legacy_wireless_core_init(wldev);
3931 if (err) {
3932 b43legacyerr(wl, "Resume failed at core init\n");
3933 goto out;
3934 }
3935 }
3936 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
3937 err = b43legacy_wireless_core_start(wldev);
3938 if (err) {
3939 b43legacy_wireless_core_exit(wldev);
3940 b43legacyerr(wl, "Resume failed at core start\n");
3941 goto out;
3942 }
3943 }
75388acd
LF		 3944
3945 b43legacydbg(wl, "Device resumed.\n");
3946out:
4104863f 3947 mutex_unlock(&wl->mutex);
75388acd
LF		 3948 return err;
3949}
3950
3951#else /* CONFIG_PM */
3952# define b43legacy_suspend NULL
3953# define b43legacy_resume NULL
3954#endif /* CONFIG_PM */
3955
3956static struct ssb_driver b43legacy_ssb_driver = {
3957 .name = KBUILD_MODNAME,
3958 .id_table = b43legacy_ssb_tbl,
3959 .probe = b43legacy_probe,
3960 .remove = b43legacy_remove,
3961 .suspend = b43legacy_suspend,
3962 .resume = b43legacy_resume,
3963};
3964
6fff1c64
SB		 3965static void b43legacy_print_driverinfo(void)
3966{
2f1f00fc 3967 const char *feat_pci = "", *feat_leds = "",
6fff1c64
SB		 3968 *feat_pio = "", *feat_dma = "";
3969
3970#ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
3971 feat_pci = "P";
3972#endif
3973#ifdef CONFIG_B43LEGACY_LEDS
3974 feat_leds = "L";
3975#endif
6fff1c64
SB		 3976#ifdef CONFIG_B43LEGACY_PIO
3977 feat_pio = "I";
3978#endif
3979#ifdef CONFIG_B43LEGACY_DMA
3980 feat_dma = "D";
3981#endif
c256e05b 3982 printk(KERN_INFO "Broadcom 43xx-legacy driver loaded "
2f1f00fc 3983 "[ Features: %s%s%s%s, Firmware-ID: "
6fff1c64 3984 B43legacy_SUPPORTED_FIRMWARE_ID " ]\n",
2f1f00fc 3985 feat_pci, feat_leds, feat_pio, feat_dma);
6fff1c64
SB		 3986}
3987
75388acd
LF		 3988static int __init b43legacy_init(void)
3989{
3990 int err;
3991
3992 b43legacy_debugfs_init();
3993
3994 err = ssb_driver_register(&b43legacy_ssb_driver);
3995 if (err)
3996 goto err_dfs_exit;
3997
6fff1c64
SB		 3998 b43legacy_print_driverinfo();
3999
75388acd
LF		 4000 return err;
4001
4002err_dfs_exit:
4003 b43legacy_debugfs_exit();
4004 return err;
4005}
4006
4007static void __exit b43legacy_exit(void)
4008{
4009 ssb_driver_unregister(&b43legacy_ssb_driver);
4010 b43legacy_debugfs_exit();
4011}
4012
4013module_init(b43legacy_init)
4014module_exit(b43legacy_exit)
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