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b43: N PHY: Fix compilation after removal of typdef b43_c32
[net-next-2.6.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
819d772b
JL		 25#include <linux/delay.h>
26#include <linux/types.h>
27
424047e6 28#include "b43.h"
3d0da751 29#include "phy_n.h"
53a6e234 30#include "tables_nphy.h"
bbec398c 31#include "main.h"
424047e6 32
f8187b5b
RM		 33struct nphy_txgains {
34 u16 txgm[2];
35 u16 pga[2];
36 u16 pad[2];
37 u16 ipa[2];
38};
39
40struct nphy_iqcal_params {
41 u16 txgm;
42 u16 pga;
43 u16 pad;
44 u16 ipa;
45 u16 cal_gain;
46 u16 ncorr[5];
47};
48
49struct nphy_iq_est {
50 s32 iq0_prod;
51 u32 i0_pwr;
52 u32 q0_pwr;
53 s32 iq1_prod;
54 u32 i1_pwr;
55 u32 q1_pwr;
56};
424047e6 57
67c0d6e2
RM		 58enum b43_nphy_rf_sequence {
59 B43_RFSEQ_RX2TX,
60 B43_RFSEQ_TX2RX,
61 B43_RFSEQ_RESET2RX,
62 B43_RFSEQ_UPDATE_GAINH,
63 B43_RFSEQ_UPDATE_GAINL,
64 B43_RFSEQ_UPDATE_GAINU,
65};
66
67static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
68 enum b43_nphy_rf_sequence seq);
69
53a6e234
MB		 70void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
71{//TODO
72}
73
18c8adeb 74static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234
MB		 75{//TODO
76}
77
18c8adeb
MB		 78static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
79 bool ignore_tssi)
80{//TODO
81 return B43_TXPWR_RES_DONE;
82}
83
d1591314
MB		 84static void b43_chantab_radio_upload(struct b43_wldev *dev,
85 const struct b43_nphy_channeltab_entry *e)
86{
87 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
88 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
89 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
90 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
91 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
92 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
93 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
94 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
95 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
96 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
97 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
98 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
99 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
100 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
101 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
102 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
103 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
104 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
105 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
106 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
107 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
108 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
109}
110
111static void b43_chantab_phy_upload(struct b43_wldev *dev,
112 const struct b43_nphy_channeltab_entry *e)
113{
114 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
115 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
116 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
117 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
118 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
119 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
120}
121
122static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
123{
124 //TODO
125}
126
ef1a628d
MB		 127/* Tune the hardware to a new channel. */
128static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
53a6e234 129{
d1591314
MB		 130 const struct b43_nphy_channeltab_entry *tabent;
131
132 tabent = b43_nphy_get_chantabent(dev, channel);
133 if (!tabent)
134 return -ESRCH;
135
136 //FIXME enable/disable band select upper20 in RXCTL
137 if (0 /*FIXME 5Ghz*/)
138 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
139 else
140 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
141 b43_chantab_radio_upload(dev, tabent);
142 udelay(50);
143 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
144 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
145 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
146 udelay(300);
147 if (0 /*FIXME 5Ghz*/)
148 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
149 else
150 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
151 b43_chantab_phy_upload(dev, tabent);
152 b43_nphy_tx_power_fix(dev);
53a6e234 153
d1591314 154 return 0;
53a6e234
MB		 155}
156
157static void b43_radio_init2055_pre(struct b43_wldev *dev)
158{
159 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
160 ~B43_NPHY_RFCTL_CMD_PORFORCE);
161 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
162 B43_NPHY_RFCTL_CMD_CHIP0PU |
163 B43_NPHY_RFCTL_CMD_OEPORFORCE);
164 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
165 B43_NPHY_RFCTL_CMD_PORFORCE);
166}
167
168static void b43_radio_init2055_post(struct b43_wldev *dev)
169{
170 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
171 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
172 int i;
173 u16 val;
174
175 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
176 msleep(1);
738f0f43
GS		 177 if ((sprom->revision != 4) ||
178 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
53a6e234
MB		 179 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
180 (binfo->type != 0x46D) ||
181 (binfo->rev < 0x41)) {
182 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
183 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
184 msleep(1);
185 }
186 }
187 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
188 msleep(1);
189 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
190 msleep(1);
191 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
192 msleep(1);
193 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
194 msleep(1);
195 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
196 msleep(1);
197 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
198 msleep(1);
199 for (i = 0; i < 100; i++) {
200 val = b43_radio_read16(dev, B2055_CAL_COUT2);
201 if (val & 0x80)
202 break;
203 udelay(10);
204 }
205 msleep(1);
206 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
207 msleep(1);
ef1a628d 208 nphy_channel_switch(dev, dev->phy.channel);
53a6e234
MB		 209 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
210 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
211 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
212 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
213}
214
215/* Initialize a Broadcom 2055 N-radio */
216static void b43_radio_init2055(struct b43_wldev *dev)
217{
218 b43_radio_init2055_pre(dev);
219 if (b43_status(dev) < B43_STAT_INITIALIZED)
220 b2055_upload_inittab(dev, 0, 1);
221 else
222 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
223 b43_radio_init2055_post(dev);
224}
225
226void b43_nphy_radio_turn_on(struct b43_wldev *dev)
227{
228 b43_radio_init2055(dev);
229}
230
231void b43_nphy_radio_turn_off(struct b43_wldev *dev)
232{
233 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
234 ~B43_NPHY_RFCTL_CMD_EN);
235}
236
4772ae10
RM		 237/*
238 * Upload the N-PHY tables.
239 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
240 */
95b66bad
MB		 241static void b43_nphy_tables_init(struct b43_wldev *dev)
242{
4772ae10
RM		 243 if (dev->phy.rev < 3)
244 b43_nphy_rev0_1_2_tables_init(dev);
245 else
246 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 247}
248
249static void b43_nphy_workarounds(struct b43_wldev *dev)
250{
251 struct b43_phy *phy = &dev->phy;
252 unsigned int i;
253
254 b43_phy_set(dev, B43_NPHY_IQFLIP,
255 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
95b66bad
MB		 256 if (1 /* FIXME band is 2.4GHz */) {
257 b43_phy_set(dev, B43_NPHY_CLASSCTL,
258 B43_NPHY_CLASSCTL_CCKEN);
259 } else {
260 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
261 ~B43_NPHY_CLASSCTL_CCKEN);
262 }
263 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
264 b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
265
266 /* Fixup some tables */
267 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
268 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
269 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
270 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
271 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
272 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
273 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
274 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
275 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
276 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
277
278 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
279 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
280 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
281 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
282
283 //TODO set RF sequence
284
285 /* Set narrowband clip threshold */
286 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
287 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
288
289 /* Set wideband clip 2 threshold */
290 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
291 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
292 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
293 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
294 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
295 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
296
297 /* Set Clip 2 detect */
298 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
299 B43_NPHY_C1_CGAINI_CL2DETECT);
300 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
301 B43_NPHY_C2_CGAINI_CL2DETECT);
302
303 if (0 /*FIXME*/) {
304 /* Set dwell lengths */
305 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
306 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
307 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
308 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
309
310 /* Set gain backoff */
311 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
312 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
313 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
314 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
315 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
316 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
317
318 /* Set HPVGA2 index */
319 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
320 ~B43_NPHY_C1_INITGAIN_HPVGA2,
321 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
322 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
323 ~B43_NPHY_C2_INITGAIN_HPVGA2,
324 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
325
326 //FIXME verify that the specs really mean to use autoinc here.
327 for (i = 0; i < 3; i++)
328 b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
329 }
330
331 /* Set minimum gain value */
332 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
333 ~B43_NPHY_C1_MINGAIN,
334 23 << B43_NPHY_C1_MINGAIN_SHIFT);
335 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
336 ~B43_NPHY_C2_MINGAIN,
337 23 << B43_NPHY_C2_MINGAIN_SHIFT);
338
339 if (phy->rev < 2) {
340 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
341 ~B43_NPHY_SCRAM_SIGCTL_SCM);
342 }
343
344 /* Set phase track alpha and beta */
345 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
346 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
347 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
348 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
349 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
350 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
351}
352
e50cbcf6
RM		 353/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
354static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
355{
356 struct b43_phy_n *nphy = dev->phy.n;
357 enum ieee80211_band band;
358 u16 tmp;
359
360 if (!enable) {
361 nphy->rfctrl_intc1_save = b43_phy_read(dev,
362 B43_NPHY_RFCTL_INTC1);
363 nphy->rfctrl_intc2_save = b43_phy_read(dev,
364 B43_NPHY_RFCTL_INTC2);
365 band = b43_current_band(dev->wl);
366 if (dev->phy.rev >= 3) {
367 if (band == IEEE80211_BAND_5GHZ)
368 tmp = 0x600;
369 else
370 tmp = 0x480;
371 } else {
372 if (band == IEEE80211_BAND_5GHZ)
373 tmp = 0x180;
374 else
375 tmp = 0x120;
376 }
377 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
378 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
379 } else {
380 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
381 nphy->rfctrl_intc1_save);
382 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
383 nphy->rfctrl_intc2_save);
384 }
385}
386
fe3e46e8
RM		 387/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
388static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
389{
390 struct b43_phy_n *nphy = dev->phy.n;
391 u16 tmp;
392 enum ieee80211_band band = b43_current_band(dev->wl);
393 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
394 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
395
396 if (dev->phy.rev >= 3) {
397 if (ipa) {
398 tmp = 4;
399 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
400 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
401 }
402
403 tmp = 1;
404 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
405 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
406 }
407}
408
4a933c85
RM		 409/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
410static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
411{
412 u32 tmslow;
413
414 if (dev->phy.type != B43_PHYTYPE_N)
415 return;
416
417 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
418 if (force)
419 tmslow |= SSB_TMSLOW_FGC;
420 else
421 tmslow &= ~SSB_TMSLOW_FGC;
422 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
423}
424
425/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
95b66bad
MB		 426static void b43_nphy_reset_cca(struct b43_wldev *dev)
427{
428 u16 bbcfg;
429
4a933c85 430 b43_nphy_bmac_clock_fgc(dev, 1);
95b66bad 431 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
4a933c85
RM		 432 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
433 udelay(1);
434 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
435 b43_nphy_bmac_clock_fgc(dev, 0);
67c0d6e2 436 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
95b66bad
MB		 437}
438
ad9716e8
RM		 439/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
440static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
441{
442 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
443
444 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
445 if (preamble == 1)
446 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
447 else
448 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
449
450 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
451}
452
4f4ab6cd
RM		 453/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
454static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
455{
456 struct b43_phy_n *nphy = dev->phy.n;
457
458 bool override = false;
459 u16 chain = 0x33;
460
461 if (nphy->txrx_chain == 0) {
462 chain = 0x11;
463 override = true;
464 } else if (nphy->txrx_chain == 1) {
465 chain = 0x22;
466 override = true;
467 }
468
469 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
470 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
471 chain);
472
473 if (override)
474 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
475 B43_NPHY_RFSEQMODE_CAOVER);
476 else
477 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
478 ~B43_NPHY_RFSEQMODE_CAOVER);
479}
480
2faa6b83
RM		 481/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
482static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
483 u16 samps, u8 time, bool wait)
484{
485 int i;
486 u16 tmp;
487
488 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
489 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
490 if (wait)
491 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
492 else
493 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
494
495 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
496
497 for (i = 1000; i; i--) {
498 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
499 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
500 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
501 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
502 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
503 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
504 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
505 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
506
507 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
508 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
509 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
510 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
511 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
512 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
513 return;
514 }
515 udelay(10);
516 }
517 memset(est, 0, sizeof(*est));
518}
519
a67162ab
RM		 520/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
521static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
522 struct b43_phy_n_iq_comp *pcomp)
523{
524 if (write) {
525 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
526 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
527 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
528 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
529 } else {
530 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
531 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
532 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
533 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
534 }
535}
536
026816fc
RM		 537/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
538static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
539{
540 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
541
542 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
543 if (core == 0) {
544 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
545 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
546 } else {
547 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
548 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
549 }
550 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
551 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
552 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
553 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
554 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
555 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
556 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
557 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
558}
559
560/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
561static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
562{
563 u8 rxval, txval;
564 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
565
566 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
567 if (core == 0) {
568 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
569 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
570 } else {
571 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
572 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
573 }
574 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
575 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
576 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
577 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
578 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
579 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
580 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
581 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
582
583 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
584 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
585
586 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
587 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
588 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
589 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
590 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
591 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
592 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
593 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
594
595 if (core == 0) {
596 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
597 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
598 } else {
599 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
600 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
601 }
602
603 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */
604 /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */
67c0d6e2 605 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
026816fc
RM		 606
607 if (core == 0) {
608 rxval = 1;
609 txval = 8;
610 } else {
611 rxval = 4;
612 txval = 2;
613 }
614
615 /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */
616 /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */
617}
618
34a56f2c
RM		 619/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
620static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
621{
622 int i;
623 s32 iq;
624 u32 ii;
625 u32 qq;
626 int iq_nbits, qq_nbits;
627 int arsh, brsh;
628 u16 tmp, a, b;
629
630 struct nphy_iq_est est;
631 struct b43_phy_n_iq_comp old;
632 struct b43_phy_n_iq_comp new = { };
633 bool error = false;
634
635 if (mask == 0)
636 return;
637
638 b43_nphy_rx_iq_coeffs(dev, false, &old);
639 b43_nphy_rx_iq_coeffs(dev, true, &new);
640 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
641 new = old;
642
643 for (i = 0; i < 2; i++) {
644 if (i == 0 && (mask & 1)) {
645 iq = est.iq0_prod;
646 ii = est.i0_pwr;
647 qq = est.q0_pwr;
648 } else if (i == 1 && (mask & 2)) {
649 iq = est.iq1_prod;
650 ii = est.i1_pwr;
651 qq = est.q1_pwr;
652 } else {
653 B43_WARN_ON(1);
654 continue;
655 }
656
657 if (ii + qq < 2) {
658 error = true;
659 break;
660 }
661
662 iq_nbits = fls(abs(iq));
663 qq_nbits = fls(qq);
664
665 arsh = iq_nbits - 20;
666 if (arsh >= 0) {
667 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
668 tmp = ii >> arsh;
669 } else {
670 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
671 tmp = ii << -arsh;
672 }
673 if (tmp == 0) {
674 error = true;
675 break;
676 }
677 a /= tmp;
678
679 brsh = qq_nbits - 11;
680 if (brsh >= 0) {
681 b = (qq << (31 - qq_nbits));
682 tmp = ii >> brsh;
683 } else {
684 b = (qq << (31 - qq_nbits));
685 tmp = ii << -brsh;
686 }
687 if (tmp == 0) {
688 error = true;
689 break;
690 }
691 b = int_sqrt(b / tmp - a * a) - (1 << 10);
692
693 if (i == 0 && (mask & 0x1)) {
694 if (dev->phy.rev >= 3) {
695 new.a0 = a & 0x3FF;
696 new.b0 = b & 0x3FF;
697 } else {
698 new.a0 = b & 0x3FF;
699 new.b0 = a & 0x3FF;
700 }
701 } else if (i == 1 && (mask & 0x2)) {
702 if (dev->phy.rev >= 3) {
703 new.a1 = a & 0x3FF;
704 new.b1 = b & 0x3FF;
705 } else {
706 new.a1 = b & 0x3FF;
707 new.b1 = a & 0x3FF;
708 }
709 }
710 }
711
712 if (error)
713 new = old;
714
715 b43_nphy_rx_iq_coeffs(dev, true, &new);
716}
717
09146400
RM		 718/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
719static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
720{
721 u16 array[4];
722 int i;
723
724 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
725 for (i = 0; i < 4; i++)
726 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
727
728 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
729 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
730 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
731 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
732}
733
bbec398c
RM		 734/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
735static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
736{
737 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
738 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
739}
740
741/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
742static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
743{
744 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
745 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
746}
747
748/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
749static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
750{
751 u16 tmp;
752
753 if (dev->dev->id.revision == 16)
754 b43_mac_suspend(dev);
755
756 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
757 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
758 B43_NPHY_CLASSCTL_WAITEDEN);
759 tmp &= ~mask;
760 tmp |= (val & mask);
761 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
762
763 if (dev->dev->id.revision == 16)
764 b43_mac_enable(dev);
765
766 return tmp;
767}
768
5c1a140a
RM		 769/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
770static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
771{
772 struct b43_phy *phy = &dev->phy;
773 struct b43_phy_n *nphy = phy->n;
774
775 if (enable) {
776 u16 clip[] = { 0xFFFF, 0xFFFF };
777 if (nphy->deaf_count++ == 0) {
778 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
779 b43_nphy_classifier(dev, 0x7, 0);
780 b43_nphy_read_clip_detection(dev, nphy->clip_state);
781 b43_nphy_write_clip_detection(dev, clip);
782 }
783 b43_nphy_reset_cca(dev);
784 } else {
785 if (--nphy->deaf_count == 0) {
786 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
787 b43_nphy_write_clip_detection(dev, nphy->clip_state);
788 }
789 }
790}
791
53ae8e8c
RM		 792/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
793static void b43_nphy_stop_playback(struct b43_wldev *dev)
794{
795 struct b43_phy_n *nphy = dev->phy.n;
796 u16 tmp;
797
798 if (nphy->hang_avoid)
799 b43_nphy_stay_in_carrier_search(dev, 1);
800
801 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
802 if (tmp & 0x1)
803 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
804 else if (tmp & 0x2)
805 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
806
807 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
808
809 if (nphy->bb_mult_save & 0x80000000) {
810 tmp = nphy->bb_mult_save & 0xFFFF;
d41a3552 811 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
53ae8e8c
RM		 812 nphy->bb_mult_save = 0;
813 }
814
815 if (nphy->hang_avoid)
816 b43_nphy_stay_in_carrier_search(dev, 0);
817}
818
59af099b
RM		 819/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
820static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
821 bool test)
822{
823 int i;
f2982181 824 u16 bw, len, rot, angle;
da860475 825 struct b43_c32 *samples;
f2982181 826
59af099b
RM		 827
828 bw = (dev->phy.is_40mhz) ? 40 : 20;
829 len = bw << 3;
830
831 if (test) {
832 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
833 bw = 82;
834 else
835 bw = 80;
836
837 if (dev->phy.is_40mhz)
838 bw <<= 1;
839
840 len = bw << 1;
841 }
842
da860475 843 samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
59af099b
RM		 844 rot = (((freq * 36) / bw) << 16) / 100;
845 angle = 0;
846
f2982181
RM		 847 for (i = 0; i < len; i++) {
848 samples[i] = b43_cordic(angle);
849 angle += rot;
850 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
851 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
59af099b
RM		 852 }
853
f2982181
RM		 854 /* TODO: Call N PHY Load Sample Table with buffer, len as arguments */
855 kfree(samples);
856 return len;
59af099b
RM		 857}
858
10a79873
RM		 859/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
860static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
861 u16 wait, bool iqmode, bool dac_test)
862{
863 struct b43_phy_n *nphy = dev->phy.n;
864 int i;
865 u16 seq_mode;
866 u32 tmp;
867
868 if (nphy->hang_avoid)
869 b43_nphy_stay_in_carrier_search(dev, true);
870
871 if ((nphy->bb_mult_save & 0x80000000) == 0) {
872 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
873 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
874 }
875
876 if (!dev->phy.is_40mhz)
877 tmp = 0x6464;
878 else
879 tmp = 0x4747;
880 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
881
882 if (nphy->hang_avoid)
883 b43_nphy_stay_in_carrier_search(dev, false);
884
885 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
886
887 if (loops != 0xFFFF)
888 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
889 else
890 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
891
892 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
893
894 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
895
896 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
897 if (iqmode) {
898 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
899 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
900 } else {
901 if (dac_test)
902 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
903 else
904 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
905 }
906 for (i = 0; i < 100; i++) {
907 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
908 i = 0;
909 break;
910 }
911 udelay(10);
912 }
913 if (i)
914 b43err(dev->wl, "run samples timeout\n");
915
916 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
917}
918
59af099b
RM		 919/*
920 * Transmits a known value for LO calibration
921 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
922 */
923static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
924 bool iqmode, bool dac_test)
925{
926 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
927 if (samp == 0)
928 return -1;
929 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
930 return 0;
931}
932
6dcd9d91
RM		 933/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
934static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
935{
936 struct b43_phy_n *nphy = dev->phy.n;
937 int i, j;
938 u32 tmp;
939 u32 cur_real, cur_imag, real_part, imag_part;
940
941 u16 buffer[7];
942
943 if (nphy->hang_avoid)
944 b43_nphy_stay_in_carrier_search(dev, true);
945
9145834e 946 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
6dcd9d91
RM		 947
948 for (i = 0; i < 2; i++) {
949 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
950 (buffer[i * 2 + 1] & 0x3FF);
951 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
952 (((i + 26) << 10) | 320));
953 for (j = 0; j < 128; j++) {
954 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
955 ((tmp >> 16) & 0xFFFF));
956 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
957 (tmp & 0xFFFF));
958 }
959 }
960
961 for (i = 0; i < 2; i++) {
962 tmp = buffer[5 + i];
963 real_part = (tmp >> 8) & 0xFF;
964 imag_part = (tmp & 0xFF);
965 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
966 (((i + 26) << 10) | 448));
967
968 if (dev->phy.rev >= 3) {
969 cur_real = real_part;
970 cur_imag = imag_part;
971 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
972 }
973
974 for (j = 0; j < 128; j++) {
975 if (dev->phy.rev < 3) {
976 cur_real = (real_part * loscale[j] + 128) >> 8;
977 cur_imag = (imag_part * loscale[j] + 128) >> 8;
978 tmp = ((cur_real & 0xFF) << 8) |
979 (cur_imag & 0xFF);
980 }
981 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
982 ((tmp >> 16) & 0xFFFF));
983 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
984 (tmp & 0xFFFF));
985 }
986 }
987
988 if (dev->phy.rev >= 3) {
989 b43_shm_write16(dev, B43_SHM_SHARED,
990 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
991 b43_shm_write16(dev, B43_SHM_SHARED,
992 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
993 }
994
995 if (nphy->hang_avoid)
996 b43_nphy_stay_in_carrier_search(dev, false);
997}
998
67c0d6e2 999/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
95b66bad
MB		 1000static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1001 enum b43_nphy_rf_sequence seq)
1002{
1003 static const u16 trigger[] = {
1004 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1005 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1006 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1007 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1008 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1009 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1010 };
1011 int i;
c57199bc 1012 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
95b66bad
MB		 1013
1014 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1015
1016 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1017 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1018 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1019 for (i = 0; i < 200; i++) {
1020 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1021 goto ok;
1022 msleep(1);
1023 }
1024 b43err(dev->wl, "RF sequence status timeout\n");
1025ok:
c57199bc 1026 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
95b66bad
MB		 1027}
1028
75377b24
RM		 1029/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1030static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1031 u16 value, u8 core, bool off)
1032{
1033 int i;
1034 u8 index = fls(field);
1035 u8 addr, en_addr, val_addr;
1036 /* we expect only one bit set */
3ed0fac3 1037 B43_WARN_ON(field & (~(1 << (index - 1))));
75377b24
RM		 1038
1039 if (dev->phy.rev >= 3) {
1040 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1041 for (i = 0; i < 2; i++) {
1042 if (index == 0 || index == 16) {
1043 b43err(dev->wl,
1044 "Unsupported RF Ctrl Override call\n");
1045 return;
1046 }
1047
1048 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1049 en_addr = B43_PHY_N((i == 0) ?
1050 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1051 val_addr = B43_PHY_N((i == 0) ?
1052 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1053
1054 if (off) {
1055 b43_phy_mask(dev, en_addr, ~(field));
1056 b43_phy_mask(dev, val_addr,
1057 ~(rf_ctrl->val_mask));
1058 } else {
1059 if (core == 0 || ((1 << core) & i) != 0) {
1060 b43_phy_set(dev, en_addr, field);
1061 b43_phy_maskset(dev, val_addr,
1062 ~(rf_ctrl->val_mask),
1063 (value << rf_ctrl->val_shift));
1064 }
1065 }
1066 }
1067 } else {
1068 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1069 if (off) {
1070 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1071 value = 0;
1072 } else {
1073 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1074 }
1075
1076 for (i = 0; i < 2; i++) {
1077 if (index <= 1 || index == 16) {
1078 b43err(dev->wl,
1079 "Unsupported RF Ctrl Override call\n");
1080 return;
1081 }
1082
1083 if (index == 2 || index == 10 ||
1084 (index >= 13 && index <= 15)) {
1085 core = 1;
1086 }
1087
1088 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1089 addr = B43_PHY_N((i == 0) ?
1090 rf_ctrl->addr0 : rf_ctrl->addr1);
1091
1092 if ((core & (1 << i)) != 0)
1093 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1094 (value << rf_ctrl->shift));
1095
1096 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1097 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1098 B43_NPHY_RFCTL_CMD_START);
1099 udelay(1);
1100 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1101 }
1102 }
1103}
1104
95b66bad
MB		 1105static void b43_nphy_bphy_init(struct b43_wldev *dev)
1106{
1107 unsigned int i;
1108 u16 val;
1109
1110 val = 0x1E1F;
1111 for (i = 0; i < 14; i++) {
1112 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1113 val -= 0x202;
1114 }
1115 val = 0x3E3F;
1116 for (i = 0; i < 16; i++) {
1117 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1118 val -= 0x202;
1119 }
1120 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1121}
1122
3c95627d
RM		 1123/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1124static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1125 s8 offset, u8 core, u8 rail, u8 type)
1126{
1127 u16 tmp;
1128 bool core1or5 = (core == 1) || (core == 5);
1129 bool core2or5 = (core == 2) || (core == 5);
1130
1131 offset = clamp_val(offset, -32, 31);
1132 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1133
1134 if (core1or5 && (rail == 0) && (type == 2))
1135 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1136 if (core1or5 && (rail == 1) && (type == 2))
1137 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1138 if (core2or5 && (rail == 0) && (type == 2))
1139 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1140 if (core2or5 && (rail == 1) && (type == 2))
1141 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1142 if (core1or5 && (rail == 0) && (type == 0))
1143 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1144 if (core1or5 && (rail == 1) && (type == 0))
1145 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1146 if (core2or5 && (rail == 0) && (type == 0))
1147 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1148 if (core2or5 && (rail == 1) && (type == 0))
1149 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1150 if (core1or5 && (rail == 0) && (type == 1))
1151 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1152 if (core1or5 && (rail == 1) && (type == 1))
1153 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1154 if (core2or5 && (rail == 0) && (type == 1))
1155 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1156 if (core2or5 && (rail == 1) && (type == 1))
1157 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1158 if (core1or5 && (rail == 0) && (type == 6))
1159 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1160 if (core1or5 && (rail == 1) && (type == 6))
1161 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1162 if (core2or5 && (rail == 0) && (type == 6))
1163 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1164 if (core2or5 && (rail == 1) && (type == 6))
1165 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1166 if (core1or5 && (rail == 0) && (type == 3))
1167 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1168 if (core1or5 && (rail == 1) && (type == 3))
1169 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1170 if (core2or5 && (rail == 0) && (type == 3))
1171 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1172 if (core2or5 && (rail == 1) && (type == 3))
1173 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1174 if (core1or5 && (type == 4))
1175 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1176 if (core2or5 && (type == 4))
1177 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1178 if (core1or5 && (type == 5))
1179 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1180 if (core2or5 && (type == 5))
1181 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1182}
1183
1184/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1185static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1186{
1187 u16 val;
1188
1189 if (dev->phy.rev >= 3) {
1190 /* TODO */
1191 } else {
1192 if (type < 3)
1193 val = 0;
1194 else if (type == 6)
1195 val = 1;
1196 else if (type == 3)
1197 val = 2;
1198 else
1199 val = 3;
1200
1201 val = (val << 12) | (val << 14);
1202 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1203 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1204
1205 if (type < 3) {
1206 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1207 (type + 1) << 4);
1208 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1209 (type + 1) << 4);
1210 }
1211
1212 /* TODO use some definitions */
1213 if (code == 0) {
1214 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1215 if (type < 3) {
1216 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1217 0xFEC7, 0);
1218 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1219 0xEFDC, 0);
1220 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1221 0xFFFE, 0);
1222 udelay(20);
1223 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1224 0xFFFE, 0);
1225 }
1226 } else {
1227 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1228 0x3000);
1229 if (type < 3) {
1230 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1231 0xFEC7, 0x0180);
1232 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1233 0xEFDC, (code << 1 | 0x1021));
1234 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1235 0xFFFE, 0x0001);
1236 udelay(20);
1237 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1238 0xFFFE, 0);
1239 }
1240 }
1241 }
1242}
1243
dfb4aa5d
RM		 1244/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1245static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1246{
1247 int i;
1248 for (i = 0; i < 2; i++) {
1249 if (type == 2) {
1250 if (i == 0) {
1251 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1252 0xFC, buf[0]);
1253 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1254 0xFC, buf[1]);
1255 } else {
1256 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1257 0xFC, buf[2 * i]);
1258 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1259 0xFC, buf[2 * i + 1]);
1260 }
1261 } else {
1262 if (i == 0)
1263 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1264 0xF3, buf[0] << 2);
1265 else
1266 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1267 0xF3, buf[2 * i + 1] << 2);
1268 }
1269 }
1270}
1271
1272/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1273static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1274 u8 nsamp)
1275{
1276 int i;
1277 int out;
1278 u16 save_regs_phy[9];
1279 u16 s[2];
1280
1281 if (dev->phy.rev >= 3) {
1282 save_regs_phy[0] = b43_phy_read(dev,
1283 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1284 save_regs_phy[1] = b43_phy_read(dev,
1285 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1286 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1287 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1288 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1289 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1290 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1291 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1292 }
1293
1294 b43_nphy_rssi_select(dev, 5, type);
1295
1296 if (dev->phy.rev < 2) {
1297 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1298 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1299 }
1300
1301 for (i = 0; i < 4; i++)
1302 buf[i] = 0;
1303
1304 for (i = 0; i < nsamp; i++) {
1305 if (dev->phy.rev < 2) {
1306 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1307 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1308 } else {
1309 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1310 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1311 }
1312
1313 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1314 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1315 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1316 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1317 }
1318 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1319 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1320
1321 if (dev->phy.rev < 2)
1322 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1323
1324 if (dev->phy.rev >= 3) {
1325 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1326 save_regs_phy[0]);
1327 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1328 save_regs_phy[1]);
1329 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1330 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1331 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1332 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1333 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1334 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1335 }
1336
1337 return out;
1338}
1339
4cb99775
RM		 1340/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1341static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 1342{
90b9738d
RM		 1343 int i, j;
1344 u8 state[4];
1345 u8 code, val;
1346 u16 class, override;
1347 u8 regs_save_radio[2];
1348 u16 regs_save_phy[2];
1349 s8 offset[4];
1350
1351 u16 clip_state[2];
1352 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1353 s32 results_min[4] = { };
1354 u8 vcm_final[4] = { };
1355 s32 results[4][4] = { };
1356 s32 miniq[4][2] = { };
1357
1358 if (type == 2) {
1359 code = 0;
1360 val = 6;
1361 } else if (type < 2) {
1362 code = 25;
1363 val = 4;
1364 } else {
1365 B43_WARN_ON(1);
1366 return;
1367 }
1368
1369 class = b43_nphy_classifier(dev, 0, 0);
1370 b43_nphy_classifier(dev, 7, 4);
1371 b43_nphy_read_clip_detection(dev, clip_state);
1372 b43_nphy_write_clip_detection(dev, clip_off);
1373
1374 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1375 override = 0x140;
1376 else
1377 override = 0x110;
1378
1379 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1380 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1381 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1382 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1383
1384 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1385 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1386 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1387 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1388
1389 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1390 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1391 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1392 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1393 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1394 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1395
1396 b43_nphy_rssi_select(dev, 5, type);
1397 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1398 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1399
1400 for (i = 0; i < 4; i++) {
1401 u8 tmp[4];
1402 for (j = 0; j < 4; j++)
1403 tmp[j] = i;
1404 if (type != 1)
1405 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1406 b43_nphy_poll_rssi(dev, type, results[i], 8);
1407 if (type < 2)
1408 for (j = 0; j < 2; j++)
1409 miniq[i][j] = min(results[i][2 * j],
1410 results[i][2 * j + 1]);
1411 }
1412
1413 for (i = 0; i < 4; i++) {
1414 s32 mind = 40;
1415 u8 minvcm = 0;
1416 s32 minpoll = 249;
1417 s32 curr;
1418 for (j = 0; j < 4; j++) {
1419 if (type == 2)
1420 curr = abs(results[j][i]);
1421 else
1422 curr = abs(miniq[j][i / 2] - code * 8);
1423
1424 if (curr < mind) {
1425 mind = curr;
1426 minvcm = j;
1427 }
1428
1429 if (results[j][i] < minpoll)
1430 minpoll = results[j][i];
1431 }
1432 results_min[i] = minpoll;
1433 vcm_final[i] = minvcm;
1434 }
1435
1436 if (type != 1)
1437 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1438
1439 for (i = 0; i < 4; i++) {
1440 offset[i] = (code * 8) - results[vcm_final[i]][i];
1441
1442 if (offset[i] < 0)
1443 offset[i] = -((abs(offset[i]) + 4) / 8);
1444 else
1445 offset[i] = (offset[i] + 4) / 8;
1446
1447 if (results_min[i] == 248)
1448 offset[i] = code - 32;
1449
1450 if (i % 2 == 0)
1451 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1452 type);
1453 else
1454 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1455 type);
1456 }
1457
1458 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1459 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1460
1461 switch (state[2]) {
1462 case 1:
1463 b43_nphy_rssi_select(dev, 1, 2);
1464 break;
1465 case 4:
1466 b43_nphy_rssi_select(dev, 1, 0);
1467 break;
1468 case 2:
1469 b43_nphy_rssi_select(dev, 1, 1);
1470 break;
1471 default:
1472 b43_nphy_rssi_select(dev, 1, 1);
1473 break;
1474 }
1475
1476 switch (state[3]) {
1477 case 1:
1478 b43_nphy_rssi_select(dev, 2, 2);
1479 break;
1480 case 4:
1481 b43_nphy_rssi_select(dev, 2, 0);
1482 break;
1483 default:
1484 b43_nphy_rssi_select(dev, 2, 1);
1485 break;
1486 }
1487
1488 b43_nphy_rssi_select(dev, 0, type);
1489
1490 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1491 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1492 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1493 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1494
1495 b43_nphy_classifier(dev, 7, class);
1496 b43_nphy_write_clip_detection(dev, clip_state);
4cb99775
RM		 1497}
1498
1499/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1500static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1501{
1502 /* TODO */
1503}
1504
1505/*
1506 * RSSI Calibration
1507 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1508 */
1509static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1510{
1511 if (dev->phy.rev >= 3) {
1512 b43_nphy_rev3_rssi_cal(dev);
1513 } else {
1514 b43_nphy_rev2_rssi_cal(dev, 2);
1515 b43_nphy_rev2_rssi_cal(dev, 0);
1516 b43_nphy_rev2_rssi_cal(dev, 1);
1517 }
95b66bad
MB		 1518}
1519
42e1547e
RM		 1520/*
1521 * Restore RSSI Calibration
1522 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1523 */
1524static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1525{
1526 struct b43_phy_n *nphy = dev->phy.n;
1527
1528 u16 *rssical_radio_regs = NULL;
1529 u16 *rssical_phy_regs = NULL;
1530
1531 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1532 if (!nphy->rssical_chanspec_2G)
1533 return;
1534 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1535 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1536 } else {
1537 if (!nphy->rssical_chanspec_5G)
1538 return;
1539 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1540 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1541 }
1542
1543 /* TODO use some definitions */
1544 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1545 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1546
1547 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1548 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1549 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1550 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1551
1552 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1553 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1554 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1555 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1556
1557 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1558 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1559 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1560 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1561}
1562
2f258b74
RM		 1563/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1564static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1565{
1566 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1567 if (dev->phy.rev >= 6) {
1568 /* TODO If the chip is 47162
1569 return txpwrctrl_tx_gain_ipa_rev5 */
1570 return txpwrctrl_tx_gain_ipa_rev6;
1571 } else if (dev->phy.rev >= 5) {
1572 return txpwrctrl_tx_gain_ipa_rev5;
1573 } else {
1574 return txpwrctrl_tx_gain_ipa;
1575 }
1576 } else {
1577 return txpwrctrl_tx_gain_ipa_5g;
1578 }
1579}
1580
c4a92003
RM		 1581/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
1582static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
1583{
1584 struct b43_phy_n *nphy = dev->phy.n;
1585 u16 *save = nphy->tx_rx_cal_radio_saveregs;
1586
1587 if (dev->phy.rev >= 3) {
1588 /* TODO */
1589 } else {
1590 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
1591 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
1592
1593 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
1594 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
1595
1596 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
1597 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
1598
1599 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
1600 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
1601
1602 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
1603 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
1604
1605 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
1606 B43_NPHY_BANDCTL_5GHZ)) {
1607 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
1608 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
1609 } else {
1610 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
1611 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
1612 }
1613
1614 if (dev->phy.rev < 2) {
1615 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
1616 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
1617 } else {
1618 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
1619 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
1620 }
1621 }
1622}
1623
e9762492
RM		 1624/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
1625static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
1626 struct nphy_txgains target,
1627 struct nphy_iqcal_params *params)
1628{
1629 int i, j, indx;
1630 u16 gain;
1631
1632 if (dev->phy.rev >= 3) {
1633 params->txgm = target.txgm[core];
1634 params->pga = target.pga[core];
1635 params->pad = target.pad[core];
1636 params->ipa = target.ipa[core];
1637 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
1638 (params->pad << 4) | (params->ipa);
1639 for (j = 0; j < 5; j++)
1640 params->ncorr[j] = 0x79;
1641 } else {
1642 gain = (target.pad[core]) | (target.pga[core] << 4) |
1643 (target.txgm[core] << 8);
1644
1645 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
1646 1 : 0;
1647 for (i = 0; i < 9; i++)
1648 if (tbl_iqcal_gainparams[indx][i][0] == gain)
1649 break;
1650 i = min(i, 8);
1651
1652 params->txgm = tbl_iqcal_gainparams[indx][i][1];
1653 params->pga = tbl_iqcal_gainparams[indx][i][2];
1654 params->pad = tbl_iqcal_gainparams[indx][i][3];
1655 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
1656 (params->pad << 2);
1657 for (j = 0; j < 4; j++)
1658 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
1659 }
1660}
1661
de7ed0c6
RM		 1662/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
1663static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
1664{
1665 struct b43_phy_n *nphy = dev->phy.n;
1666 int i;
1667 u16 scale, entry;
1668
1669 u16 tmp = nphy->txcal_bbmult;
1670 if (core == 0)
1671 tmp >>= 8;
1672 tmp &= 0xff;
1673
1674 for (i = 0; i < 18; i++) {
1675 scale = (ladder_lo[i].percent * tmp) / 100;
1676 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 1677 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 1678
1679 scale = (ladder_iq[i].percent * tmp) / 100;
1680 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 1681 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 1682 }
1683}
1684
45ca697e
RM		 1685/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
1686static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
1687{
1688 int i;
1689 for (i = 0; i < 15; i++)
1690 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
1691 tbl_tx_filter_coef_rev4[2][i]);
1692}
1693
1694/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
1695static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
1696{
1697 int i, j;
1698 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
1699 u16 offset[] = { 0x186, 0x195, 0x2C5 };
1700
1701 for (i = 0; i < 3; i++)
1702 for (j = 0; j < 15; j++)
1703 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
1704 tbl_tx_filter_coef_rev4[i][j]);
1705
1706 if (dev->phy.is_40mhz) {
1707 for (j = 0; j < 15; j++)
1708 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
1709 tbl_tx_filter_coef_rev4[3][j]);
1710 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1711 for (j = 0; j < 15; j++)
1712 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
1713 tbl_tx_filter_coef_rev4[5][j]);
1714 }
1715
1716 if (dev->phy.channel == 14)
1717 for (j = 0; j < 15; j++)
1718 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
1719 tbl_tx_filter_coef_rev4[6][j]);
1720}
1721
b0022e15
RM		 1722/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
1723static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
1724{
1725 struct b43_phy_n *nphy = dev->phy.n;
1726
1727 u16 curr_gain[2];
1728 struct nphy_txgains target;
1729 const u32 *table = NULL;
1730
1731 if (nphy->txpwrctrl == 0) {
1732 int i;
1733
1734 if (nphy->hang_avoid)
1735 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 1736 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 1737 if (nphy->hang_avoid)
1738 b43_nphy_stay_in_carrier_search(dev, false);
1739
1740 for (i = 0; i < 2; ++i) {
1741 if (dev->phy.rev >= 3) {
1742 target.ipa[i] = curr_gain[i] & 0x000F;
1743 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
1744 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
1745 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
1746 } else {
1747 target.ipa[i] = curr_gain[i] & 0x0003;
1748 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
1749 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
1750 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
1751 }
1752 }
1753 } else {
1754 int i;
1755 u16 index[2];
1756 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
1757 B43_NPHY_TXPCTL_STAT_BIDX) >>
1758 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1759 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
1760 B43_NPHY_TXPCTL_STAT_BIDX) >>
1761 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1762
1763 for (i = 0; i < 2; ++i) {
1764 if (dev->phy.rev >= 3) {
1765 enum ieee80211_band band =
1766 b43_current_band(dev->wl);
1767
1768 if ((nphy->ipa2g_on &&
1769 band == IEEE80211_BAND_2GHZ) ||
1770 (nphy->ipa5g_on &&
1771 band == IEEE80211_BAND_5GHZ)) {
1772 table = b43_nphy_get_ipa_gain_table(dev);
1773 } else {
1774 if (band == IEEE80211_BAND_5GHZ) {
1775 if (dev->phy.rev == 3)
1776 table = b43_ntab_tx_gain_rev3_5ghz;
1777 else if (dev->phy.rev == 4)
1778 table = b43_ntab_tx_gain_rev4_5ghz;
1779 else
1780 table = b43_ntab_tx_gain_rev5plus_5ghz;
1781 } else {
1782 table = b43_ntab_tx_gain_rev3plus_2ghz;
1783 }
1784 }
1785
1786 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
1787 target.pad[i] = (table[index[i]] >> 20) & 0xF;
1788 target.pga[i] = (table[index[i]] >> 24) & 0xF;
1789 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
1790 } else {
1791 table = b43_ntab_tx_gain_rev0_1_2;
1792
1793 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
1794 target.pad[i] = (table[index[i]] >> 18) & 0x3;
1795 target.pga[i] = (table[index[i]] >> 20) & 0x7;
1796 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
1797 }
1798 }
1799 }
1800
1801 return target;
1802}
1803
e53de674
RM		 1804/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
1805static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
1806{
1807 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1808
1809 if (dev->phy.rev >= 3) {
1810 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
1811 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
1812 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
1813 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
1814 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 1815 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
1816 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 1817 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
1818 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
1819 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
1820 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
1821 b43_nphy_reset_cca(dev);
1822 } else {
1823 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
1824 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
1825 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 1826 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
1827 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 1828 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
1829 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
1830 }
1831}
1832
1833/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
1834static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
1835{
1836 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1837 u16 tmp;
1838
1839 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1840 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1841 if (dev->phy.rev >= 3) {
1842 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
1843 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
1844
1845 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1846 regs[2] = tmp;
1847 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
1848
1849 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1850 regs[3] = tmp;
1851 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
1852
1853 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
de9a47f9 1854 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
e53de674 1855
c643a66e 1856 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 1857 regs[5] = tmp;
d41a3552 1858 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 1859
1860 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 1861 regs[6] = tmp;
d41a3552 1862 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 1863 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1864 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1865
1866 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 1, 3 */
1867 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 2, 1 */
1868 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 8, 2 */
1869
1870 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
1871 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
1872 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
1873 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
1874 } else {
1875 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
1876 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
1877 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1878 regs[2] = tmp;
1879 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 1880 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 1881 regs[3] = tmp;
1882 tmp |= 0x2000;
d41a3552 1883 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 1884 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 1885 regs[4] = tmp;
1886 tmp |= 0x2000;
d41a3552 1887 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 1888 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1889 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1890 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1891 tmp = 0x0180;
1892 else
1893 tmp = 0x0120;
1894 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
1895 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
1896 }
1897}
1898
2f258b74
RM		 1899/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
1900static void b43_nphy_restore_cal(struct b43_wldev *dev)
1901{
1902 struct b43_phy_n *nphy = dev->phy.n;
1903
1904 u16 coef[4];
1905 u16 *loft = NULL;
1906 u16 *table = NULL;
1907
1908 int i;
1909 u16 *txcal_radio_regs = NULL;
1910 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
1911
1912 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1913 if (nphy->iqcal_chanspec_2G == 0)
1914 return;
1915 table = nphy->cal_cache.txcal_coeffs_2G;
1916 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
1917 } else {
1918 if (nphy->iqcal_chanspec_5G == 0)
1919 return;
1920 table = nphy->cal_cache.txcal_coeffs_5G;
1921 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
1922 }
1923
2581b143 1924 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 1925
1926 for (i = 0; i < 4; i++) {
1927 if (dev->phy.rev >= 3)
1928 table[i] = coef[i];
1929 else
1930 coef[i] = 0;
1931 }
1932
2581b143
RM		 1933 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
1934 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
1935 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 1936
1937 if (dev->phy.rev < 2)
1938 b43_nphy_tx_iq_workaround(dev);
1939
1940 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1941 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
1942 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
1943 } else {
1944 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
1945 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
1946 }
1947
1948 /* TODO use some definitions */
1949 if (dev->phy.rev >= 3) {
1950 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
1951 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
1952 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
1953 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
1954 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
1955 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
1956 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
1957 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
1958 } else {
1959 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
1960 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
1961 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
1962 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
1963 }
1964 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
1965}
1966
fb43b8e2
RM		 1967/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
1968static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
1969 struct nphy_txgains target,
1970 bool full, bool mphase)
1971{
1972 struct b43_phy_n *nphy = dev->phy.n;
1973 int i;
1974 int error = 0;
1975 int freq;
1976 bool avoid = false;
1977 u8 length;
1978 u16 tmp, core, type, count, max, numb, last, cmd;
1979 const u16 *table;
1980 bool phy6or5x;
1981
1982 u16 buffer[11];
1983 u16 diq_start = 0;
1984 u16 save[2];
1985 u16 gain[2];
1986 struct nphy_iqcal_params params[2];
1987 bool updated[2] = { };
1988
1989 b43_nphy_stay_in_carrier_search(dev, true);
1990
1991 if (dev->phy.rev >= 4) {
1992 avoid = nphy->hang_avoid;
1993 nphy->hang_avoid = 0;
1994 }
1995
9145834e 1996 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 1997
1998 for (i = 0; i < 2; i++) {
1999 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2000 gain[i] = params[i].cal_gain;
2001 }
2581b143
RM		 2002
2003 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 2004
2005 b43_nphy_tx_cal_radio_setup(dev);
e53de674 2006 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 2007
2008 phy6or5x = dev->phy.rev >= 6 ||
2009 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2010 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2011 if (phy6or5x) {
2012 /* TODO */
2013 }
2014
2015 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2016
aa4c7b2a 2017 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 2018 freq = 2500;
2019 else
2020 freq = 5000;
2021
2022 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 2023 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2024 0xFFFF, 0, true, false);
fb43b8e2 2025 else
59af099b 2026 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 2027
2028 if (error == 0) {
2029 if (nphy->mphase_cal_phase_id > 2) {
2030 table = nphy->mphase_txcal_bestcoeffs;
2031 length = 11;
2032 if (dev->phy.rev < 3)
2033 length -= 2;
2034 } else {
2035 if (!full && nphy->txiqlocal_coeffsvalid) {
2036 table = nphy->txiqlocal_bestc;
2037 length = 11;
2038 if (dev->phy.rev < 3)
2039 length -= 2;
2040 } else {
2041 full = true;
2042 if (dev->phy.rev >= 3) {
2043 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2044 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2045 } else {
2046 table = tbl_tx_iqlo_cal_startcoefs;
2047 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2048 }
2049 }
2050 }
2051
2581b143 2052 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 2053
2054 if (full) {
2055 if (dev->phy.rev >= 3)
2056 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2057 else
2058 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2059 } else {
2060 if (dev->phy.rev >= 3)
2061 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2062 else
2063 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2064 }
2065
2066 if (mphase) {
2067 count = nphy->mphase_txcal_cmdidx;
2068 numb = min(max,
2069 (u16)(count + nphy->mphase_txcal_numcmds));
2070 } else {
2071 count = 0;
2072 numb = max;
2073 }
2074
2075 for (; count < numb; count++) {
2076 if (full) {
2077 if (dev->phy.rev >= 3)
2078 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2079 else
2080 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2081 } else {
2082 if (dev->phy.rev >= 3)
2083 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2084 else
2085 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2086 }
2087
2088 core = (cmd & 0x3000) >> 12;
2089 type = (cmd & 0x0F00) >> 8;
2090
2091 if (phy6or5x && updated[core] == 0) {
2092 b43_nphy_update_tx_cal_ladder(dev, core);
2093 updated[core] = 1;
2094 }
2095
2096 tmp = (params[core].ncorr[type] << 8) | 0x66;
2097 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2098
2099 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 2100 buffer[0] = b43_ntab_read(dev,
2101 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 2102 diq_start = buffer[0];
2103 buffer[0] = 0;
d41a3552
RM		 2104 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2105 0);
fb43b8e2
RM		 2106 }
2107
2108 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2109 for (i = 0; i < 2000; i++) {
2110 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2111 if (tmp & 0xC000)
2112 break;
2113 udelay(10);
2114 }
2115
9145834e
RM		 2116 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2117 buffer);
2581b143
RM		 2118 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2119 buffer);
fb43b8e2
RM		 2120
2121 if (type == 1 || type == 3 || type == 4)
2122 buffer[0] = diq_start;
2123 }
2124
2125 if (mphase)
2126 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2127
2128 last = (dev->phy.rev < 3) ? 6 : 7;
2129
2130 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 2131 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 2132 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 2133 if (dev->phy.rev < 3) {
2134 buffer[0] = 0;
2135 buffer[1] = 0;
2136 buffer[2] = 0;
2137 buffer[3] = 0;
2138 }
2581b143
RM		 2139 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2140 buffer);
2141 b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2142 buffer);
2143 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2144 buffer);
2145 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2146 buffer);
fb43b8e2
RM		 2147 length = 11;
2148 if (dev->phy.rev < 3)
2149 length -= 2;
9145834e
RM		 2150 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2151 nphy->txiqlocal_bestc);
fb43b8e2
RM		 2152 nphy->txiqlocal_coeffsvalid = true;
2153 /* TODO: Set nphy->txiqlocal_chanspec to
2154 the current channel */
2155 } else {
2156 length = 11;
2157 if (dev->phy.rev < 3)
2158 length -= 2;
9145834e
RM		 2159 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2160 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 2161 }
2162
53ae8e8c 2163 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 2164 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2165 }
2166
e53de674 2167 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 2168 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 2169
2170 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2171 b43_nphy_tx_iq_workaround(dev);
2172
2173 if (dev->phy.rev >= 4)
2174 nphy->hang_avoid = avoid;
2175
2176 b43_nphy_stay_in_carrier_search(dev, false);
2177
2178 return error;
2179}
2180
15931e31
RM		 2181/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2182static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2183 struct nphy_txgains target, u8 type, bool debug)
2184{
2185 struct b43_phy_n *nphy = dev->phy.n;
2186 int i, j, index;
2187 u8 rfctl[2];
2188 u8 afectl_core;
2189 u16 tmp[6];
2190 u16 cur_hpf1, cur_hpf2, cur_lna;
2191 u32 real, imag;
2192 enum ieee80211_band band;
2193
2194 u8 use;
2195 u16 cur_hpf;
2196 u16 lna[3] = { 3, 3, 1 };
2197 u16 hpf1[3] = { 7, 2, 0 };
2198 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 2199 u32 power[3] = { };
15931e31
RM		 2200 u16 gain_save[2];
2201 u16 cal_gain[2];
2202 struct nphy_iqcal_params cal_params[2];
2203 struct nphy_iq_est est;
2204 int ret = 0;
2205 bool playtone = true;
2206 int desired = 13;
2207
2208 b43_nphy_stay_in_carrier_search(dev, 1);
2209
2210 if (dev->phy.rev < 2)
2211 ;/* TODO: Call N PHY Reapply TX Cal Coeffs */
9145834e 2212 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 2213 for (i = 0; i < 2; i++) {
2214 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2215 cal_gain[i] = cal_params[i].cal_gain;
2216 }
2581b143 2217 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 2218
2219 for (i = 0; i < 2; i++) {
2220 if (i == 0) {
2221 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2222 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2223 afectl_core = B43_NPHY_AFECTL_C1;
2224 } else {
2225 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2226 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2227 afectl_core = B43_NPHY_AFECTL_C2;
2228 }
2229
2230 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2231 tmp[2] = b43_phy_read(dev, afectl_core);
2232 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2233 tmp[4] = b43_phy_read(dev, rfctl[0]);
2234 tmp[5] = b43_phy_read(dev, rfctl[1]);
2235
2236 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2237 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2238 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2239 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2240 (1 - i));
2241 b43_phy_set(dev, afectl_core, 0x0006);
2242 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2243
2244 band = b43_current_band(dev->wl);
2245
2246 if (nphy->rxcalparams & 0xFF000000) {
2247 if (band == IEEE80211_BAND_5GHZ)
2248 b43_phy_write(dev, rfctl[0], 0x140);
2249 else
2250 b43_phy_write(dev, rfctl[0], 0x110);
2251 } else {
2252 if (band == IEEE80211_BAND_5GHZ)
2253 b43_phy_write(dev, rfctl[0], 0x180);
2254 else
2255 b43_phy_write(dev, rfctl[0], 0x120);
2256 }
2257
2258 if (band == IEEE80211_BAND_5GHZ)
2259 b43_phy_write(dev, rfctl[1], 0x148);
2260 else
2261 b43_phy_write(dev, rfctl[1], 0x114);
2262
2263 if (nphy->rxcalparams & 0x10000) {
2264 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2265 (i + 1));
2266 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2267 (2 - i));
2268 }
2269
2270 for (j = 0; i < 4; j++) {
2271 if (j < 3) {
2272 cur_lna = lna[j];
2273 cur_hpf1 = hpf1[j];
2274 cur_hpf2 = hpf2[j];
2275 } else {
2276 if (power[1] > 10000) {
2277 use = 1;
2278 cur_hpf = cur_hpf1;
2279 index = 2;
2280 } else {
2281 if (power[0] > 10000) {
2282 use = 1;
2283 cur_hpf = cur_hpf1;
2284 index = 1;
2285 } else {
2286 index = 0;
2287 use = 2;
2288 cur_hpf = cur_hpf2;
2289 }
2290 }
2291 cur_lna = lna[index];
2292 cur_hpf1 = hpf1[index];
2293 cur_hpf2 = hpf2[index];
2294 cur_hpf += desired - hweight32(power[index]);
2295 cur_hpf = clamp_val(cur_hpf, 0, 10);
2296 if (use == 1)
2297 cur_hpf1 = cur_hpf;
2298 else
2299 cur_hpf2 = cur_hpf;
2300 }
2301
2302 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2303 (cur_lna << 2));
75377b24
RM		 2304 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2305 false);
de9a47f9 2306 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 2307 b43_nphy_stop_playback(dev);
15931e31
RM		 2308
2309 if (playtone) {
59af099b
RM		 2310 ret = b43_nphy_tx_tone(dev, 4000,
2311 (nphy->rxcalparams & 0xFFFF),
2312 false, false);
15931e31
RM		 2313 playtone = false;
2314 } else {
10a79873
RM		 2315 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2316 false, false);
15931e31
RM		 2317 }
2318
2319 if (ret == 0) {
2320 if (j < 3) {
2321 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2322 false);
2323 if (i == 0) {
2324 real = est.i0_pwr;
2325 imag = est.q0_pwr;
2326 } else {
2327 real = est.i1_pwr;
2328 imag = est.q1_pwr;
2329 }
2330 power[i] = ((real + imag) / 1024) + 1;
2331 } else {
2332 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2333 }
53ae8e8c 2334 b43_nphy_stop_playback(dev);
15931e31
RM		 2335 }
2336
2337 if (ret != 0)
2338 break;
2339 }
2340
2341 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2342 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2343 b43_phy_write(dev, rfctl[1], tmp[5]);
2344 b43_phy_write(dev, rfctl[0], tmp[4]);
2345 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2346 b43_phy_write(dev, afectl_core, tmp[2]);
2347 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2348
2349 if (ret != 0)
2350 break;
2351 }
2352
75377b24 2353 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
67c0d6e2 2354 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 2355 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 2356
2357 b43_nphy_stay_in_carrier_search(dev, 0);
2358
2359 return ret;
2360}
2361
2362static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2363 struct nphy_txgains target, u8 type, bool debug)
2364{
2365 return -1;
2366}
2367
2368/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2369static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2370 struct nphy_txgains target, u8 type, bool debug)
2371{
2372 if (dev->phy.rev >= 3)
2373 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2374 else
2375 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2376}
2377
0988a7a1
RM		 2378/*
2379 * Init N-PHY
2380 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2381 */
424047e6
MB		 2382int b43_phy_initn(struct b43_wldev *dev)
2383{
0988a7a1 2384 struct ssb_bus *bus = dev->dev->bus;
95b66bad 2385 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 2386 struct b43_phy_n *nphy = phy->n;
2387 u8 tx_pwr_state;
2388 struct nphy_txgains target;
95b66bad 2389 u16 tmp;
0988a7a1
RM		 2390 enum ieee80211_band tmp2;
2391 bool do_rssi_cal;
2392
2393 u16 clip[2];
2394 bool do_cal = false;
95b66bad 2395
0988a7a1
RM		 2396 if ((dev->phy.rev >= 3) &&
2397 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2398 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2399 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2400 }
2401 nphy->deaf_count = 0;
95b66bad 2402 b43_nphy_tables_init(dev);
0988a7a1
RM		 2403 nphy->crsminpwr_adjusted = false;
2404 nphy->noisevars_adjusted = false;
95b66bad
MB		 2405
2406 /* Clear all overrides */
0988a7a1
RM		 2407 if (dev->phy.rev >= 3) {
2408 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2409 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2410 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2411 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2412 } else {
2413 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2414 }
95b66bad
MB		 2415 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2416 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 2417 if (dev->phy.rev < 6) {
2418 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
2419 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
2420 }
95b66bad
MB		 2421 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2422 ~(B43_NPHY_RFSEQMODE_CAOVER |
2423 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 2424 if (dev->phy.rev >= 3)
2425 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 2426 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
2427
0988a7a1
RM		 2428 if (dev->phy.rev <= 2) {
2429 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
2430 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2431 ~B43_NPHY_BPHY_CTL3_SCALE,
2432 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
2433 }
95b66bad
MB		 2434 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
2435 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
2436
0988a7a1
RM		 2437 if (bus->sprom.boardflags2_lo & 0x100 ||
2438 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
2439 bus->boardinfo.type == 0x8B))
2440 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
2441 else
2442 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
2443 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
2444 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
2445 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 2446
ad9716e8 2447 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 2448 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 2449
2450 if (phy->rev < 2) {
2451 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
2452 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
2453 }
0988a7a1
RM		 2454
2455 tmp2 = b43_current_band(dev->wl);
2456 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
2457 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
2458 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
2459 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
2460 nphy->papd_epsilon_offset[0] << 7);
2461 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
2462 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
2463 nphy->papd_epsilon_offset[1] << 7);
45ca697e 2464 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 2465 } else if (phy->rev >= 5) {
45ca697e 2466 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 2467 }
2468
95b66bad 2469 b43_nphy_workarounds(dev);
95b66bad 2470
0988a7a1 2471 /* Reset CCA, in init code it differs a little from standard way */
730dd705 2472 b43_nphy_bmac_clock_fgc(dev, 1);
0988a7a1
RM		 2473 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
2474 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
2475 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
730dd705 2476 b43_nphy_bmac_clock_fgc(dev, 0);
0988a7a1
RM		 2477
2478 /* TODO N PHY MAC PHY Clock Set with argument 1 */
2479
e50cbcf6 2480 b43_nphy_pa_override(dev, false);
95b66bad
MB		 2481 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
2482 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 2483 b43_nphy_pa_override(dev, true);
0988a7a1 2484
bbec398c
RM		 2485 b43_nphy_classifier(dev, 0, 0);
2486 b43_nphy_read_clip_detection(dev, clip);
0988a7a1
RM		 2487 tx_pwr_state = nphy->txpwrctrl;
2488 /* TODO N PHY TX power control with argument 0
2489 (turning off power control) */
2490 /* TODO Fix the TX Power Settings */
2491 /* TODO N PHY TX Power Control Idle TSSI */
2492 /* TODO N PHY TX Power Control Setup */
2493
2494 if (phy->rev >= 3) {
2495 /* TODO */
2496 } else {
2581b143
RM		 2497 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
2498 b43_ntab_tx_gain_rev0_1_2);
2499 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
2500 b43_ntab_tx_gain_rev0_1_2);
0988a7a1 2501 }
95b66bad 2502
0988a7a1
RM		 2503 if (nphy->phyrxchain != 3)
2504 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
2505 if (nphy->mphase_cal_phase_id > 0)
2506 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
2507
2508 do_rssi_cal = false;
2509 if (phy->rev >= 3) {
2510 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2511 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
2512 else
2513 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
2514
2515 if (do_rssi_cal)
4cb99775 2516 b43_nphy_rssi_cal(dev);
0988a7a1 2517 else
42e1547e 2518 b43_nphy_restore_rssi_cal(dev);
0988a7a1 2519 } else {
4cb99775 2520 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 2521 }
2522
2523 if (!((nphy->measure_hold & 0x6) != 0)) {
2524 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2525 do_cal = (nphy->iqcal_chanspec_2G == 0);
2526 else
2527 do_cal = (nphy->iqcal_chanspec_5G == 0);
2528
2529 if (nphy->mute)
2530 do_cal = false;
2531
2532 if (do_cal) {
b0022e15 2533 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 2534
2535 if (nphy->antsel_type == 2)
2536 ;/*TODO NPHY Superswitch Init with argument 1*/
2537 if (nphy->perical != 2) {
90b9738d 2538 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 2539 if (phy->rev >= 3) {
2540 nphy->cal_orig_pwr_idx[0] =
2541 nphy->txpwrindex[0].index_internal;
2542 nphy->cal_orig_pwr_idx[1] =
2543 nphy->txpwrindex[1].index_internal;
2544 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 2545 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 2546 }
2547 }
2548 }
2549 }
2550
0988a7a1
RM		 2551 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
2552 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
15931e31 2553 ;/* Call N PHY Save Cal */
0988a7a1 2554 else if (nphy->mphase_cal_phase_id == 0)
15931e31 2555 ;/* N PHY Periodic Calibration with argument 3 */
0988a7a1
RM		 2556 } else {
2557 b43_nphy_restore_cal(dev);
2558 }
0988a7a1 2559
6dcd9d91 2560 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
0988a7a1
RM		 2561 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
2562 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
2563 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
2564 if (phy->rev >= 3 && phy->rev <= 6)
2565 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 2566 b43_nphy_tx_lp_fbw(dev);
0988a7a1 2567 /* TODO N PHY Spur Workaround */
95b66bad
MB		 2568
2569 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
53a6e234 2570 return 0;
424047e6 2571}
ef1a628d
MB		 2572
2573static int b43_nphy_op_allocate(struct b43_wldev *dev)
2574{
2575 struct b43_phy_n *nphy;
2576
2577 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
2578 if (!nphy)
2579 return -ENOMEM;
2580 dev->phy.n = nphy;
2581
ef1a628d
MB		 2582 return 0;
2583}
2584
fb11137a 2585static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 2586{
fb11137a
MB		 2587 struct b43_phy *phy = &dev->phy;
2588 struct b43_phy_n *nphy = phy->n;
ef1a628d 2589
fb11137a 2590 memset(nphy, 0, sizeof(*nphy));
ef1a628d 2591
fb11137a 2592 //TODO init struct b43_phy_n
ef1a628d
MB		 2593}
2594
fb11137a 2595static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 2596{
fb11137a
MB		 2597 struct b43_phy *phy = &dev->phy;
2598 struct b43_phy_n *nphy = phy->n;
ef1a628d 2599
ef1a628d 2600 kfree(nphy);
fb11137a
MB		 2601 phy->n = NULL;
2602}
2603
2604static int b43_nphy_op_init(struct b43_wldev *dev)
2605{
2606 return b43_phy_initn(dev);
ef1a628d
MB		 2607}
2608
2609static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
2610{
2611#if B43_DEBUG
2612 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
2613 /* OFDM registers are onnly available on A/G-PHYs */
2614 b43err(dev->wl, "Invalid OFDM PHY access at "
2615 "0x%04X on N-PHY\n", offset);
2616 dump_stack();
2617 }
2618 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
2619 /* Ext-G registers are only available on G-PHYs */
2620 b43err(dev->wl, "Invalid EXT-G PHY access at "
2621 "0x%04X on N-PHY\n", offset);
2622 dump_stack();
2623 }
2624#endif /* B43_DEBUG */
2625}
2626
2627static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
2628{
2629 check_phyreg(dev, reg);
2630 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2631 return b43_read16(dev, B43_MMIO_PHY_DATA);
2632}
2633
2634static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2635{
2636 check_phyreg(dev, reg);
2637 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2638 b43_write16(dev, B43_MMIO_PHY_DATA, value);
2639}
2640
2641static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2642{
2643 /* Register 1 is a 32-bit register. */
2644 B43_WARN_ON(reg == 1);
2645 /* N-PHY needs 0x100 for read access */
2646 reg |= 0x100;
2647
2648 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2649 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2650}
2651
2652static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2653{
2654 /* Register 1 is a 32-bit register. */
2655 B43_WARN_ON(reg == 1);
2656
2657 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2658 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2659}
2660
2661static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 2662 bool blocked)
ef1a628d
MB		 2663{//TODO
2664}
2665
cb24f57f
MB		 2666static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
2667{
2668 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
2669 on ? 0 : 0x7FFF);
2670}
2671
ef1a628d
MB		 2672static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
2673 unsigned int new_channel)
2674{
2675 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2676 if ((new_channel < 1) || (new_channel > 14))
2677 return -EINVAL;
2678 } else {
2679 if (new_channel > 200)
2680 return -EINVAL;
2681 }
2682
2683 return nphy_channel_switch(dev, new_channel);
2684}
2685
2686static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
2687{
2688 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2689 return 1;
2690 return 36;
2691}
2692
ef1a628d
MB		 2693const struct b43_phy_operations b43_phyops_n = {
2694 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 2695 .free = b43_nphy_op_free,
2696 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 2697 .init = b43_nphy_op_init,
ef1a628d
MB		 2698 .phy_read = b43_nphy_op_read,
2699 .phy_write = b43_nphy_op_write,
2700 .radio_read = b43_nphy_op_radio_read,
2701 .radio_write = b43_nphy_op_radio_write,
2702 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 2703 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 2704 .switch_channel = b43_nphy_op_switch_channel,
2705 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 2706 .recalc_txpower = b43_nphy_op_recalc_txpower,
2707 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 2708};
Clone of davem's net-next-2.6 tree