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b43: N-PHY: split RSSI calibration into 2 functions (rev2, rev3)
[net-next-2.6.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
819d772b
JL		 25#include <linux/delay.h>
26#include <linux/types.h>
27
424047e6 28#include "b43.h"
3d0da751 29#include "phy_n.h"
53a6e234 30#include "tables_nphy.h"
424047e6 31
f8187b5b
RM		 32struct nphy_txgains {
33 u16 txgm[2];
34 u16 pga[2];
35 u16 pad[2];
36 u16 ipa[2];
37};
38
39struct nphy_iqcal_params {
40 u16 txgm;
41 u16 pga;
42 u16 pad;
43 u16 ipa;
44 u16 cal_gain;
45 u16 ncorr[5];
46};
47
48struct nphy_iq_est {
49 s32 iq0_prod;
50 u32 i0_pwr;
51 u32 q0_pwr;
52 s32 iq1_prod;
53 u32 i1_pwr;
54 u32 q1_pwr;
55};
424047e6 56
53a6e234
MB		 57void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
58{//TODO
59}
60
18c8adeb 61static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234
MB		 62{//TODO
63}
64
18c8adeb
MB		 65static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
66 bool ignore_tssi)
67{//TODO
68 return B43_TXPWR_RES_DONE;
69}
70
d1591314
MB		 71static void b43_chantab_radio_upload(struct b43_wldev *dev,
72 const struct b43_nphy_channeltab_entry *e)
73{
74 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
75 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
76 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
77 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
78 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
79 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
80 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
81 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
82 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
83 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
84 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
85 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
86 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
87 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
88 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
89 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
90 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
91 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
92 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
93 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
94 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
95 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
96}
97
98static void b43_chantab_phy_upload(struct b43_wldev *dev,
99 const struct b43_nphy_channeltab_entry *e)
100{
101 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
102 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
103 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
104 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
105 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
106 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
107}
108
109static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
110{
111 //TODO
112}
113
ef1a628d
MB		 114/* Tune the hardware to a new channel. */
115static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
53a6e234 116{
d1591314
MB		 117 const struct b43_nphy_channeltab_entry *tabent;
118
119 tabent = b43_nphy_get_chantabent(dev, channel);
120 if (!tabent)
121 return -ESRCH;
122
123 //FIXME enable/disable band select upper20 in RXCTL
124 if (0 /*FIXME 5Ghz*/)
125 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
126 else
127 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
128 b43_chantab_radio_upload(dev, tabent);
129 udelay(50);
130 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
131 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
132 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
133 udelay(300);
134 if (0 /*FIXME 5Ghz*/)
135 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
136 else
137 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
138 b43_chantab_phy_upload(dev, tabent);
139 b43_nphy_tx_power_fix(dev);
53a6e234 140
d1591314 141 return 0;
53a6e234
MB		 142}
143
144static void b43_radio_init2055_pre(struct b43_wldev *dev)
145{
146 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
147 ~B43_NPHY_RFCTL_CMD_PORFORCE);
148 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
149 B43_NPHY_RFCTL_CMD_CHIP0PU |
150 B43_NPHY_RFCTL_CMD_OEPORFORCE);
151 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
152 B43_NPHY_RFCTL_CMD_PORFORCE);
153}
154
155static void b43_radio_init2055_post(struct b43_wldev *dev)
156{
157 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
158 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
159 int i;
160 u16 val;
161
162 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
163 msleep(1);
738f0f43
GS		 164 if ((sprom->revision != 4) ||
165 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
53a6e234
MB		 166 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
167 (binfo->type != 0x46D) ||
168 (binfo->rev < 0x41)) {
169 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
170 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
171 msleep(1);
172 }
173 }
174 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
175 msleep(1);
176 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
177 msleep(1);
178 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
179 msleep(1);
180 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
181 msleep(1);
182 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
183 msleep(1);
184 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
185 msleep(1);
186 for (i = 0; i < 100; i++) {
187 val = b43_radio_read16(dev, B2055_CAL_COUT2);
188 if (val & 0x80)
189 break;
190 udelay(10);
191 }
192 msleep(1);
193 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
194 msleep(1);
ef1a628d 195 nphy_channel_switch(dev, dev->phy.channel);
53a6e234
MB		 196 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
197 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
198 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
199 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
200}
201
202/* Initialize a Broadcom 2055 N-radio */
203static void b43_radio_init2055(struct b43_wldev *dev)
204{
205 b43_radio_init2055_pre(dev);
206 if (b43_status(dev) < B43_STAT_INITIALIZED)
207 b2055_upload_inittab(dev, 0, 1);
208 else
209 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
210 b43_radio_init2055_post(dev);
211}
212
213void b43_nphy_radio_turn_on(struct b43_wldev *dev)
214{
215 b43_radio_init2055(dev);
216}
217
218void b43_nphy_radio_turn_off(struct b43_wldev *dev)
219{
220 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
221 ~B43_NPHY_RFCTL_CMD_EN);
222}
223
95b66bad
MB		 224#define ntab_upload(dev, offset, data) do { \
225 unsigned int i; \
226 for (i = 0; i < (offset##_SIZE); i++) \
227 b43_ntab_write(dev, (offset) + i, (data)[i]); \
228 } while (0)
229
4772ae10
RM		 230/*
231 * Upload the N-PHY tables.
232 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
233 */
95b66bad
MB		 234static void b43_nphy_tables_init(struct b43_wldev *dev)
235{
4772ae10
RM		 236 if (dev->phy.rev < 3)
237 b43_nphy_rev0_1_2_tables_init(dev);
238 else
239 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 240}
241
242static void b43_nphy_workarounds(struct b43_wldev *dev)
243{
244 struct b43_phy *phy = &dev->phy;
245 unsigned int i;
246
247 b43_phy_set(dev, B43_NPHY_IQFLIP,
248 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
95b66bad
MB		 249 if (1 /* FIXME band is 2.4GHz */) {
250 b43_phy_set(dev, B43_NPHY_CLASSCTL,
251 B43_NPHY_CLASSCTL_CCKEN);
252 } else {
253 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
254 ~B43_NPHY_CLASSCTL_CCKEN);
255 }
256 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
257 b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
258
259 /* Fixup some tables */
260 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
261 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
262 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
263 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
264 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
265 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
266 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
267 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
268 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
269 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
270
271 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
272 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
273 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
274 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
275
276 //TODO set RF sequence
277
278 /* Set narrowband clip threshold */
279 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
280 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
281
282 /* Set wideband clip 2 threshold */
283 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
284 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
285 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
286 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
287 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
288 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
289
290 /* Set Clip 2 detect */
291 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
292 B43_NPHY_C1_CGAINI_CL2DETECT);
293 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
294 B43_NPHY_C2_CGAINI_CL2DETECT);
295
296 if (0 /*FIXME*/) {
297 /* Set dwell lengths */
298 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
299 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
300 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
301 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
302
303 /* Set gain backoff */
304 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
305 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
306 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
307 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
308 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
309 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
310
311 /* Set HPVGA2 index */
312 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
313 ~B43_NPHY_C1_INITGAIN_HPVGA2,
314 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
315 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
316 ~B43_NPHY_C2_INITGAIN_HPVGA2,
317 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
318
319 //FIXME verify that the specs really mean to use autoinc here.
320 for (i = 0; i < 3; i++)
321 b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
322 }
323
324 /* Set minimum gain value */
325 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
326 ~B43_NPHY_C1_MINGAIN,
327 23 << B43_NPHY_C1_MINGAIN_SHIFT);
328 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
329 ~B43_NPHY_C2_MINGAIN,
330 23 << B43_NPHY_C2_MINGAIN_SHIFT);
331
332 if (phy->rev < 2) {
333 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
334 ~B43_NPHY_SCRAM_SIGCTL_SCM);
335 }
336
337 /* Set phase track alpha and beta */
338 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
339 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
340 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
341 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
342 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
343 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
344}
345
4a933c85
RM		 346/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
347static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
348{
349 u32 tmslow;
350
351 if (dev->phy.type != B43_PHYTYPE_N)
352 return;
353
354 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
355 if (force)
356 tmslow |= SSB_TMSLOW_FGC;
357 else
358 tmslow &= ~SSB_TMSLOW_FGC;
359 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
360}
361
362/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
95b66bad
MB		 363static void b43_nphy_reset_cca(struct b43_wldev *dev)
364{
365 u16 bbcfg;
366
4a933c85 367 b43_nphy_bmac_clock_fgc(dev, 1);
95b66bad 368 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
4a933c85
RM		 369 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
370 udelay(1);
371 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
372 b43_nphy_bmac_clock_fgc(dev, 0);
373 /* TODO: N PHY Force RF Seq with argument 2 */
95b66bad
MB		 374}
375
376enum b43_nphy_rf_sequence {
377 B43_RFSEQ_RX2TX,
378 B43_RFSEQ_TX2RX,
379 B43_RFSEQ_RESET2RX,
380 B43_RFSEQ_UPDATE_GAINH,
381 B43_RFSEQ_UPDATE_GAINL,
382 B43_RFSEQ_UPDATE_GAINU,
383};
384
385static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
386 enum b43_nphy_rf_sequence seq)
387{
388 static const u16 trigger[] = {
389 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
390 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
391 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
392 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
393 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
394 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
395 };
396 int i;
397
398 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
399
400 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
401 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
402 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
403 for (i = 0; i < 200; i++) {
404 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
405 goto ok;
406 msleep(1);
407 }
408 b43err(dev->wl, "RF sequence status timeout\n");
409ok:
410 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
411 ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
412}
413
414static void b43_nphy_bphy_init(struct b43_wldev *dev)
415{
416 unsigned int i;
417 u16 val;
418
419 val = 0x1E1F;
420 for (i = 0; i < 14; i++) {
421 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
422 val -= 0x202;
423 }
424 val = 0x3E3F;
425 for (i = 0; i < 16; i++) {
426 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
427 val -= 0x202;
428 }
429 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
430}
431
4cb99775
RM		 432/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
433static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 434{
4cb99775
RM		 435 /* TODO */
436}
437
438/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
439static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
440{
441 /* TODO */
442}
443
444/*
445 * RSSI Calibration
446 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
447 */
448static void b43_nphy_rssi_cal(struct b43_wldev *dev)
449{
450 if (dev->phy.rev >= 3) {
451 b43_nphy_rev3_rssi_cal(dev);
452 } else {
453 b43_nphy_rev2_rssi_cal(dev, 2);
454 b43_nphy_rev2_rssi_cal(dev, 0);
455 b43_nphy_rev2_rssi_cal(dev, 1);
456 }
95b66bad
MB		 457}
458
0988a7a1
RM		 459/*
460 * Init N-PHY
461 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
462 */
424047e6
MB		 463int b43_phy_initn(struct b43_wldev *dev)
464{
0988a7a1 465 struct ssb_bus *bus = dev->dev->bus;
95b66bad 466 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 467 struct b43_phy_n *nphy = phy->n;
468 u8 tx_pwr_state;
469 struct nphy_txgains target;
95b66bad 470 u16 tmp;
0988a7a1
RM		 471 enum ieee80211_band tmp2;
472 bool do_rssi_cal;
473
474 u16 clip[2];
475 bool do_cal = false;
95b66bad 476
0988a7a1
RM		 477 if ((dev->phy.rev >= 3) &&
478 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
479 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
480 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
481 }
482 nphy->deaf_count = 0;
95b66bad 483 b43_nphy_tables_init(dev);
0988a7a1
RM		 484 nphy->crsminpwr_adjusted = false;
485 nphy->noisevars_adjusted = false;
95b66bad
MB		 486
487 /* Clear all overrides */
0988a7a1
RM		 488 if (dev->phy.rev >= 3) {
489 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
490 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
491 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
492 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
493 } else {
494 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
495 }
95b66bad
MB		 496 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
497 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 498 if (dev->phy.rev < 6) {
499 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
500 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
501 }
95b66bad
MB		 502 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
503 ~(B43_NPHY_RFSEQMODE_CAOVER |
504 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 505 if (dev->phy.rev >= 3)
506 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 507 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
508
0988a7a1
RM		 509 if (dev->phy.rev <= 2) {
510 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
511 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
512 ~B43_NPHY_BPHY_CTL3_SCALE,
513 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
514 }
95b66bad
MB		 515 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
516 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
517
0988a7a1
RM		 518 if (bus->sprom.boardflags2_lo & 0x100 ||
519 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
520 bus->boardinfo.type == 0x8B))
521 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
522 else
523 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
524 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
525 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
526 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 527
0988a7a1
RM		 528 /* TODO MIMO-Config */
529 /* TODO Update TX/RX chain */
95b66bad
MB		 530
531 if (phy->rev < 2) {
532 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
533 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
534 }
0988a7a1
RM		 535
536 tmp2 = b43_current_band(dev->wl);
537 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
538 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
539 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
540 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
541 nphy->papd_epsilon_offset[0] << 7);
542 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
543 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
544 nphy->papd_epsilon_offset[1] << 7);
545 /* TODO N PHY IPA Set TX Dig Filters */
546 } else if (phy->rev >= 5) {
547 /* TODO N PHY Ext PA Set TX Dig Filters */
548 }
549
95b66bad 550 b43_nphy_workarounds(dev);
95b66bad 551
0988a7a1
RM		 552 /* Reset CCA, in init code it differs a little from standard way */
553 /* b43_nphy_bmac_clock_fgc(dev, 1); */
554 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
555 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
556 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
557 /* b43_nphy_bmac_clock_fgc(dev, 0); */
558
559 /* TODO N PHY MAC PHY Clock Set with argument 1 */
560
561 /* b43_nphy_pa_override(dev, false); */
95b66bad
MB		 562 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
563 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
0988a7a1
RM		 564 /* b43_nphy_pa_override(dev, true); */
565
566 /* b43_nphy_classifier(dev, 0, 0); */
567 /* b43_nphy_read_clip_detection(dev, clip); */
568 tx_pwr_state = nphy->txpwrctrl;
569 /* TODO N PHY TX power control with argument 0
570 (turning off power control) */
571 /* TODO Fix the TX Power Settings */
572 /* TODO N PHY TX Power Control Idle TSSI */
573 /* TODO N PHY TX Power Control Setup */
574
575 if (phy->rev >= 3) {
576 /* TODO */
577 } else {
578 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
579 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
580 }
95b66bad 581
0988a7a1
RM		 582 if (nphy->phyrxchain != 3)
583 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
584 if (nphy->mphase_cal_phase_id > 0)
585 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
586
587 do_rssi_cal = false;
588 if (phy->rev >= 3) {
589 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
590 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
591 else
592 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
593
594 if (do_rssi_cal)
4cb99775 595 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 596 else
597 ;/* b43_nphy_restore_rssi_cal(dev); */
598 } else {
4cb99775 599 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 600 }
601
602 if (!((nphy->measure_hold & 0x6) != 0)) {
603 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
604 do_cal = (nphy->iqcal_chanspec_2G == 0);
605 else
606 do_cal = (nphy->iqcal_chanspec_5G == 0);
607
608 if (nphy->mute)
609 do_cal = false;
610
611 if (do_cal) {
612 /* target = b43_nphy_get_tx_gains(dev); */
613
614 if (nphy->antsel_type == 2)
615 ;/*TODO NPHY Superswitch Init with argument 1*/
616 if (nphy->perical != 2) {
617 /* b43_nphy_rssi_cal(dev); */
618 if (phy->rev >= 3) {
619 nphy->cal_orig_pwr_idx[0] =
620 nphy->txpwrindex[0].index_internal;
621 nphy->cal_orig_pwr_idx[1] =
622 nphy->txpwrindex[1].index_internal;
623 /* TODO N PHY Pre Calibrate TX Gain */
624 /*target = b43_nphy_get_tx_gains(dev)*/
625 }
626 }
627 }
628 }
629
630 /*
631 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
632 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
633 Call N PHY Save Cal
634 else if (nphy->mphase_cal_phase_id == 0)
635 N PHY Periodic Calibration with argument 3
636 } else {
637 b43_nphy_restore_cal(dev);
638 }
639 */
640
641 /* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
642 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
643 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
644 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
645 if (phy->rev >= 3 && phy->rev <= 6)
646 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
647 /* b43_nphy_tx_lp_fbw(dev); */
648 /* TODO N PHY Spur Workaround */
95b66bad
MB		 649
650 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
53a6e234 651 return 0;
424047e6 652}
ef1a628d
MB		 653
654static int b43_nphy_op_allocate(struct b43_wldev *dev)
655{
656 struct b43_phy_n *nphy;
657
658 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
659 if (!nphy)
660 return -ENOMEM;
661 dev->phy.n = nphy;
662
ef1a628d
MB		 663 return 0;
664}
665
fb11137a 666static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 667{
fb11137a
MB		 668 struct b43_phy *phy = &dev->phy;
669 struct b43_phy_n *nphy = phy->n;
ef1a628d 670
fb11137a 671 memset(nphy, 0, sizeof(*nphy));
ef1a628d 672
fb11137a 673 //TODO init struct b43_phy_n
ef1a628d
MB		 674}
675
fb11137a 676static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 677{
fb11137a
MB		 678 struct b43_phy *phy = &dev->phy;
679 struct b43_phy_n *nphy = phy->n;
ef1a628d 680
ef1a628d 681 kfree(nphy);
fb11137a
MB		 682 phy->n = NULL;
683}
684
685static int b43_nphy_op_init(struct b43_wldev *dev)
686{
687 return b43_phy_initn(dev);
ef1a628d
MB		 688}
689
690static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
691{
692#if B43_DEBUG
693 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
694 /* OFDM registers are onnly available on A/G-PHYs */
695 b43err(dev->wl, "Invalid OFDM PHY access at "
696 "0x%04X on N-PHY\n", offset);
697 dump_stack();
698 }
699 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
700 /* Ext-G registers are only available on G-PHYs */
701 b43err(dev->wl, "Invalid EXT-G PHY access at "
702 "0x%04X on N-PHY\n", offset);
703 dump_stack();
704 }
705#endif /* B43_DEBUG */
706}
707
708static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
709{
710 check_phyreg(dev, reg);
711 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
712 return b43_read16(dev, B43_MMIO_PHY_DATA);
713}
714
715static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
716{
717 check_phyreg(dev, reg);
718 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
719 b43_write16(dev, B43_MMIO_PHY_DATA, value);
720}
721
722static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
723{
724 /* Register 1 is a 32-bit register. */
725 B43_WARN_ON(reg == 1);
726 /* N-PHY needs 0x100 for read access */
727 reg |= 0x100;
728
729 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
730 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
731}
732
733static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
734{
735 /* Register 1 is a 32-bit register. */
736 B43_WARN_ON(reg == 1);
737
738 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
739 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
740}
741
742static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 743 bool blocked)
ef1a628d
MB		 744{//TODO
745}
746
cb24f57f
MB		 747static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
748{
749 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
750 on ? 0 : 0x7FFF);
751}
752
ef1a628d
MB		 753static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
754 unsigned int new_channel)
755{
756 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
757 if ((new_channel < 1) || (new_channel > 14))
758 return -EINVAL;
759 } else {
760 if (new_channel > 200)
761 return -EINVAL;
762 }
763
764 return nphy_channel_switch(dev, new_channel);
765}
766
767static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
768{
769 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
770 return 1;
771 return 36;
772}
773
ef1a628d
MB		 774const struct b43_phy_operations b43_phyops_n = {
775 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 776 .free = b43_nphy_op_free,
777 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 778 .init = b43_nphy_op_init,
ef1a628d
MB		 779 .phy_read = b43_nphy_op_read,
780 .phy_write = b43_nphy_op_write,
781 .radio_read = b43_nphy_op_radio_read,
782 .radio_write = b43_nphy_op_radio_write,
783 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 784 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 785 .switch_channel = b43_nphy_op_switch_channel,
786 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 787 .recalc_txpower = b43_nphy_op_recalc_txpower,
788 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 789};
Clone of davem's net-next-2.6 tree