]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/wireless/b43/phy_n.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
b43: N-PHY: implement RSSI selection and offset scaling
[net-next-2.6.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
819d772b
JL		 25#include <linux/delay.h>
26#include <linux/types.h>
27
424047e6 28#include "b43.h"
3d0da751 29#include "phy_n.h"
53a6e234 30#include "tables_nphy.h"
bbec398c 31#include "main.h"
424047e6 32
f8187b5b
RM		 33struct nphy_txgains {
34 u16 txgm[2];
35 u16 pga[2];
36 u16 pad[2];
37 u16 ipa[2];
38};
39
40struct nphy_iqcal_params {
41 u16 txgm;
42 u16 pga;
43 u16 pad;
44 u16 ipa;
45 u16 cal_gain;
46 u16 ncorr[5];
47};
48
49struct nphy_iq_est {
50 s32 iq0_prod;
51 u32 i0_pwr;
52 u32 q0_pwr;
53 s32 iq1_prod;
54 u32 i1_pwr;
55 u32 q1_pwr;
56};
424047e6 57
53a6e234
MB		 58void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
59{//TODO
60}
61
18c8adeb 62static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234
MB		 63{//TODO
64}
65
18c8adeb
MB		 66static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
67 bool ignore_tssi)
68{//TODO
69 return B43_TXPWR_RES_DONE;
70}
71
d1591314
MB		 72static void b43_chantab_radio_upload(struct b43_wldev *dev,
73 const struct b43_nphy_channeltab_entry *e)
74{
75 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
76 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
77 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
78 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
79 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
80 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
81 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
82 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
83 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
84 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
85 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
86 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
87 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
88 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
89 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
90 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
91 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
92 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
93 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
94 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
95 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
96 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
97}
98
99static void b43_chantab_phy_upload(struct b43_wldev *dev,
100 const struct b43_nphy_channeltab_entry *e)
101{
102 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
103 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
104 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
105 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
106 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
107 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
108}
109
110static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
111{
112 //TODO
113}
114
ef1a628d
MB		 115/* Tune the hardware to a new channel. */
116static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
53a6e234 117{
d1591314
MB		 118 const struct b43_nphy_channeltab_entry *tabent;
119
120 tabent = b43_nphy_get_chantabent(dev, channel);
121 if (!tabent)
122 return -ESRCH;
123
124 //FIXME enable/disable band select upper20 in RXCTL
125 if (0 /*FIXME 5Ghz*/)
126 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
127 else
128 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
129 b43_chantab_radio_upload(dev, tabent);
130 udelay(50);
131 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
132 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
133 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
134 udelay(300);
135 if (0 /*FIXME 5Ghz*/)
136 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
137 else
138 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
139 b43_chantab_phy_upload(dev, tabent);
140 b43_nphy_tx_power_fix(dev);
53a6e234 141
d1591314 142 return 0;
53a6e234
MB		 143}
144
145static void b43_radio_init2055_pre(struct b43_wldev *dev)
146{
147 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
148 ~B43_NPHY_RFCTL_CMD_PORFORCE);
149 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
150 B43_NPHY_RFCTL_CMD_CHIP0PU |
151 B43_NPHY_RFCTL_CMD_OEPORFORCE);
152 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
153 B43_NPHY_RFCTL_CMD_PORFORCE);
154}
155
156static void b43_radio_init2055_post(struct b43_wldev *dev)
157{
158 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
159 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
160 int i;
161 u16 val;
162
163 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
164 msleep(1);
738f0f43
GS		 165 if ((sprom->revision != 4) ||
166 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
53a6e234
MB		 167 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
168 (binfo->type != 0x46D) ||
169 (binfo->rev < 0x41)) {
170 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
171 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
172 msleep(1);
173 }
174 }
175 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
176 msleep(1);
177 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
178 msleep(1);
179 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
180 msleep(1);
181 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
182 msleep(1);
183 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
184 msleep(1);
185 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
186 msleep(1);
187 for (i = 0; i < 100; i++) {
188 val = b43_radio_read16(dev, B2055_CAL_COUT2);
189 if (val & 0x80)
190 break;
191 udelay(10);
192 }
193 msleep(1);
194 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
195 msleep(1);
ef1a628d 196 nphy_channel_switch(dev, dev->phy.channel);
53a6e234
MB		 197 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
198 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
199 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
200 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
201}
202
203/* Initialize a Broadcom 2055 N-radio */
204static void b43_radio_init2055(struct b43_wldev *dev)
205{
206 b43_radio_init2055_pre(dev);
207 if (b43_status(dev) < B43_STAT_INITIALIZED)
208 b2055_upload_inittab(dev, 0, 1);
209 else
210 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
211 b43_radio_init2055_post(dev);
212}
213
214void b43_nphy_radio_turn_on(struct b43_wldev *dev)
215{
216 b43_radio_init2055(dev);
217}
218
219void b43_nphy_radio_turn_off(struct b43_wldev *dev)
220{
221 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
222 ~B43_NPHY_RFCTL_CMD_EN);
223}
224
95b66bad
MB		 225#define ntab_upload(dev, offset, data) do { \
226 unsigned int i; \
227 for (i = 0; i < (offset##_SIZE); i++) \
228 b43_ntab_write(dev, (offset) + i, (data)[i]); \
229 } while (0)
230
4772ae10
RM		 231/*
232 * Upload the N-PHY tables.
233 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
234 */
95b66bad
MB		 235static void b43_nphy_tables_init(struct b43_wldev *dev)
236{
4772ae10
RM		 237 if (dev->phy.rev < 3)
238 b43_nphy_rev0_1_2_tables_init(dev);
239 else
240 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 241}
242
243static void b43_nphy_workarounds(struct b43_wldev *dev)
244{
245 struct b43_phy *phy = &dev->phy;
246 unsigned int i;
247
248 b43_phy_set(dev, B43_NPHY_IQFLIP,
249 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
95b66bad
MB		 250 if (1 /* FIXME band is 2.4GHz */) {
251 b43_phy_set(dev, B43_NPHY_CLASSCTL,
252 B43_NPHY_CLASSCTL_CCKEN);
253 } else {
254 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
255 ~B43_NPHY_CLASSCTL_CCKEN);
256 }
257 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
258 b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
259
260 /* Fixup some tables */
261 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
262 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
263 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
264 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
265 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
266 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
267 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
268 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
269 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
270 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
271
272 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
273 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
274 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
275 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
276
277 //TODO set RF sequence
278
279 /* Set narrowband clip threshold */
280 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
281 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
282
283 /* Set wideband clip 2 threshold */
284 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
285 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
286 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
287 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
288 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
289 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
290
291 /* Set Clip 2 detect */
292 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
293 B43_NPHY_C1_CGAINI_CL2DETECT);
294 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
295 B43_NPHY_C2_CGAINI_CL2DETECT);
296
297 if (0 /*FIXME*/) {
298 /* Set dwell lengths */
299 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
300 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
301 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
302 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
303
304 /* Set gain backoff */
305 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
306 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
307 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
308 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
309 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
310 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
311
312 /* Set HPVGA2 index */
313 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
314 ~B43_NPHY_C1_INITGAIN_HPVGA2,
315 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
316 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
317 ~B43_NPHY_C2_INITGAIN_HPVGA2,
318 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
319
320 //FIXME verify that the specs really mean to use autoinc here.
321 for (i = 0; i < 3; i++)
322 b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
323 }
324
325 /* Set minimum gain value */
326 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
327 ~B43_NPHY_C1_MINGAIN,
328 23 << B43_NPHY_C1_MINGAIN_SHIFT);
329 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
330 ~B43_NPHY_C2_MINGAIN,
331 23 << B43_NPHY_C2_MINGAIN_SHIFT);
332
333 if (phy->rev < 2) {
334 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
335 ~B43_NPHY_SCRAM_SIGCTL_SCM);
336 }
337
338 /* Set phase track alpha and beta */
339 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
340 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
341 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
342 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
343 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
344 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
345}
346
4a933c85
RM		 347/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
348static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
349{
350 u32 tmslow;
351
352 if (dev->phy.type != B43_PHYTYPE_N)
353 return;
354
355 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
356 if (force)
357 tmslow |= SSB_TMSLOW_FGC;
358 else
359 tmslow &= ~SSB_TMSLOW_FGC;
360 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
361}
362
363/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
95b66bad
MB		 364static void b43_nphy_reset_cca(struct b43_wldev *dev)
365{
366 u16 bbcfg;
367
4a933c85 368 b43_nphy_bmac_clock_fgc(dev, 1);
95b66bad 369 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
4a933c85
RM		 370 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
371 udelay(1);
372 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
373 b43_nphy_bmac_clock_fgc(dev, 0);
374 /* TODO: N PHY Force RF Seq with argument 2 */
95b66bad
MB		 375}
376
bbec398c
RM		 377/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
378static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
379{
380 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
381 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
382}
383
384/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
385static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
386{
387 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
388 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
389}
390
391/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
392static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
393{
394 u16 tmp;
395
396 if (dev->dev->id.revision == 16)
397 b43_mac_suspend(dev);
398
399 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
400 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
401 B43_NPHY_CLASSCTL_WAITEDEN);
402 tmp &= ~mask;
403 tmp |= (val & mask);
404 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
405
406 if (dev->dev->id.revision == 16)
407 b43_mac_enable(dev);
408
409 return tmp;
410}
411
95b66bad
MB		 412enum b43_nphy_rf_sequence {
413 B43_RFSEQ_RX2TX,
414 B43_RFSEQ_TX2RX,
415 B43_RFSEQ_RESET2RX,
416 B43_RFSEQ_UPDATE_GAINH,
417 B43_RFSEQ_UPDATE_GAINL,
418 B43_RFSEQ_UPDATE_GAINU,
419};
420
421static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
422 enum b43_nphy_rf_sequence seq)
423{
424 static const u16 trigger[] = {
425 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
426 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
427 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
428 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
429 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
430 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
431 };
432 int i;
433
434 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
435
436 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
437 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
438 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
439 for (i = 0; i < 200; i++) {
440 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
441 goto ok;
442 msleep(1);
443 }
444 b43err(dev->wl, "RF sequence status timeout\n");
445ok:
446 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
447 ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
448}
449
450static void b43_nphy_bphy_init(struct b43_wldev *dev)
451{
452 unsigned int i;
453 u16 val;
454
455 val = 0x1E1F;
456 for (i = 0; i < 14; i++) {
457 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
458 val -= 0x202;
459 }
460 val = 0x3E3F;
461 for (i = 0; i < 16; i++) {
462 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
463 val -= 0x202;
464 }
465 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
466}
467
3c95627d
RM		 468/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
469static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
470 s8 offset, u8 core, u8 rail, u8 type)
471{
472 u16 tmp;
473 bool core1or5 = (core == 1) || (core == 5);
474 bool core2or5 = (core == 2) || (core == 5);
475
476 offset = clamp_val(offset, -32, 31);
477 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
478
479 if (core1or5 && (rail == 0) && (type == 2))
480 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
481 if (core1or5 && (rail == 1) && (type == 2))
482 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
483 if (core2or5 && (rail == 0) && (type == 2))
484 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
485 if (core2or5 && (rail == 1) && (type == 2))
486 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
487 if (core1or5 && (rail == 0) && (type == 0))
488 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
489 if (core1or5 && (rail == 1) && (type == 0))
490 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
491 if (core2or5 && (rail == 0) && (type == 0))
492 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
493 if (core2or5 && (rail == 1) && (type == 0))
494 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
495 if (core1or5 && (rail == 0) && (type == 1))
496 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
497 if (core1or5 && (rail == 1) && (type == 1))
498 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
499 if (core2or5 && (rail == 0) && (type == 1))
500 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
501 if (core2or5 && (rail == 1) && (type == 1))
502 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
503 if (core1or5 && (rail == 0) && (type == 6))
504 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
505 if (core1or5 && (rail == 1) && (type == 6))
506 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
507 if (core2or5 && (rail == 0) && (type == 6))
508 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
509 if (core2or5 && (rail == 1) && (type == 6))
510 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
511 if (core1or5 && (rail == 0) && (type == 3))
512 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
513 if (core1or5 && (rail == 1) && (type == 3))
514 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
515 if (core2or5 && (rail == 0) && (type == 3))
516 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
517 if (core2or5 && (rail == 1) && (type == 3))
518 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
519 if (core1or5 && (type == 4))
520 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
521 if (core2or5 && (type == 4))
522 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
523 if (core1or5 && (type == 5))
524 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
525 if (core2or5 && (type == 5))
526 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
527}
528
529/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
530static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
531{
532 u16 val;
533
534 if (dev->phy.rev >= 3) {
535 /* TODO */
536 } else {
537 if (type < 3)
538 val = 0;
539 else if (type == 6)
540 val = 1;
541 else if (type == 3)
542 val = 2;
543 else
544 val = 3;
545
546 val = (val << 12) | (val << 14);
547 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
548 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
549
550 if (type < 3) {
551 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
552 (type + 1) << 4);
553 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
554 (type + 1) << 4);
555 }
556
557 /* TODO use some definitions */
558 if (code == 0) {
559 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
560 if (type < 3) {
561 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
562 0xFEC7, 0);
563 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
564 0xEFDC, 0);
565 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
566 0xFFFE, 0);
567 udelay(20);
568 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
569 0xFFFE, 0);
570 }
571 } else {
572 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
573 0x3000);
574 if (type < 3) {
575 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
576 0xFEC7, 0x0180);
577 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
578 0xEFDC, (code << 1 | 0x1021));
579 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
580 0xFFFE, 0x0001);
581 udelay(20);
582 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
583 0xFFFE, 0);
584 }
585 }
586 }
587}
588
4cb99775
RM		 589/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
590static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 591{
4cb99775
RM		 592 /* TODO */
593}
594
595/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
596static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
597{
598 /* TODO */
599}
600
601/*
602 * RSSI Calibration
603 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
604 */
605static void b43_nphy_rssi_cal(struct b43_wldev *dev)
606{
607 if (dev->phy.rev >= 3) {
608 b43_nphy_rev3_rssi_cal(dev);
609 } else {
610 b43_nphy_rev2_rssi_cal(dev, 2);
611 b43_nphy_rev2_rssi_cal(dev, 0);
612 b43_nphy_rev2_rssi_cal(dev, 1);
613 }
95b66bad
MB		 614}
615
0988a7a1
RM		 616/*
617 * Init N-PHY
618 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
619 */
424047e6
MB		 620int b43_phy_initn(struct b43_wldev *dev)
621{
0988a7a1 622 struct ssb_bus *bus = dev->dev->bus;
95b66bad 623 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 624 struct b43_phy_n *nphy = phy->n;
625 u8 tx_pwr_state;
626 struct nphy_txgains target;
95b66bad 627 u16 tmp;
0988a7a1
RM		 628 enum ieee80211_band tmp2;
629 bool do_rssi_cal;
630
631 u16 clip[2];
632 bool do_cal = false;
95b66bad 633
0988a7a1
RM		 634 if ((dev->phy.rev >= 3) &&
635 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
636 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
637 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
638 }
639 nphy->deaf_count = 0;
95b66bad 640 b43_nphy_tables_init(dev);
0988a7a1
RM		 641 nphy->crsminpwr_adjusted = false;
642 nphy->noisevars_adjusted = false;
95b66bad
MB		 643
644 /* Clear all overrides */
0988a7a1
RM		 645 if (dev->phy.rev >= 3) {
646 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
647 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
648 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
649 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
650 } else {
651 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
652 }
95b66bad
MB		 653 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
654 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 655 if (dev->phy.rev < 6) {
656 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
657 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
658 }
95b66bad
MB		 659 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
660 ~(B43_NPHY_RFSEQMODE_CAOVER |
661 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 662 if (dev->phy.rev >= 3)
663 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 664 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
665
0988a7a1
RM		 666 if (dev->phy.rev <= 2) {
667 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
668 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
669 ~B43_NPHY_BPHY_CTL3_SCALE,
670 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
671 }
95b66bad
MB		 672 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
673 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
674
0988a7a1
RM		 675 if (bus->sprom.boardflags2_lo & 0x100 ||
676 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
677 bus->boardinfo.type == 0x8B))
678 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
679 else
680 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
681 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
682 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
683 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 684
0988a7a1
RM		 685 /* TODO MIMO-Config */
686 /* TODO Update TX/RX chain */
95b66bad
MB		 687
688 if (phy->rev < 2) {
689 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
690 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
691 }
0988a7a1
RM		 692
693 tmp2 = b43_current_band(dev->wl);
694 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
695 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
696 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
697 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
698 nphy->papd_epsilon_offset[0] << 7);
699 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
700 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
701 nphy->papd_epsilon_offset[1] << 7);
702 /* TODO N PHY IPA Set TX Dig Filters */
703 } else if (phy->rev >= 5) {
704 /* TODO N PHY Ext PA Set TX Dig Filters */
705 }
706
95b66bad 707 b43_nphy_workarounds(dev);
95b66bad 708
0988a7a1
RM		 709 /* Reset CCA, in init code it differs a little from standard way */
710 /* b43_nphy_bmac_clock_fgc(dev, 1); */
711 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
712 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
713 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
714 /* b43_nphy_bmac_clock_fgc(dev, 0); */
715
716 /* TODO N PHY MAC PHY Clock Set with argument 1 */
717
718 /* b43_nphy_pa_override(dev, false); */
95b66bad
MB		 719 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
720 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
0988a7a1
RM		 721 /* b43_nphy_pa_override(dev, true); */
722
bbec398c
RM		 723 b43_nphy_classifier(dev, 0, 0);
724 b43_nphy_read_clip_detection(dev, clip);
0988a7a1
RM		 725 tx_pwr_state = nphy->txpwrctrl;
726 /* TODO N PHY TX power control with argument 0
727 (turning off power control) */
728 /* TODO Fix the TX Power Settings */
729 /* TODO N PHY TX Power Control Idle TSSI */
730 /* TODO N PHY TX Power Control Setup */
731
732 if (phy->rev >= 3) {
733 /* TODO */
734 } else {
735 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
736 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
737 }
95b66bad 738
0988a7a1
RM		 739 if (nphy->phyrxchain != 3)
740 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
741 if (nphy->mphase_cal_phase_id > 0)
742 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
743
744 do_rssi_cal = false;
745 if (phy->rev >= 3) {
746 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
747 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
748 else
749 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
750
751 if (do_rssi_cal)
4cb99775 752 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 753 else
754 ;/* b43_nphy_restore_rssi_cal(dev); */
755 } else {
4cb99775 756 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 757 }
758
759 if (!((nphy->measure_hold & 0x6) != 0)) {
760 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
761 do_cal = (nphy->iqcal_chanspec_2G == 0);
762 else
763 do_cal = (nphy->iqcal_chanspec_5G == 0);
764
765 if (nphy->mute)
766 do_cal = false;
767
768 if (do_cal) {
769 /* target = b43_nphy_get_tx_gains(dev); */
770
771 if (nphy->antsel_type == 2)
772 ;/*TODO NPHY Superswitch Init with argument 1*/
773 if (nphy->perical != 2) {
774 /* b43_nphy_rssi_cal(dev); */
775 if (phy->rev >= 3) {
776 nphy->cal_orig_pwr_idx[0] =
777 nphy->txpwrindex[0].index_internal;
778 nphy->cal_orig_pwr_idx[1] =
779 nphy->txpwrindex[1].index_internal;
780 /* TODO N PHY Pre Calibrate TX Gain */
781 /*target = b43_nphy_get_tx_gains(dev)*/
782 }
783 }
784 }
785 }
786
787 /*
788 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
789 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
790 Call N PHY Save Cal
791 else if (nphy->mphase_cal_phase_id == 0)
792 N PHY Periodic Calibration with argument 3
793 } else {
794 b43_nphy_restore_cal(dev);
795 }
796 */
797
798 /* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
799 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
800 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
801 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
802 if (phy->rev >= 3 && phy->rev <= 6)
803 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
804 /* b43_nphy_tx_lp_fbw(dev); */
805 /* TODO N PHY Spur Workaround */
95b66bad
MB		 806
807 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
53a6e234 808 return 0;
424047e6 809}
ef1a628d
MB		 810
811static int b43_nphy_op_allocate(struct b43_wldev *dev)
812{
813 struct b43_phy_n *nphy;
814
815 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
816 if (!nphy)
817 return -ENOMEM;
818 dev->phy.n = nphy;
819
ef1a628d
MB		 820 return 0;
821}
822
fb11137a 823static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 824{
fb11137a
MB		 825 struct b43_phy *phy = &dev->phy;
826 struct b43_phy_n *nphy = phy->n;
ef1a628d 827
fb11137a 828 memset(nphy, 0, sizeof(*nphy));
ef1a628d 829
fb11137a 830 //TODO init struct b43_phy_n
ef1a628d
MB		 831}
832
fb11137a 833static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 834{
fb11137a
MB		 835 struct b43_phy *phy = &dev->phy;
836 struct b43_phy_n *nphy = phy->n;
ef1a628d 837
ef1a628d 838 kfree(nphy);
fb11137a
MB		 839 phy->n = NULL;
840}
841
842static int b43_nphy_op_init(struct b43_wldev *dev)
843{
844 return b43_phy_initn(dev);
ef1a628d
MB		 845}
846
847static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
848{
849#if B43_DEBUG
850 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
851 /* OFDM registers are onnly available on A/G-PHYs */
852 b43err(dev->wl, "Invalid OFDM PHY access at "
853 "0x%04X on N-PHY\n", offset);
854 dump_stack();
855 }
856 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
857 /* Ext-G registers are only available on G-PHYs */
858 b43err(dev->wl, "Invalid EXT-G PHY access at "
859 "0x%04X on N-PHY\n", offset);
860 dump_stack();
861 }
862#endif /* B43_DEBUG */
863}
864
865static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
866{
867 check_phyreg(dev, reg);
868 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
869 return b43_read16(dev, B43_MMIO_PHY_DATA);
870}
871
872static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
873{
874 check_phyreg(dev, reg);
875 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
876 b43_write16(dev, B43_MMIO_PHY_DATA, value);
877}
878
879static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
880{
881 /* Register 1 is a 32-bit register. */
882 B43_WARN_ON(reg == 1);
883 /* N-PHY needs 0x100 for read access */
884 reg |= 0x100;
885
886 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
887 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
888}
889
890static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
891{
892 /* Register 1 is a 32-bit register. */
893 B43_WARN_ON(reg == 1);
894
895 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
896 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
897}
898
899static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 900 bool blocked)
ef1a628d
MB		 901{//TODO
902}
903
cb24f57f
MB		 904static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
905{
906 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
907 on ? 0 : 0x7FFF);
908}
909
ef1a628d
MB		 910static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
911 unsigned int new_channel)
912{
913 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
914 if ((new_channel < 1) || (new_channel > 14))
915 return -EINVAL;
916 } else {
917 if (new_channel > 200)
918 return -EINVAL;
919 }
920
921 return nphy_channel_switch(dev, new_channel);
922}
923
924static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
925{
926 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
927 return 1;
928 return 36;
929}
930
ef1a628d
MB		 931const struct b43_phy_operations b43_phyops_n = {
932 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 933 .free = b43_nphy_op_free,
934 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 935 .init = b43_nphy_op_init,
ef1a628d
MB		 936 .phy_read = b43_nphy_op_read,
937 .phy_write = b43_nphy_op_write,
938 .radio_read = b43_nphy_op_radio_read,
939 .radio_write = b43_nphy_op_radio_write,
940 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 941 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 942 .switch_channel = b43_nphy_op_switch_channel,
943 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 944 .recalc_txpower = b43_nphy_op_recalc_txpower,
945 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 946};
Clone of davem's net-next-2.6 tree